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gem5/gem5: upgrade to 20.1.0.5

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This is the latest point release in the 20.1 series, and also fixes the build with
scons 4.1 (which is now in master).

Change-Id: I31b8aabc8af47cc64af68f2fd0ee2b9b9b656e89
Signed-off-by: Ross Burton <ross.burton@arm.com>
This commit is contained in:
Ross Burton
2021-06-08 12:21:11 +01:00
parent 40611d12f5
commit 6aeef23f3d
4 changed files with 4 additions and 78 deletions
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meta-gem5/recipes-devtools/gem5/files/pyinit-threads.patch
-32
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@@ -1,32 +0,0 @@
Upstream-Status: Backport
Signed-off-by: Ross Burton <ross.burton@arm.com>
From ae2ee2a4a51914cf78deb5c253a3b03cbb53ce72 Mon Sep 17 00:00:00 2001
From: Boris Staletic <boris.staletic@gmail.com>
Date: Mon, 15 Jun 2020 19:36:43 +0200
Subject: [PATCH] Avoid using deprecated API in python 3.9
The PyEval_InitThreads() and PyEval_ThreadsInitialized() functions are
now deprecated and will be removed in Python 3.11. Calling
PyEval_InitThreads() now does nothing. The GIL is initialized by
Py_Initialize() since Python 3.7.
---
include/pybind11/detail/internals.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/pybind11/detail/internals.h b/include/pybind11/detail/internals.h
index 6224dfb22..166a18a32 100644
--- a/ext/pybind11/include/pybind11/detail/internals.h
+++ b/ext/pybind11/include/pybind11/detail/internals.h
@@ -273,7 +273,10 @@ PYBIND11_NOINLINE inline internals &get_internals() {
auto *&internals_ptr = *internals_pp;
internals_ptr = new internals();
#if defined(WITH_THREAD)
- PyEval_InitThreads();
+
+ #if PY_VERSION_HEX < 0x03090000
+ PyEval_InitThreads();
+ #endif
PyThreadState *tstate = PyThreadState_Get();
#if PY_VERSION_HEX >= 0x03070000
internals_ptr->tstate = PyThread_tss_alloc();
meta-gem5/recipes-devtools/gem5/gem5-aarch64-native/0002-arch-arm-Fix-atomics-permission-checks-in-TLB.patch
-38
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@@ -1,38 +0,0 @@
From c47920d81c4c29e8c868c005ff4330c46becbad5 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Wed, 03 Mar 2021 11:38:06 +0000
Subject: [PATCH] arch-arm: Fix atomics permission checks in TLB
For stage 2 translations, atomic accesses were not checking the
access permission bits in the page table descriptors, and were
instead wrongly using the nature of the request itself
(r/w booleans).
Change-Id: I27fbc95f04ea659e77ad5a3afb551873c9c971f0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42073
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Upstream-Status: Backport
Signed-off-By: Nathan Dunne <nathan.dunne@arm.com>
---
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index fd72d25..8e5b3ca 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -872,8 +872,7 @@
// sctlr.wxn overrides the xn bit
grant = !wxn && !xn;
} else if (is_atomic) {
- grant = r && w;
- grant_read = r;
+ grant = hap;
} else if (is_write) {
grant = hap & 0x2;
} else { // is_read
meta-gem5/recipes-devtools/gem5/gem5-aarch64-native_20.bb
+1 -2
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@@ -1,7 +1,6 @@
require gem5-source_20.inc
SRC_URI += "file://0001-dev-arm-SMMUv3-enable-interrupt-interface.patch \
file://0002-arch-arm-Fix-atomics-permission-checks-in-TLB.patch"
SRC_URI += "file://0001-dev-arm-SMMUv3-enable-interrupt-interface.patch"
BPN = "gem5-aarch64-native"
meta-gem5/recipes-devtools/gem5/gem5-source_20.inc
+3 -6
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@@ -1,12 +1,9 @@
# gem5 sources v20.1.0.3
LIC_FILES_CHKSUM = "file://COPYING;md5=2d9514d69d8abf88b6e9125e759bf0ab \
file://LICENSE;md5=a585e2893cee63d16a1d8bc16c6297ec"
SRC_URI = "git://gem5.googlesource.com/public/gem5;protocol=https;nobranch=1 \
file://pyinit-threads.patch"
RELEASE_TAG = "v20.1.0.3"
SRCREV = "cd21b5a5519940a0fa9b9a2dde68f30403d17f7e"
SRC_URI = "git://gem5.googlesource.com/public/gem5;protocol=https;nobranch=1"
RELEASE_TAG = "v20.1.0.5"
SRCREV = "31cd81fdec46bae4b48d4f3788776936389dbdec"
PV = "${RELEASE_TAG}"