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arm-bsp/linux-linaro-arm-5.4: n1sdp: pcie: add quirk support to enable remote chip PCIe
Base address mapping for remote chip Root PCIe ECAM space. Remote Chip PCIe topology is enumerated in Firmware and current change takes reference of enumerated PCIe hierarchy of Remote chip into the kernel and include in complete PCIe topology for kernel framework. Change-Id: I2bbceb5c89cc8fb4609e646652917cd97d638a27 Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Khasim Mohammed
committed by
Jon Mason
Jon Mason
parent
2eeea26a51
commit
87e8e14b9a
+134
@@ -0,0 +1,134 @@
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Upstream-Status: Inappropriate [will not be submitted as its an hack required to fix the hardware issue]
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This patch is picked from the git repository:
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https://git.linaro.org/landing-teams/working/arm/n1sdp-pcie-quirk.git/patch/?id=04b7e76d0fe6481a803f58e54e008a1489d713a5
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Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
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From 94892f681463908e4a879258dfd6053bbb025447 Mon Sep 17 00:00:00 2001
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From: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
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Date: Fri, 31 Jul 2020 15:32:24 +0530
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Subject: [PATCH 5/5] n1sdp: pcie: add quirk support enabling remote chip PCIe
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Base address mapping for remote chip Root PCIe ECAM space.
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Remote Chip PCIe topology is enumerated in Firmware and current
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change takes referecne of enumerated PCIe hierarchy of Remote chip into the
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kernel and include in complete PCIe topology for kernel framework.
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Change-Id: I368e51c535ac66e48bd356bd33da6c49f1a0fb2a
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Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
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---
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drivers/acpi/pci_mcfg.c | 1 +
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drivers/pci/controller/pcie-n1sdp.c | 34 ++++++++++++++++++++++++++---
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include/linux/pci-ecam.h | 1 +
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3 files changed, 33 insertions(+), 3 deletions(-)
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diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
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index 7a2b41b9ab57..53d073ef941f 100644
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--- a/drivers/acpi/pci_mcfg.c
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+++ b/drivers/acpi/pci_mcfg.c
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@@ -149,6 +149,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
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/* N1SDP SoC with v1 PCIe controller */
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N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
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N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
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+ N1SDP_ECAM_MCFG(0x20181101, 2, &pci_n1sdp_remote_pcie_ecam_ops),
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};
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static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
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diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
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index 04c0de043817..19b573468ac5 100644
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--- a/drivers/pci/controller/pcie-n1sdp.c
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+++ b/drivers/pci/controller/pcie-n1sdp.c
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@@ -28,8 +28,10 @@
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/* Platform specific values as hardcoded in the firmware. */
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#define AP_NS_SHARED_MEM_BASE 0x06000000
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-#define MAX_SEGMENTS 2 /* Two PCIe root complexes. */
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+/* Two PCIe root complexes in One Chip + One PCIe RC in Remote Chip*/
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+#define MAX_SEGMENTS 3
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#define BDF_TABLE_SIZE SZ_16K
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+#define REMOTE_CHIP_ADDR_OFFSET 0x40000000000
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/*
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* Shared memory layout as written by the SCP upon boot time:
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@@ -100,7 +102,10 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
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if (segment >= MAX_SEGMENTS)
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return -ENODEV;
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- table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
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+ if (segment > 1)
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+ table_base = AP_NS_SHARED_MEM_BASE + REMOTE_CHIP_ADDR_OFFSET;
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+ else
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+ table_base = AP_NS_SHARED_MEM_BASE + segment * BDF_TABLE_SIZE;
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if (!request_mem_region(table_base, BDF_TABLE_SIZE,
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"PCIe valid BDFs")) {
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@@ -122,7 +127,13 @@ static int pci_n1sdp_init(struct pci_config_window *cfg, unsigned int segment)
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memcpy_fromio(pcie_discovery_data[segment], shared_data, bdfs_size);
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- rc_remapped_addr[segment] = devm_ioremap_nocache(dev,
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+
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+ if (segment > 1)
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+ rc_remapped_addr[segment] = devm_ioremap_nocache(dev,
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+ shared_data->rc_base_addr + REMOTE_CHIP_ADDR_OFFSET,
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+ PCI_CFG_SPACE_EXP_SIZE);
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+ else
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+ rc_remapped_addr[segment] = devm_ioremap_nocache(dev,
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shared_data->rc_base_addr,
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PCI_CFG_SPACE_EXP_SIZE);
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if (!rc_remapped_addr[segment]) {
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@@ -145,6 +156,11 @@ static int pci_n1sdp_ccix_init(struct pci_config_window *cfg)
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return pci_n1sdp_init(cfg, 1);
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}
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+static int pci_n1sdp_remote_pcie_init(struct pci_config_window *cfg)
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+{
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+ return pci_n1sdp_init(cfg, 2);
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+}
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+
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struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops = {
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.bus_shift = 20,
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.init = pci_n1sdp_pcie_init,
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@@ -165,6 +181,16 @@ struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops = {
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}
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};
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+struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops = {
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+ .bus_shift = 20,
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+ .init = pci_n1sdp_remote_pcie_init,
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+ .pci_ops = {
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+ .map_bus = pci_n1sdp_map_bus,
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+ .read = pci_generic_config_read32,
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+ .write = pci_generic_config_write32,
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+ }
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+};
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+
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static const struct of_device_id n1sdp_pcie_of_match[] = {
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{ .compatible = "arm,n1sdp-pcie" },
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{ },
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@@ -186,6 +212,8 @@ static int n1sdp_pcie_probe(struct platform_device *pdev)
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return pci_host_common_probe(pdev, &pci_n1sdp_pcie_ecam_ops);
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case 1:
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return pci_host_common_probe(pdev, &pci_n1sdp_ccix_ecam_ops);
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+ case 2:
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+ return pci_host_common_probe(pdev, &pci_n1sdp_remote_pcie_ecam_ops);
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}
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dev_err(&pdev->dev, "Invalid segment number, must be smaller than %d\n",
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diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
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index 03cdea69f4e8..2270662428e1 100644
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--- a/include/linux/pci-ecam.h
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+++ b/include/linux/pci-ecam.h
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@@ -59,6 +59,7 @@ extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
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extern struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
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extern struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
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extern struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops; /* Arm N1SDP PCIe */
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+extern struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops; /* Arm N1SDP PCIe */
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#endif
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#ifdef CONFIG_PCI_HOST_COMMON
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--
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2.25.0
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@@ -11,6 +11,7 @@ SRC_URI_append_n1sdp = " \
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file://0002-pci_quirk-add-acs-override-for-PCI-devices.patch \
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file://0003-pcie-Add-quirk-for-the-Arm-Neoverse-N1SDP-platform.patch \
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file://0004-n1sdp-update-n1sdp-pci-quirk-for-SR-IOV-support.patch \
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file://0005-n1sdp-pcie-add-quirk-support-enabling-remote-chip-PC.patch \
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file://enable-realtek-R8169.cfg \
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file://scripts-dtc-remove-redundant-YYLOC.patch \
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"
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