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arm-bsp/corstone500: removal of support

Browse Source 
corstone500 is End-of-life'd (EOL'ed).  Remove support for it from the
tree.

Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Jon Mason
2023-08-30 13:37:39 -05:00
parent bddec6c800
commit b8367b72bf
15 changed files with 1 additions and 620 deletions
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8
.gitlab-ci.yml
View File

@@ -104,14 +104,6 @@ update-repos:
# VIRT: [none, xen]
# TESTING: testimage
corstone500:
extends: .build
parallel:
matrix:
- TESTING: testimage
tags:
- x86_64
corstone1000-fvp:
extends: .build
parallel:

12
ci/corstone500.yml
View File

@@ -1,12 +0,0 @@
header:
version: 14
includes:
- ci/base.yml
- ci/fvp.yml
- ci/poky-tiny.yml
local_conf_header:
fvp-config: |
IMAGE_FEATURES:remove = " ssh-server-dropbear"
machine: corstone500

1
ci/fvps.yml
View File

@@ -15,7 +15,6 @@ local_conf_header:
target:
- nativesdk-fvp-base-a-aem
- nativesdk-fvp-corstone500
- nativesdk-fvp-corstone1000
- nativesdk-fvp-n1-edge
- nativesdk-fvp-sgi575

2
ci/jobs-to-kas
View File

@@ -3,7 +3,7 @@
# This script is expecting an input of machine name, optionally followed by a
# colon and a list of one or more parameters separated by commas between
# brackets. For example, the following are acceptable:
# corstone500
# corstone1000-mps3
# fvp-base: [testimage]
# qemuarm64-secureboot: [clang, glibc, testimage]
#

50
kas/corstone500.yml
View File

@@ -1,50 +0,0 @@
header:
version: 11
includes:
- kas/fvp-eula.yml
env:
DISPLAY: ""
distro: poky-tiny
defaults:
repos:
refspec: master
repos:
meta-arm:
layers:
meta-arm:
meta-arm-bsp:
meta-arm-toolchain:
poky:
url: https://git.yoctoproject.org/git/poky
refspec: master
layers:
meta:
meta-poky:
meta-yocto-bsp:
meta-openembedded:
url: https://git.openembedded.org/meta-openembedded
refspec: master
layers:
meta-oe:
meta-python:
local_conf_header:
base: |
CONF_VERSION = "2"
PACKAGE_CLASSES = "package_ipk"
BB_NUMBER_THREADS ?= "16"
PARALLEL_MAKE ?= "-j16"
PACKAGECONFIG:append:pn-perf = " coresight"
fvp-config: |
IMAGE_CLASSES:append = " ${@bb.utils.contains('BUILD_ARCH', 'x86_64', 'fvpboot', '', d)}"
machine: corstone500
target:
- core-image-minimal

49
meta-arm-bsp/conf/machine/corstone500.conf
View File

@@ -1,49 +0,0 @@
#@TYPE: Machine
#@NAME: Corstone-500 machine
#@DESCRIPTION: Machine configuration for the Corstone-500 platform
require conf/machine/include/arm/armv7a/tune-cortexa5.inc
# Corstone-500 is built against poky-tiny distro.
# poky-tiny sets PREFERRED_PROVIDER_virtual/kernel to linux-yocto-tiny.
# Since distro config is evaluated after the machine config, we need to
# use the strongest override possible (forcevariable) so the
# PREFERRED_PROVIDER_virtual/kernel specified in the machine config will
# apply.
#
PREFERRED_PROVIDER_virtual/kernel:forcevariable = "linux-yocto"
PREFERRED_VERSION_linux-yocto ?= "6.1%"
EXTRA_IMAGEDEPENDS += "trusted-firmware-a u-boot"
IMAGE_CLASSES += "wic_nopt"
IMAGE_FSTYPES:forcevariable = "cpio.gz squashfs wic wic.nopt"
SERIAL_CONSOLES = "115200;ttyAMA0"
# Corstone-500 u-boot configuration
UBOOT_MACHINE = "corstone500_defconfig"
UBOOT_IMAGE_ENTRYPOINT = "0x84000000"
UBOOT_IMAGE_LOADADDRESS = "0x84000000"
PREFERRED_VERSION_u-boot ?= "2023.07%"
# making sure EXTRA_IMAGEDEPENDS will be used while creating the image
WKS_FILE_DEPENDS:append = " ${EXTRA_IMAGEDEPENDS}"
WKS_FILE ?= "core-image-minimal.corstone500.wks"
TEST_TARGET = "OEFVPTarget"
TEST_SUITES = "fvp_boot"
FVP_PROVIDER ?= "fvp-corstone500-native"
FVP_EXE ?= "FVP_Corstone-500"
FVP_CONFIG[board.flashloader0.fname] ?= "bl1.bin"
FVP_DATA ?= "css.cluster.cpu0=${IMAGE_NAME}.wic.nopt@0x80000000"
FVP_CONSOLE ?= "terminal_0"
FVP_TERMINALS[css.terminal_0] ?= "console"
FVP_TERMINALS[css.terminal_1] ?= ""
# Disable openssl in kmod to shink the initramfs size
PACKAGECONFIG:remove:pn-kmod = "openssl"
IMAGE_NAME_SUFFIX = ""

28
meta-arm-bsp/documentation/corstone500.md
View File

@@ -1,28 +0,0 @@
# Corstone-500 Platform Support in meta-arm-bsp
## Howto Build and Run
### Configuration:
Use the kas
### Build:
``bash$ kas build kas/corstone500.yml
### Run:
Building using kas should have fetch the Fixed Virtual Platform for this
platform and installed at:
build/tmp/sysroots-components/x86_64/fvp-corstone500-native/usr/bin/./FVP_Corstone-500
with this in place is possible to launch the FVP using the runfvp inside the
scripts directory:
cd scripts
./runfvp ../build/tmp/deploy/images/corstone500/core-image-minimal-corstone500.fvpconf --console
this will output the console in the launching terminal

17
meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone500.inc
View File

@@ -1,17 +0,0 @@
# Corstone-500 specific TFA support
COMPATIBLE_MACHINE = "corstone500"
TFA_PLATFORM = "a5ds"
TFA_DEBUG = "1"
TFA_UBOOT = "1"
TFA_BUILD_TARGET = "all fip"
TFA_INSTALL_TARGET = "bl1.bin fip.bin"
EXTRA_OEMAKE:append = " \
ARCH=aarch32 \
FVP_HW_CONFIG_DTS=fdts/a5ds.dts \
ARM_ARCH_MAJOR=7 \
AARCH32_SP=sp_min \
ARM_CORTEX_A5=yes \
ARM_XLAT_TABLES_LIB_V1=1 \
"

1
meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_%.bbappend
View File

@@ -3,7 +3,6 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files/:"
# Machine specific TFAs
MACHINE_TFA_REQUIRE ?= ""
MACHINE_TFA_REQUIRE:corstone500 = "trusted-firmware-a-corstone500.inc"
MACHINE_TFA_REQUIRE:corstone1000 = "trusted-firmware-a-corstone1000.inc"
MACHINE_TFA_REQUIRE:fvp-base = "trusted-firmware-a-fvp.inc"
MACHINE_TFA_REQUIRE:juno = "trusted-firmware-a-juno.inc"

120
meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0001-armv7-adding-generic-timer-access-through-MMIO.patch
View File

@@ -1,120 +0,0 @@
From 1f5d48695b896fcaf913eda788117b14afe84e39 Mon Sep 17 00:00:00 2001
From: Rui Miguel Silva <rui.silva@linaro.org>
Date: Wed, 18 Dec 2019 21:52:34 +0000
Subject: [PATCH] armv7: adding generic timer access through MMIO
This driver enables the ARMv7 generic timer.
The access to the timer registers is through memory mapping (MMIO).
This driver can be used by u-boot to access to the timer through MMIO
when arch_timer is not available in the core (access using system
instructions not possible), for example, in case of Cortex-A5.
This driver configures and enables the generic timer at
the u-boot initcall level (timer_init) before u-boot relocation.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Upstream-Status: Pending [Not submitted to upstream yet]
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/mmio_timer.c | 75 +++++++++++++++++++++++++++++++++
2 files changed, 76 insertions(+)
create mode 100644 arch/arm/cpu/armv7/mmio_timer.c
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 653eef8ad79e..5859b2e2120b 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o
obj-$(CONFIG_IPROC) += iproc-common/
obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
+obj-$(CONFIG_SYS_MMIO_TIMER) += mmio_timer.o
ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
diff --git a/arch/arm/cpu/armv7/mmio_timer.c b/arch/arm/cpu/armv7/mmio_timer.c
new file mode 100644
index 000000000000..edd806e06e42
--- /dev/null
+++ b/arch/arm/cpu/armv7/mmio_timer.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <bootstage.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CNTCTLBASE 0x1a020000UL
+#define CNTREADBASE 0x1a030000UL
+#define CNTEN (1 << 0)
+#define CNTFCREQ (1 << 8)
+
+static inline uint32_t mmio_read32(uintptr_t addr)
+{
+ return *(volatile uint32_t*)addr;
+}
+
+static inline void mmio_write32(uintptr_t addr, uint32_t data)
+{
+ *(volatile uint32_t*)addr = data;
+}
+
+int timer_init(void)
+{
+ /* calculate the frequency in ms */
+ gd->arch.timer_rate_hz = COUNTER_FREQUENCY / CONFIG_SYS_HZ;
+
+ /* configure CNTFID0 register: set the base frequency */
+ mmio_write32(CNTCTLBASE + 0x20, COUNTER_FREQUENCY);
+
+ /*
+ * configure CNTCR register:
+ * enable the generic counter and;
+ * select the first frequency entry
+ */
+ mmio_write32(CNTCTLBASE, CNTFCREQ | CNTEN);
+
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ return (((u64)(mmio_read32(CNTREADBASE + 0x4)) << 32) |
+ mmio_read32(CNTREADBASE));
+}
+
+ulong get_timer(ulong base)
+{
+ return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long endtime;
+
+ endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
+ 1000UL);
+
+ endtime += get_ticks();
+
+ while (get_ticks() < endtime)
+ ;
+}
+
+ulong get_tbclk(void)
+{
+ return gd->arch.timer_rate_hz;
+}

297
meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0002-board-arm-add-corstone500-board.patch
View File

@@ -1,297 +0,0 @@
From e296c84e276e8ccc39dd593442a4f3f8655b1f57 Mon Sep 17 00:00:00 2001
From: Rui Miguel Silva <rui.silva@linaro.org>
Date: Wed, 8 Jan 2020 09:48:11 +0000
Subject: [PATCH] board: arm: add corstone500 board
Add support for the Arm corstone500 platform, with a cortex-a5
chip, add the default configuration, initialization and
makefile for this system.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Upstream-Status: Pending [Not submitted to upstream yet]
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
---
arch/arm/Kconfig | 10 +++
board/armltd/corstone500/Kconfig | 12 +++
board/armltd/corstone500/Makefile | 8 ++
board/armltd/corstone500/corstone500.c | 48 ++++++++++++
configs/corstone500_defconfig | 41 ++++++++++
include/configs/corstone500.h | 103 +++++++++++++++++++++++++
6 files changed, 222 insertions(+)
create mode 100644 board/armltd/corstone500/Kconfig
create mode 100644 board/armltd/corstone500/Makefile
create mode 100644 board/armltd/corstone500/corstone500.c
create mode 100644 configs/corstone500_defconfig
create mode 100644 include/configs/corstone500.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 99264a64780c..522e3e549c8d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1338,6 +1338,15 @@ config TARGET_CORSTONE1000
select PL01X_SERIAL
select DM
+config TARGET_CORSTONE500
+ bool "Support Corstone500"
+ select CPU_V7A
+ select SEMIHOSTING
+ select PL01X_SERIAL
+ help
+ This enables support for Corstone500 ARM which is a
+ Cortex-A5 system
+
config TARGET_TOTAL_COMPUTE
bool "Support Total Compute Platform"
select ARM64
@@ -2294,6 +2303,7 @@ source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig"
source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig"
+source "board/armltd/corstone500/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
diff --git a/board/armltd/corstone500/Kconfig b/board/armltd/corstone500/Kconfig
new file mode 100644
index 000000000000..8e689bd1fdc8
--- /dev/null
+++ b/board/armltd/corstone500/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CORSTONE500
+
+config SYS_BOARD
+ default "corstone500"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "corstone500"
+
+endif
diff --git a/board/armltd/corstone500/Makefile b/board/armltd/corstone500/Makefile
new file mode 100644
index 000000000000..6598fdd3ae0d
--- /dev/null
+++ b/board/armltd/corstone500/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 ARM Limited
+# (C) Copyright 2022 Linaro
+# Rui Miguel Silva <rui.silva@linaro.org>
+#
+
+obj-y := corstone500.o
diff --git a/board/armltd/corstone500/corstone500.c b/board/armltd/corstone500/corstone500.c
new file mode 100644
index 000000000000..19ec5564291f
--- /dev/null
+++ b/board/armltd/corstone500/corstone500.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 ARM Limited
+ * (C) Copyright 2022 Linaro
+ * Rui Miguel Silva <rui.silva@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+
+static const struct pl01x_serial_plat serial_platdata = {
+ .base = V2M_UART0,
+ .type = TYPE_PL011,
+ .clock = CFG_PL011_CLOCK,
+};
+
+U_BOOT_DRVINFO(corstone500_serials) = {
+ .name = "serial_pl01x",
+ .plat = &serial_platdata,
+};
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
diff --git a/configs/corstone500_defconfig b/configs/corstone500_defconfig
new file mode 100644
index 000000000000..91661beb8d8d
--- /dev/null
+++ b/configs/corstone500_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_TARGET_CORSTONE500=y
+CONFIG_TEXT_BASE=0x88000000
+CONFIG_SYS_MALLOC_LEN=0x840000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x40000
+CONFIG_SYS_PROMPT="corstone500# "
+CONFIG_IDENT_STRING=" corstone500 aarch32"
+CONFIG_SYS_LOAD_ADDR=0x90000000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xff000000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1a200000 root=/dev/ram0 rw loglevel=9"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_CONSOLE is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_ARMFLASH=y
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_DM=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SERIAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/corstone500.h b/include/configs/corstone500.h
new file mode 100644
index 000000000000..555e0e44e432
--- /dev/null
+++ b/include/configs/corstone500.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 ARM Limited
+ * (C) Copyright 2022 Linaro
+ * Rui Miguel Silva <rui.silva@linaro.org>
+ *
+ * Configuration for Cortex-A5 Corstone500. Parts were derived from other ARM
+ * configurations.
+ */
+
+#ifndef __CORSTONE500_H
+#define __CORSTONE500_H
+
+/* Generic Timer Definitions */
+#define CONFIG_SYS_HZ_CLOCK 7500000
+#define CONFIG_SYS_HZ 1000
+#define COUNTER_FREQUENCY CONFIG_SYS_HZ_CLOCK
+
+#ifdef CONFIG_CORSTONE500_MEMORY_MAP_EXTENDED
+#define V2M_SRAM0 0x00010000
+#define V2M_SRAM1 0x02200000
+#define V2M_QSPI 0x0a800000
+#else
+#define V2M_SRAM0 0x00000000
+#define V2M_SRAM1 0x02000000
+#define V2M_QSPI 0x08000000
+#endif
+
+#define V2M_DEBUG 0x10000000
+#define V2M_BASE_PERIPH 0x1a000000
+#define V2M_A5_PERIPH 0x1c000000
+#define V2M_L2CC_PERIPH 0x1c010000
+
+#define V2M_MASTER_EXPANSION0 0x40000000
+#define V2M_MASTER_EXPANSION1 0x60000000
+
+#define V2M_BASE 0x80000000
+
+#define V2M_PERIPH_OFFSET(x) (x << 16)
+
+#define V2M_SYSID (V2M_BASE_PERIPH)
+#define V2M_SYCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1))
+#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(2))
+#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(3))
+#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(4))
+#define V2M_TIMER0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(5))
+
+#define V2M_WATCHDOG_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(16))
+#define V2M_WATCHDOG_REFRESH (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(17))
+
+#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32))
+#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33))
+
+#define V2M_RTC (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34))
+#define V2M_TRNG (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35))
+
+/* PL011 Serial Configuration */
+#define CONFIG_CONS_INDEX 0
+#define CFG_PL011_CLOCK 7500000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1 (V2M_BASE)
+
+/* Top 16MB reserved for secure world use */
+#define DRAM_SEC_SIZE 0x01000000
+#define PHYS_SDRAM_1_SIZE (0x80000000 - DRAM_SEC_SIZE)
+
+/* Miscellaneous configurable options */
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+#define CONFIG_SYS_MMIO_TIMER
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "kernel_name=Image\0" \
+ "kernel_addr=0x80f00000\0" \
+ "initrd_name=ramdisk.img\0" \
+ "initrd_addr=0x84000000\0" \
+ "fdt_name=devtree.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+#define CONFIG_BOOTCOMMAND "echo copy to RAM...; " \
+ "cp.b 0x80100000 $kernel_addr 0xb00000; " \
+ "cp.b 0x80d00000 $initrd_addr 0x800000; " \
+ "bootz $kernel_addr $initrd_addr:0x800000 $fdt_addr"
+
+/* Monitor Command Prompt */
+#define CFG_SYS_FLASH_BASE 0x80000000
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_ADDR 0x0a7c0000
+#define CONFIG_ENV_SECT_SIZE 0x0040000
+
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+#define FLASH_MAX_SECTOR_SI 0x00040000
+#define CONFIG_ENV_IS_IN_FLASH 1
+#endif

7
meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend
View File

@@ -1,12 +1,5 @@
FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
#
# Corstone-500 MACHINE
#
SRC_URI:append:corstone500 = " \
file://0001-armv7-adding-generic-timer-access-through-MMIO.patch \
file://0002-board-arm-add-corstone500-board.patch"
#
# Corstone1000 64-bit machines
#

7
meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc
View File

@@ -19,13 +19,6 @@ SRC_URI:append:juno = " ${SRC_URI_KMETA}"
SRC_URI:append:n1sdp = " ${SRC_URI_KMETA}"
SRCREV:arm-platforms-kmeta = "6147e82375aa9df8f2a162d42ea6406c79c854c5"
#
# Corstone-500 KMACHINE
#
COMPATIBLE_MACHINE:corstone500 = "corstone500"
KBUILD_DEFCONFIG:corstone500 = "multi_v7_defconfig"
KCONFIG_MODE:corstone500 = "--alldefconfig"
#
# Corstone1000 KMACHINE
#

12
meta-arm-bsp/wic/core-image-minimal.corstone500.wks
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@@ -1,12 +0,0 @@
# WIC partitioning for corstone500
# Layout and maximum sizes (to be defined):
#
# Rawcopy of the FIP binary
part --source rawcopy --sourceparams="file=fip.bin" --no-table --align 1 --fixed-size 1
# Rawcopy of the kernel binary
part --source rawcopy --sourceparams="file=zImage" --no-table --fixed-size 12
# Rawcopy of the rootfs
part --source rawcopy --sourceparams="file=${IMGDEPLOYDIR}/core-image-minimal-corstone500.squashfs" --no-table

10
meta-arm/recipes-devtools/fvp/fvp-corstone500.bb
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@@ -1,10 +0,0 @@
require fvp-ecosystem.inc
MODEL = "Corstone-500"
MODEL_CODE = "FVP_Corstone_500"
PV = "11.12.59"
SRC_URI[sha256sum] = "26f0fbb52de2ccdb4c7b40b6f4ddb5eabdcb8173775fdd11c9a12173326f8614"
LIC_FILES_CHKSUM = "file://license_terms/license_agreement.txt;md5=1a33828e132ba71861c11688dbb0bd16 \
file://license_terms/third_party_licenses.txt;md5=47473b1e04b70938cf0a7ffea8ea4cc3"