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arm-bsp/u-boot: corstone1000: Enable secondary cores for Corstone-1000 FVP

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This changeset adds secondary cpu nodes for Corstone-1000 FVP dts.

Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
This commit is contained in:
Harsimran Singh Tungal
2024-06-18 16:27:21 +01:00
committed by Jon Mason
parent 3e13dfa18a
commit c42a7ffd3e
2 changed files with 64 additions and 0 deletions
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1
meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc
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@@ -64,6 +64,7 @@ SRC_URI:append = " \
file://0046-Corstone1000-Change-MMCOMM-buffer-location.patch \
file://0047-corstone1000-dts-add-external-system-node.patch \
file://0048-corstone1000-Enable-UEFI-Secure-boot.patch \
file://0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch \
"
do_configure:append() {

63
meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch Normal file
View File

@@ -0,0 +1,63 @@
From 68708d6b4953f58a0484b9a83efa8318747cea80 Mon Sep 17 00:00:00 2001
From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Date: Thu, 9 May 2024 14:16:55 +0000
Subject: [PATCH] arm: dts: corstone1000: enable secondary cores for FVP
Add the secondary cores nodes in the dts file
Upstream-Status: Submitted [https://lore.kernel.org/all/20240612100421.47938-1-harsimransingh.tungal@arm.com/]
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
---
arch/arm/dts/corstone1000-fvp.dts | 25 +++++++++++++++++++++++++
arch/arm/dts/corstone1000.dtsi | 2 +-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
index 26b0f1b3ce..3076fb9f34 100644
--- a/arch/arm/dts/corstone1000-fvp.dts
+++ b/arch/arm/dts/corstone1000-fvp.dts
@@ -49,3 +49,28 @@
clock-names = "smclk", "apb_pclk";
};
};
+
+&cpus {
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+};
+
diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
index 1e0ec075e4..5d9d95b21c 100644
--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
@@ -21,7 +21,7 @@
stdout-path = "serial0:115200n8";
};
- cpus {
+ cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1