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arm-bsp/scp-firmware: update a patch that is now upstream

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Change-Id: Ibfa8f7d3c0f38fcde514170211264ec02efff953
Signed-off-by: Ross Burton <ross.burton@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Ross Burton
2020-12-15 09:22:31 +00:00
committed by Jon Mason
parent 5b98ef9d65
commit c90cf8ce5a
1 changed files with 14 additions and 21 deletions
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35
meta-arm-bsp/recipes-bsp/scp-firmware/files/n1sdp/0001-product-n1sdp-set-CCIX-speed-to-GEN3-to-work-with-in.patch
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@@ -1,13 +1,9 @@
Upstream-Status: Inappropriate [will not be submitted as its only required till hardware gets fixed]
The patch is picked from git repo:
https://git.linaro.org/landing-teams/working/arm/n1sdp-pcie-quirk.git/tree/scp/0001-product-n1sdp-set-CCIX-speed-to-GEN3-to-work-with-in.patch
Upstream-Status: Backport
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
From a6d545cf9b6c46f2ea415d64fa81eb4771cfb51c Mon Sep 17 00:00:00 2001
From 3deb59c5f4c64aa092bb3a4ebc018acf3f746f47 Mon Sep 17 00:00:00 2001
From: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Date: Thu, 28 May 2020 16:19:12 +0530
Date: Tue, 10 Nov 2020 12:31:04 +0530
Subject: [PATCH] product/n1sdp: set CCIX speed to GEN3 to work with interposer
C2C setup
@@ -15,23 +11,22 @@ Set CCIX speed to GEN3 to work with interposer C2C setup
In this use case set downstream/upstream port transmitter
preset value to 4.
Change-Id: I16e72a5eaa105386a64ab4ffe56f67134c670313
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Change-Id: I635566574babbb7591b5bba97105f76f1f8e550a
---
.../module/n1sdp_pcie/src/mod_n1sdp_pcie.c | 33 +++++++++++++++----
1 file changed, 26 insertions(+), 7 deletions(-)
.../module/n1sdp_pcie/src/mod_n1sdp_pcie.c | 30 ++++++++++++++-----
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c
index 19fa5a5..a93e6cc 100644
index 901e0464..ba02144f 100644
--- a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c
+++ b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c
@@ -206,7 +206,13 @@ static int n1sdp_pcie_phy_init(fwk_id_t id)
@@ -206,7 +206,12 @@ static int n1sdp_pcie_phy_init(fwk_id_t id)
if (dev_ctx == NULL)
return FWK_E_PARAM;
- gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3;
+ if ((n1sdp_get_chipid() != 0x0) ||
+ !dev_ctx->config->ccix_capable ||
+ if ((n1sdp_get_chipid() != 0x0) || !dev_ctx->config->ccix_capable ||
+ pcie_ctx.c2c_api->is_slave_alive())
+ gen_speed = PCIE_GEN_3;
+ else
@@ -40,13 +35,12 @@ index 19fa5a5..a93e6cc 100644
lane_count = LAN_COUNT_IN_X_16;
FWK_LOG_INFO("[%s] Initializing PHY...", pcie_type[did]);
@@ -239,7 +245,13 @@ static int n1sdp_pcie_controller_init(fwk_id_t id, bool ep_mode)
@@ -239,7 +244,12 @@ static int n1sdp_pcie_controller_init(fwk_id_t id, bool ep_mode)
if (dev_ctx == NULL)
return FWK_E_PARAM;
- gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3;
+ if ((n1sdp_get_chipid() != 0x0) ||
+ !dev_ctx->config->ccix_capable ||
+ if ((n1sdp_get_chipid() != 0x0) || !dev_ctx->config->ccix_capable ||
+ pcie_ctx.c2c_api->is_slave_alive())
+ gen_speed = PCIE_GEN_3;
+ else
@@ -55,13 +49,12 @@ index 19fa5a5..a93e6cc 100644
lane_count = LAN_COUNT_IN_X_16;
if (ep_mode) {
@@ -282,12 +294,19 @@ static int n1sdp_pcie_link_training(fwk_id_t id, bool ep_mode)
@@ -282,12 +292,18 @@ static int n1sdp_pcie_link_training(fwk_id_t id, bool ep_mode)
if (dev_ctx == NULL)
return FWK_E_PARAM;
- gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3;
+ if ((n1sdp_get_chipid() != 0x0) ||
+ !dev_ctx->config->ccix_capable ||
+ if ((n1sdp_get_chipid() != 0x0) || !dev_ctx->config->ccix_capable ||
+ pcie_ctx.c2c_api->is_slave_alive()) {
+ gen_speed = PCIE_GEN_3;
+ down_stream_tx_preset = PCIE_RC_TX_PRESET_VALUE;
@@ -81,5 +74,5 @@ index 19fa5a5..a93e6cc 100644
if (gen_speed >= PCIE_GEN_3 && !ep_mode) {
FWK_LOG_INFO(
--
2.25.0
2.25.1