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arm-bsp/trusted-firmware-a: corstone1000: remove TF-A 2.11.0 recipe
Remove TF-A 2.11.0 Yocto recipe. Remove patches that are now upstreamed in TF-A 2.12 Signed-off-by: Clément Faure <clement.faure@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Clément Faure
Jon Mason
@@ -1,32 +0,0 @@
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From d70a07562d3b0a7b4441922fd3ce136565927d04 Mon Sep 17 00:00:00 2001
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From: Emekcan Aras <Emekcan.Aras@arm.com>
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Date: Wed, 21 Feb 2024 07:57:36 +0000
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Subject: [PATCH] fix(corstone1000): pass spsr value explicitly
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Passes spsr value for BL32 (OPTEE) explicitly between different boot
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stages.
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Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30116/2]
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Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
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---
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.../corstone1000/common/corstone1000_bl2_mem_params_desc.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
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index fe521a9fa..2cc096f38 100644
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--- a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
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+++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
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@@ -72,7 +72,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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.ep_info.pc = BL33_BASE,
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-
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+ .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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+ DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = BL33_BASE,
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--
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2.25.1
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@@ -1,92 +0,0 @@
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From 19600e6718e1a5b2ac8ec27d471acdafce0e433e Mon Sep 17 00:00:00 2001
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From: Emekcan Aras <Emekcan.Aras@arm.com>
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Date: Thu, 25 Apr 2024 11:30:58 +0100
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Subject: [PATCH] fix(corstone1000): remove unused NS_SHARED_RAM region
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After enabling additional features in Trusted Services, the size of BL32 image
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(OP-TEE + Trusted Services SPs) is larger now. To create more space in secure RAM
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for BL32 image, this patch removes NS_SHARED_RAM region which is not currently used by
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corstone1000 platform.
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Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
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Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30117/2]
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---
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.../corstone1000/common/corstone1000_plat.c | 1 -
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.../common/include/platform_def.h | 19 +------------------
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2 files changed, 1 insertion(+), 19 deletions(-)
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
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index ed3801caa..a9475859a 100644
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--- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
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+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
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@@ -23,7 +23,6 @@
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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- ARM_MAP_NS_SHARED_RAM,
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ARM_MAP_NS_DRAM1,
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CORSTONE1000_MAP_DEVICE,
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CORSTONE1000_EXTERNAL_FLASH,
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diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
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index 442d187f0..18fce4486 100644
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--- a/plat/arm/board/corstone1000/common/include/platform_def.h
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+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
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@@ -90,9 +90,6 @@
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* partition size: 176 KB
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* content: BL2
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*
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- * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
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- * partition size: 512 KB
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- * content: BL33 (u-boot)
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*/
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/* DDR memory */
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@@ -117,11 +114,7 @@
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/* The remaining Trusted SRAM is used to load the BL images */
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#define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */
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-/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */
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-#define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K)
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-
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#define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \
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- ARM_NS_SHARED_RAM_SIZE - \
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ARM_SHARED_RAM_SIZE)
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#define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */
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@@ -160,11 +153,6 @@
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/* NS memory */
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-/* The last 512KB of the SRAM is allocated as shared memory */
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-#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \
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- (PLAT_ARM_MAX_BL31_SIZE + \
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- PLAT_ARM_MAX_BL32_SIZE))
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-
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#define BL33_BASE ARM_DRAM1_BASE
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#define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/
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#define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
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@@ -266,7 +254,7 @@
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#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
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#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
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-#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE)
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+#define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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@@ -295,11 +283,6 @@
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ARM_SHARED_RAM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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-#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \
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- ARM_NS_SHARED_RAM_BASE, \
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- ARM_NS_SHARED_RAM_SIZE, \
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- MT_MEMORY | MT_RW | MT_NS)
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-
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#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
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ARM_NS_DRAM1_BASE, \
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ARM_NS_DRAM1_SIZE, \
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--
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2.25.1
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@@ -1,46 +0,0 @@
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From 37f92eeb4361626072e690adb3b0bb20db7c2fca Mon Sep 17 00:00:00 2001
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From: Emekcan Aras <Emekcan.Aras@arm.com>
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Date: Wed, 15 May 2024 13:54:51 +0100
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Subject: [PATCH] fix(corstone1000): clean the cache and disable interrupt
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before system reset
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Corstone1000 does not properly clean the cache and disable gic interrupts
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before the reset. This causes a race condition especially in FVP after reset.
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This adds proper sequence before resetting the platform.
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Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
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Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30118/2]
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---
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plat/arm/board/corstone1000/common/corstone1000_pm.c | 9 +++++++++
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1 file changed, 9 insertions(+)
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
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index 4b0a791e7..a52e945bf 100644
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--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
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+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
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@@ -7,6 +7,7 @@
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#include <lib/psci/psci.h>
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#include <plat/arm/common/plat_arm.h>
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#include <platform_def.h>
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+#include <drivers/arm/gicv2.h>
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/*******************************************************************************
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* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
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* platform layer will take care of registering the handlers with PSCI.
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@@ -18,6 +19,14 @@ static void __dead2 corstone1000_system_reset(void)
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uint32_t volatile * const watchdog_ctrl_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_CTRL_REG;
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uint32_t volatile * const watchdog_val_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_VAL_REG;
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+ /* Flush and invalidate data cache */
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+ dcsw_op_all(DCCISW);
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+ /*
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+ * Disable GIC CPU interface to prevent pending interrupt
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+ * from waking up the AP from WFI.
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+ */
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+ gicv2_cpuif_disable();
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+
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*(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL;
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*watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE;
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while (1) {
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--
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2.25.1
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@@ -1,161 +0,0 @@
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From dcc9cf5111c41edc691f007bd97548d96f5efddb Mon Sep 17 00:00:00 2001
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From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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Date: Thu, 9 May 2024 16:59:34 +0000
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Subject: [PATCH] feat(corstone1000): add multicore support for fvp
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This changeset adds the multicore support for the Corstone-1000 FVP.
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It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
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for the secondary cores.
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Upstream-Status: Backport [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/29176]
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Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
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---
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.../common/corstone1000_helpers.S | 26 +++++++++++
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.../corstone1000/common/corstone1000_pm.c | 43 ++++++++++++++++++-
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.../common/include/platform_def.h | 15 ++++++-
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plat/arm/board/corstone1000/platform.mk | 7 +++
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4 files changed, 89 insertions(+), 2 deletions(-)
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
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index cbe27c3b5..90dc4fee6 100644
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--- a/plat/arm/board/corstone1000/common/corstone1000_helpers.S
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+++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
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@@ -21,8 +21,34 @@
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* --------------------------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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+#if defined(CORSTONE1000_FVP_MULTICORE)
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+
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+ /* Calculate the address of our hold entry */
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+ bl plat_my_core_pos
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+ lsl x0, x0, #CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT
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+ mov_imm x2, CORSTONE1000_SECONDARY_CORE_HOLD_BASE
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+
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+ /* Set the wait state for the secondary core */
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+ mov_imm x3, CORSTONE1000_SECONDARY_CORE_STATE_WAIT
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+ str x3, [x2, x0]
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+ dmb ish
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+
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+ /* Poll until the primary core signals to go */
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+poll_mailbox:
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+ ldr x1, [x2, x0]
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+ cmp x1, #CORSTONE1000_SECONDARY_CORE_STATE_WAIT
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+ beq 1f
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+ mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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+ ldr x1, [x0]
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+ br x1
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+1:
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+ wfe
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+ b poll_mailbox
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+#else
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cb_panic:
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b cb_panic
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+#endif
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+
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
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index a52e945bf..979243317 100644
|
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--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
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+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
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@@ -33,10 +33,51 @@ static void __dead2 corstone1000_system_reset(void)
|
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wfi();
|
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}
|
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}
|
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+#if defined(CORSTONE1000_FVP_MULTICORE)
|
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+int corstone1000_validate_ns_entrypoint(uintptr_t entrypoint)
|
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+{
|
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+ /*
|
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+ * Check if the non secure entrypoint lies within the non
|
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+ * secure DRAM.
|
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+ */
|
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+ if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
|
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+ return PSCI_E_SUCCESS;
|
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+ }
|
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+ return PSCI_E_INVALID_ADDRESS;
|
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+}
|
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+
|
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+int corstone1000_pwr_domain_on(u_register_t mpidr)
|
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+{
|
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+ int core_index = plat_core_pos_by_mpidr(mpidr);
|
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+ uint64_t *secondary_core_hold_base = (uint64_t *)CORSTONE1000_SECONDARY_CORE_HOLD_BASE;
|
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|
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+ /* Validate the core index */
|
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+ if ((core_index < 0) || (core_index > PLATFORM_CORE_COUNT)) {
|
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+ return PSCI_E_INVALID_PARAMS;
|
||||
+ }
|
||||
+ secondary_core_hold_base[core_index] = CORSTONE1000_SECONDARY_CORE_STATE_GO;
|
||||
+ dsbish();
|
||||
+ sev();
|
||||
+
|
||||
+ return PSCI_E_SUCCESS;
|
||||
+}
|
||||
+
|
||||
+void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
+{
|
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+ (void)target_state;
|
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+ plat_arm_gic_init();
|
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+}
|
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+#endif
|
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plat_psci_ops_t plat_arm_psci_pm_ops = {
|
||||
+#if defined(CORSTONE1000_FVP_MULTICORE)
|
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+ .pwr_domain_on = corstone1000_pwr_domain_on,
|
||||
+ .pwr_domain_on_finish = corstone1000_pwr_domain_on_finish,
|
||||
+ .validate_ns_entrypoint = corstone1000_validate_ns_entrypoint,
|
||||
+ .system_reset = corstone1000_system_reset,
|
||||
+#else
|
||||
+ .validate_ns_entrypoint = NULL,
|
||||
.system_reset = corstone1000_system_reset,
|
||||
- .validate_ns_entrypoint = NULL
|
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+#endif
|
||||
};
|
||||
|
||||
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
|
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diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
|
||||
index b9a1d43df..c4839ccf3 100644
|
||||
--- a/plat/arm/board/corstone1000/common/include/platform_def.h
|
||||
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
|
||||
@@ -249,7 +249,20 @@
|
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*/
|
||||
#define ARM_LOCAL_STATE_OFF U(2)
|
||||
|
||||
-#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
|
||||
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
|
||||
+
|
||||
+#if defined(CORSTONE1000_FVP_MULTICORE)
|
||||
+/* The secondary core entrypoint address points to bl31_warm_entrypoint
|
||||
+ * and the address size is 8 bytes */
|
||||
+#define CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE UL(0x8)
|
||||
+
|
||||
+#define CORSTONE1000_SECONDARY_CORE_HOLD_BASE (PLAT_ARM_TRUSTED_MAILBOX_BASE + \
|
||||
+ CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE)
|
||||
+#define CORSTONE1000_SECONDARY_CORE_STATE_WAIT ULL(0)
|
||||
+#define CORSTONE1000_SECONDARY_CORE_STATE_GO ULL(1)
|
||||
+#define CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT ULL(3)
|
||||
+#endif
|
||||
+
|
||||
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
|
||||
|
||||
#define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE)
|
||||
diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
|
||||
index fd08803e8..45092ace9 100644
|
||||
--- a/plat/arm/board/corstone1000/platform.mk
|
||||
+++ b/plat/arm/board/corstone1000/platform.mk
|
||||
@@ -31,6 +31,13 @@ override NEED_BL31 := yes
|
||||
NEED_BL32 ?= yes
|
||||
override NEED_BL33 := yes
|
||||
|
||||
+ENABLE_MULTICORE := 0
|
||||
+ifneq ($(filter ${TARGET_PLATFORM}, fvp),)
|
||||
+ifeq (${ENABLE_MULTICORE},1)
|
||||
+$(eval $(call add_define,CORSTONE1000_FVP_MULTICORE))
|
||||
+endif
|
||||
+endif
|
||||
+
|
||||
# Add CORSTONE1000_WITH_BL32 as a preprocessor define (-D option)
|
||||
ifeq (${NEED_BL32},yes)
|
||||
$(eval $(call add_define,CORSTONE1000_WITH_BL32))
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@@ -1,28 +0,0 @@
|
||||
From 8070bf4a89492727b6da3fb7bdec61748eae1d7d Mon Sep 17 00:00:00 2001
|
||||
From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
|
||||
Date: Tue, 2 Jul 2024 12:49:12 +0000
|
||||
Subject: [PATCH] fix(corstone1000): include platform header file
|
||||
|
||||
Include platform.h file in order to remove compiler warnings
|
||||
|
||||
Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/29727]
|
||||
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
|
||||
---
|
||||
plat/arm/board/corstone1000/common/corstone1000_pm.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
|
||||
index 979243317..9babe5b11 100644
|
||||
--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
|
||||
+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <plat/arm/common/plat_arm.h>
|
||||
#include <platform_def.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
+#include <plat/common/platform.h>
|
||||
/*******************************************************************************
|
||||
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
|
||||
* platform layer will take care of registering the handlers with PSCI.
|
||||
--
|
||||
2.34.1
|
||||
|
||||
@@ -5,11 +5,6 @@ COMPATIBLE_MACHINE = "(corstone1000)"
|
||||
FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:"
|
||||
SRC_URI:append = " \
|
||||
file://0001-Fix-FF-A-version-in-SPMC-manifest.patch \
|
||||
file://0002-fix-corstone1000-pass-spsr-value-explicitly.patch \
|
||||
file://0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch \
|
||||
file://0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch \
|
||||
file://0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch \
|
||||
file://0006-feat-corstone1000-include-platform-header-file.patch \
|
||||
"
|
||||
|
||||
TFA_DEBUG = "1"
|
||||
|
||||
@@ -1,20 +0,0 @@
|
||||
require recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc
|
||||
|
||||
# TF-A v2.11.0
|
||||
SRCREV_tfa = "f2735ebccf5173f74c0458736ec526276106097e"
|
||||
SRCBRANCH = "master"
|
||||
|
||||
LIC_FILES_CHKSUM += "file://docs/license.rst;md5=b5fbfdeb6855162dded31fadcd5d4dc5"
|
||||
|
||||
# in TF-A src, docs/getting_started/prerequisites.rst lists the expected version mbedtls
|
||||
# mbedtls-3.6.0
|
||||
SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls;branch=main"
|
||||
SRCREV_mbedtls = "2ca6c285a0dd3f33982dd57299012dacab1ff206"
|
||||
|
||||
LIC_FILES_CHKSUM_MBEDTLS = "file://mbedtls/LICENSE;md5=379d5819937a6c2f1ef1630d341e026d"
|
||||
|
||||
# continue to boot also without TPM
|
||||
SRC_URI += "\
|
||||
file://0001-qemu_measured_boot.c-ignore-TPM-error-and-continue-w.patch \
|
||||
file://0001-fix-zynqmp-handle-secure-SGI-at-EL1-for-OP-TEE.patch \
|
||||
"
|
||||
Reference in New Issue
Block a user