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arm-bsp/trusted-firmware-a: Upgrade Corstone1000 to TF-A v2.10
Upgrades trusted-firmware-a and align with changes in v2.10 for Corstone-1000. Signed-off-by: Emekcan Aras <emekcan.aras@arm.com> Signed-off-by: Delane Brandy <delane.brandy@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Emekcan Aras
Jon Mason
@@ -7,7 +7,7 @@ PREFERRED_VERSION_trusted-firmware-m ?= "1.8.%"
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# TF-A
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TFA_PLATFORM = "corstone1000"
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PREFERRED_VERSION_trusted-firmware-a ?= "2.9.%"
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PREFERRED_VERSION_trusted-firmware-a ?= "2.10.%"
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PREFERRED_VERSION_tf-a-tests ?= "2.8.%"
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TFA_BL2_BINARY = "bl2-corstone1000.bin"
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-162
@@ -1,162 +0,0 @@
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From fa7ab9b40babee29d2aadb267dfce7a96f8989d4 Mon Sep 17 00:00:00 2001
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From: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
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Date: Mon, 9 Jan 2023 13:59:06 +0000
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Subject: [PATCH] feat(corstone1000): bl2 loads fip based on metadata
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Previously bl2 was reading the boot_index directly with a hard coded
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address and then set the fip image spec with fip offsets base based on
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the boot_index value.
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This commit removes this logic and rely on PSA_FWU_SUPPORT
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which reads the fip partition based on the active firmware bank written in
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metadata.
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Note: fip partition contains signature area at the begining. Hence, the fip
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image starts at fip partition + fip signature area size.
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Upstream-Status: Pending
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Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
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---
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bl2/bl2_main.c | 4 +++
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.../corstone1000/common/corstone1000_plat.c | 32 ++++++-------------
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.../common/include/platform_def.h | 12 +++----
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tools/cert_create/Makefile | 4 +--
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tools/fiptool/Makefile | 4 +--
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5 files changed, 24 insertions(+), 32 deletions(-)
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diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
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index ce83692e0ebc..1a9febc007b2 100644
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--- a/bl2/bl2_main.c
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+++ b/bl2/bl2_main.c
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@@ -87,6 +87,10 @@ void bl2_main(void)
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/* Perform remaining generic architectural setup in S-EL1 */
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bl2_arch_setup();
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+#if ARM_GPT_SUPPORT
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+ partition_init(GPT_IMAGE_ID);
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+#endif
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+
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#if PSA_FWU_SUPPORT
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fwu_init();
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#endif /* PSA_FWU_SUPPORT */
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
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index 0235f8b8474c..7f9708a82489 100644
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--- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
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+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
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@@ -33,36 +33,17 @@ const mmap_region_t plat_arm_mmap[] = {
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static void set_fip_image_source(void)
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{
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const struct plat_io_policy *policy;
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- /*
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- * metadata for firmware update is written at 0x0000 offset of the flash.
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- * PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted.
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- * As per firmware update spec, at a given point of time, only one bank
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- * is active. This means, TF-A should boot from the same bank as TF-M.
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- */
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- volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG);
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-
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- if (*boot_bank_flag > 1) {
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- VERBOSE("Boot_bank is set higher than possible values");
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- }
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-
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- VERBOSE("Boot bank flag = %u.\n\r", *boot_bank_flag);
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policy = FCONF_GET_PROPERTY(arm, io_policies, FIP_IMAGE_ID);
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assert(policy != NULL);
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assert(policy->image_spec != 0UL);
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+ /* FIP Partition contains Signature area at the begining which TF-A doesn't expect */
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io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec;
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+ spec->offset += FIP_SIGNATURE_AREA_SIZE;
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+ spec->length -= FIP_SIGNATURE_AREA_SIZE;
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- if ((*boot_bank_flag) == 0) {
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- VERBOSE("Booting from bank 0: fip offset = 0x%lx\n\r",
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- PLAT_ARM_FIP_BASE_BANK0);
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- spec->offset = PLAT_ARM_FIP_BASE_BANK0;
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- } else {
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- VERBOSE("Booting from bank 1: fip offset = 0x%lx\n\r",
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- PLAT_ARM_FIP_BASE_BANK1);
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- spec->offset = PLAT_ARM_FIP_BASE_BANK1;
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- }
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}
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void bl2_platform_setup(void)
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@@ -75,6 +56,13 @@ void bl2_platform_setup(void)
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set_fip_image_source();
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}
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+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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+ u_register_t arg2, u_register_t arg3)
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+{
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+ arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
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+ NOTICE("CS1k: early at bl2_platform_setup\n");
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+}
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+
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/* corstone1000 only has one always-on power domain and there
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* is no power control present
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*/
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diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
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index 584d485f3ea7..0bfab05a482b 100644
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--- a/plat/arm/board/corstone1000/common/include/platform_def.h
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+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
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@@ -173,16 +173,16 @@
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/* NOR Flash */
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-#define PLAT_ARM_BOOT_BANK_FLAG UL(0x08002000)
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-#define PLAT_ARM_FIP_BASE_BANK0 UL(0x081EF000)
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-#define PLAT_ARM_FIP_BASE_BANK1 UL(0x0916F000)
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-#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */
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-
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#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
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#define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */
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+#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */
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-#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE_BANK0
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+#define PLAT_ARM_FLASH_IMAGE_BASE UL(0x08000000)
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#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE
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+#define PLAT_ARM_FIP_OFFSET_IN_GPT (0x86000)
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+
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+/* FIP Information */
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+#define FIP_SIGNATURE_AREA_SIZE (0x1000) /* 4 KB */
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
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index 042e844626bd..45b76a022f91 100644
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--- a/tools/cert_create/Makefile
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+++ b/tools/cert_create/Makefile
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@@ -78,8 +78,8 @@ INC_DIR += -I ./include -I ${PLAT_INCLUDE} -I ${OPENSSL_DIR}/include
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# directory. However, for a local build of OpenSSL, the built binaries are
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# located under the main project directory (i.e.: ${OPENSSL_DIR}, not
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# ${OPENSSL_DIR}/lib/).
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-LIB_DIR := -L ${OPENSSL_DIR}/lib -L ${OPENSSL_DIR}
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-LIB := -lssl -lcrypto
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+LIB_DIR := -L ${OPENSSL_DIR}/lib -L ${OPENSSL_DIR} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS}
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+LIB := -lssl -lcrypto ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS}
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HOSTCC ?= gcc
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diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
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index 2ebee33931ba..dcfd314bee89 100644
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--- a/tools/fiptool/Makefile
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+++ b/tools/fiptool/Makefile
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@@ -39,7 +39,7 @@ HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3)
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# directory. However, for a local build of OpenSSL, the built binaries are
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# located under the main project directory (i.e.: ${OPENSSL_DIR}, not
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# ${OPENSSL_DIR}/lib/).
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-LDLIBS := -L${OPENSSL_DIR}/lib -L${OPENSSL_DIR} -lcrypto
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+LDLIBS := -L${OPENSSL_DIR}/lib -L${OPENSSL_DIR} -lcrypto ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS} ${BUILD_LDFLAGS}
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ifeq (${V},0)
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Q := @
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@@ -47,7 +47,7 @@ else
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Q :=
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endif
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-INCLUDE_PATHS := -I../../include/tools_share -I${OPENSSL_DIR}/include
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+INCLUDE_PATHS := -I../../include/tools_share -I${OPENSSL_DIR}/include ${BUILD_CFLAGS} ${BUILD_CFLAGS} ${BUILD_CFLAGS} ${BUILD_CFLAGS} ${BUILD_CFLAGS} ${BUILD_CFLAGS}
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HOSTCC ?= gcc
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+32
@@ -0,0 +1,32 @@
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From d70a07562d3b0a7b4441922fd3ce136565927d04 Mon Sep 17 00:00:00 2001
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From: Emekcan Aras <Emekcan.Aras@arm.com>
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Date: Wed, 21 Feb 2024 07:57:36 +0000
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Subject: [PATCH] fix(corstone1000): pass spsr value explicitly
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Passes spsr value for BL32 (OPTEE) explicitly between different boot
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stages.
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Upstream-Status: Pending
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Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
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---
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.../corstone1000/common/corstone1000_bl2_mem_params_desc.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
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index fe521a9fa..2cc096f38 100644
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--- a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
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+++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
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@@ -72,7 +72,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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.ep_info.pc = BL33_BASE,
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-
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+ .ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
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+ DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = BL33_BASE,
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--
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2.25.1
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-28
@@ -1,28 +0,0 @@
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From 33078d8ef143e8c79f06399de46dd26e1d53a220 Mon Sep 17 00:00:00 2001
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From: Gauri Sahnan <Gauri.Sahnan@arm.com>
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Date: Tue, 8 Aug 2023 17:16:51 +0100
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Subject: fix(corstone1000): add cpuhelpers to makefile
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Adds cpu_helpers.S to the Makefile to align with the changes in new
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trusted-firmware-a version.
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Signed-off-by: Gauri Sahnan <Gauri.Sahnan@arm.com>
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Upstream-Status: Pending [Not submitted to upstream yet]
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---
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plat/arm/board/corstone1000/platform.mk | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
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index 3edffe087..079e9d6c1 100644
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--- a/plat/arm/board/corstone1000/platform.mk
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+++ b/plat/arm/board/corstone1000/platform.mk
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@@ -43,6 +43,7 @@ BL2_SOURCES += plat/arm/board/corstone1000/common/corstone1000_security.c \
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plat/arm/board/corstone1000/common/corstone1000_err.c \
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plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c \
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lib/utils/mem_region.c \
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+ lib/cpus/aarch64/cpu_helpers.S \
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plat/arm/board/corstone1000/common/corstone1000_helpers.S \
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plat/arm/board/corstone1000/common/corstone1000_plat.c \
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plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \
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--
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2.25.1
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+54
@@ -0,0 +1,54 @@
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From 684b8f88238f522b52eb102485762e02e6b1671a Mon Sep 17 00:00:00 2001
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From: Emekcan Aras <Emekcan.Aras@arm.com>
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Date: Fri, 23 Feb 2024 13:17:59 +0000
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Subject: [PATCH] fix(spmd): remove EL3 interrupt registration
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This configuration should not be done for corstone1000 and similar
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platforms. GICv2 systems only support EL3 interrupts and can have SEL1 component
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as SPMC.
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Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
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Upstream-Status: Inappropriate [Discussions of fixing this in a better way is ongoing in upstream]
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---
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services/std_svc/spmd/spmd_main.c | 24 ------------------------
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1 file changed, 24 deletions(-)
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diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
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index 066571e9b..313f05bf3 100644
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--- a/services/std_svc/spmd/spmd_main.c
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+++ b/services/std_svc/spmd/spmd_main.c
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@@ -580,30 +580,6 @@ static int spmd_spmc_init(void *pm_addr)
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panic();
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}
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- /*
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- * Permit configurations where the SPM resides at S-EL1/2 and upon a
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- * Group0 interrupt triggering while the normal world runs, the
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- * interrupt is routed either through the EHF or directly to the SPMD:
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- *
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- * EL3_EXCEPTION_HANDLING=0: the Group0 interrupt is routed to the SPMD
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- * for handling by spmd_group0_interrupt_handler_nwd.
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- *
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- * EL3_EXCEPTION_HANDLING=1: the Group0 interrupt is routed to the EHF.
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- *
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- */
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-#if (EL3_EXCEPTION_HANDLING == 0)
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- /*
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- * Register an interrupt handler routing Group0 interrupts to SPMD
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- * while the NWd is running.
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- */
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- rc = register_interrupt_type_handler(INTR_TYPE_EL3,
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- spmd_group0_interrupt_handler_nwd,
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- flags);
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- if (rc != 0) {
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- panic();
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- }
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-#endif
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-
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return 0;
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}
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--
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2.25.1
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@@ -5,9 +5,9 @@ COMPATIBLE_MACHINE = "(corstone1000)"
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FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:"
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SRC_URI:append = " \
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file://0001-Fix-FF-A-version-in-SPMC-manifest.patch \
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file://0002-feat-corstone1000-bl2-loads-fip-based-on-metadata.patch \
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file://0003-psci-SMCCC_ARCH_FEATURES-discovery-through-PSCI_FEATURES.patch \
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file://0004-fix-corstone1000-add-cpuhelper-to-makefile.patch \
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file://0002-psci-SMCCC_ARCH_FEATURES-discovery-through-PSCI_FEATURES.patch \
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file://0003-fix-corstone1000-pass-spsr-value-explicitly.patch \
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file://0004-fix-spmd-remove-EL3-interrupt-registration.patch \
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"
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TFA_DEBUG = "1"
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@@ -51,4 +51,5 @@ EXTRA_OEMAKE:append = " \
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ERRATA_A35_855472=1 \
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ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
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BL32=${RECIPE_SYSROOT}/${nonarch_base_libdir}/firmware/tee-pager_v2.bin \
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FVP_USE_GIC_DRIVER=FVP_GICV2 \
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"
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Block a user