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ci,doc,kas,arm-bsp,arm: Remove support for fvp-baser-aemv8r64 machine

Browse Source 
The fvp-baser-aemv8r64 machine will not be actively maintained.

Signed-off-by: Divin Raj <divin.raj@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Divin Raj
2023-09-29 14:26:50 +01:00
committed by Jon Mason
parent 32e06a2328
commit fd13de4f85
48 changed files with 1 additions and 9450 deletions
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8
.gitlab-ci.yml
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@@ -125,14 +125,6 @@ fvp-base:
- TESTING: testimage
- FIRMWARE: edk2
fvp-baser-aemv8r64:
extends: .build
parallel:
matrix:
- TESTING: testimage
tags:
- x86_64
fvps:
extends: .build

7
ci/fvp-baser-aemv8r64.yml
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@@ -1,7 +0,0 @@
header:
version: 14
includes:
- ci/base.yml
- ci/fvp.yml
machine: fvp-baser-aemv8r64

2
documentation/runfvp.md
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@@ -55,7 +55,7 @@ The name of the FVP binary itself, for example `fvp-base` uses `FVP_Base_RevC-2x
The name of the recipe that provides the FVP executable set in `FVP_EXE`, for example `fvp-base` uses `fvp-base-a-aem-native`. This *must* be a `-native` recipe as the binary will be executed on the build host.
There are recipes for common FVPs in meta-arm already, and writing new recipes is trivial. For FVPs which are free to download `fvp-base-a-aem.bb` is a good example. Some FVPs must be downloaded separately as they need an account on Arm's website, `fvp-base-r-aem.bb` is a good example of those.
There are recipes for common FVPs in meta-arm already, and writing new recipes is trivial. For FVPs which are free to download `fvp-base-a-aem.bb` is a good example. Some FVPs must be downloaded separately as they need an account on Arm's website.
If `FVP_PROVIDER` is not set then it is assumed that `FVP_EXE` is installed on the host already.

42
kas/fvp-baser-aemv8r64-bsp.yml
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@@ -1,42 +0,0 @@
header:
version: 9
includes:
- kas/fvp-eula.yml
env:
DISPLAY: ""
distro: poky
machine: fvp-baser-aemv8r64
defaults:
repos:
refspec: master
repos:
meta-arm:
url: https://git.yoctoproject.org/git/meta-arm
path: layers/meta-arm
layers:
meta-arm:
meta-arm-bsp:
meta-arm-toolchain:
poky:
url: https://git.yoctoproject.org/git/poky
path: layers/poky
layers:
meta:
meta-poky:
local_conf_header:
base: |
CONF_VERSION = "2"
PACKAGE_CLASSES = "package_ipk"
PACKAGECONFIG:remove:pn-qemu-system-native = "gtk+ sdl"
EXTRA_IMAGE_FEATURES:append = " debug-tweaks ssh-server-openssh"
CORE_IMAGE_EXTRA_INSTALL:append = " ssh-pregen-hostkeys"
IMAGE_CLASSES:append = " testimage"
target:
- core-image-minimal

8
kas/fvp-baser-aemv8r64-rt-bsp.yml
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@@ -1,8 +0,0 @@
header:
version: 9
includes:
- kas/fvp-baser-aemv8r64-bsp.yml
local_conf_header:
base-rt: |
PREFERRED_PROVIDER_virtual/kernel = "linux-yocto-rt"

66
meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf
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@@ -1,66 +0,0 @@
# Configuration for Fixed Virtual Platform BaseR AEMv8r64 Machine
#@TYPE: Machine
#@NAME: FVP BaseR AEMv8r64 Machine
#@DESCRIPTION: Machine configuration for FVP BaseR AEMv8r64
require conf/machine/include/arm/armv8r/arch-armv8r64.inc
EXTRA_IMAGEDEPENDS += "boot-wrapper-aarch64"
PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto"
PREFERRED_VERSION_u-boot ?= "2023.01"
KERNEL_IMAGETYPE = "Image"
KERNEL_DEVICETREE = "arm/fvp-baser-aemv8r64.dtb"
UBOOT_MACHINE ?= "vexpress_aemv8r_defconfig"
SERIAL_CONSOLES = "115200;ttyAMA0"
IMAGE_CLASSES:append = " fvpboot"
IMAGE_FSTYPES += "wic"
WKS_FILE ?= "efi-disk.wks.in"
EFI_PROVIDER ?= "grub-efi"
MACHINE_FEATURES:append = " efi"
IMAGE_NAME_SUFFIX = ""
# As this is a virtual target that will not be used in the real world there is
# no need for real SSH keys.
MACHINE_EXTRA_RRECOMMENDS += "ssh-pregen-hostkeys"
# testimage configuration
TEST_TARGET = "OEFVPTarget"
TEST_SUITES:append = " fvp_boot fvp_devices"
TEST_TARGET_IP ?= "127.0.0.1:2222"
TEST_SERVER_IP ?= "127.0.1.1"
TEST_FVP_DEVICES ?= "rtc watchdog networking virtiorng cpu_hotplug"
FVP_EXTRA_ARGS = "-a cluster0*=linux-system.axf"
FVP_PROVIDER ?= "fvp-base-r-aem-native"
FVP_EXE ?= "FVP_BaseR_AEMv8R"
FVP_CONSOLE ?= "terminal_0"
# FVP parameters
FVP_CONFIG[bp.exclusive_monitor.monitor_access_level] ?= "2"
FVP_CONFIG[bp.refcounter.non_arch_start_at_default] ?= "1"
FVP_CONFIG[bp.refcounter.use_real_time] ?= "1"
FVP_CONFIG[bp.ve_sysregs.exit_on_shutdown] ?= "1"
FVP_CONFIG[bp.virtio_net.enabled] ?= "1"
FVP_CONFIG[bp.virtio_net.hostbridge.userNetPorts] ?= "2222=22"
FVP_CONFIG[bp.virtio_net.hostbridge.userNetworking] ?= "1"
FVP_CONFIG[bp.virtio_net.secure_accesses] = "1"
FVP_CONFIG[bp.virtio_rng.enabled] ?= "1"
FVP_CONFIG[bp.virtio_rng.secure_accesses] = "1"
FVP_CONFIG[bp.virtioblockdevice.image_path] ?= "${IMAGE_NAME}.wic"
FVP_CONFIG[bp.virtioblockdevice.secure_accesses] = "1"
FVP_CONFIG[cache_state_modelled] ?= "0"
FVP_CONFIG[cci400.force_on_from_start] = "1"
FVP_CONFIG[cluster0.gicv3.cpuintf-mmap-access-level] ?= "2"
FVP_CONFIG[cluster0.gicv3.extended-interrupt-range-support] ?= "1"
FVP_CONFIG[cluster0.gicv3.SRE-EL2-enable-RAO] ?= "1"
FVP_CONFIG[cluster0.gicv3.SRE-enable-action-on-mmap] ?= "2"
FVP_CONFIG[cluster0.has_aarch64] ?= "1"
FVP_CONFIG[gic_distributor.GICD_CTLR-DS-1-means-secure-only] ?= "1"
FVP_CONFIG[gic_distributor.has-two-security-states] ?= "0"

10
meta-arm-bsp/conf/machine/include/arm/armv8r/arch-armv8r64.inc
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@@ -1,10 +0,0 @@
require conf/machine/include/arm/arch-armv8r.inc
TUNE_FEATURES:tune-armv8r =+ "aarch64"
PACKAGE_EXTRA_ARCHS:tune-armv8r =+ "aarch64"
BASE_LIB:tune-armv8r = "lib64"
BASE_LIB:tune-armv8r-crc = "lib64"
BASE_LIB:tune-armv8r-crypto = "lib64"
BASE_LIB:tune-armv8r-simd = "lib64"
BASE_LIB:tune-armv8r-crc-simd = "lib64"
BASE_LIB:tune-armv8r-crc-crypto-simd = "lib64"

264
meta-arm-bsp/documentation/fvp-baser-aemv8r64.md
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@@ -1,264 +0,0 @@
Armv8-R AArch64 AEM FVP Support in meta-arm-bsp
===============================================
Overview
--------
Fixed Virtual Platforms (FVP) are complete simulations of an Arm system,
including processor, memory and peripherals. These are set out in a
"programmer's view", which gives you a comprehensive model on which to build
and test your software.
The Armv8-R AEM FVP is a free of charge Armv8-R Fixed Virtual Platform. It
supports the latest Armv8-R feature set.
This BSP implements a reference stack for the AArch64 support in the R-class
first announced with the Cortex-R82 processor:
https://developer.arm.com/ip-products/processors/cortex-r/cortex-r82
Fast Models Fixed Virtual Platforms (FVP) Reference Guide:
https://developer.arm.com/docs/100966/latest
BSP Support
-----------
The fvp-baser-aemv8r64 Yocto MACHINE supports the following BSP components,
where either a standard or Real-Time Linux kernel (PREEMPT\_RT) can be built
and run:
- FVP_Base_AEMv8R: v11.22.14
- boot-wrapper-aarch64: provides PSCI support
- U-Boot: v2022.07 - provides UEFI services
- Linux kernel: linux-yocto-5.15
- Linux kernel with PREEMPT\_RT support: linux-yocto-rt-5.15
Note that the Real-Time Linux kernel (PREEMPT\_RT) does not use the real-time
architectural extensions of the Armv8-R feature set.
High-Level Architecture
-----------------------
The diagram below shows the current boot flow:
+---------------------------------------------------------------+
| Linux kernel |
+---------------------------------------------------------------+
/|\ /|\
| |
| UEFI services |
| PSCI services |
\|/ |
+----------------+ | S-EL1
----| U-Boot |------------------------------|-----------
+----------------+ | S-EL2
/|\ |
| |
| |
| |
+--------------------------------------------------\|/----------+
| +----------------+ +----------------+ |
| boot-wrapper-aarch64 | Device tree | | PSCI handler | |
| +----------------+ +----------------+ |
+---------------------------------------------------------------+
The firmware binary (generated as `linux-system.axf`) includes
boot-wrapper-aarch64, the flattened device tree and U-Boot. U-Boot is configured
to automatically detect a virtio block device and boot the UEFI payload at the
path `/efi/boot/bootaa64.efi`. Using the standard build, the first partition
contains a Grub image at this path, which boots the Linux kernel at `/Image` on
the same partition. The second partition of the image contains the Linux root
file system.
There is no EL3 or non-secure world in the Armv8-R AArch64 architecture, so the
reset vector starts boot-wrapper-aarch64 at S-EL2. Boot-wrapper-aarch64 is
compiled with the `--enable-keep-el` flag, which causes it to boot U-Boot at
S-EL2 too. U-Boot is compiled with the `CONFIG_ARMV8_SWITCH_TO_EL1` flag, which
causes it to switch to S-EL1 before booting Linux.
The bundled device tree is passed to U-Boot via register x0. U-Boot passes the
same device tree to Linux via the UEFI system table.
Power state management is provided by PSCI services in boot-wrapper-aarch64.
Linux accesses the PSCI handler via HVC calls to S-EL2. U-Boot has been patched
to prevent it from overriding the exception vector at S-EL2. The PSCI handler
memory region is added to a `/memreserve/` node in the device tree.
Please note that the final firmware architecture for the fvp-baser-aemv8r64 is
not yet stabilized. The patches in this layer are provided for development and
evaluation purposes only, and should not be used in production firmware.
Quick start: Howto Build and Run
--------------------------------
### Host environment setup
The following instructions have been tested on hosts running Ubuntu 18.04 and
Ubuntu 20.04.
Install the required packages for the build host:
https://docs.yoctoproject.org/singleindex.html#required-packages-for-the-build-host
Kas is a setup tool for bitbake based projects. The minimal supported version
is 3.0, install it like so:
pip3 install --user --upgrade kas
For more details on kas, see https://kas.readthedocs.io/.
To build the images for the fvp-baser-aemv8r64 machine, you also need to accept
the EULA at
https://developer.arm.com/downloads/-/arm-ecosystem-fvps/eula
by setting the following environment variable:
ARM_FVP_EULA_ACCEPT="True"
**Note:** The host machine should have at least 50 GBytes of free disk space
for the next steps to work correctly.
### Fetch sources
To fetch and build the ongoing development of the software stack follow the
instructions on this document.
To fetch and build the version 1 (single core) find instructions at https://community.arm.com/developer/tools-software/oss-platforms/w/docs/633/release-1-single-core
To fetch and build the version 2 (linux smp) find instructions at https://community.arm.com/developer/tools-software/oss-platforms/w/docs/634/release-2---smp
Fetch the meta-arm repository into a build directory:
mkdir -p ~/fvp-baser-aemv8r64-build
cd ~/fvp-baser-aemv8r64-build
git clone https://git.yoctoproject.org/git/meta-arm
### Build
Building with the standard Linux kernel:
cd ~/fvp-baser-aemv8r64-build
export ARM_FVP_EULA_ACCEPT="True"
kas build meta-arm/kas/fvp-baser-aemv8r64-bsp.yml
Building with the Real-Time Linux kernel (PREEMPT\_RT):
cd ~/fvp-baser-aemv8r64-build
export ARM_FVP_EULA_ACCEPT="True"
kas build meta-arm/kas/fvp-baser-aemv8r64-rt-bsp.yml
### Run
To run an image after the build is done with the standard Linux kernel:
kas shell --keep-config-unchanged \
meta-arm/kas/fvp-baser-aemv8r64-bsp.yml \
--command "../layers/meta-arm/scripts/runfvp \
--console "
To run an image after the build is done with the Real-Time Linux kernel
(PREEMPT\_RT):
kas shell --keep-config-unchanged \
meta-arm/kas/fvp-baser-aemv8r64-rt-bsp.yml \
--command "../layers/meta-arm/scripts/runfvp \
--console "
**Note:** The terminal console login is `root` without password.
To finish the fvp emulation, you need to close the telnet session:
- Escape to telnet console with ``ctrl+]``.
- Run ``quit`` to close the session.
### Networking
The FVP is configured by default to use "user-mode networking", which simulates
an IP router and DHCP server to avoid additional host dependencies and
networking configuration. Outbound connections work automatically, e.g. by
running:
wget www.arm.com
Inbound connections require an explicit port mapping from the host. By default,
port 2222 on the host is mapped to port 22 on the FVP, so that the following
command will connect to an ssh server running on the FVP:
ssh root@localhost -p 2222
Note that user-mode networking does not support ICMP, so `ping` will not work.
For more information about user-mode networking, please see
https://developer.arm.com/documentation/100964/1117/Introduction-to-Fast-Models/User-mode-networking?lang=en
### File sharing between host and fvp
It is possible to share a directory between the host machine and the fvp using
the virtio P9 device component included in the kernel. To do so, create a
directory to be mounted from the host machine:
mkdir /path/to/host-mount-dir
Then, add the following parameter containing the path to the directory when
launching the model:
--parameter 'bp.virtiop9device.root_path=/path/to/host-mount-dir'
e.g. for the standard Linux kernel:
kas shell --keep-config-unchanged \
meta-arm/kas/fvp-baser-aemv8r64-bsp.yml \
--command "../layers/meta-arm/scripts/runfvp \
--console -- --parameter \
'bp.virtiop9device.root_path=/path/to/host-mount-dir'"
Once you are logged into the fvp, the host directory can be mounted in a
directory on the model using the following command:
mount -t 9p -o trans=virtio,version=9p2000.L FM /path/to/fvp-mount-dir
Devices supported in the kernel
-------------------------------
- serial
- virtio 9p
- virtio disk
- virtio network
- virtio rng
- watchdog
- rtc
Known Issues and Limitations
----------------------------
- Only PSCI CPU\_ON and CPU\_OFF functions are supported
- Linux kernel does not support booting from secure EL2 on Armv8-R AArch64
- Linux KVM does not support Armv8-R AArch64
- Device DMA memory cache-coherence issue: the FVP `cache_state_modelled`
parameter will affect the cache coherence behavior of peripherals’ DMA. When
users set `cache_state_modelled=1`, they also have to set
`cci400.force_on_from_start=1` to force the FVP to enable snooping on upstream
ports.
Change Log
----------
- Enabled the ability for U-Boot to apply device tree overlays
- Fixed bug in U-Boot that caused changes to the `memory` node in the device
tree to be ignored.
- Added boot-wrapper-aarch64 support for booting SMP payloads at S-EL2.
- Enabled testimage support by default.
- Added virtio\_rng to improve random number generation.
- Added U-Boot v2022.01 for UEFI support.
- Updated Linux kernel version from 5.14 to 5.15 for both standard and
Real-Time (PREEMPT\_RT) builds.
- Updated boot-wrapper-aarch64 revision and added support for booting U-Boot.
- Included boot-wrapper-aarch64 PSCI services in `/memreserve/` region.
- Fixed the counter frequency initialization in boot-wrapper-aarch64.
- Configured the FVP to use the default RAM size of 4 Gb
- Fixed PL011 and SP805 register sizes in the device tree.
- Added virtio\_net User Networking mode by default and removed instructions
about tap networking setup.
- Updated Linux kernel version from 5.10 to 5.14 for both standard and
Real-Time (PREEMPT\_RT) builds.
- Enabled SMP support via boot-wrapper-aarch64 providing the PSCI CPU\_ON and
CPU\_OFF functions.
- Introduced Armv8-R64 compiler flags.
- Added Linux PREEMPT\_RT support via linux-yocto-rt-5.10.
- Added support for file sharing with the host machine using Virtio P9.
- Added support for runfvp.
- Added performance event support (PMU) in the Linux device tree.
- Introduced the fvp-baser-aemv8r64 machine and its BSP composed of
boot-wrapper-aarch64 and linux-yocto-5.10 supporting serial, virtio disk,
virtio network, watchdog and rtc.

36
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/boot-wrapper-aarch64-fvp-baser-aemv8r64.inc
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@@ -1,36 +0,0 @@
COMPATIBLE_MACHINE = "fvp-baser-aemv8r64"
FILESEXTRAPATHS:prepend := "${THISDIR}/files/${MACHINE}:"
SRC_URI:append = " \
file://0001-aarch64-Rename-labels-and-prepare-for-lower-EL-booti.patch \
file://0002-aarch64-Prepare-for-EL1-booting.patch \
file://0003-aarch64-Prepare-for-lower-EL-booting.patch \
file://0004-gic-v3-Prepare-for-gicv3-with-EL2.patch \
file://0005-aarch64-Prepare-for-booting-with-EL2.patch \
file://0006-aarch64-Introduce-EL2-boot-code-for-Armv8-R-AArch64.patch \
file://0007-Allow-enable-psci-to-choose-between-smc-and-hvc.patch \
file://0008-aarch64-Disable-CNTPCT_EL0-trap-for-v8-R64.patch \
file://0009-lds-Mark-the-mem-range.patch \
file://0010-common-Introduce-the-libfdt.patch \
file://0011-common-Add-essential-libc-functions.patch \
file://0012-Makefile-Add-the-libfdt-to-the-Makefile-system.patch \
file://0013-platform-Add-print_hex-func.patch \
file://0014-common-Add-mem-usage-to-memreserve.patch \
file://0015-boot-Add-the-enable-keep-el-compile-option.patch \
file://0016-Makefile-Change-COUNTER_FREQ-to-100-MHz.patch \
file://0017-PSCI-Apply-flush-cache-after-setting-branch_data.patch \
file://0018-PSCI-Add-function-call-entry-point.patch \
file://0019-lds-Rearrange-and-mark-the-sections.patch \
file://0020-common-Provide-firmware-info-using-libfdt.patch \
file://0021-boot-Enable-firmware-node-initialization.patch \
"
BOOT_WRAPPER_AARCH64_CMDLINE = "\
earlycon console=ttyAMA0 loglevel=8 rootfstype=ext4 root=/dev/vda1 rw"
EXTRA_OECONF += "--enable-psci=hvc --enable-keep-el"
TUNE_CCARGS = ""
BOOT_WRAPPER_AARCH64_KERNEL = "u-boot.bin"
do_deploy[depends] += "u-boot:do_deploy"

4
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/boot-wrapper-aarch64_%.bbappend
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@@ -1,4 +0,0 @@
MACHINE_BOOT_WRAPPER_AARCH64_REQUIRE ?= ""
MACHINE_BOOT_WRAPPER_AARCH64_REQUIRE:fvp-baser-aemv8r64 ?= "boot-wrapper-aarch64-fvp-baser-aemv8r64.inc"
require ${MACHINE_BOOT_WRAPPER_AARCH64_REQUIRE}

135
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0001-aarch64-Rename-labels-and-prepare-for-lower-EL-booti.patch
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@@ -1,135 +0,0 @@
From 545f6950ae4dc55b4974986aa9629adb16eaf4e1 Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 25 May 2021 07:25:00 +0100
Subject: [PATCH] aarch64: Rename labels and prepare for lower EL booting
Prepare for booting from lower EL. Rename *_el3 relavant labels with
*_el_max and *_no_el3 with *_keep_el. Since the original _no_el3 means
"We neither do init sequence at this highest EL nor drop to lower EL
when entering to kernel", we rename it with _keep_el to make it more
clear for lower EL initialisation.
Upstream-Status: Pending
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
---
arch/aarch64/boot.S | 28 ++++++++++++++++++++--------
arch/aarch64/psci.S | 9 +++++----
arch/aarch64/spin.S | 4 ++--
3 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index d682ba5..fab694e 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -34,18 +34,30 @@ ASM_FUNC(_start)
/*
* EL3 initialisation
+ * Boot sequence
+ * If CurrentEL == EL3, then goto EL3 initialisation and drop to
+ * lower EL before entering the kernel.
+ * Else, no initialisation and keep the current EL before
+ * entering the kernel.
*/
mrs x0, CurrentEL
cmp x0, #CURRENTEL_EL3
- b.eq 1f
+ b.eq el3_init
+ /*
+ * We stay in the current EL for entering the kernel
+ */
mov w0, #1
- ldr x1, =flag_no_el3
+ ldr x1, =flag_keep_el
str w0, [x1]
- b start_no_el3
+ b start_keep_el
-1: mov x0, #0x30 // RES1
+ /*
+ * EL3 initialisation
+ */
+el3_init:
+ mov x0, #0x30 // RES1
orr x0, x0, #(1 << 0) // Non-secure EL1
orr x0, x0, #(1 << 8) // HVC enable
@@ -145,7 +157,7 @@ ASM_FUNC(_start)
bl gic_secure_init
- b start_el3
+ b start_el_max
err_invalid_id:
b .
@@ -172,7 +184,7 @@ ASM_FUNC(jump_kernel)
bl find_logical_id
bl setup_stack // Reset stack pointer
- ldr w0, flag_no_el3
+ ldr w0, flag_keep_el
cmp w0, #0 // Prepare Z flag
mov x0, x20
@@ -181,7 +193,7 @@ ASM_FUNC(jump_kernel)
mov x3, x23
b.eq 1f
- br x19 // No EL3
+ br x19 // Keep current EL
1: mov x4, #SPSR_KERNEL
@@ -199,5 +211,5 @@ ASM_FUNC(jump_kernel)
.data
.align 3
-flag_no_el3:
+flag_keep_el:
.long 0
diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S
index 8bd224b..7b8919a 100644
--- a/arch/aarch64/psci.S
+++ b/arch/aarch64/psci.S
@@ -79,7 +79,7 @@ smc_exit:
ldp x18, x19, [sp], #16
eret
-ASM_FUNC(start_el3)
+ASM_FUNC(start_el_max)
ldr x0, =vector
bl setup_vector
@@ -89,10 +89,11 @@ ASM_FUNC(start_el3)
b psci_first_spin
/*
- * This PSCI implementation requires EL3. Without EL3 we'll only boot the
- * primary cpu, all others will be trapped in an infinite loop.
+ * This PSCI implementation requires the highest EL(EL3 or Armv8-R EL2).
+ * Without the highest EL, we'll only boot the primary cpu, all othersr
+ * will be trapped in an infinite loop.
*/
-ASM_FUNC(start_no_el3)
+ASM_FUNC(start_keep_el)
cpuid x0, x1
bl find_logical_id
cbz x0, psci_first_spin
diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S
index 1ea1c0b..bfb1d47 100644
--- a/arch/aarch64/spin.S
+++ b/arch/aarch64/spin.S
@@ -12,8 +12,8 @@
.text
-ASM_FUNC(start_el3)
-ASM_FUNC(start_no_el3)
+ASM_FUNC(start_el_max)
+ASM_FUNC(start_keep_el)
cpuid x0, x1
bl find_logical_id

48
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0002-aarch64-Prepare-for-EL1-booting.patch
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@@ -1,48 +0,0 @@
From bad32d3fc127a421be416b17e4f7d6d514f06abb Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 25 May 2021 07:25:00 +0100
Subject: [PATCH] aarch64: Prepare for EL1 booting
When booting from EL1, add a check and skip the init of
sctlr_el2 in jump_kernel
Upstream-Status: Pending
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
arch/aarch64/boot.S | 6 +++++-
arch/aarch64/include/asm/cpu.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index fab694e..5105b41 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -177,10 +177,14 @@ ASM_FUNC(jump_kernel)
ldr x0, =SCTLR_EL1_KERNEL
msr sctlr_el1, x0
+ mrs x0, CurrentEL
+ cmp x0, #CURRENTEL_EL2
+ b.lt 1f
+
ldr x0, =SCTLR_EL2_KERNEL
msr sctlr_el2, x0
- cpuid x0, x1
+1: cpuid x0, x1
bl find_logical_id
bl setup_stack // Reset stack pointer
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 49d3f86..3767da3 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -11,6 +11,7 @@
#define MPIDR_ID_BITS 0xff00ffffff
+#define CURRENTEL_EL2 (2 << 2)
#define CURRENTEL_EL3 (3 << 2)
/*

55
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0003-aarch64-Prepare-for-lower-EL-booting.patch
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@@ -1,55 +0,0 @@
From 252cbd36e51414b60ab68306f9c38e358709494d Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 25 May 2021 07:25:00 +0100
Subject: [PATCH] aarch64: Prepare for lower EL booting
Save SPSR_KERNEL into spsr_to_elx during el3_init.
The jump_kernel will load spsr_to_elx into spsr_el3.
This change will make it easier to control whether drop to lower EL
before jumping to the kernel.
Upstream-Status: Pending
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
arch/aarch64/boot.S | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index 5105b41..243198d 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -151,7 +151,16 @@ el3_init:
mov x0, #ZCR_EL3_LEN_MAX // SVE: Enable full vector len
msr ZCR_EL3, x0 // for EL2.
-1:
+ /*
+ * Save SPSR_KERNEL into spsr_to_elx.
+ * The jump_kernel will load spsr_to_elx into spsr_el3
+ */
+1: mov w0, #SPSR_KERNEL
+ ldr x1, =spsr_to_elx
+ str w0, [x1]
+ b el_max_init
+
+el_max_init:
ldr x0, =COUNTER_FREQ
msr cntfrq_el0, x0
@@ -199,7 +208,7 @@ ASM_FUNC(jump_kernel)
b.eq 1f
br x19 // Keep current EL
-1: mov x4, #SPSR_KERNEL
+1: ldr w4, spsr_to_elx
/*
* If bit 0 of the kernel address is set, we're entering in AArch32
@@ -217,3 +226,5 @@ ASM_FUNC(jump_kernel)
.align 3
flag_keep_el:
.long 0
+spsr_to_elx:
+ .long 0

105
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0004-gic-v3-Prepare-for-gicv3-with-EL2.patch
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@@ -1,105 +0,0 @@
From bff110a95a5e4c9db2d61e629b4aa4b84530201e Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 25 May 2021 07:25:00 +0100
Subject: [PATCH] gic-v3: Prepare for gicv3 with EL2
This is a preparation for allowing boot-wrapper configuring the gicv3
with EL2.
When confiuring with EL2, since there is no ICC_CTLR_EL2, the
ICC_CTLR_EL3 cannot be replaced with ICC_CTLR_EL2 simply.
See [https://developer.arm.com/documentation/ihi0069/latest/].
As the caller, gic_secure_init expects the ICC_CTLR to be written,
we change the function into gic_init_icc_ctlr(). In the GIC spec,
the r/w bits in this register ([6:0]) either affect EL3 IRQ routing
(not applicable since no EL3), non-secure IRQ handling (not applicable
since only secure state in Armv8-R aarch64), or are aliased to
ICC_CTLR_EL1 bits.
So, based on this, the new gic_init_icc_ctlr() would be:
When currentEL is EL3, init ICC_CTLR_EL3 as before.
When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET.
Upstream-Status: Pending
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
arch/aarch32/include/asm/gic-v3.h | 7 +++++++
arch/aarch64/include/asm/gic-v3.h | 23 ++++++++++++++++++++---
common/gic-v3.c | 2 +-
3 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
index 65f38de..11e7bc7 100644
--- a/arch/aarch32/include/asm/gic-v3.h
+++ b/arch/aarch32/include/asm/gic-v3.h
@@ -9,6 +9,8 @@
#ifndef __ASM_AARCH32_GICV3_H
#define __ASM_AARCH32_GICV3_H
+#define ICC_CTLR_RESET (0UL)
+
static inline void gic_write_icc_sre(uint32_t val)
{
asm volatile ("mcr p15, 6, %0, c12, c12, 5" : : "r" (val));
@@ -19,4 +21,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));
}
+static inline void gic_init_icc_ctlr()
+{
+ gic_write_icc_ctlr(ICC_CTLR_RESET);
+}
+
#endif
diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
index 5b32380..090ab0b 100644
--- a/arch/aarch64/include/asm/gic-v3.h
+++ b/arch/aarch64/include/asm/gic-v3.h
@@ -15,14 +15,31 @@
#define ICC_CTLR_EL3 "S3_6_C12_C12_4"
#define ICC_PMR_EL1 "S3_0_C4_C6_0"
+#define ICC_CTLR_EL3_RESET (0UL)
+#define ICC_CTLR_EL1_RESET (0UL)
+
+static inline uint32_t current_el(void)
+{
+ uint32_t val;
+
+ asm volatile ("mrs %0, CurrentEL" : "=r" (val));
+ return val;
+}
+
static inline void gic_write_icc_sre(uint32_t val)
{
- asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
+ if (current_el() == CURRENTEL_EL3)
+ asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
+ else
+ asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
}
-static inline void gic_write_icc_ctlr(uint32_t val)
+static inline void gic_init_icc_ctlr()
{
- asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
+ if (current_el() == CURRENTEL_EL3)
+ asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (ICC_CTLR_EL3_RESET));
+ else
+ asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (ICC_CTLR_EL1_RESET));
}
#endif
diff --git a/common/gic-v3.c b/common/gic-v3.c
index 6207007..a0fe564 100644
--- a/common/gic-v3.c
+++ b/common/gic-v3.c
@@ -117,6 +117,6 @@ void gic_secure_init(void)
gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE);
isb();
- gic_write_icc_ctlr(0);
+ gic_init_icc_ctlr();
isb();
}

63
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0005-aarch64-Prepare-for-booting-with-EL2.patch
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@@ -1,63 +0,0 @@
From ba955efb35ce1d41b562190d7c2fbcbcf8ef97ff Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 25 May 2021 07:25:00 +0100
Subject: [PATCH] aarch64: Prepare for booting with EL2
Prepare for allowing boot-wrapper to be entered in EL2.
Detect current EL and set the corresponding EL registers.
Upstream-Status: Pending
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
arch/aarch64/boot.S | 8 ++++++++
arch/aarch64/utils.S | 10 +++++++++-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index 243198d..3593ca5 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -216,10 +216,18 @@ ASM_FUNC(jump_kernel)
*/
bfi x4, x19, #5, #1
+ mrs x5, CurrentEL
+ cmp x5, #CURRENTEL_EL2
+ b.eq 1f
+
msr elr_el3, x19
msr spsr_el3, x4
eret
+1: msr elr_el2, x19
+ msr spsr_el2, x4
+ eret
+
.ltorg
.data
diff --git a/arch/aarch64/utils.S b/arch/aarch64/utils.S
index 85c7f8a..f02a249 100644
--- a/arch/aarch64/utils.S
+++ b/arch/aarch64/utils.S
@@ -34,10 +34,18 @@ ASM_FUNC(find_logical_id)
ret
/*
- * Setup EL3 vectors
+ * Setup EL3/EL2 vectors
* x0: vector address
*/
ASM_FUNC(setup_vector)
+ mrs x1, CurrentEL
+ cmp x1, #CURRENTEL_EL2
+ b.eq 1f
+
msr VBAR_EL3, x0
isb
ret
+
+1: msr VBAR_EL2, x0
+ isb
+ ret

182
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0006-aarch64-Introduce-EL2-boot-code-for-Armv8-R-AArch64.patch
View File

@@ -1,182 +0,0 @@
From 8e44fac113d935affed1550480631f3fe7f30584 Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 25 May 2021 07:25:00 +0100
Subject: [PATCH] aarch64: Introduce EL2 boot code for Armv8-R AArch64
The Armv8-R AArch64 profile does not support the EL3 exception level.
The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU
at EL1, which allows to run off-the-shelf Linux. However EL2 only
supports a PMSA, which is not supported by Linux, so we need to drop
into EL1 before entering the kernel.
We add a new err_invalid_arch symbol as a dead loop. If we detect the
current Armv8-R aarch64 only supports with PMSA, meaning we cannot boot
Linux anymore, then we jump to err_invalid_arch.
During Armv8-R aarch64 init, to make sure nothing unexpected traps into
EL2, we auto-detect and config FIEN and EnSCXT in HCR_EL2.
The boot sequence is:
If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
before entering the kernel.
If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64),
if id_aa64mmfr0_el1.MSA_frac == 0x2,
then goto Armv8-R AArch64 initialisation and drop to EL1 before
entering the kernel.
else, which means VMSA unsupported and cannot boot Linux,
goto err_invalid_arch (dead loop).
Else, no initialisation and keep the current EL before entering the
kernel.
Upstream-Status: Pending
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
---
arch/aarch64/boot.S | 92 +++++++++++++++++++++++++++++++++-
arch/aarch64/include/asm/cpu.h | 2 +
2 files changed, 92 insertions(+), 2 deletions(-)
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index 3593ca5..a219ea7 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -37,16 +37,24 @@ ASM_FUNC(_start)
* Boot sequence
* If CurrentEL == EL3, then goto EL3 initialisation and drop to
* lower EL before entering the kernel.
+ * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf, then
+ * If id_aa64mmfr0_el1.MSA_frac == 0x2, then goto
+ * Armv8-R AArch64 initialisation and drop to EL1 before
+ * entering the kernel.
+ * Else, which means VMSA unsupported and cannot boot Linux,
+ * goto err_invalid_arch (dead loop).
* Else, no initialisation and keep the current EL before
* entering the kernel.
*/
mrs x0, CurrentEL
- cmp x0, #CURRENTEL_EL3
- b.eq el3_init
+ cmp x0, #CURRENTEL_EL2
+ bgt el3_init
+ beq el2_init
/*
* We stay in the current EL for entering the kernel
*/
+keep_el:
mov w0, #1
ldr x1, =flag_keep_el
str w0, [x1]
@@ -160,6 +168,85 @@ el3_init:
str w0, [x1]
b el_max_init
+ /*
+ * EL2 Armv8-R AArch64 initialisation
+ */
+el2_init:
+ /* Detect Armv8-R AArch64 */
+ mrs x1, id_aa64mmfr0_el1
+ /*
+ * Check MSA, bits [51:48]:
+ * 0xf means Armv8-R AArch64.
+ * If not 0xf, proceed in Armv8-A EL2.
+ */
+ ubfx x0, x1, #48, #4 // MSA
+ cmp x0, 0xf
+ bne keep_el
+ /*
+ * Check MSA_frac, bits [55:52]:
+ * 0x2 means EL1&0 translation regime also supports VMSAv8-64.
+ */
+ ubfx x0, x1, #52, #4 // MSA_frac
+ cmp x0, 0x2
+ /*
+ * If not 0x2, no VMSA, so cannot boot Linux and dead loop.
+ * Also, since the architecture guarantees that those CPUID
+ * fields never lose features when the value in a field
+ * increases, we use blt to cover it.
+ */
+ blt err_invalid_arch
+
+ mrs x0, midr_el1
+ msr vpidr_el2, x0
+
+ mrs x0, mpidr_el1
+ msr vmpidr_el2, x0
+
+ mov x0, #(1 << 31) // VTCR_MSA: VMSAv8-64 support
+ msr vtcr_el2, x0
+
+ /* Init HCR_EL2 */
+ mov x0, #(1 << 31) // RES1: Armv8-R aarch64 only
+
+ mrs x1, id_aa64pfr0_el1
+ ubfx x2, x1, #56, 4 // ID_AA64PFR0_EL1.CSV2
+ cmp x2, 0x2
+ b.lt 1f
+ /*
+ * Disable trap when accessing SCTXNUM_EL0 or SCTXNUM_EL1
+ * if FEAT_CSV2.
+ */
+ orr x0, x0, #(1 << 53) // HCR_EL2.EnSCXT
+
+1: ubfx x2, x1, #28, 4 // ID_AA64PFR0_EL1.RAS
+ cmp x2, 0x2
+ b.lt 1f
+ /* Disable trap when accessing ERXPFGCDN_EL1 if FEAT_RASv1p1. */
+ orr x0, x0, #(1 << 47) // HCR_EL2.FIEN
+
+ /* Enable pointer authentication if present */
+1: mrs x1, id_aa64isar1_el1
+ /*
+ * If ID_AA64ISAR1_EL1.{GPI, GPA, API, APA} == {0000, 0000, 0000, 0000}
+ * then HCR_EL2.APK and HCR_EL2.API are RES 0.
+ * Else
+ * set HCR_EL2.APK and HCR_EL2.API.
+ */
+ ldr x2, =(((0xff) << 24) | (0xff << 4))
+ and x1, x1, x2
+ cbz x1, 1f
+
+ orr x0, x0, #(1 << 40) // HCR_EL2.APK
+ orr x0, x0, #(1 << 41) // HCR_EL2.API
+
+1: msr hcr_el2, x0
+ isb
+
+ mov w0, #SPSR_KERNEL_EL1
+ ldr x1, =spsr_to_elx
+ str w0, [x1]
+ // fall through
+
el_max_init:
ldr x0, =COUNTER_FREQ
msr cntfrq_el0, x0
@@ -169,6 +256,7 @@ el_max_init:
b start_el_max
err_invalid_id:
+err_invalid_arch:
b .
/*
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 3767da3..3c0e00d 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -25,6 +25,7 @@
#define SPSR_I (1 << 7) /* IRQ masked */
#define SPSR_F (1 << 6) /* FIQ masked */
#define SPSR_T (1 << 5) /* Thumb */
+#define SPSR_EL1H (5 << 0) /* EL1 Handler mode */
#define SPSR_EL2H (9 << 0) /* EL2 Handler mode */
#define SPSR_HYP (0x1a << 0) /* M[3:0] = hyp, M[4] = AArch32 */
@@ -50,6 +51,7 @@
#else
#define SCTLR_EL1_KERNEL SCTLR_EL1_RES1
#define SPSR_KERNEL (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H)
+#define SPSR_KERNEL_EL1 (SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H)
#endif
#ifndef __ASSEMBLY__

89
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0007-Allow-enable-psci-to-choose-between-smc-and-hvc.patch
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@@ -1,89 +0,0 @@
From 0b9a966b8a28961b078215ee7169e32a976d5e7d Mon Sep 17 00:00:00 2001
From: Qi Feng <qi.feng@arm.com>
Date: Wed, 26 May 2021 17:52:01 +0800
Subject: [PATCH] Allow --enable-psci to choose between smc and hvc
According to Armv8-R AArch64 manual [1], Armv8-R AArch64 does not
support smc:
- Pseudocode for AArch64.CheckForSMCUndefOrTrap has this snippet:
if !HaveEL(EL3) || PSTATE.EL == EL0 then
UNDEFINED;
And Armv8-R AArch64 does not have EL3.
- In the document of HCR_EL2 TSC bit:
If EL3 is not implemented and HCR_EL2.NV is 0, it is IMPLEMENTATION
DEFINED whether this bit is:
- RES0.
- Implemented with the functionality as described in HCR_EL2.TSC.
So hvc is needed in this situation. And due to the lack of libfdt, the
psci method cannot be modified at runtime.
To use smc, use --enable-psci or --enable-psci=smc.
To use hvc, use --enable-psci=hvc.
[1]: https://developer.arm.com/documentation/ddi0600/latest/
Issue-Id: SCM-2654
Upstream-Status: Pending
Signed-off-by: Qi Feng <qi.feng@arm.com>
Change-Id: Ib8afabdad2d98bc37371d165bbb6f1f9b88bfc87
Upstream-Status: Pending
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
---
Makefile.am | 10 +++++-----
configure.ac | 14 +++++++++-----
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/Makefile.am b/Makefile.am
index 5731a19..fc66662 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -50,11 +50,11 @@ endif
if PSCI
ARCH_OBJ += psci.o
COMMON_OBJ += psci.o
-PSCI_NODE := psci { \
- compatible = \"arm,psci\"; \
- method = \"smc\"; \
- cpu_on = <$(PSCI_CPU_ON)>; \
- cpu_off = <$(PSCI_CPU_OFF)>; \
+PSCI_NODE := psci { \
+ compatible = \"arm,psci\"; \
+ method = \"$(PSCI_METHOD)\"; \
+ cpu_on = <$(PSCI_CPU_ON)>; \
+ cpu_off = <$(PSCI_CPU_OFF)>; \
};
CPU_NODES := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/addpsci.pl $(KERNEL_DTB))
else
diff --git a/configure.ac b/configure.ac
index 9e3b722..53e51be 100644
--- a/configure.ac
+++ b/configure.ac
@@ -83,13 +83,17 @@ AS_IF([test "x$X_IMAGE" != "x"],
# Allow a user to pass --enable-psci
AC_ARG_ENABLE([psci],
AS_HELP_STRING([--disable-psci], [disable the psci boot method]),
- [USE_PSCI=$enableval], [USE_PSCI="yes"])
-AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes"])
-AS_IF([test "x$USE_PSCI" = "xyes"], [], [USE_PSCI=no])
-
-AS_IF([test "x$USE_PSCI" != "xyes" -a "x$KERNEL_ES" = "x32"],
+ [case "${enableval}" in
+ yes|smc) USE_PSCI=smc ;;
+ hvc) USE_PSCI=hvc ;;
+ *) AC_MSG_ERROR([Bad value "${enableval}" for --enable-psci. Use "smc" or "hvc"]) ;;
+ esac], [USE_PSCI="yes"])
+AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes" -o "x$USE_PSCI" = "xsmc" -o "x$USE_PSCI" = "xhvc"])
+
+AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"],
[AC_MSG_ERROR([With an AArch32 kernel, boot method must be PSCI.])]
)
+AC_SUBST([PSCI_METHOD], [$USE_PSCI])
# Allow a user to pass --with-initrd
AC_ARG_WITH([initrd],

48
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0008-aarch64-Disable-CNTPCT_EL0-trap-for-v8-R64.patch
View File

@@ -1,48 +0,0 @@
From 521c121eccb386aca7c75d92528e495546adccec Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Mon, 25 Oct 2021 17:09:13 +0800
Subject: [PATCH] aarch64: Disable CNTPCT_EL0 trap for v8-R64
To allow EL1 to access CNTPCT_EL0 without traping into EL2, we need to
set CNTHCTL_EL2.EL1PCTEN to 1.
For v8-R64, the CNTHCTL_EL2 register follows the v8-A architecture.
However, as described in the v8-A architecture profile, the
CNTHCTL_EL2's bit assignments are different according to whether the
FEAT_VHE is implemented.
Since v8-R64 does not support FEAT_VHE, we do not need to detect
FEAT_VHE. We can simply set CNTHCTL_EL2.EL1PCTEN to 1.
Issue-ID: SCM-3508
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: I4147e66341c8153312021e6f2ab67d0037246da1
---
arch/aarch64/boot.S | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index a219ea7..27b1139 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -240,6 +240,18 @@ el2_init:
orr x0, x0, #(1 << 41) // HCR_EL2.API
1: msr hcr_el2, x0
+
+ /*
+ * To disable trap when accessing CNTPCT_EL0, we need to set
+ * CNTHCTL_EL2.EL1PCTEN to 1. However, the CNTHCTL_EL2 bit assignments
+ * are different according to whether the FEAT_VHE is implemented.
+ *
+ * For Armv8-R AArch64, FEAT_VHE is not supported, so we do not need to
+ * detect FEAT_VHE(ID_AA64MMFR1_EL1.VH) and simply set
+ * CNTHCTL_EL2.EL1PCTEN to 1.
+ */
+ mov x0, #1 // CNTHCTL_EL2.EL1PCTEN
+ msr cnthctl_el2, x0
isb
mov w0, #SPSR_KERNEL_EL1

38
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0009-lds-Mark-the-mem-range.patch
View File

@@ -1,38 +0,0 @@
From 780df234d98db81485b1f351f902a68def35c9d4 Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 2 Nov 2021 15:10:28 +0800
Subject: [PATCH] lds: Mark the mem range
Add firmware_start and firmware_end, so that we can use them to
calculate the mem range of boot-wrapper and then set the range to
/memreserve/ of dtb.
Issue-ID: SCM-3815
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: Idc5a2894e193c75381049a0f359b4b2a51c567ee
---
model.lds.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/model.lds.S b/model.lds.S
index d4e7e13..ab98ddf 100644
--- a/model.lds.S
+++ b/model.lds.S
@@ -64,6 +64,7 @@ SECTIONS
#endif
.boot PHYS_OFFSET: {
+ PROVIDE(firmware_start = .);
*(.init)
*(.text*)
*(.data* .rodata* .bss* COMMON)
@@ -76,6 +77,7 @@ SECTIONS
mbox = .;
QUAD(0x0)
}
+ PROVIDE(firmware_end = .);
ASSERT(etext <= (PHYS_OFFSET + TEXT_LIMIT), ".text overflow!")
}

6044
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0010-common-Introduce-the-libfdt.patch
View File

File diff suppressed because it is too large Load Diff

101
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0011-common-Add-essential-libc-functions.patch
View File

@@ -1,101 +0,0 @@
From e2eff4f80e65cb3fcbe6345b5376a6bf7de7e2cc Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 28 Dec 2021 17:28:25 +0800
Subject: [PATCH] common: Add essential libc functions
The libfdt uses some of the libc functions, e.g. memcmp, memmove,
strlen .etc. Add them in lib.c.
The code is copied from TF-A (v2.5) [1] project, which is under the
terms of BSD license. It is the same with boot-wrapper.
[1]: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
Issue-Id: SCM-3814
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: If3b55b00afa8694c7522df989a41e0b38eda1d38
---
common/lib.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/common/lib.c b/common/lib.c
index fcf5f69..0be1c4a 100644
--- a/common/lib.c
+++ b/common/lib.c
@@ -32,4 +32,73 @@ void *memset(void *s, int c, size_t n)
return s;
}
-/* TODO: memmove and memcmp could also be called */
+int memcmp(const void *s1, const void *s2, size_t len)
+{
+ const unsigned char *s = s1;
+ const unsigned char *d = s2;
+ unsigned char sc;
+ unsigned char dc;
+
+ while (len--) {
+ sc = *s++;
+ dc = *d++;
+ if (sc - dc)
+ return (sc - dc);
+ }
+
+ return 0;
+}
+
+void *memmove(void *dst, const void *src, size_t len)
+{
+ if ((size_t)dst - (size_t)src >= len) {
+ /* destination not in source data, so can safely use memcpy */
+ return memcpy(dst, src, len);
+ } else {
+ /* copy backwards... */
+ const char *end = dst;
+ const char *s = (const char *)src + len;
+ char *d = (char *)dst + len;
+ while (d != end)
+ *--d = *--s;
+ }
+ return dst;
+}
+
+void *memchr(const void *src, int c, size_t len)
+{
+ const unsigned char *s = src;
+
+ while (len--) {
+ if (*s == (unsigned char)c)
+ return (void *) s;
+ s++;
+ }
+
+ return NULL;
+}
+
+char *strrchr(const char *p, int ch)
+{
+ char *save;
+ char c;
+
+ c = ch;
+ for (save = NULL;; ++p) {
+ if (*p == c)
+ save = (char *)p;
+ if (*p == '\0')
+ return (save);
+ }
+ /* NOTREACHED */
+}
+
+size_t strlen(const char *s)
+{
+ const char *cursor = s;
+
+ while (*cursor)
+ cursor++;
+
+ return cursor - s;
+}

61
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0012-Makefile-Add-the-libfdt-to-the-Makefile-system.patch
View File

@@ -1,61 +0,0 @@
From f4d5cf4c3424598a2b3bb391717313b70c79ea28 Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 28 Dec 2021 17:42:48 +0800
Subject: [PATCH] Makefile: Add the libfdt to the Makefile system
Add the libfdt into Makefile system. The libfdt uses const value and
thus gcc will enable the stack guard. The stack guard will fail the
compile. Add -fno-stack-protector to fix it.
Issue-Id: SCM-3814
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: I472bc28cdc5cde3b22461a4b7d7a3752ae382b4b
---
Makefile.am | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/Makefile.am b/Makefile.am
index fc66662..ab2c3a9 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -36,6 +36,9 @@ PSCI_CPU_OFF := 0x84000002
COMMON_SRC := common/
COMMON_OBJ := boot.o bakery_lock.o platform.o lib.o
+LIBFDT_SRC := common/libfdt/
+LIBFDT_OBJS := fdt.o fdt_ro.o fdt_rw.o
+
ARCH_OBJ := boot.o stack.o utils.o
if BOOTWRAPPER_32
@@ -127,11 +130,12 @@ CFLAGS += -I$(top_srcdir)/include/ -I$(top_srcdir)/$(ARCH_SRC)/include/
CFLAGS += -Wall -fomit-frame-pointer
CFLAGS += -ffreestanding -nostdlib
CFLAGS += -fno-stack-protector
+CFLAGS += -fno-stack-protector
CFLAGS += -ffunction-sections -fdata-sections
CFLAGS += -fno-pic -fno-pie
LDFLAGS += --gc-sections
-OBJ := $(addprefix $(ARCH_SRC),$(ARCH_OBJ)) $(addprefix $(COMMON_SRC),$(COMMON_OBJ))
+OBJ := $(addprefix $(ARCH_SRC),$(ARCH_OBJ)) $(addprefix $(COMMON_SRC),$(COMMON_OBJ)) $(addprefix $(LIBFDT_SRC),$(LIBFDT_OBJS))
# Don't lookup all prerequisites in $(top_srcdir), only the source files. When
# building outside the source tree $(ARCH_SRC) needs to be created.
@@ -152,10 +156,13 @@ $(ARCH_SRC):
$(COMMON_SRC):
$(MKDIR_P) $@
+$(LIBFDT_SRC):
+ $(MKDIR_P) $@
+
%.o: %.S Makefile | $(ARCH_SRC)
$(CC) $(CPPFLAGS) -D__ASSEMBLY__ $(CFLAGS) $(DEFINES) -c -o $@ $<
-%.o: %.c Makefile | $(COMMON_SRC)
+%.o: %.c Makefile | $(COMMON_SRC) $(LIBFDT_SRC)
$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c -o $@ $<
model.lds: $(LD_SCRIPT) Makefile

67
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0013-platform-Add-print_hex-func.patch
View File

@@ -1,67 +0,0 @@
From f0ece5e8cac761a76a86df7204bae7c6ef09215f Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Wed, 29 Dec 2021 10:50:21 +0800
Subject: [PATCH] platform: Add print_hex func
Refine the print functions, and add a new print_hex func to print hex
numbers.
Issue-Id: SCM-3814
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: Ic960345d9ef0b41d81d30c4a4dbd9c31139907c4
---
common/platform.c | 33 +++++++++++++++++++++++++--------
1 file changed, 25 insertions(+), 8 deletions(-)
diff --git a/common/platform.c b/common/platform.c
index d11f568..8269392 100644
--- a/common/platform.c
+++ b/common/platform.c
@@ -30,20 +30,37 @@
#define V2M_SYS(reg) ((void *)SYSREGS_BASE + V2M_SYS_##reg)
#endif
-static void print_string(const char *str)
+static void print_char(const char c)
{
uint32_t flags;
+ do {
+ flags = raw_readl(PL011(UARTFR));
+ } while (flags & PL011_UARTFR_FIFO_FULL);
+ raw_writel(c, PL011(UARTDR));
+
+ do {
+ flags = raw_readl(PL011(UARTFR));
+ } while (flags & PL011_UARTFR_BUSY);
+}
+
+void print_string(const char *str)
+{
while (*str) {
- do
- flags = raw_readl(PL011(UARTFR));
- while (flags & PL011_UARTFR_FIFO_FULL);
+ print_char(*str++);
+ }
+}
- raw_writel(*str++, PL011(UARTDR));
+#define HEX_CHARS_PER_INT (2 * sizeof(int))
+
+void print_hex(unsigned int val)
+{
- do
- flags = raw_readl(PL011(UARTFR));
- while (flags & PL011_UARTFR_BUSY);
+ const char hex_chars[16] = "0123456789abcdef";
+ int i;
+ for (i = HEX_CHARS_PER_INT - 1; i >= 0; i--) {
+ int v = (val >> (4 * i)) & 0xf;
+ print_char(hex_chars[v]);
}
}

96
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0014-common-Add-mem-usage-to-memreserve.patch
View File

@@ -1,96 +0,0 @@
From f4704146e1af9f6e0a2220db6b39a328c813fac1 Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Wed, 19 Jan 2022 16:19:02 +0800
Subject: [PATCH] common: Add mem usage to /memreserve/
Set /memreserve/ to prevent next boot stages from overrding PSCI
services with libfdt.
Issue-Id: SCM-3815
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: I2ea80cdf736a910fa2c3deb622e21d50f04be960
---
Makefile.am | 2 +-
common/boot.c | 1 +
common/device_tree.c | 34 ++++++++++++++++++++++++++++++++++
include/boot.h | 1 +
4 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 common/device_tree.c
diff --git a/Makefile.am b/Makefile.am
index ab2c3a9..e905602 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -34,7 +34,7 @@ endif
PSCI_CPU_OFF := 0x84000002
COMMON_SRC := common/
-COMMON_OBJ := boot.o bakery_lock.o platform.o lib.o
+COMMON_OBJ := boot.o bakery_lock.o platform.o lib.o device_tree.o
LIBFDT_SRC := common/libfdt/
LIBFDT_OBJS := fdt.o fdt_ro.o fdt_rw.o
diff --git a/common/boot.c b/common/boot.c
index c74d34c..ee2bea0 100644
--- a/common/boot.c
+++ b/common/boot.c
@@ -63,6 +63,7 @@ void __noreturn first_spin(unsigned int cpu, unsigned long *mbox,
{
if (cpu == 0) {
init_platform();
+ dt_add_memreserve();
*mbox = (unsigned long)&entrypoint;
sevl();
diff --git a/common/device_tree.c b/common/device_tree.c
new file mode 100644
index 0000000..4d0876c
--- /dev/null
+++ b/common/device_tree.c
@@ -0,0 +1,34 @@
+/*
+ * device_tree.c - Basic device tree node handler
+ *
+ * Copyright (C) 2021 ARM Limited. All rights reserved.
+ *
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE.txt file.
+ */
+#include <libfdt.h>
+
+extern unsigned long dtb;
+extern char firmware_start[], firmware_end[];
+
+extern void print_string(const char *str);
+
+static void *blob;
+
+
+void dt_add_memreserve(void)
+{
+ int ret;
+
+ blob = (void*)&dtb;
+ print_string("Add /memreserve/\n\r");
+
+ fdt_open_into(blob, blob, fdt_totalsize(blob) +
+ sizeof(struct fdt_reserve_entry));
+ ret = fdt_add_mem_rsv(blob, (uint64_t)firmware_start,
+ (uint64_t)(firmware_end - firmware_start));
+
+ if(ret < 0) {
+ print_string("reserve mem add err\n\r");
+ }
+}
diff --git a/include/boot.h b/include/boot.h
index d75e013..c3e2ec1 100644
--- a/include/boot.h
+++ b/include/boot.h
@@ -16,4 +16,5 @@ void __noreturn spin(unsigned long *mbox, unsigned long invalid, int is_entry);
void __noreturn first_spin(unsigned int cpu, unsigned long *mbox,
unsigned long invalid_addr);
+void dt_add_memreserve(void);
#endif

102
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0015-boot-Add-the-enable-keep-el-compile-option.patch
View File

@@ -1,102 +0,0 @@
From 5995f83592aea874f5b423538e36675e2204582b Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 4 Jan 2022 17:01:55 +0800
Subject: [PATCH] boot: Add the --enable-keep-el compile option
Add --enable-keep-el compile option to enable boot-wrapper booting next
stage at EL2.
The Armv8R AArch64 boots at EL2. If the next stage requires EL2 booting,
the boot-wrapper should not drop to EL1.
Currently, this option only works for Armv8R AArch64. Also, to work with
Linux PSCI, this option will cause secondary cores booting at EL1.
Issue-Id: SCM-3813
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: I3ba9c87cf0b59d163ca433f74c9e3a46e5ca2c63
---
Makefile.am | 4 ++++
arch/aarch64/boot.S | 6 +++++-
common/psci.c | 6 ++++++
configure.ac | 5 +++++
4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/Makefile.am b/Makefile.am
index e905602..6604baa 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -33,6 +33,10 @@ PSCI_CPU_ON := 0xc4000003
endif
PSCI_CPU_OFF := 0x84000002
+if KEEP_EL
+DEFINES += -DKEEP_EL
+endif
+
COMMON_SRC := common/
COMMON_OBJ := boot.o bakery_lock.o platform.o lib.o device_tree.o
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index 27b1139..c079d22 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -254,7 +254,11 @@ el2_init:
msr cnthctl_el2, x0
isb
+#ifdef KEEP_EL
+ mov w0, #SPSR_KERNEL
+#else
mov w0, #SPSR_KERNEL_EL1
+#endif
ldr x1, =spsr_to_elx
str w0, [x1]
// fall through
@@ -334,5 +338,5 @@ ASM_FUNC(jump_kernel)
.align 3
flag_keep_el:
.long 0
-spsr_to_elx:
+ASM_DATA(spsr_to_elx)
.long 0
diff --git a/common/psci.c b/common/psci.c
index a0e8700..945780b 100644
--- a/common/psci.c
+++ b/common/psci.c
@@ -18,6 +18,8 @@
#error "No MPIDRs provided"
#endif
+extern unsigned int spsr_to_elx;
+
static unsigned long branch_table[NR_CPUS];
bakery_ticket_t branch_table_lock[NR_CPUS];
@@ -44,6 +46,10 @@ static int psci_cpu_on(unsigned long target_mpidr, unsigned long address)
ret = psci_store_address(cpu, address);
bakery_unlock(branch_table_lock, this_cpu);
+#ifdef KEEP_EL
+ spsr_to_elx = SPSR_KERNEL_EL1;
+#endif
+
return ret;
}
diff --git a/configure.ac b/configure.ac
index 53e51be..0e07db3 100644
--- a/configure.ac
+++ b/configure.ac
@@ -25,6 +25,11 @@ AS_IF([test "x$BOOTWRAPPER_ES" = x32 -a "x$KERNEL_ES" != x32],
[AC_MSG_ERROR([a 32-bit boot-wrapper cannot launch a 64-bit kernel])]
)
+AC_ARG_ENABLE([keep-el],
+ AC_HELP_STRING([--enable-keep-el], [keep exception level when start kernel]),
+ [KEEP_EL=yes], [KEEP_EL=no])
+AM_CONDITIONAL([KEEP_EL], [test "x$KEEP_EL" = xyes])
+
# Allow a user to pass --with-kernel-dir
AC_ARG_WITH([kernel-dir],
AS_HELP_STRING([--with-kernel-dir], [specify the root Linux kernel build directory (required)]),

31
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0016-Makefile-Change-COUNTER_FREQ-to-100-MHz.patch
View File

@@ -1,31 +0,0 @@
From 0c0695cd3160ccdb95bae29b7668918015c0b6aa Mon Sep 17 00:00:00 2001
From: Peter Hoyes <Peter.Hoyes@arm.com>
Date: Tue, 1 Feb 2022 11:28:46 +0000
Subject: [PATCH] Makefile: Change COUNTER_FREQ to 100 MHz
Older Arm Fast Models (AEM < RevC) had a base frequency of 24 MHz. but
the RevC base models use 100 MHz. There is not a robust method of
determining the configured base frequency at runtime, so update
COUNTER_FREQ to be 100 MHz.
Issue-Id: SCM-3871
Upstream-Status: Pending
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Change-Id: Ia9ad0f8ee488d1a887791f1fa1d8f3bf9c5887fd
---
Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile.am b/Makefile.am
index 6604baa..cc6504e 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -13,7 +13,7 @@ SCRIPT_DIR := $(top_srcdir)/scripts
PHYS_OFFSET := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findmem.pl $(KERNEL_DTB))
UART_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,pl011')
SYSREGS_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,vexpress-sysreg' 2> /dev/null)
-COUNTER_FREQ := 24000000
+COUNTER_FREQ := 100000000
CPU_IDS := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findcpuids.pl $(KERNEL_DTB))
NR_CPUS := $(shell echo $(CPU_IDS) | tr ',' ' ' | wc -w)

49
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0017-PSCI-Apply-flush-cache-after-setting-branch_data.patch
View File

@@ -1,49 +0,0 @@
From fa73d885be85eee4369b292ec601e7b024a68807 Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 2 Nov 2021 10:48:39 +0800
Subject: [PATCH] PSCI: Apply flush cache after setting branch_data
For v8-R64, Hypervisor calls boot-wrapper's PSCI service using simple
function call (instead of hvc).
In this case, hypervisor's main core has enabled MPU and cache, but
the secondary cores which are spinning have not enabled cache.
That means if the main core set the branch_data to 1 to boot other
cores, the secondary cores cannot see the change of branch_data and
also cannot break the spin.
Thus, the PSCI service in boot-wrapper needs a cache flush after
setting branch_data in order to let other cores see the change.
Issue-ID: SCM-3816
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: Ifc282091c54d8fb2ffdb8cfa7fd3ffc1f4be717e
---
common/psci.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/common/psci.c b/common/psci.c
index 945780b..6efc695 100644
--- a/common/psci.c
+++ b/common/psci.c
@@ -24,12 +24,18 @@ static unsigned long branch_table[NR_CPUS];
bakery_ticket_t branch_table_lock[NR_CPUS];
+static inline void flush_per_cpu_data(void *data)
+{
+ asm volatile ("dc cvac, %0" : : "r" (data));
+}
+
static int psci_store_address(unsigned int cpu, unsigned long address)
{
if (branch_table[cpu] != PSCI_ADDR_INVALID)
return PSCI_RET_ALREADY_ON;
branch_table[cpu] = address;
+ flush_per_cpu_data((void*)&(branch_table[cpu]));
return PSCI_RET_SUCCESS;
}

71
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0018-PSCI-Add-function-call-entry-point.patch
View File

@@ -1,71 +0,0 @@
From 9da48e3433b919868650cd60e28827273a42c63b Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 25 Jan 2022 14:56:36 +0800
Subject: [PATCH] PSCI: Add function call entry point
The max exception level of Armv8R AArch64 is EL2, which means it has no
exclusive EL for firmware. That is, firmware and hypervisors have to share
the EL2. Also, hypervisors cannot call firmware services via a 'smc'
instruction. Thus, boot-wrapper has to provide a function entry point
for Armv8R AArch64.
Issue-Id: SCM-3816
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: I06ec8e50298603155c6d8ae2330e71db2f111182
---
common/psci.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/common/psci.c b/common/psci.c
index 6efc695..8fdefb5 100644
--- a/common/psci.c
+++ b/common/psci.c
@@ -20,6 +20,8 @@
extern unsigned int spsr_to_elx;
+unsigned long flag_from_smc_fn[NR_CPUS];
+
static unsigned long branch_table[NR_CPUS];
bakery_ticket_t branch_table_lock[NR_CPUS];
@@ -49,12 +51,14 @@ static int psci_cpu_on(unsigned long target_mpidr, unsigned long address)
return PSCI_RET_INVALID_PARAMETERS;
bakery_lock(branch_table_lock, this_cpu);
- ret = psci_store_address(cpu, address);
- bakery_unlock(branch_table_lock, this_cpu);
-
#ifdef KEEP_EL
- spsr_to_elx = SPSR_KERNEL_EL1;
+ if (!flag_from_smc_fn[this_cpu]) {
+ spsr_to_elx = SPSR_KERNEL_EL1;
+ flush_per_cpu_data((void*)&(spsr_to_elx));
+ }
#endif
+ ret = psci_store_address(cpu, address);
+ bakery_unlock(branch_table_lock, this_cpu);
return ret;
}
@@ -90,6 +94,18 @@ long psci_call(unsigned long fid, unsigned long arg1, unsigned long arg2)
}
}
+long smc_fn_entry(unsigned long fid, unsigned long arg1, unsigned long arg2)
+{
+ long ret;
+ unsigned int this_cpu = this_cpu_logical_id();
+
+ flag_from_smc_fn[this_cpu] = 1;
+ ret = psci_call(fid, arg1, arg2);
+ flag_from_smc_fn[this_cpu] = 0;
+
+ return ret;
+}
+
void __noreturn psci_first_spin(unsigned int cpu)
{
if (cpu == MPIDR_INVALID)

58
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0019-lds-Rearrange-and-mark-the-sections.patch
View File

@@ -1,58 +0,0 @@
From 7c5e40d9f8699a55ac2187c035429c643e6d0ef0 Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Tue, 2 Nov 2021 15:10:28 +0800
Subject: [PATCH] lds: Rearrange and mark the sections
To make it possible for the next stage to protect sections with MPU,
boot-wrapper needs to provide the text and data section information.
By rearranging the .data .rodata and .vector sections, all sections
can be split into 2 big sections:
- RO and Executable
- RW and Non-Executable
Add firmware_data to mark the boundry, thus:
firmware_start to firmware_data - 1 indicates RO and Executable section,
firmware_data to firmware_end - 1 indicates RW and Non-Executable
section.
Also, the firmware_data and firmware_end should align with 64 bytes,
since Armv8R AArch64 MPU requires it.
Issue-ID: SCM-3816
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: I55342aa7492f2c7b5c16ab9a6472c8cb45cff8fd
---
model.lds.S | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/model.lds.S b/model.lds.S
index ab98ddf..85451f9 100644
--- a/model.lds.S
+++ b/model.lds.S
@@ -63,12 +63,16 @@ SECTIONS
}
#endif
+#define FIRMWARE_ALIGN . = ALIGN(1 << 6)
.boot PHYS_OFFSET: {
PROVIDE(firmware_start = .);
*(.init)
*(.text*)
- *(.data* .rodata* .bss* COMMON)
*(.vectors)
+ *(.rodata*)
+ FIRMWARE_ALIGN;
+ PROVIDE(firmware_data = .);
+ *(.data* .bss* COMMON)
*(.stack)
PROVIDE(etext = .);
}
@@ -77,6 +81,7 @@ SECTIONS
mbox = .;
QUAD(0x0)
}
+ FIRMWARE_ALIGN;
PROVIDE(firmware_end = .);
ASSERT(etext <= (PHYS_OFFSET + TEXT_LIMIT), ".text overflow!")

342
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0020-common-Provide-firmware-info-using-libfdt.patch
View File

@@ -1,342 +0,0 @@
From 3c1140c29c39561848056fb4b9a03042b00279f3 Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Wed, 29 Dec 2021 15:17:38 +0800
Subject: [PATCH] common: Provide firmware info using libfdt
Boot-wrapper uses libfdt to provide more info in device tree.
We add a new node to include those new firmware relevant infomation.
The new node defined as follows:
fw-shared-info {
compatible = "firmware,shared_info";
#address-cells = <0x02>;
#size-cells = <0x02>;
version = "1.0";
regions = <START_ADDR_HIGH START_ADDR_LOW SIZE_HIGH SIZE_LOW
0x0 0x80000000 0x0 0x400000
0x0 0x90000000 0x0 0x400000
0x0 0xA0000000 0x0 0x400000>;
regions-permission = "RX", "R", "RWX", "RW";
regions-cache = "Cache", "NCache", "Cache", "Device"
function_entry = <ENTRY_ADDR_HIGH ENRTY_ADDR_LOW>;
};
The node path is /fw-shared-info.
For boot-wrapper, in real case, it will be:
fw-shared-info {
compatible = "firmware,shared_info";
#address-cells = <0x02>;
#size-cells = <0x02>;
version = "1.0";
regions = <0x0 firmware_start 0x0 firmware_code_size
0x0 firmware_data 0x0 firmware_data_size>;
regions-permission = "RX", "RW";
regions-cache = "Cache", "Cache";
function_entry = <0x0 smc_fn_entry>;
};
Issue-Id: SCM-3816
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: I6ebc59ce2bd3939b0fe066720d57821eaa1bed27
---
common/device_tree.c | 271 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 270 insertions(+), 1 deletion(-)
diff --git a/common/device_tree.c b/common/device_tree.c
index 4d0876c..7f7befc 100644
--- a/common/device_tree.c
+++ b/common/device_tree.c
@@ -8,13 +8,225 @@
*/
#include <libfdt.h>
+#define DEVICE_TREE_DEBUG 1
+
+#define FW_NODE_NAME "/fw-shared-info"
+#define FW_COMPAT "firmware,shared_info"
+#define FW_INFO_VER "1.0"
+
+#ifdef BOOTWRAPPER_32
+#define CELL_NUM 1
+#define VAL_TYPE uint32_t
+#else
+#define CELL_NUM 2
+#define VAL_TYPE uint64_t
+#endif
+
+#define ALIGN(x) (((x) + (FDT_TAGSIZE) - 1) & ~((FDT_TAGSIZE) - 1))
+
extern unsigned long dtb;
-extern char firmware_start[], firmware_end[];
+extern char firmware_start[], firmware_data[], firmware_end[];
+
+extern long smc_fn_entry(unsigned long, unsigned long, unsigned long);
extern void print_string(const char *str);
+extern void print_hex(unsigned int val);
static void *blob;
+static char *realloc_node(char *fdt, const char *name)
+{
+ int delta;
+ int new_sz;
+ /* FDT_BEGIN_NODE, node name in off_struct and FDT_END_NODE */
+ delta = sizeof(struct fdt_node_header) + ALIGN(strlen(name) + 1)
+ + FDT_TAGSIZE;
+ new_sz = fdt_totalsize(fdt) + delta;
+ fdt_open_into(fdt, fdt, new_sz);
+ return fdt;
+}
+
+static int create_node(const char *node_name)
+{
+ int node = 0;
+ char *p;
+
+ p = strrchr(node_name, '/');
+ if (!p) {
+ print_string("node name without '/'\r\n");
+ return -1;
+ }
+ *p = '\0';
+
+ blob = realloc_node(blob, p + 1);
+
+ if (p > node_name) {
+ node = fdt_path_offset(blob, node_name);
+ if (node < 0) {
+ print_string("no node name\r\n");
+ return -1;
+ }
+ }
+
+ node = fdt_add_subnode(blob, node, p + 1);
+ if (node < 0) {
+ print_string("add subnode err\r\n");
+ return -1;
+ }
+
+ return node;
+}
+
+static int dt_create_fw_node(void) {
+ int fw_node;
+
+ fw_node = fdt_path_offset(blob, FW_NODE_NAME);
+
+ if(fw_node < 0) {
+ fw_node = create_node(FW_NODE_NAME);
+ }
+
+ return fw_node;
+}
+
+static char *realloc_property(char *fdt, int nodeoffset, const char *name,
+ int newlen)
+{
+ int delta = 0;
+ int oldlen = 0;
+ int new_sz;
+
+ if (!fdt_get_property(fdt, nodeoffset, name, &oldlen))
+ delta = sizeof(struct fdt_property) + strlen(name) + 1;
+
+ if (newlen > oldlen)
+ delta += ALIGN(newlen) - ALIGN(oldlen);
+
+ new_sz = fdt_totalsize(fdt) + delta;
+ fdt_open_into(fdt, fdt, new_sz);
+ return fdt;
+}
+
+static void dt_set_prop(int node, char *property, void *buf, int len)
+{
+ int err;
+
+ err = fdt_setprop(blob, node, property, buf, len);
+ if (err == -FDT_ERR_NOSPACE) {
+ blob = realloc_property(blob, node, property, len);
+ err = fdt_setprop(blob, node, property, buf, len);
+ }
+ if (err) {
+ print_string("fdt error\n\r");
+ }
+}
+
+static void dt_set_prop_u32(int node, char *property, uint32_t val)
+{
+ fdt32_t fdt_val = cpu_to_fdt32(val);
+ int len = sizeof(fdt32_t);
+
+ dt_set_prop(node, property, (void*)&fdt_val, len);
+}
+
+static void dt_set_prop_u64(int node, char *property, uint64_t val)
+{
+ fdt64_t fdt_val = cpu_to_fdt64(val);
+ int len = sizeof(fdt64_t);
+
+ dt_set_prop(node, property, (void*)&fdt_val, len);
+}
+
+/* This dt_set_prop_u32_array maybe unused according to the BOOTWRAPPER_32 */
+__attribute__((unused))
+static void dt_set_prop_u32_array(int node, char *property, uint32_t *vals,
+ int size)
+{
+ fdt32_t *fdt_vals = (fdt32_t*)vals;
+ int len = sizeof(fdt32_t) * size;
+
+ for (int i = 0; i < size; i++) {
+ fdt_vals[i] = cpu_to_fdt32(vals[i]);
+ }
+
+ dt_set_prop(node, property, (void*)fdt_vals, len);
+}
+
+static void dt_set_prop_u64_array(int node, char *property, uint64_t *vals,
+ int size)
+{
+ fdt64_t *fdt_vals = (fdt64_t*)vals;
+ int len = sizeof(fdt64_t) * size;
+
+ for (int i = 0; i < size; i++) {
+ fdt_vals[i] = cpu_to_fdt64(vals[i]);
+ }
+
+ dt_set_prop(node, property, (void*)fdt_vals, len);
+}
+
+#if DEVICE_TREE_DEBUG
+static void dt_dump_string(const void *s, int len)
+{
+ char *sub = (char*)s;
+ int sublen;
+ while(*sub && ((uint64_t)sub - (uint64_t)s) < len) {
+ sublen = strlen(sub) + 1;
+ print_string(sub);
+ print_string(" ");
+ sub += sublen;
+ }
+ print_string("\n\r");
+}
+
+static void dt_dump_fdt32_array(const void *vals, int len)
+{
+ fdt32_t *fdt_vals = (fdt32_t*)vals;
+ len = len / sizeof(fdt32_t);
+ for (int i = 0; i < len; i++) {
+ print_hex(fdt32_to_cpu(fdt_vals[i]));
+ print_string(" ");
+ }
+ print_string("\n\r");
+}
+
+static void dt_dump(int node, char *property, char type)
+{
+ const void *val;
+ int len;
+
+ val = fdt_getprop(blob, node, property, &len);
+ print_string(property);
+ print_string(": ");
+
+ if (type == 's') {
+ /* string type */
+ dt_dump_string(val, len);
+ return;
+ }
+
+ /* uint type */
+ dt_dump_fdt32_array(val, len);
+}
+
+void dt_dump_all(int node)
+{
+ if (node >= 0) {
+ print_string(FW_NODE_NAME" info:\r\n");
+ dt_dump(node, "compatible", 's');
+ dt_dump(node, "version", 's');
+ dt_dump(node, "function_entry", 'i');
+ dt_dump(node, "address-cells", 'i');
+ dt_dump(node, "size-cells", 'i');
+ dt_dump(node, "regions", 'i');
+ dt_dump(node, "regions-permission", 's');
+ dt_dump(node, "regions-cache", 's');
+ print_string("\r\n");
+ }
+}
+#else
+void dt_dump_all(int node) { (void*)node; return; }
+#endif
void dt_add_memreserve(void)
{
@@ -32,3 +244,60 @@ void dt_add_memreserve(void)
print_string("reserve mem add err\n\r");
}
}
+
+void dt_fw_node_init(int enable)
+{
+ int fw_node;
+
+ VAL_TYPE regions[] = {
+ /* code region: start, end, ro, x, cachable */
+ (VAL_TYPE)firmware_start,
+ (VAL_TYPE)(firmware_data - firmware_start),
+ /* data region: start, end, rw, xn, cachable */
+ (VAL_TYPE)firmware_data,
+ (VAL_TYPE)(firmware_end - firmware_data),
+ };
+ int regions_num = sizeof(regions) / sizeof(VAL_TYPE);
+ char regions_permission[] = "RX\0RW";
+ char regions_cache[] = "Cache\0Cache";
+
+ if (!enable)
+ return;
+
+ print_string("Prepare "FW_NODE_NAME" node\n\r");
+
+ blob = (void*)&dtb;
+
+ if(fdt_path_offset(blob, "/psci") < 0) {
+ print_string("/psci node not found\n\r");
+ return;
+ }
+
+ fw_node = dt_create_fw_node();
+
+ if(fw_node < 0) {
+ print_string(FW_NODE_NAME" node create err\n\r");
+ }
+
+ dt_set_prop(fw_node, "compatible", FW_COMPAT, sizeof(FW_COMPAT));
+ dt_set_prop(fw_node, "version", FW_INFO_VER, sizeof(FW_INFO_VER));
+
+ dt_set_prop_u32(fw_node, "address-cells", CELL_NUM);
+ dt_set_prop_u32(fw_node, "size-cells", CELL_NUM);
+ dt_set_prop(fw_node, "regions-permission", regions_permission,
+ sizeof(regions_permission));
+ dt_set_prop(fw_node, "regions-cache", regions_cache,
+ sizeof(regions_cache));
+
+#ifdef BOOTWRAPPER_32
+ dt_set_prop_u32_array(fw_node, "regions", regions, regions_num);
+ dt_set_prop_u32(fw_node, "function_entry", (VAL_TYPE)smc_fn_entry);
+#else
+ dt_set_prop_u64_array(fw_node, "regions", regions, regions_num);
+ dt_set_prop_u64(fw_node, "function_entry", (VAL_TYPE)smc_fn_entry);
+#endif
+
+ fdt_pack(blob);
+
+ dt_dump_all(fw_node);
+}

95
meta-arm-bsp/recipes-bsp/boot-wrapper-aarch64/files/fvp-baser-aemv8r64/0021-boot-Enable-firmware-node-initialization.patch
View File

@@ -1,95 +0,0 @@
From b1105e862e8f770fc195bc20e9c64d231dd32f66 Mon Sep 17 00:00:00 2001
From: Jaxson Han <jaxson.han@arm.com>
Date: Wed, 29 Dec 2021 15:33:17 +0800
Subject: [PATCH] boot: Enable firmware node initialization
Enable the firmware node initialization, so that the next stage
(hypervisor) could share the EL2 with firmware (boot-wrapper). The next
stage (hypervisor) get the smccc entry point, code/data sections, the
sections attrs and firmware node version and so on.
It is worth noting that this EL2 sharing mechanism is only for Armv8R
AArch64, thus add flag_v8r to record if the arch is Armv8R AArch64.
Enable the firmware node initialization only if it is Armv8R AArch64.
Also, we increase the stack size to 1024 to fix the stack overflow issue
when using the libfdt.
Add -fno-builtin options to CFLAGS to avoid the issue that the 'memset'
in common/lib.c conflicts with builtin 'memset' function. GCC version
>= 10 will have an incorrect compilation without -fno-builtin;
Issue-Id: SCM-3816
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Change-Id: Ib274485a34d26215595fd0cd737be86610289817
---
Makefile.am | 4 ++--
arch/aarch64/boot.S | 6 ++++++
common/boot.c | 4 ++++
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/Makefile.am b/Makefile.am
index cc6504e..fbe6b81 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -23,7 +23,7 @@ DEFINES += -DCPU_IDS=$(CPU_IDS)
DEFINES += -DNR_CPUS=$(NR_CPUS)
DEFINES += $(if $(SYSREGS_BASE), -DSYSREGS_BASE=$(SYSREGS_BASE), )
DEFINES += -DUART_BASE=$(UART_BASE)
-DEFINES += -DSTACK_SIZE=256
+DEFINES += -DSTACK_SIZE=1024
if KERNEL_32
DEFINES += -DKERNEL_32
@@ -134,7 +134,7 @@ CFLAGS += -I$(top_srcdir)/include/ -I$(top_srcdir)/$(ARCH_SRC)/include/
CFLAGS += -Wall -fomit-frame-pointer
CFLAGS += -ffreestanding -nostdlib
CFLAGS += -fno-stack-protector
-CFLAGS += -fno-stack-protector
+CFLAGS += -fno-stack-protector -fno-builtin
CFLAGS += -ffunction-sections -fdata-sections
CFLAGS += -fno-pic -fno-pie
LDFLAGS += --gc-sections
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index c079d22..daaa674 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -261,6 +261,10 @@ el2_init:
#endif
ldr x1, =spsr_to_elx
str w0, [x1]
+
+ mov w0, #1
+ ldr x1, =flag_v8r
+ str w0, [x1]
// fall through
el_max_init:
@@ -340,3 +344,5 @@ flag_keep_el:
.long 0
ASM_DATA(spsr_to_elx)
.long 0
+ASM_DATA(flag_v8r)
+ .long 0
diff --git a/common/boot.c b/common/boot.c
index ee2bea0..38b2dca 100644
--- a/common/boot.c
+++ b/common/boot.c
@@ -11,6 +11,9 @@
extern unsigned long entrypoint;
extern unsigned long dtb;
+extern unsigned int flag_v8r;
+
+extern void dt_fw_node_init(int enable);
void init_platform(void);
@@ -64,6 +67,7 @@ void __noreturn first_spin(unsigned int cpu, unsigned long *mbox,
if (cpu == 0) {
init_platform();
dt_add_memreserve();
+ dt_fw_node_init(flag_v8r == 1);
*mbox = (unsigned long)&entrypoint;
sevl();

257
meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0001-armv8-Add-ARMv8-MPU-configuration-logic.patch
View File

@@ -1,257 +0,0 @@
From 401a88bf6019941d4095476de76af5893686d6f6 Mon Sep 17 00:00:00 2001
From: Peter Hoyes <Peter.Hoyes@arm.com>
Date: Wed, 26 May 2021 17:41:10 +0100
Subject: [PATCH] armv8: Add ARMv8 MPU configuration logic
Detect whether an MMU is present at the current exception level. If
not, initialize the MPU instead of the MMU during init, and clear the
MPU regions before transition to Linux.
The MSA in use at EL1&0 may be configurable but can only by determined
by inspecting VTCR_EL2 at EL2, so assume that there is an MMU for
backwards compatibility.
Provide a default (blank) MPU memory map, which can be overridden by
board configurations.
Issue-Id: SCM-2443
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Change-Id: I0ee3879f9d7f03fe940664b3551c68eeaa458d17
---
arch/arm/cpu/armv8/cache_v8.c | 101 ++++++++++++++++++++++++++++++-
arch/arm/include/asm/armv8/mpu.h | 59 ++++++++++++++++++
arch/arm/include/asm/system.h | 19 ++++++
3 files changed, 176 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/include/asm/armv8/mpu.h
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 2a226fd063..8611a35eb3 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -15,6 +15,7 @@
#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
+#include <asm/armv8/mpu.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -385,6 +386,91 @@ __weak u64 get_page_table_size(void)
return size;
}
+static void mpu_clear_regions(void)
+{
+ int i;
+
+ for (i = 0; mpu_mem_map[i].end || mpu_mem_map[i].attrs; i++) {
+ setup_el2_mpu_region(i, 0, 0);
+ }
+}
+
+static struct mpu_region default_mpu_mem_map[] = {{0,}};
+__weak struct mpu_region *mpu_mem_map = default_mpu_mem_map;
+
+static void mpu_setup(void)
+{
+ int i;
+
+ if (current_el() != 2) {
+ panic("MPU configuration is only supported at EL2");
+ }
+
+ set_sctlr(get_sctlr() & ~(CR_M | CR_WXN));
+
+ asm volatile("msr MAIR_EL2, %0" : : "r" MEMORY_ATTRIBUTES);
+
+ for (i = 0; mpu_mem_map[i].end || mpu_mem_map[i].attrs; i++) {
+ setup_el2_mpu_region(i,
+ PRBAR_ADDRESS(mpu_mem_map[i].start)
+ | PRBAR_OUTER_SH | PRBAR_AP_RW_ANY,
+ PRLAR_ADDRESS(mpu_mem_map[i].end)
+ | mpu_mem_map[i].attrs | PRLAR_EN_BIT
+ );
+ }
+
+ set_sctlr(get_sctlr() | CR_M);
+}
+
+static bool el_has_mmu(void)
+{
+ if (current_el() < 2) {
+ // We have no way of knowing, so assuming we have an MMU
+ return true;
+ }
+
+ uint64_t id_aa64mmfr0;
+ asm volatile("mrs %0, id_aa64mmfr0_el1"
+ : "=r" (id_aa64mmfr0) : : "cc");
+ uint64_t msa = id_aa64mmfr0 & ID_AA64MMFR0_EL1_MSA_MASK;
+ uint64_t msa_frac = id_aa64mmfr0 & ID_AA64MMFR0_EL1_MSA_FRAC_MASK;
+
+ switch (msa) {
+ case ID_AA64MMFR0_EL1_MSA_VMSA:
+ /*
+ * VMSA supported in all translation regimes.
+ * No support for PMSA.
+ */
+ return true;
+ case ID_AA64MMFR0_EL1_MSA_USE_FRAC:
+ /* See MSA_frac for the supported MSAs. */
+ switch (msa_frac) {
+ case ID_AA64MMFR0_EL1_MSA_FRAC_NO_PMSA:
+ /*
+ * PMSA not supported in any translation
+ * regime.
+ */
+ return true;
+ case ID_AA64MMFR0_EL1_MSA_FRAC_VMSA:
+ /*
+ * PMSA supported in all translation
+ * regimes. No support for VMSA.
+ */
+ case ID_AA64MMFR0_EL1_MSA_FRAC_PMSA:
+ /*
+ * PMSA supported in all translation
+ * regimes.
+ */
+ return false;
+ default:
+ panic("Unsupported id_aa64mmfr0_el1 " \
+ "MSA_frac value");
+ }
+ default:
+ panic("Unsupported id_aa64mmfr0_el1 MSA value");
+ }
+}
+
void setup_pgtables(void)
{
int i;
@@ -499,8 +585,13 @@ void dcache_enable(void)
/* The data cache is not active unless the mmu is enabled */
if (!(get_sctlr() & CR_M)) {
invalidate_dcache_all();
- __asm_invalidate_tlb_all();
- mmu_setup();
+
+ if (el_has_mmu()) {
+ __asm_invalidate_tlb_all();
+ mmu_setup();
+ } else {
+ mpu_setup();
+ }
}
/* Set up page tables only once (it is done also by mmu_setup()) */
@@ -523,7 +614,11 @@ void dcache_disable(void)
set_sctlr(sctlr & ~(CR_C|CR_M));
flush_dcache_all();
- __asm_invalidate_tlb_all();
+
+ if (el_has_mmu())
+ __asm_invalidate_tlb_all();
+ else
+ mpu_clear_regions();
}
int dcache_status(void)
diff --git a/arch/arm/include/asm/armv8/mpu.h b/arch/arm/include/asm/armv8/mpu.h
new file mode 100644
index 0000000000..8de627cafd
--- /dev/null
+++ b/arch/arm/include/asm/armv8/mpu.h
@@ -0,0 +1,59 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * (C) Copyright 2021 Arm Limited
+ */
+
+#ifndef _ASM_ARMV8_MPU_H_
+#define _ASM_ARMV8_MPU_H_
+
+#include <asm/armv8/mmu.h>
+#include <linux/stringify.h>
+
+#define PRSELR_EL2 S3_4_c6_c2_1
+#define PRBAR_EL2 S3_4_c6_c8_0
+#define PRLAR_EL2 S3_4_c6_c8_1
+#define MPUIR_EL2 S3_4_c0_c0_4
+
+#define PRBAR_ADDRESS(addr) ((addr) & ~(0x3fULL))
+
+/* Access permissions */
+#define PRBAR_AP(val) (((val) & 0x3) << 2)
+#define PRBAR_AP_RW_HYP PRBAR_AP(0x0)
+#define PRBAR_AP_RW_ANY PRBAR_AP(0x1)
+#define PRBAR_AP_RO_HYP PRBAR_AP(0x2)
+#define PRBAR_AP_RO_ANY PRBAR_AP(0x3)
+
+/* Shareability */
+#define PRBAR_SH(val) (((val) & 0x3) << 4)
+#define PRBAR_NON_SH PRBAR_SH(0x0)
+#define PRBAR_OUTER_SH PRBAR_SH(0x2)
+#define PRBAR_INNER_SH PRBAR_SH(0x3)
+
+/* Memory attribute (MAIR idx) */
+#define PRLAR_ATTRIDX(val) (((val) & 0x7) << 1)
+#define PRLAR_EN_BIT (0x1)
+#define PRLAR_ADDRESS(addr) ((addr) & ~(0x3fULL))
+
+#ifndef __ASSEMBLY__
+
+static inline void setup_el2_mpu_region(uint8_t region, uint64_t base, uint64_t limit)
+{
+ asm volatile("msr " __stringify(PRSELR_EL2) ", %0" : : "r" (region));
+ asm volatile("msr " __stringify(PRBAR_EL2) ", %0" : : "r" (base));
+ asm volatile("msr " __stringify(PRLAR_EL2) ", %0" : : "r" (limit));
+
+ asm volatile("isb");
+}
+
+#endif
+
+struct mpu_region {
+ u64 start;
+ u64 end;
+ u64 attrs;
+};
+
+extern struct mpu_region *mpu_mem_map;
+
+#endif /* _ASM_ARMV8_MPU_H_ */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 87d1c77e8b..4510db98a2 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -95,6 +95,25 @@
auth algorithm */
#define ID_AA64ISAR1_EL1_APA (0xF << 4) /* QARMA address auth algorithm */
+/*
+ * ID_AA64MMFR0_EL1 bits definitions
+ */
+#define ID_AA64MMFR0_EL1_MSA_FRAC_MASK (0xFUL << 52) /* Memory system
+ architecture
+ frac */
+#define ID_AA64MMFR0_EL1_MSA_FRAC_VMSA (0x2UL << 52) /* EL1&0 supports
+ VMSA */
+#define ID_AA64MMFR0_EL1_MSA_FRAC_PMSA (0x1UL << 52) /* EL1&0 only
+ supports PMSA*/
+#define ID_AA64MMFR0_EL1_MSA_FRAC_NO_PMSA (0x0UL << 52) /* No PMSA
+ support */
+#define ID_AA64MMFR0_EL1_MSA_MASK (0xFUL << 48) /* Memory system
+ architecture */
+#define ID_AA64MMFR0_EL1_MSA_USE_FRAC (0xFUL << 48) /* Use MSA_FRAC */
+#define ID_AA64MMFR0_EL1_MSA_VMSA (0x0UL << 48) /* Memory system
+ architecture
+ is VMSA */
+
/*
* ID_AA64PFR0_EL1 bits definitions
*/

59
meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch
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@@ -1,59 +0,0 @@
From 5b42322cb57692dbea7d2c39fd8769b6f0f6b7af Mon Sep 17 00:00:00 2001
From: Qi Feng <qi.feng@arm.com>
Date: Tue, 26 Jul 2022 18:13:23 +0800
Subject: [PATCH] vexpress64: add MPU memory map for the BASER_FVP
The previous patch added support for initializing an Armv8 MPU. There is only an
MPU at S-EL2 on the BASER_FVP, so add a platform-specific MPU memory map.
See https://developer.arm.com/documentation/100964/1117/Base-Platform/Base---memory/BaseR-Platform-memory-map
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Qi Feng <qi.feng@arm.com>
---
board/armltd/vexpress64/vexpress64.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index af326dc6f4..2310d18eb7 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -19,6 +19,7 @@
#include <dm/platform_data/serial_pl01x.h>
#include "pcie.h"
#include <asm/armv8/mmu.h>
+#include <asm/armv8/mpu.h>
#ifdef CONFIG_VIRTIO_NET
#include <virtio_types.h>
#include <virtio.h>
@@ -37,6 +38,27 @@ U_BOOT_DRVINFO(vexpress_serials) = {
.plat = &serial_plat,
};
+static struct mpu_region vexpress64_aemv8r_mem_map[] = {
+ {
+ .start = 0x0UL,
+ .end = 0x7fffffffUL,
+ .attrs = PRLAR_ATTRIDX(MT_NORMAL)
+ }, {
+ .start = 0x80000000UL,
+ .end = 0xffffffffUL,
+ .attrs = PRLAR_ATTRIDX(MT_DEVICE_NGNRNE)
+ }, {
+ .start = 0x100000000UL,
+ .end = 0xffffffffffUL,
+ .attrs = PRLAR_ATTRIDX(MT_NORMAL)
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mpu_region *mpu_mem_map = vexpress64_aemv8r_mem_map;
+
static struct mm_region vexpress64_mem_map[] = {
{
.virt = V2M_PA_BASE,

104
meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch
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@@ -1,104 +0,0 @@
From ffb0f72a67926c3053308cf03420bc0c36675d42 Mon Sep 17 00:00:00 2001
From: Peter Hoyes <Peter.Hoyes@arm.com>
Date: Fri, 10 Dec 2021 11:41:19 +0000
Subject: [PATCH] armv8: Allow disabling exception vectors on non-SPL builds
On the BASER_FVP, U-Boot shares EL2 with another bootloader, so we do
not wish to overide the exception vector, but we are also not using an
SPL build.
Therefore, add ARMV8_EXCEPTION_VECTORS, which disables exception vectors
in a similar way to ARMV8_SPL_EXCEPTION_VECTORS.
Rename ARMV8_SPL_EXCEPTION_VECTORS -> SPL_ARMV8_EXCEPTION_VECTORS so
that both config flags be be targeted using CONFIG_IS_ENABLED.
Issue-Id: SCM-3728
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Change-Id: I0cf0fc6d7ef4d45791411cf1f67c65e198cc8b2b
---
arch/arm/cpu/armv8/Kconfig | 10 ++++++++--
arch/arm/cpu/armv8/Makefile | 6 ++----
arch/arm/cpu/armv8/start.S | 4 ++--
configs/vexpress_aemv8r_defconfig | 1 +
4 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 1305238c9d..dec4be0e30 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -1,8 +1,8 @@
if ARM64
-config ARMV8_SPL_EXCEPTION_VECTORS
+config ARMV8_EXCEPTION_VECTORS
bool "Install crash dump exception vectors"
- depends on SPL
+ default y
help
The default exception vector table is only used for the crash
dump, but still takes quite a lot of space in the image size.
@@ -10,6 +10,12 @@ config ARMV8_SPL_EXCEPTION_VECTORS
Say N here if you are running out of code space in the image
and want to save some space at the cost of less debugging info.
+config SPL_ARMV8_EXCEPTION_VECTORS
+ bool "Install crash dump exception vectors in the SPL"
+ depends on SPL
+ help
+ Same as ARMV8_EXCEPTION_VECTORS, but for SPL builds
+
config ARMV8_MULTIENTRY
bool "Enable multiple CPUs to enter into U-Boot"
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index 2e4bf9e038..001a31cae7 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -13,10 +13,8 @@ ifndef CONFIG_$(SPL_)SYS_DCACHE_OFF
obj-y += cache_v8.o
obj-y += cache.o
endif
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o
-else
-obj-y += exceptions.o
+obj-$(CONFIG_$(SPL_)ARMV8_EXCEPTION_VECTORS) += exceptions.o
+ifndef CONFIG_SPL_BUILD
obj-y += exception_level.o
endif
obj-y += tlb.o
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index f3ea858577..7fad901336 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -104,7 +104,7 @@ pie_skip_reloc:
pie_fixup_done:
#endif
-#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(ARMV8_EXCEPTION_VECTORS)
.macro set_vbar, regname, reg
msr \regname, \reg
.endm
@@ -354,7 +354,7 @@ ENDPROC(smp_kick_all_cpus)
/*-----------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
-#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(ARMV8_EXCEPTION_VECTORS)
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig
index 495eb1dee3..683d983c36 100644
--- a/configs/vexpress_aemv8r_defconfig
+++ b/configs/vexpress_aemv8r_defconfig
@@ -16,3 +16,4 @@ CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=541
# CONFIG_MMC is not set
CONFIG_VIRTIO_MMIO=y
+CONFIG_ARMV8_EXCEPTION_VECTORS=n

140
meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch
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@@ -1,140 +0,0 @@
From 14e204ffca5870d6bfd238627937a2028c88589d Mon Sep 17 00:00:00 2001
From: Peter Hoyes <Peter.Hoyes@arm.com>
Date: Wed, 14 Jul 2021 12:44:27 +0100
Subject: [PATCH] armv8: ARMV8_SWITCH_TO_EL1 improvements
Convert CONFIG_ARMV8_SWITCH_TO_EL1 to a Kconfig variable.
Add support for switching to EL1 to bootefi.
Add the environment variable armv8_switch_to_el1 to allow configuring
whether to switch to EL1 at runtime. This overrides the compile-time
option.
Issue-Id: SCM-3728
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Change-Id: If98478148d6d8d1f732acac5439276700614815f
---
arch/arm/cpu/armv8/exception_level.c | 21 ++++++++++++++--
arch/arm/lib/bootm.c | 36 ++++++++++++++++------------
configs/vexpress_aemv8r_defconfig | 1 +
3 files changed, 41 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv8/exception_level.c b/arch/arm/cpu/armv8/exception_level.c
index b11936548f..4aad1550f4 100644
--- a/arch/arm/cpu/armv8/exception_level.c
+++ b/arch/arm/cpu/armv8/exception_level.c
@@ -40,19 +40,36 @@ static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
* trusted firmware being one embodiment). The operating system shall be
* started at exception level EL2. So here we check the exception level
* and switch it if necessary.
+ *
+ * If armv8_switch_to_el1 (config or env var) is enabled, also switch to EL1
+ * before booting the operating system.
*/
void switch_to_non_secure_mode(void)
{
struct jmp_buf_data non_secure_jmp;
/* On AArch64 we need to make sure we call our payload in < EL3 */
- if (current_el() == 3) {
+
+ int switch_to_el1 = env_get_yesno("armv8_switch_to_el1");
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ if (switch_to_el1 == -1) {
+ switch_to_el1 = 1;
+ }
+#endif
+
+ if (current_el() > 2) {
if (setjmp(&non_secure_jmp))
return;
dcache_disable(); /* flush cache before switch to EL2 */
-
/* Move into EL2 and keep running there */
armv8_switch_to_el2((uintptr_t)&non_secure_jmp, 0, 0, 0,
(uintptr_t)entry_non_secure, ES_TO_AARCH64);
+ } else if (switch_to_el1 == 1 && current_el() > 1) {
+ if (setjmp(&non_secure_jmp))
+ return;
+ dcache_disable(); /* flush cache before switch to EL1 */
+ /* Move into EL1 and keep running there */
+ armv8_switch_to_el1((uintptr_t)&non_secure_jmp, 0, 0, 0,
+ (uintptr_t)entry_non_secure, ES_TO_AARCH64);
}
}
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index e414ef8267..9a86c17d2a 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -270,7 +270,6 @@ __weak void update_os_arch_secondary_cores(uint8_t os_arch)
{
}
-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
static void switch_to_el1(void)
{
if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
@@ -285,7 +284,6 @@ static void switch_to_el1(void)
ES_TO_AARCH64);
}
#endif
-#endif
/* Subcommand: GO */
static void boot_jump_linux(struct bootm_headers *images, int flag)
@@ -312,21 +310,29 @@ static void boot_jump_linux(struct bootm_headers *images, int flag)
update_os_arch_secondary_cores(images->os.arch);
+ int armv8_switch_to_el1 = env_get_yesno("armv8_switch_to_el1");
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
- armv8_switch_to_el2((u64)images->ft_addr, 0, 0, 0,
- (u64)switch_to_el1, ES_TO_AARCH64);
-#else
- if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
- (images->os.arch == IH_ARCH_ARM))
- armv8_switch_to_el2(0, (u64)gd->bd->bi_arch_number,
- (u64)images->ft_addr, 0,
- (u64)images->ep,
- ES_TO_AARCH32);
- else
- armv8_switch_to_el2((u64)images->ft_addr, 0, 0, 0,
- images->ep,
- ES_TO_AARCH64);
+ if (armv8_switch_to_el1 == -1) {
+ armv8_switch_to_el1 = 1;
+ }
#endif
+ if (armv8_switch_to_el1 == 1) {
+ armv8_switch_to_el2((u64)images->ft_addr, 0, 0, 0,
+ (u64)switch_to_el1, ES_TO_AARCH64);
+ } else {
+ if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
+ (images->os.arch == IH_ARCH_ARM))
+ armv8_switch_to_el2(0,
+ (u64)gd->bd->bi_arch_number,
+ (u64)images->ft_addr, 0,
+ (u64)images->ep,
+ ES_TO_AARCH32);
+ else
+ armv8_switch_to_el2((u64)images->ft_addr,
+ 0, 0, 0,
+ images->ep,
+ ES_TO_AARCH64);
+ }
}
#else
unsigned long machid = gd->bd->bi_arch_number;
diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig
index 683d983c36..6044f82b00 100644
--- a/configs/vexpress_aemv8r_defconfig
+++ b/configs/vexpress_aemv8r_defconfig
@@ -17,3 +17,4 @@ CONFIG_SYS_PBSIZE=541
# CONFIG_MMC is not set
CONFIG_VIRTIO_MMIO=y
CONFIG_ARMV8_EXCEPTION_VECTORS=n
+CONFIG_ARMV8_SWITCH_TO_EL1=y

80
meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0005-armv8-Make-disabling-HVC-configurable-when-switching.patch
View File

@@ -1,80 +0,0 @@
From e3d24bc1fd0b09915b5181de1282f7008bbf776f Mon Sep 17 00:00:00 2001
From: Peter Hoyes <Peter.Hoyes@arm.com>
Date: Fri, 10 Dec 2021 16:37:26 +0000
Subject: [PATCH] armv8: Make disabling HVC configurable when switching to EL1
On the BASER_FVP there is no EL3, so HVC is used to provide PSCI
services. Therefore we cannot disable hypercalls.
Create CONFIG_ARMV8_DISABLE_HVC (dependent on CONFIG_ARMV8_TO_EL1) to
control whether to disable HVC exceptions in HCR_EL2->HCD
Issue-Id: SCM-3728
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Change-Id: I463d82f1db8a3cafcab40a9c0c208753569cc300
---
arch/arm/cpu/armv8/Kconfig | 9 +++++++++
arch/arm/include/asm/macro.h | 10 ++++++++--
configs/vexpress_aemv8r_defconfig | 1 +
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index dec4be0e30..95c03487a2 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -208,4 +208,13 @@ config ARMV8_CE_SHA256
endif
+config ARMV8_DISABLE_HVC
+ bool "Disable HVC calls before switching to EL1"
+ depends on ARMV8_SWITCH_TO_EL1
+ default y
+ help
+ If switching to EL1 before loading the operating system, disable taking
+ hypercalls back to EL2. May be disabled if, for example, PSCI services are
+ running at EL2.
+
endif
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 1a1edc9870..7167739210 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -296,9 +296,12 @@ lr .req x30
ldr \tmp2, =(ID_AA64ISAR1_EL1_GPI | ID_AA64ISAR1_EL1_GPA | \
ID_AA64ISAR1_EL1_API | ID_AA64ISAR1_EL1_APA)
tst \tmp, \tmp2
- mov \tmp2, #(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS)
+ mov \tmp2, #(HCR_EL2_RW_AARCH64)
orr \tmp, \tmp2, #(HCR_EL2_APK | HCR_EL2_API)
csel \tmp, \tmp2, \tmp, eq
+#ifdef CONFIG_ARMV8_DISABLE_HVC
+ orr \tmp, \tmp, #(HCR_EL2_HCD_DIS)
+#endif
msr hcr_el2, \tmp
/* Return to the EL1_SP1 mode from EL2 */
@@ -311,7 +314,10 @@ lr .req x30
1:
/* Initialize HCR_EL2 */
- ldr \tmp, =(HCR_EL2_RW_AARCH32 | HCR_EL2_HCD_DIS)
+ ldr \tmp, =(HCR_EL2_RW_AARCH32)
+#ifdef CONFIG_ARMV8_DISABLE_HVC
+ orr \tmp, \tmp, #(HCR_EL2_HCD_DIS)
+#endif
msr hcr_el2, \tmp
/* Return to AArch32 Supervisor mode from EL2 */
diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig
index 6044f82b00..6226f6b2c1 100644
--- a/configs/vexpress_aemv8r_defconfig
+++ b/configs/vexpress_aemv8r_defconfig
@@ -18,3 +18,4 @@ CONFIG_SYS_PBSIZE=541
CONFIG_VIRTIO_MMIO=y
CONFIG_ARMV8_EXCEPTION_VECTORS=n
CONFIG_ARMV8_SWITCH_TO_EL1=y
+CONFIG_ARMV8_DISABLE_HVC=n

30
meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch
View File

@@ -1,30 +0,0 @@
From 571f44d5292cfead6f68bf4c6c9519872337bfd0 Mon Sep 17 00:00:00 2001
From: Qi Feng <qi.feng@arm.com>
Date: Thu, 28 Jul 2022 17:47:18 +0800
Subject: [PATCH] vexpress64: Do not set COUNTER_FREQUENCY
VExpress boards normally run as a second-stage bootloader so should not
need to modify CNTFRQ_EL0. On the BASER_FVP, U-Boot can modify it if
running at EL2, but shouldn't because it might be different from the
value being used by the first-stage bootloader (which might be
providing PSCI services).
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Qi Feng <qi.feng@arm.com>
---
configs/vexpress_aemv8r_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig
index 6226f6b2c1..b902a6a7d9 100644
--- a/configs/vexpress_aemv8r_defconfig
+++ b/configs/vexpress_aemv8r_defconfig
@@ -1,5 +1,4 @@
CONFIG_ARM=y
-CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_VEXPRESS64=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="arm_fvp"

25
meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch
View File

@@ -1,25 +0,0 @@
From df01346bb63c821cf8e73202e2894ceda9cb692b Mon Sep 17 00:00:00 2001
From: Peter Hoyes <Peter.Hoyes@arm.com>
Date: Tue, 22 Feb 2022 15:32:51 +0000
Subject: [PATCH] vexpress64: Enable LIBFDT_OVERLAY in the vexpress_aemv8r
defconfig
Issue-Id: SCM-3874
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Change-Id: Ide0532cf2de89f1bca9c8d4bd2ed0c1a1c57599f
---
configs/vexpress_aemv8r_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/vexpress_aemv8r_defconfig b/configs/vexpress_aemv8r_defconfig
index b902a6a7d9..a58a9db385 100644
--- a/configs/vexpress_aemv8r_defconfig
+++ b/configs/vexpress_aemv8r_defconfig
@@ -18,3 +18,4 @@ CONFIG_VIRTIO_MMIO=y
CONFIG_ARMV8_EXCEPTION_VECTORS=n
CONFIG_ARMV8_SWITCH_TO_EL1=y
CONFIG_ARMV8_DISABLE_HVC=n
+CONFIG_OF_LIBFDT_OVERLAY=y

103
meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch
View File

@@ -1,103 +0,0 @@
From 665ab8253a0e3e17db54a1682bbee0f5659939a2 Mon Sep 17 00:00:00 2001
From: Peter Hoyes <Peter.Hoyes@arm.com>
Date: Wed, 18 May 2022 15:24:19 +0100
Subject: [PATCH] armv8: Allow PRBAR MPU attributes to be configured
In a previous patch, support was added to initialize an S-EL2 MPU on
armv8r64 machines. This implementation allowed the PRLAR attribute
index to be configured, but not the shareability and access permission
attributes in PRBAR. These attributes were hard-coded as "outer
shareable" and "read/write at EL1 and EL0".
Add separate prlar_attrs and prbar_attrs to the MPU region struct so
that these attributes can be configured on a per-region basis.
For the BASER_FVP, ensure the MPU memory attributes match those in the
existing vexpress64 board MMU configuration ("non shareable" for device
memory and "inner shareable" for normal memory).
Issue-Id: SCM-4641
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Change-Id: I6b72aead91ad12412262aa32c61a53e12eab3984
---
arch/arm/cpu/armv8/cache_v8.c | 12 ++++++++----
arch/arm/include/asm/armv8/mpu.h | 3 ++-
board/armltd/vexpress64/vexpress64.c | 9 ++++++---
3 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 8611a35eb3..f7de952187 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -390,7 +390,9 @@ static void mpu_clear_regions(void)
{
int i;
- for (i = 0; mpu_mem_map[i].end || mpu_mem_map[i].attrs; i++) {
+ for (i = 0; mpu_mem_map[i].end ||
+ mpu_mem_map[i].prbar_attrs ||
+ mpu_mem_map[i].prlar_attrs; i++) {
setup_el2_mpu_region(i, 0, 0);
}
}
@@ -410,12 +412,14 @@ static void mpu_setup(void)
asm volatile("msr MAIR_EL2, %0" : : "r" MEMORY_ATTRIBUTES);
- for (i = 0; mpu_mem_map[i].end || mpu_mem_map[i].attrs; i++) {
+ for (i = 0; mpu_mem_map[i].end ||
+ mpu_mem_map[i].prbar_attrs ||
+ mpu_mem_map[i].prlar_attrs; i++) {
setup_el2_mpu_region(i,
PRBAR_ADDRESS(mpu_mem_map[i].start)
- | PRBAR_OUTER_SH | PRBAR_AP_RW_ANY,
+ | mpu_mem_map[i].prbar_attrs,
PRLAR_ADDRESS(mpu_mem_map[i].end)
- | mpu_mem_map[i].attrs | PRLAR_EN_BIT
+ | mpu_mem_map[i].prlar_attrs | PRLAR_EN_BIT
);
}
diff --git a/arch/arm/include/asm/armv8/mpu.h b/arch/arm/include/asm/armv8/mpu.h
index 8de627cafd..dd4c689ea6 100644
--- a/arch/arm/include/asm/armv8/mpu.h
+++ b/arch/arm/include/asm/armv8/mpu.h
@@ -51,7 +51,8 @@ static inline void setup_el2_mpu_region(uint8_t region, uint64_t base, uint64_t
struct mpu_region {
u64 start;
u64 end;
- u64 attrs;
+ u64 prbar_attrs;
+ u64 prlar_attrs;
};
extern struct mpu_region *mpu_mem_map;
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
index 2310d18eb7..531fa4d618 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -42,15 +42,18 @@ static struct mpu_region vexpress64_aemv8r_mem_map[] = {
{
.start = 0x0UL,
.end = 0x7fffffffUL,
- .attrs = PRLAR_ATTRIDX(MT_NORMAL)
+ .prbar_attrs = PRBAR_INNER_SH | PRBAR_AP_RW_ANY,
+ .prlar_attrs = PRLAR_ATTRIDX(MT_NORMAL)
}, {
.start = 0x80000000UL,
.end = 0xffffffffUL,
- .attrs = PRLAR_ATTRIDX(MT_DEVICE_NGNRNE)
+ .prbar_attrs = PRBAR_OUTER_SH | PRBAR_AP_RW_ANY,
+ .prlar_attrs = PRLAR_ATTRIDX(MT_DEVICE_NGNRNE)
}, {
.start = 0x100000000UL,
.end = 0xffffffffffUL,
- .attrs = PRLAR_ATTRIDX(MT_NORMAL)
+ .prbar_attrs = PRBAR_INNER_SH | PRBAR_AP_RW_ANY,
+ .prlar_attrs = PRLAR_ATTRIDX(MT_NORMAL)
}, {
/* List terminator */
0,

61
meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Enable-icache-when-switching-exception-levels-.patch
View File

@@ -1,61 +0,0 @@
From c7301588a3aec9ebf36749da601d0d6e3d807bfc Mon Sep 17 00:00:00 2001
From: Peter Hoyes <Peter.Hoyes@arm.com>
Date: Thu, 19 May 2022 09:02:32 +0100
Subject: [PATCH] armv8: Enable icache when switching exception levels in
bootefi
bootefi calls the function switch_to_non_secure_mode before calling the
UEFI payload to handle the case where U-Boot is running at EL3.
For AArch64, the UEFI specification states that:
The core will be configured as follows:
* MMU enabled
* Instruction and data caches enabled
These requirements should be followed when switching exception levels
for EFI applications.
This function already disables and re-enables the data cache prior to
switching exception levels, but omits the instruction cache, meaning
the function returns with the instruction cache disabled at the new
exception level. Fix this by calling icache_disable prior to switching
exception levels and icache_enable afterwards.
Issue-Id: SCM-4641
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Upstream-Status: Inappropriate [other]
Implementation pending further discussion
Change-Id: I678cd5ba39b56e124ab7854608289cd14651ce65
---
arch/arm/cpu/armv8/exception_level.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/armv8/exception_level.c b/arch/arm/cpu/armv8/exception_level.c
index 4aad1550f4..0a3e5428e7 100644
--- a/arch/arm/cpu/armv8/exception_level.c
+++ b/arch/arm/cpu/armv8/exception_level.c
@@ -27,6 +27,7 @@
static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
{
dcache_enable();
+ icache_enable();
debug("Reached non-secure mode\n");
/* Restore stack and registers saved in switch_to_non_secure_mode() */
@@ -61,6 +62,7 @@ void switch_to_non_secure_mode(void)
if (setjmp(&non_secure_jmp))
return;
dcache_disable(); /* flush cache before switch to EL2 */
+ icache_disable();
/* Move into EL2 and keep running there */
armv8_switch_to_el2((uintptr_t)&non_secure_jmp, 0, 0, 0,
(uintptr_t)entry_non_secure, ES_TO_AARCH64);
@@ -68,6 +70,7 @@ void switch_to_non_secure_mode(void)
if (setjmp(&non_secure_jmp))
return;
dcache_disable(); /* flush cache before switch to EL1 */
+ icache_disable();
/* Move into EL1 and keep running there */
armv8_switch_to_el1((uintptr_t)&non_secure_jmp, 0, 0, 0,
(uintptr_t)entry_non_secure, ES_TO_AARCH64);

17
meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend
View File

@@ -56,23 +56,6 @@ SRC_URI:append:corstone1000 = " \
SRC_URI:append:fvp-base = " file://bootargs.cfg \
file://0001-Revert-vexpress64-pick-DRAM-size-from-DT.patch \
"
#
# FVP BASER
#
SRC_URI:append:fvp-baser-aemv8r64 = " \
file://0001-armv8-Add-ARMv8-MPU-configuration-logic.patch \
file://0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch \
file://0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch \
file://0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch \
file://0005-armv8-Make-disabling-HVC-configurable-when-switching.patch \
file://0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch \
file://0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch \
file://0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch \
file://0009-armv8-Enable-icache-when-switching-exception-levels-.patch \
"
#
# Juno Machines
#

6
meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/fvp-baser-aemv8r64-preempt-rt.scc
View File

@@ -1,6 +0,0 @@
define KMACHINE fvp-baser-aemv8r64
define KTYPE preempt-rt
define KARCH arm64
include ktypes/preempt-rt/preempt-rt.scc
include fvp-baser-aemv8r64.scc

7
meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/fvp-baser-aemv8r64-standard.scc
View File

@@ -1,7 +0,0 @@
define KMACHINE fvp-baser-aemv8r64
define KTYPE standard
define KARCH arm64
include ktypes/standard/standard.scc
include fvp-baser-aemv8r64.scc

4
meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/fvp-baser-aemv8r64.scc
View File

@@ -1,4 +0,0 @@
kconf hardware arm64.cfg
kconf hardware fvp-common-peripherals.cfg
include cfg/virtio.scc
include virtio-9p.scc

212
meta-arm-bsp/recipes-kernel/linux/files/fvp-baser-aemv8r64/fvp-baser-aemv8r64.dts
View File

@@ -1,212 +0,0 @@
/dts-v1/;
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
interrupt-parent = <0x1>;
model = "Generated";
compatible = "arm,base";
memory@0 {
#address-cells = <0x2>;
#size-cells = <0x2>;
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>,
<0x00000008 0x80000000 0x0 0x80000000>;
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu-map {
cluster0 {
core0 { thread0 { cpu = <&CPU_0>; }; };
core1 { thread0 { cpu = <&CPU_1>; }; };
core2 { thread0 { cpu = <&CPU_2>; }; };
core3 { thread0 { cpu = <&CPU_3>; }; };
};
};
CPU_0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x7f800>;
};
CPU_1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x7f808>;
};
CPU_2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x7f810>;
};
CPU_3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x7f818>;
};
};
interrupt-controller@af000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <0x3>;
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
interrupt-controller;
#redistributor-regions = <0x1>;
reg = <0x0 0xaf000000 0x0 0x10000>, // GICD
<0x0 0xaf100000 0x0 0x100000>, // GICR
<0x0 0xac000000 0x0 0x2000>, // GICC
<0x0 0xac010000 0x0 0x2000>, // GICH
<0x0 0xac02f000 0x0 0x2000>; // GICV
interrupts = <0x1 9 0x4>;
linux,phandle = <0x1>;
phandle = <0x1>;
its: msi-controller@2f020000 {
#msi-cells = <1>;
compatible = "arm,gic-v3-its";
reg = <0x0 0xaf020000 0x0 0x20000>; // GITS
msi-controller;
};
};
refclk100mhz: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
refclk24mhz: refclk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "refclk24mhz";
};
refclk1hz: refclk1hz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1>;
clock-output-names = "refclk1hz";
};
uart@9c090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x9c090000 0x0 0x1000>;
interrupts = <0x0 5 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart@9c0a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x9c0a0000 0x0 0x1000>;
interrupts = <0x0 6 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart@9c0b0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x9c0b0000 0x0 0x1000>;
interrupts = <0x0 7 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart@9c0c0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x9c0c0000 0x0 0x1000>;
interrupts = <0x0 8 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
};
wdt@9c0f0000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0x9c0f0000 0x0 0x1000>;
interrupts = <0x0 0 0x4>;
clocks = <&refclk24mhz>, <&refclk100mhz>;
clock-names = "wdog_clk", "apb_pclk";
};
rtc@9c170000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x0 0x9c170000 0x0 0x1000>;
interrupts = <0x0 4 0x4>;
clocks = <&refclk1hz>;
clock-names = "apb_pclk";
};
virtio-block@9c130000 {
compatible = "virtio,mmio";
reg = <0 0x9c130000 0 0x200>;
interrupts = <0x0 42 0x4>;
};
virtio-p9@9c140000{
compatible = "virtio,mmio";
reg = <0x0 0x9c140000 0x0 0x1000>;
interrupts = <0x0 43 0x4>;
};
virtio-net@9c150000 {
compatible = "virtio,mmio";
reg = <0 0x9c150000 0 0x200>;
interrupts = <0x0 44 0x4>;
};
virtio-rng@9c200000 {
compatible = "virtio,mmio";
reg = <0 0x9c200000 0 0x200>;
interrupts = <0x0 46 0x4>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <0x1 13 0xff08>,
<0x1 14 0xff08>,
<0x1 11 0xff08>,
<0x1 4 0xff08>;
clock-frequency = <100000000>;
};
aliases {
serial0 = "/uart@9c090000";
serial1 = "/uart@9c0a0000";
serial2 = "/uart@9c0b0000";
serial3 = "/uart@9c0c0000";
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <0 60 4>,
<0 61 4>,
<0 62 4>,
<0 63 4>;
};
chosen {
bootargs = "earlycon console=ttyAMA0 loglevel=8 rootfstype=ext4 root=/dev/vda1 rw";
stdout-path = "serial0";
};
};

8
meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc
View File

@@ -14,7 +14,6 @@ ARMBSPFILESPATHS := "${THISDIR}:${THISDIR}/files:"
# Arm platforms kmeta
SRC_URI_KMETA = "file://arm-platforms-kmeta;type=kmeta;name=arm-platforms-kmeta;destsuffix=arm-platforms-kmeta"
SRC_URI:append:fvp-base = " ${SRC_URI_KMETA}"
SRC_URI:append:fvp-baser-aemv8r64 = " ${SRC_URI_KMETA}"
SRC_URI:append:juno = " ${SRC_URI_KMETA}"
SRC_URI:append:n1sdp = " ${SRC_URI_KMETA}"
SRCREV:arm-platforms-kmeta = "6147e82375aa9df8f2a162d42ea6406c79c854c5"
@@ -58,13 +57,6 @@ KMACHINE:fvp-base = "fvp"
FILESEXTRAPATHS:prepend:fvp-base := "${ARMBSPFILESPATHS}"
SRC_URI:append:fvp-base = " file://0001-arm64-dts-fvp-Enable-virtio-rng-support.patch"
#
# FVP BaseR AEMv8r64 Machine
#
COMPATIBLE_MACHINE:fvp-baser-aemv8r64 = "fvp-baser-aemv8r64"
FILESEXTRAPATHS:prepend:fvp-baser-aemv8r64 := "${ARMBSPFILESPATHS}"
SRC_URI:append:fvp-baser-aemv8r64 = " file://fvp-baser-aemv8r64.dts;subdir=git/arch/arm64/boot/dts/arm"
#
# Juno KMACHINE
#

1
meta-arm-bsp/recipes-kernel/linux/linux-yocto-rt_%.bbappend
View File

@@ -1,6 +1,5 @@
# Only enable linux-yocto-rt for n1sdp and the Armv8-R AArch64 AEM FVP
LINUX_YOCTO_RT_REQUIRE ?= ""
LINUX_YOCTO_RT_REQUIRE:n1sdp = "linux-arm-platforms.inc"
LINUX_YOCTO_RT_REQUIRE:fvp-baser-aemv8r64 = "linux-arm-platforms.inc"
require ${LINUX_YOCTO_RT_REQUIRE}

10
meta-arm/recipes-devtools/fvp/fvp-base-r-aem_11.22.14.bb
View File

@@ -1,10 +0,0 @@
require fvp-envelope.inc
SUMMARY = "Arm Fixed Virtual Platform - Armv8-R Base Architecture Envelope Model FVP"
LIC_FILES_CHKSUM = "file://license_terms/license_agreement.txt;md5=1a33828e132ba71861c11688dbb0bd16 \
file://license_terms/third_party_licenses/third_party_licenses.txt;md5=34a1ba318d745f05e6197def68ea5411 \
file://license_terms/third_party_licenses/arm_license_management_utilities/third_party_licenses.txt;md5=c09526c02e631abb95ad61528892552d"
SRC_URI[fvp-x86_64.sha256sum] = "e819bfbccd91749345e3c7c6db22cbe41e02223118eb6395a4307ca81b175f7a"
MODEL_CODE = "FVP_Base_AEMv8R"