arm/trusted-firmware-a: add branch name for mbedtls

It appears that the mbedtls team have moved the SHA which
meta-arm was using from master branch. It is still present
in mbedtls-2.16 branch so this is now used.

Change-Id: If24915b1a1dc889d55b359863943439c76f6ca85
Signed-off-by: Prabin CA <prabin.ca@arm.com>
Signed-off-by: Ross Burton <ross.burton@arm.com>

meta-arm-autonomy/conf/distro/include/arm-autonomy-host.inc

@@ -2,6 +2,7 @@
 
 # We need to have xen and ipv4 activated
 DISTRO_FEATURES_append = " xen ipv4"
+DISTRO_FEATURES_NATIVE_append = " arm-autonomy-host"
 
 # Don't include kernels in standard images when building arm-autonomy-host
 # If the kernel image is needed in the rootfs the following should be set from

meta-arm-autonomy/dynamic-layers/meta-arm-bsp/recipes-devtools/gem5/gem5-aarch64-native_20.bbappend

@@ -0,0 +1,7 @@
+# When booting gem5-arm64 with Xen we need to set the cpu as Cortex A53 and
+# remove support for pointer authentification
+GEM5_RUN_EXTRA_append = " \
+${@bb.utils.contains('DISTRO_FEATURES_NATIVE', 'arm-autonomy-host', \
+'--param=system.cpu_cluster[0].cpus[0].isa[0].midr=0x410fd030 \
+--param=system.cpu_cluster[0].cpus[0].isa[0].id_aa64isar1_el1=0x0', \
+'', d)}"

meta-arm-autonomy/dynamic-layers/meta-arm-bsp/recipes-extended/xenguest/xenguest-network-bridge.bbappend

@@ -1,2 +1,10 @@
+XENGUEST_NETWORK_BRIDGE_MEMBERS_n1sdp ?= "eth0"
+
+XENGUEST_NETWORK_BRIDGE_MEMBERS_fvp-base ?= "eth0"
+
+XENGUEST_NETWORK_BRIDGE_MEMBERS_foundation-armv8 ?= "eth0"
+
+XENGUEST_NETWORK_BRIDGE_MEMBERS_gem5-arm64 ?= "eth0"
+
 # Juno board has 2 network interfaces, add both of them to the bridge
 XENGUEST_NETWORK_BRIDGE_MEMBERS_juno ?= "eth0 eth1"

meta-arm-autonomy/recipes-extended/xenguest/files/xenguest-init

@@ -12,6 +12,9 @@ fi
 
 source ${XENGUEST_CONF_BASE}/xenguest-manager.conf
 
+# Make sure we properly initialized the Dom0
+/usr/bin/xenguest-manager check-xen || exit $?
+
 # Create guest list
 guestlist=$(/usr/bin/xenguest-manager list)
 

meta-arm-autonomy/recipes-extended/xenguest/files/xenguest-manager

@@ -56,10 +56,14 @@ EOF
 
 function xenguest_volume_init()
 {
+    # Return:
+    # 0 - success
+    # 1 - failure
+
     if [ -z "${XENGUEST_VOLUME_DEVICE:-}" -o \
         ! -b ${XENGUEST_VOLUME_DEVICE:-} ]; then
         echo "${PREF} Invalid volume device in configuration: ${XENGUEST_VOLUME_DEVICE:-}"
-        exit 1
+        return 1
     fi
 
     if [ -z "${XENGUEST_VOLUME_NAME:-}" ]; then
@@ -69,14 +73,26 @@ function xenguest_volume_init()
 
     pvs ${XENGUEST_VOLUME_DEVICE} > /dev/null 2>&1
     if [ $? -ne 0 ]; then
-        echo "${PREF} Initialize lvm on ${XENGUEST_VOLUME_DEVICE}"
-        echo "pvcreate -f ${XENGUEST_VOLUME_DEVICE}" >> ${LOGFILE} 2>&1
-        pvcreate -f ${XENGUEST_VOLUME_DEVICE} >> ${LOGFILE} 2>&1
-        if [ $? -ne 0 ]; then
-            echo "${PREF} Error"
-            exit 1
+        # Check if there is no filesystem in the block device
+        echo "lsblk -n -o FSTYPE ${XENGUEST_VOLUME_DEVICE}" >> ${LOGFILE} 2>&1
+        filesystem=$(lsblk -n -o FSTYPE ${XENGUEST_VOLUME_DEVICE} 2>> ${LOGFILE})
+        if [[ $? -eq 0 && -z "$filesystem" ]]; then
+            echo "${PREF} Initialize lvm on ${XENGUEST_VOLUME_DEVICE}"
+            echo "pvcreate -f ${XENGUEST_VOLUME_DEVICE}" >> ${LOGFILE} 2>&1
+            pvcreate -f ${XENGUEST_VOLUME_DEVICE} >> ${LOGFILE} 2>&1
+            if [ $? -ne 0 ]; then
+                echo "${PREF} Error: initialing lvm on " \
+                     "${XENGUEST_VOLUME_DEVICE} failed." | tee -a ${LOGFILE}
+                return 1
+            fi
+        else
+            [ -z "$filesystem" ] || \
+                echo "${PREF} Error: The ${XENGUEST_VOLUME_DEVICE} is already " \
+                     "formatted as $filesystem." | tee -a ${LOGFILE}
+            return 1
         fi
     fi
+
     vgs ${XENGUEST_VOLUME_NAME} > /dev/null 2>&1
     if [ $? -ne 0 ]; then
         echo "${PREF} Create ${XENGUEST_VOLUME_NAME} volume"
@@ -85,10 +101,13 @@ function xenguest_volume_init()
         vgcreate ${XENGUEST_VOLUME_NAME} ${XENGUEST_VOLUME_DEVICE} \
             >> ${LOGFILE} 2>&1
         if [ $? -ne 0 ]; then
-            echo "${PREF} Error"
-            exit 1
+            echo "${PREF} Error: creating ${XENGUEST_VOLUME_NAME} volume " \
+                 "failed."  | tee -a ${LOGFILE}
+            return 1
         fi
     fi
+
+    return 0
 }
 
 # Detach a disk we attached to xen
@@ -102,12 +121,21 @@ function xenguest_detach_disk()
         >> ${LOGFILE} 2>&1
     if [ $? -ne 0 ]; then
         echo "${PREF} Error detaching partition ${part}"
-        exit 1
+        return 1
     fi
 }
 
 function xenguest_disk_init()
 {
+    # Inputs:
+    # $1 - guestname
+    # $2 - guestfile
+    #
+    # Outputs:
+    # 0 - success
+    # 1 - failed at guest disk preparation
+    # 2 - failed at guest disk creation
+
     guestname="$1"
     guestfile="$2"
     devname="/dev/${XENGUEST_VOLUME_NAME}/${guestname}"
@@ -119,12 +147,16 @@ function xenguest_disk_init()
         return
     fi
 
-    echo "${PREF} Create ${guestname} disk"
+    echo "${PREF} Create ${guestname} disk."
 
     # Init our volume
-    xenguest_volume_init
+    xenguest_volume_init ${guestname}
+    if [ $? -ne 0 ]; then
+        return 1
+    fi
 
-    echo "${PREF} Create hard drive for ${guestname}"
+    echo "${PREF} Create hard drive for ${guestname}." \
+         "This might take a while..."
 
 
     # Remove volume if it already exist
@@ -135,7 +167,7 @@ function xenguest_disk_init()
         lvremove -y ${devname} >> ${LOGFILE} 2>&1
         if [ $? -ne 0 ]; then
             echo "${PREF} Error removing volume ${guestname}"
-            exit 1
+            return 1
         fi
     fi
 
@@ -146,7 +178,7 @@ function xenguest_disk_init()
         >> ${LOGFILE} 2>&1
     if [ $? -ne 0 ]; then
         echo "${PREF} Error creating volume ${guestname}"
-        exit 1
+        return 1
     fi
 
     # Add partition table
@@ -154,7 +186,7 @@ function xenguest_disk_init()
     parted -s ${devname} mklabel msdos >> ${LOGFILE} 2>&1
     if [ $? -ne 0 ]; then
         echo "${PREF} Error creating partition table on ${guestname}"
-        exit 1
+        return 1
     fi
 
     # Setup disk name in xen configuration
@@ -164,7 +196,7 @@ function xenguest_disk_init()
         --xen-disk=${devname} >> ${LOGFILE} 2>&1
     if [ $? -ne 0 ]; then
         echo "${PREF} Error setting disk in xen configuration"
-        exit 1
+        return 1
     fi
 
     # Create partitions
@@ -197,7 +229,7 @@ function xenguest_disk_init()
                 ${partend} >> ${LOGFILE} 2>&1
             if [ $? -ne 0 ]; then
                 echo "${PREF} Error adding partition ${part}"
-                exit 1
+                return 1
             fi
 
             # Set next partition start to current partition end
@@ -219,7 +251,7 @@ function xenguest_disk_init()
                     *)
                         echo "${PREF} partition ${part} of ${guestname}" \
                             "fstype is invalid: ${fstype}"
-                        exit 1
+                        return 1
                         ;;
                 esac
             else
@@ -231,7 +263,7 @@ function xenguest_disk_init()
             xl block-attach 0 phy:${devname} xvda w >> ${LOGFILE} 2>&1
             if [ $? -ne 0 ]; then
                 echo "${PREF} Error attaching partition ${part}"
-                exit 1
+                return 1
             fi
 
 
@@ -247,8 +279,7 @@ function xenguest_disk_init()
 
             if [ ! -b /dev/xvda${part} ]; then
                 echo "${PREF} Partition ${part} creation error"
-                xenguest_detach_disk
-                exit 1
+                return 2
             fi
 
             if [ -n "${formatcmd}" ]; then
@@ -256,8 +287,7 @@ function xenguest_disk_init()
                 ${formatcmd} /dev/xvda${part}
                 if [ $? -ne 0 ]; then
                     echo "${PREF} Cannot create partition ${part} FS"
-                    xenguest_detach_disk
-                    exit 1
+                    return 2
                 fi
             fi
 
@@ -277,8 +307,7 @@ function xenguest_disk_init()
                         *)
                             # invalid/unknown compression type
                             echo "${PREF} Invalid file format in disk ${content}"
-                            xenguest_detach_disk
-                            exit 1
+                            return 2
                             ;;
                     esac
                     # dd into partition
@@ -288,8 +317,7 @@ function xenguest_disk_init()
                         | ${decompress} | dd of=/dev/xvda${part} >> ${LOGFILE} 2>&1
                     if [ $? -ne 0 ]; then
                         echo "${PREF} Cannot populate partition ${part}"
-                        xenguest_detach_disk
-                        exit 1
+                        return 2
                     fi
                     ;;
                 *.tar*)
@@ -310,8 +338,7 @@ function xenguest_disk_init()
                         *)
                             # invalid/unknown tar type
                             echo "${PREF} Invalid file format in disk ${content}"
-                            xenguest_detach_disk
-                            exit 1
+                            return 2
                             ;;
                     esac
 
@@ -321,9 +348,8 @@ function xenguest_disk_init()
                     mount /dev/xvda${part} ${mntdir} >> ${LOGFILE} 2>&1
                     if [ $? -ne 0 ]; then
                         echo "${PREF} Cannot mount partition ${part}"
-                        xenguest_detach_disk
                         rm -rf ${mntdir}
-                        exit 1
+                        return 2
                     fi
 
                     # tar and unmount
@@ -336,16 +362,14 @@ function xenguest_disk_init()
                         echo "${PREF} Cannot populate partition ${part}"
                         umount ${mntdir}
                         rm -rf ${mntdir}
-                        xenguest_detach_disk
-                        exit 1
+                        return 2
                     fi
                     echo "umount ${mntdir}" >> ${LOGFILE} 2>&1
                     umount ${mntdir} >> ${LOGFILE} 2>&1
                     if [ $? -ne 0 ]; then
                         echo "${PREF} Error unmounting ${part}"
-                        xenguest_detach_disk
                         rm -rf ${mntdir}
-                        exit 1
+                        return 2
                     fi
                     rm -rf ${mntdir}
                     ;;
@@ -356,6 +380,9 @@ function xenguest_disk_init()
 
             # Detach disk
             xenguest_detach_disk
+            if [ $? -ne 0 ]; then
+                return 1
+            fi
         fi
     done
 
@@ -392,10 +419,21 @@ function xenguest_guest_create()
         --xen-name=${guestname} >> ${LOGFILE} 2>&1
     if [ $? -ne 0 ]; then
         echo "${PREF} Error setting guest name"
+        xenguest_guest_remove ${guestname}
         exit 1
     fi
 
     xenguest_disk_init ${guestname} ${guestfile}
+    disk_init_status=$?
+    if [ $disk_init_status -ne 0 ]; then
+        echo "${PREF} Error: ${guestname} disk creation failed."
+        if [ $disk_init_status -eq 2 ]; then
+            xenguest_detach_disk
+        fi
+        xenguest_guest_remove ${guestname}
+        exit 1
+    fi
+
 }
 
 function xenguest_guest_remove()
@@ -408,6 +446,7 @@ function xenguest_guest_remove()
     lvs ${XENGUEST_VOLUME_NAME}/${guestname} >> ${LOGFILE} 2>&1
     if [ $? -eq 0 ]; then
         # Remove guest volume
+        echo "${PREF} Removing ${guestname} volume. This might take a while..."
         echo "lvremove -y ${devname}" >> ${LOGFILE} 2>&1
         lvremove -y ${devname} >> ${LOGFILE} 2>&1
         if [ $? -ne 0 ]; then
@@ -417,6 +456,7 @@ function xenguest_guest_remove()
     fi
 
     # remove guest files
+    echo "${PREF} Removing ${guestname} configuration files."
     rm -rf ${XENGUEST_CONF_BASE}/guests/${guestname}
 }
 
@@ -566,6 +606,24 @@ case ${cmd} in
         usage
         exit 0
         ;;
+
+esac
+
+# Check if we have a valid Dom0 booted with Xen
+ERROR_MSG=$(xl info 2>&1)
+if [ $? -ne 0 ]; then
+    echo "ERROR: Xen environment is not valid!!!" | tee -a ${LOGFILE}
+    echo "ERROR: Check if Xen has booted and the kernel configuration." \
+        | tee -a ${LOGFILE}
+    echo "ERROR: Output from 'xl info' command:" | tee -a ${LOGFILE}
+    echo "$ERROR_MSG" | tee -a ${LOGFILE}
+    exit 1
+fi
+
+case ${cmd} in
+    check-xen)
+        exit 0
+        ;;
     create)
         guestfile="${arg1}"
         guestname="${arg2}"
@@ -584,6 +642,7 @@ case ${cmd} in
         fi
 
         xenguest_guest_create ${guestfile} ${guestname}
+        echo "${PREF} ${guestname} created."
         ;;
     remove)
         guestname="${arg1:-}"
@@ -601,6 +660,7 @@ case ${cmd} in
             fi
         fi
         xenguest_guest_remove ${guestname}
+        echo "${PREF} ${guestname} removed."
         ;;
     start)
         guestname="${arg1:-}"

meta-arm-autonomy/recipes-extended/xenguest/xenguest-manager.bb

@@ -46,7 +46,7 @@ do_install() {
 }
 
 # Things that we need on the target
-RDEPENDS_${PN} += "bash tar xenguest-mkimage lvm2 xen-tools parted e2fsprogs"
+RDEPENDS_${PN} += "bash tar xenguest-mkimage lvm2 xen-tools parted e2fsprogs dosfstools"
 
 FILES_${PN} += "${bindir}/xenguest-manager \
                ${sysconfdir}/xenguest"

meta-arm-autonomy/recipes-extended/xenguest/xenguest-network-bridge.bb

@@ -9,7 +9,11 @@ S = "${WORKDIR}"
 # Please refer to documentation/xenguest-network-bridge.md for documentation on
 # those parameters
 XENGUEST_NETWORK_BRIDGE_NAME ?= "xenbr0"
-XENGUEST_NETWORK_BRIDGE_MEMBERS ?= "eth0"
+
+# The XENGUEST_NETWORK_BRIDGE_MEMBERS should be set in a machine.conf
+# or bbappend file.
+#XENGUEST_NETWORK_BRIDGE_MEMBERS ?= "eth0"
+
 XENGUEST_NETWORK_BRIDGE_CONFIG ?= "xenguest-network-bridge-dhcp.cfg.in"
 
 SRC_URI = " \

meta-arm-bsp/README.md

@@ -0,0 +1 @@
+See ../README.md

meta-arm-bsp/classes/image_types_disk_img.bbclass

@@ -51,7 +51,7 @@ disk_img_createpart() {
     local imagefile="$1"
     local start="$2"
     local size="$3"
-    local fstype="${4:-ext4}"
+    local fstype="${4:-}"
     local content="${5:-}"
     local formatargs=""
 

meta-arm-bsp/conf/layer.conf

@@ -9,5 +9,5 @@ BBFILE_COLLECTIONS += "meta-arm-bsp"
 BBFILE_PATTERN_meta-arm-bsp = "^${LAYERDIR}/"
 BBFILE_PRIORITY_meta-arm-bsp = "6"
 
-LAYERDEPENDS_meta-arm-bsp = "core openembedded-layer meta-arm"
+LAYERDEPENDS_meta-arm-bsp = "core openembedded-layer meta-arm meta-kernel"
 LAYERSERIES_COMPAT_meta-arm-bsp = "warrior zeus dunfell"

meta-arm-bsp/conf/machine/a5ds.conf

@@ -6,8 +6,8 @@
 
 require conf/machine/include/tune-cortexa5.inc
 
-PREFERRED_PROVIDER_virtual/kernel ?= "linux-upstream-arm"
-PREFERRED_VERSION_linux-upstream-arm ?= "5.3%"
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-stable"
+PREFERRED_VERSION_linux-stable ?= "5.3%"
 KBUILD_DEFCONFIG = "multi_v7_defconfig"
 
 EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-a u-boot"

meta-arm-bsp/conf/machine/n1sdp.conf

@@ -15,9 +15,25 @@ IMAGE_FSTYPES += "tar.bz2 ext4"
 
 SERIAL_CONSOLES = "115200;ttyAMA0"
 
+# Set default WKS
+WKS_FILE ?= "${@bb.utils.contains("EFI_PROVIDER", "systemd-boot", "systemd-bootdisk.wks", "mkefidisk.wks", d)}"
+
 # Use kernel provided by linaro (Contains support for SCMi or HDMI)
 PREFERRED_PROVIDER_virtual/kernel ?= "linux-linaro-arm"
 PREFERRED_VERSION_linux-linaro-arm ?= "5.4%"
 
 # RTL8168E Gigabit Ethernet Controller is attached to the PCIe interface
 MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "linux-firmware-rtl8168"
+
+# Trusted firmware v2.2 version
+PREFERRED_PROVIDER_virtual/trusted-firmware-a ?= "trusted-firmware-a"
+PREFERRED_VERSION_trusted-firmware-a ?= "2.2%"
+
+EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-a"
+EXTRA_IMAGEDEPENDS += "virtual/control-processor-firmware"
+
+#UEFI EDK2 firmware
+EXTRA_IMAGEDEPENDS += "virtual/uefi-firmware"
+
+#grub-efi
+EFI_PROVIDER ?= "grub-efi"

meta-arm-bsp/conf/machine/tc0.conf

@@ -0,0 +1,27 @@
+# Configuration for TC0
+
+#@TYPE: Machine
+#@NAME: TC0
+#@DESCRIPTION: Machine configuration for TC0
+
+TUNE_FEATURES = "aarch64"
+
+require conf/machine/include/arm/arch-armv8a.inc
+
+# Das U-boot
+UBOOT_MACHINE ?= "total_compute_defconfig"
+
+# Trusted firmware A v2.3
+PREFERRED_PROVIDER_virtual/trusted-firmware-a ?= "trusted-firmware-a"
+PREFERRED_VERSION_trusted-firmware-a ?= "2.3%"
+
+EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-a"
+
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-arm64-ack"
+
+# Cannot use the default zImage on arm64
+KERNEL_IMAGETYPE = "Image"
+KERNEL_BOOTCMD = "booti"
+IMAGE_FSTYPES += "cpio.gz.u-boot"
+
+SERIAL_CONSOLES = "115200;ttyAMA0"

meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware-n1sdp.inc

@@ -0,0 +1,32 @@
+# N1SDP specific SCP configurations and build instructions
+
+SRCREV_scp    = "fd7c83561a7d76c7681d5d017fb23aa3664c028c"
+SRCREV_cmsis  = "refs/tags/5.2.0"
+SCP_PLATFORM  = "n1sdp"
+SCP_LOG_LEVEL = "INFO"
+
+COMPATIBLE_MACHINE_n1sdp = "n1sdp"
+
+PV = "2.6+git${SRCPV}"
+
+DEPENDS += "fiptool-native"
+DEPENDS += "virtual/trusted-firmware-a"
+
+do_install_append() {
+   fiptool \
+       create \
+       --scp-fw "${D}/firmware/scp_ramfw.bin" \
+       --soc-fw "${RECIPE_SYSROOT}/firmware/bl31.bin" \
+       "scp_fw.bin"
+
+   fiptool \
+       create \
+       --blob uuid=54464222-a4cf-4bf8-b1b6-cee7dade539e,file="${D}/firmware/mcp_ramfw.bin" \
+       "mcp_fw.bin"
+
+   install "scp_fw.bin" "${D}/firmware/scp_fw.bin"
+   install "mcp_fw.bin" "${D}/firmware/mcp_fw.bin"
+
+   ln -sf "scp_romfw.bin" "${D}/firmware/scp_rom.bin"
+   ln -sf "mcp_romfw.bin" "${D}/firmware/mcp_rom.bin"
+}

meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware-tc0.inc

@@ -0,0 +1,13 @@
+# TC0 specicif SCP configuration
+
+# Intermediate SHA with 2.6 baseline version
+SRCREV_scp    = "ba1db5fb0ee4a520836722f7a694177d461ab716"
+# 5.2.0 tag commit
+SRCREV_cmsis  = "80cc44bba16cb4c8f495b7aa9709d41ac50e9529"
+
+COMPATIBLE_MACHINE = "tc0"
+
+SCP_PLATFORM = "tc0"
+FW_TARGETS = "scp"
+
+PV = "2.6+git${SRCPV}"

meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware_git.bbappend

@@ -0,0 +1,8 @@
+# Include machine specific SCP configurations
+
+MACHINE_SCP_REQUIRE ?= ""
+
+MACHINE_SCP_REQUIRE_n1sdp = "scp-firmware-n1sdp.inc"
+MACHINE_SCP_REQUIRE_tc0 = "scp-firmware-tc0.inc"
+
+require ${MACHINE_SCP_REQUIRE}

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/a5ds/0001-plat-arm-a5ds-move-dtb-to-a-new-address.patch

@@ -1,31 +0,0 @@
-From d3cadbc6f1060020960dc05af0465db919bbbe2b Mon Sep 17 00:00:00 2001
-From: Rui Miguel Silva <rui.silva@linaro.org>
-Date: Fri, 30 Aug 2019 13:38:44 +0100
-Subject: [PATCH] plat/arm: a5ds: move dtb to a new address
-
-When Using bigger kernel images (>8.4MB compressed zImage) and at
-decompress and final location init stage of kernel start makes it
-override dtb at this address, to avoid this move the dtb a little
-higher in address related.
-
-Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
----
- plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
-index 9ab2d9656600..c616ff772237 100644
---- a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
-+++ b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
-@@ -10,7 +10,7 @@
-       /* Platform Config */
-       plat_arm_bl2 {
-               compatible = "arm,tb_fw";
--              hw_config_addr = <0x0 0x82000000>;
-+              hw_config_addr = <0x0 0x83000000>;
-               hw_config_max_size = <0x01000000>;
-               /* Disable authentication for development */
-               disable_auth = <0x0>;
---
-2.22.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/n1sdp/0001-n1sdp-arm-tf-disable-workaround-for-N1-Erratum-13157.patch

@@ -0,0 +1,46 @@
+From 76847eb46e77d094eb8611760dd1ab880f617321 Mon Sep 17 00:00:00 2001
+From: James Yang <James.Yang@arm.com>
+Date: Wed, 4 Sep 2019 10:49:45 -0500
+Subject: [PATCH] n1sdp/arm-tf: disable workaround for N1 Erratum 1315703 and
+ Spectre v4
+
+This patch disables the workaround for Erratum 1315703 so that the N1 CPU
+performance in the N1 SDP better reflects that of released versions of the
+N1 for software that does not require mitigation for Spectre Variant 4.
+
+N1 SDP uses N1 version r1p0, which is affected by Erratum 1315703, which
+is fixed in N1 r3p1.  The workaround for r1p0 disables the CPU performance
+feature of bypassing of stores by younger loads.  This can significantly
+affect performance.  The Erratum is classified "Cat A (Rare)" and requires
+a specific sequence of events to occur.
+
+Disabling this CPU performance feature is also the mitigation for Spectre
+Variant 4 (CVE-2018-3639).  On CPUs that provide the PSTATE.SBSS feature,
+the OS selectively applies the mitigation only to programs that require it,
+leaving the performance of other programs unaffected.  However, N1 r1p0
+does not have the PSTATE.SBSS feature (which is introduced in N1 r3p1), and
+Arm-TF does not provide the interface to to dynamically disable the CPU
+performance feature.  Therefore, applying the workaround penalizes ALL
+software running on N1 SDP, including those that do not require mitigation.
+
+This patch is meant for performance evaluation purposes ONLY and should not
+be used for software that requires a seccomp computing environment.
+
+Signed-off-by: James Yang <James.Yang@arm.com>
+---
+ plat/arm/board/n1sdp/platform.mk | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
+index 986bd70a..7e30c857 100644
+--- a/plat/arm/board/n1sdp/platform.mk
++++ b/plat/arm/board/n1sdp/platform.mk
+@@ -66,3 +66,5 @@ include plat/arm/common/arm_common.mk
+ include plat/arm/css/common/css_common.mk
+ include plat/arm/board/common/board_common.mk
+ 
++# N1SDP: disable workaround for Errata 1315703 and global Spectre v4 mitigation
++override ERRATA_N1_1315703 := 0
+-- 
+2.17.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-a5ds.inc

@@ -7,9 +7,6 @@ TFA_UBOOT = "1"
 TFA_BUILD_TARGET = "all fip"
 TFA_INSTALL_TARGET = "bl1.bin fip.bin"
 
-SRCREV = "5d3ee0764b03567bf3501edf47d67d72daff0cb3"
-LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031"
-
 EXTRA_OEMAKE_append = " \
                     ARCH=aarch32 \
                     FVP_HW_CONFIG_DTS=fdts/a5ds.dts \
@@ -18,5 +15,3 @@ EXTRA_OEMAKE_append = " \
                     ARM_CORTEX_A5=yes \
                     ARM_XLAT_TABLES_LIB_V1=1 \
                     "
-
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-n1sdp.inc

@@ -0,0 +1,12 @@
+# N1SDP specific TFA support
+
+COMPATIBLE_MACHINE = "n1sdp"
+TFA_PLATFORM       = "n1sdp"
+TFA_BUILD_TARGET   = "bl31"
+TFA_DEBUG          = "1"
+TFA_MBEDTLS        = "0"
+TFA_UBOOT          = "0"
+
+SRC_URI_append = " \
+    file://0001-n1sdp-arm-tf-disable-workaround-for-N1-Erratum-13157.patch \
+    "

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-tc0.inc

@@ -0,0 +1,21 @@
+# TCO specific TFA configuration
+
+# Intermediate SHA with 2.3 baseline version
+SRCREV_tfa = "2fe7d18b0d99fdf4c4dbf84863bb2036dfebc537"
+
+SRC_URI_append = " ${SRC_URI_MBEDTLS}"
+
+DEPENDS += "scp-firmware"
+
+COMPATIBLE_MACHINE = "tc0"
+
+TFA_PLATFORM = "tc0"
+TFA_BUILD_TARGET = "all fip"
+TFA_UBOOT = "1"
+TFA_INSTALL_TARGET = "bl1 fip"
+TFA_MBEDTLS = "1"
+TFA_DEBUG = "1"
+
+EXTRA_OEMAKE += "SCP_BL2=${RECIPE_SYSROOT}/firmware/scp_ramfw.bin"
+EXTRA_OEMAKE += "MBEDTLS_DIR=mbedtls TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \
+                     ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem"

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.%.bbappend

@@ -1,9 +1,3 @@
-# Machine specific TFAs
+FILESEXTRAPATHS_prepend := "${THISDIR}/files/:"
 
-MACHINE_TFA_REQUIRE ?= ""
-
-MACHINE_TFA_REQUIRE_foundation-armv8 = "trusted-firmware-a-fvp.inc"
-MACHINE_TFA_REQUIRE_fvp-base = "trusted-firmware-a-fvp.inc"
-MACHINE_TFA_REQUIRE_juno = "trusted-firmware-a-juno.inc"
-
-require ${MACHINE_TFA_REQUIRE}
+# Don't put machine customisation in here, use a versioned append.

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.1.bbappend

@@ -1,7 +1,6 @@
 # Machine specific TFAs
 
 MACHINE_TFA_REQUIRE ?= ""
-
-MACHINE_TFA_REQUIRE_a5ds = "trusted-firmware-a-a5ds.inc"
+MACHINE_TFA_REQUIRE_juno = "trusted-firmware-a-juno.inc"
 
 require ${MACHINE_TFA_REQUIRE}

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.2.bbappend

@@ -0,0 +1,11 @@
+# Machine specific TFAs
+
+MACHINE_TFA_REQUIRE ?= ""
+MACHINE_TFA_REQUIRE_n1sdp = "trusted-firmware-a-n1sdp.inc"
+
+require ${MACHINE_TFA_REQUIRE}
+
+# TFA referred in release tag N1SDP-2020.03.26
+SRCREV_tfa_n1sdp = "cfb3f73344217aa000aaff9d84baad7527af75bf"
+
+PV_n1sdp = "2.2+git${SRCPV}"

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.3.bbappend

@@ -0,0 +1,9 @@
+# Machine specific TFAs
+
+MACHINE_TFA_REQUIRE ?= ""
+MACHINE_TFA_REQUIRE_tc0 = "trusted-firmware-a-tc0.inc"
+MACHINE_TFA_REQUIRE_a5ds = "trusted-firmware-a-a5ds.inc"
+MACHINE_TFA_REQUIRE_foundation-armv8 = "trusted-firmware-a-fvp.inc"
+MACHINE_TFA_REQUIRE_fvp-base = "trusted-firmware-a-fvp.inc"
+
+require ${MACHINE_TFA_REQUIRE}

meta-arm-bsp/recipes-bsp/u-boot/files/tc0/0001-Add-support-for-Total-Compute.patch

@@ -0,0 +1,307 @@
+From 854c5d7b8a010d47da38735f15a31d0b7d10ae3c Mon Sep 17 00:00:00 2001
+From: Usama Arif <usama.arif@arm.com>
+Date: Fri, 3 Jul 2020 10:26:56 +0100
+Subject: [PATCH] Add support for Total Compute
+
+This includes basic platform patch support and boots
+kernel and ramdisk that have been sideloaded in DRAM.
+
+Change-Id: I2e35a1d983efd1d27572f671cad5a9fe4ad68ee6
+Signed-off-by: Usama Arif <usama.arif@arm.com>
+Upstream-Status: Pending
+---
+ arch/arm/Kconfig                         |  9 +++
+ board/armltd/totalcompute/Kconfig        | 12 ++++
+ board/armltd/totalcompute/MAINTAINERS    |  6 ++
+ board/armltd/totalcompute/Makefile       |  6 ++
+ board/armltd/totalcompute/totalcompute.c | 74 +++++++++++++++++++++++
+ configs/total_compute_defconfig          | 39 ++++++++++++
+ include/configs/total_compute.h          | 77 ++++++++++++++++++++++++
+ 7 files changed, 223 insertions(+)
+ create mode 100644 board/armltd/totalcompute/Kconfig
+ create mode 100644 board/armltd/totalcompute/MAINTAINERS
+ create mode 100644 board/armltd/totalcompute/Makefile
+ create mode 100644 board/armltd/totalcompute/totalcompute.c
+ create mode 100644 configs/total_compute_defconfig
+ create mode 100644 include/configs/total_compute.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 36c9c2fecd0..b423b7655b6 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -635,6 +635,14 @@ config TARGET_VEXPRESS_CA15_TC2
+ 	select CPU_V7_HAS_VIRT
+ 	select PL011_SERIAL
+ 
++config TARGET_TOTAL_COMPUTE
++	bool "Support Total Compute Platform"
++	select ARM64
++	select PL01X_SERIAL
++	select DM
++	select DM_SERIAL
++	select DM_ETH
++
+ config ARCH_BCMSTB
+ 	bool "Broadcom BCM7XXX family"
+ 	select CPU_V7A
+@@ -1774,6 +1782,7 @@ source "arch/arm/cpu/armv8/Kconfig"
+ 
+ source "arch/arm/mach-imx/Kconfig"
+ 
++source "board/armltd/totalcompute/Kconfig"
+ source "board/bosch/shc/Kconfig"
+ source "board/bosch/guardian/Kconfig"
+ source "board/CarMediaLab/flea3/Kconfig"
+diff --git a/board/armltd/totalcompute/Kconfig b/board/armltd/totalcompute/Kconfig
+new file mode 100644
+index 00000000000..8bd8c30a6b5
+--- /dev/null
++++ b/board/armltd/totalcompute/Kconfig
+@@ -0,0 +1,12 @@
++if TARGET_TOTAL_COMPUTE
++
++config SYS_BOARD
++	default "totalcompute"
++
++config SYS_VENDOR
++	default "armltd"
++
++config SYS_CONFIG_NAME
++	default "total_compute"
++
++endif
+diff --git a/board/armltd/totalcompute/MAINTAINERS b/board/armltd/totalcompute/MAINTAINERS
+new file mode 100644
+index 00000000000..bb09a90a309
+--- /dev/null
++++ b/board/armltd/totalcompute/MAINTAINERS
+@@ -0,0 +1,6 @@
++TOTAL_COMPUTE BOARD
++M:	Usama Arif <usama.arif@arm.com>
++S:	Maintained
++F:	board/armltd/totalcompute/
++F:	include/configs/total_compute.h
++F:	configs/total_compute_defconfig
+diff --git a/board/armltd/totalcompute/Makefile b/board/armltd/totalcompute/Makefile
+new file mode 100644
+index 00000000000..4c40afef723
+--- /dev/null
++++ b/board/armltd/totalcompute/Makefile
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0+
++#
++# (C) Copyright 2020 ARM Limited
++# Usama Arif <usama.arif@arm.com>
++
++obj-y	:= totalcompute.o
+diff --git a/board/armltd/totalcompute/totalcompute.c b/board/armltd/totalcompute/totalcompute.c
+new file mode 100644
+index 00000000000..21247e4ef0f
+--- /dev/null
++++ b/board/armltd/totalcompute/totalcompute.c
+@@ -0,0 +1,74 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * (C) Copyright 2020 ARM Limited
++ * Usama Arif <usama.arif@arm.com>
++ */
++#include <common.h>
++#include <dm.h>
++#include <init.h>
++#include <malloc.h>
++#include <errno.h>
++#include <netdev.h>
++#include <asm/io.h>
++#include <linux/compiler.h>
++#include <dm/platform_data/serial_pl01x.h>
++#include <asm/armv8/mmu.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++static const struct pl01x_serial_platdata serial_platdata = {
++	.base = UART0_BASE,
++	.type = TYPE_PL011,
++	.clock = CONFIG_PL011_CLOCK,
++};
++
++U_BOOT_DEVICE(total_compute_serials) = {
++	.name = "serial_pl01x",
++	.platdata = &serial_platdata,
++};
++
++static struct mm_region total_compute_mem_map[] = {
++	{
++		.virt = 0x0UL,
++		.phys = 0x0UL,
++		.size = 0x80000000UL,
++		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
++			 PTE_BLOCK_NON_SHARE |
++			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
++	}, {
++		.virt = 0x80000000UL,
++		.phys = 0x80000000UL,
++		.size = 0xff80000000UL,
++		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
++			 PTE_BLOCK_INNER_SHARE
++	}, {
++		/* List terminator */
++		0,
++	}
++};
++
++struct mm_region *mem_map = total_compute_mem_map;
++
++int board_init(void)
++{
++	return 0;
++}
++
++int dram_init(void)
++{
++	gd->ram_size = PHYS_SDRAM_1_SIZE;
++	return 0;
++}
++
++int dram_init_banksize(void)
++{
++	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
++
++	return 0;
++}
++
++void reset_cpu(ulong addr)
++{
++}
++
+diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig
+new file mode 100644
+index 00000000000..31d97dddc21
+--- /dev/null
++++ b/configs/total_compute_defconfig
+@@ -0,0 +1,39 @@
++CONFIG_ARM=y
++CONFIG_TARGET_TOTAL_COMPUTE=y
++CONFIG_SYS_TEXT_BASE=0xe0000000
++CONFIG_SYS_MALLOC_F_LEN=0x2000
++CONFIG_ENV_SIZE=0x10000
++CONFIG_NR_DRAM_BANKS=2
++CONFIG_DISTRO_DEFAULTS=y
++CONFIG_BOOTDELAY=1
++CONFIG_USE_BOOTARGS=y
++CONFIG_BOOTARGS="console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute video=640x480-32@60 root=/dev/vda2 ip=dhcp androidboot.selinux=permissive"
++# CONFIG_USE_BOOTCOMMAND is not set
++# CONFIG_DISPLAY_CPUINFO is not set
++# CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_SYS_PROMPT="TOTAL_COMPUTE# "
++# CONFIG_CMD_CONSOLE is not set
++# CONFIG_CMD_XIMG is not set
++# CONFIG_CMD_EDITENV is not set
++CONFIG_CMD_MEMTEST=y
++CONFIG_SYS_MEMTEST_START=0x80000000
++CONFIG_SYS_MEMTEST_END=0xff000000
++CONFIG_CMD_ARMFLASH=y
++# CONFIG_CMD_LOADS is not set
++# CONFIG_CMD_ITEST is not set
++# CONFIG_CMD_SETEXPR is not set
++# CONFIG_CMD_NFS is not set
++CONFIG_CMD_CACHE=y
++# CONFIG_CMD_MISC is not set
++CONFIG_CMD_UBI=y
++# CONFIG_ISO_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++# CONFIG_MMC is not set
++CONFIG_MTD=y
++CONFIG_MTD_DEVICE=y
++CONFIG_MTD_NOR_FLASH=y
++CONFIG_FLASH_CFI_DRIVER=y
++CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
++CONFIG_SYS_FLASH_PROTECTION=y
++CONFIG_SYS_FLASH_CFI=y
++CONFIG_OF_LIBFDT=y
+diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h
+new file mode 100644
+index 00000000000..54086205db6
+--- /dev/null
++++ b/include/configs/total_compute.h
+@@ -0,0 +1,77 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Configuration for Total Compute. Parts were derived from other ARM
++ * configurations.
++ * (C) Copyright 2020 ARM Limited
++ * Usama Arif <usama.arif@arm.com>
++ */
++
++#ifndef __TOTAL_COMPUTE_H
++#define __TOTAL_COMPUTE_H
++
++#define CONFIG_REMAKE_ELF
++
++/* Link Definitions */
++#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
++#define CONFIG_ENV_SIZE	0x10000
++
++
++#define CONFIG_SYS_BOOTM_LEN (64 << 20)
++
++#define UART0_BASE			0x7ff80000
++
++/* Generic Timer Definitions */
++#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
++
++/* Generic Interrupt Controller Definitions */
++
++#define GICD_BASE			(0x2C010000)
++#define GICC_BASE			(0x2C02f000)
++
++/* Size of malloc() pool */
++#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))
++
++/* PL011 Serial Configuration */
++#define CONFIG_PL011_CLOCK		7372800
++
++/* BOOTP options */
++#define CONFIG_BOOTP_BOOTFILESIZE
++
++/* Miscellaneous configurable options */
++#define CONFIG_SYS_LOAD_ADDR		0x90000000
++
++/* Physical Memory Map */
++#define PHYS_SDRAM_1			0x80000000
++/* Top 32MB reserved for secure world use */
++#define DRAM_SEC_SIZE		0x02000000
++#define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
++#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
++
++/* Enable memtest */
++#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
++#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
++
++#define CONFIG_EXTRA_ENV_SETTINGS	\
++				"kernel_addr_r=0x80080000\0"	\
++				"initrd_addr_r=0x88000000\0"	\
++				"fdt_addr_r=0x83000000\0"	\
++				"fdt_high=0xffffffffffffffff\0"	\
++				"initrd_high=0xffffffffffffffff\0"
++
++#define CONFIG_BOOTCOMMAND	"booti ${kernel_addr_r} ${initrd_addr_r} ${fdt_addr_r}"
++
++/* Monitor Command Prompt */
++#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
++#define CONFIG_SYS_MAXARGS		64	/* max command args */
++
++#define CONFIG_SYS_FLASH_BASE		0x0C000000
++/* 256 x 256KiB sectors */
++#define CONFIG_SYS_MAX_FLASH_SECT	256
++
++#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
++#define CONFIG_SYS_MAX_FLASH_BANKS	1
++
++#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
++#define FLASH_MAX_SECTOR_SIZE		0x00040000
++
++#endif /* __TOTAL_COMPUTE_H */
+-- 
+2.17.1
+

meta-arm-bsp/recipes-bsp/u-boot/u-boot-tc0.inc

@@ -0,0 +1,3 @@
+# TC0 specific Das U-Boot configuration and patch
+
+SRC_URI_append = ' file://0001-Add-support-for-Total-Compute.patch'

meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend

@@ -5,4 +5,8 @@ FILESEXTRAPATHS_prepend := "${THISDIR}/files/${MACHINE}:"
 SRC_URI_append_a5ds = " file://0001-armv7-add-mmio-timer.patch \
                     file://0002-board-arm-add-designstart-cortex-a5-board.patch"
 
+MACHINE_UBOOT_REQUIRE ?= ""
 
+MACHINE_UBOOT_REQUIRE_tc0 = "u-boot-tc0.inc"
+
+require ${MACHINE_UBOOT_REQUIRE}

meta-arm-bsp/recipes-bsp/uefi/edk2-firmware-n1sdp.inc

@@ -0,0 +1,19 @@
+SRC_URI = "\
+    git://git.linaro.org/landing-teams/working/arm/edk2.git;name=edk2;destsuffix=git/edk2;nobranch=1 \
+    git://git.linaro.org/landing-teams/working/arm/edk2-platforms.git;name=edk2-platforms;destsuffix=git/edk2/edk2-platforms;nobranch=1 \
+"
+
+# TAGS and commit ID as per N1SDP-2020.03.26 release
+SRCREV_edk2           = "3ff8a6bffabad761279817252014d59b6069d68a"
+SRCREV_edk2-platforms = "b6bfc4417ff13168d69c4cbf2338f62c89c82dfd"
+
+# N1SDP specific EDK2 configurations
+EDK2_BUILD_RELEASE = "0"
+EDK2_PLATFORM      = "n1sdp"
+EDK2_PLATFORM_DSC  = "N1SdpPkg/N1SdpPlatform.dsc"
+EDK2_BIN_NAME      = "BL33_AP_UEFI.fd"
+EDK2_ARCH          = "AARCH64"
+
+COMPATIBLE_MACHINE = "n1sdp"
+
+PV = "201908+git${SRCPV}"

meta-arm-bsp/recipes-bsp/uefi/edk2-firmware_git.bbappend

@@ -0,0 +1,7 @@
+# Include machine specific configurations for UEFI EDK2
+
+MACHINE_EDK2_REQUIRE ?= ""
+
+MACHINE_EDK2_REQUIRE_n1sdp = "edk2-firmware-n1sdp.inc"
+
+require ${MACHINE_EDK2_REQUIRE}

meta-arm-bsp/recipes-core/init-ifupdown/init-ifupdown_1.0.bbappend

@@ -3,5 +3,6 @@
 #
 # Enable second network interface on startup
 #
+PACKAGE_ARCH = "${MACHINE_ARCH}"
 
-FILESEXTRAPATHS_prepend_juno := "${THISDIR}/files/juno:"
+FILESEXTRAPATHS_prepend := "${THISDIR}/files:"

meta-arm-bsp/recipes-devtools/gem5/gem5-aarch64-bootloader.inc

@@ -5,10 +5,12 @@ LICENSE = "BSD"
 
 inherit deploy
 
-PROVIDES = "virtual/gem5-bootloader"
+PROVIDES += "virtual/gem5-bootloader"
 
 COMPATIBLE_MACHINE = "gem5-arm64"
 
+BOOTLOADER_SRC_PATH ?= "${S}/system/arm/bootloader/arm64"
+
 # no configure step
 do_configure[noexec] = "1"
 
@@ -16,11 +18,11 @@ do_configure[noexec] = "1"
 do_install[noexec] = "1"
 
 do_compile() {
-    oe_runmake -C system/arm/aarch64_bootloader all CROSS_COMPILE=${TARGET_PREFIX}
+    oe_runmake -C ${BOOTLOADER_SRC_PATH} all CROSS_COMPILE=${TARGET_PREFIX}
 }
 
 do_deploy() {
-    oe_runmake -C system/arm/aarch64_bootloader install \
+    oe_runmake -C ${BOOTLOADER_SRC_PATH} install \
         CROSS_COMPILE=${TARGET_PREFIX} DESTDIR=${DEPLOYDIR}/binaries
 }
 

meta-arm-bsp/recipes-devtools/gem5/gem5-aarch64-bootloader_20.bb

@@ -3,16 +3,14 @@
 LIC_FILES_CHKSUM = "file://COPYING;md5=2d9514d69d8abf88b6e9125e759bf0ab \
                     file://LICENSE;md5=a585e2893cee63d16a1d8bc16c6297ec"
 
-# The recipe is currently using a version in the release staging branch of gem5
-# until version 20 is released
-SRC_URI = "git://gem5.googlesource.com/public/gem5;protocol=https;branch=release-staging-v20.0.0.0"
+SRC_URI = "git://gem5.googlesource.com/public/gem5;protocol=https;nobranch=1"
+RELEASE_TAG = "v20.0.0.1"
+SRCREV = "332a9de33db603e0aefedae1e05134db4257ea3e"
 
-PV = "git${SRCPV}"
+PV = "${RELEASE_TAG}"
 
 S = "${WORKDIR}/git"
 
-SRCREV = "0bc5d77ed27e0765953d93c2376a4b4aea675a01"
-
 BPN = "gem5-aarch64-bootloader"
 
 require gem5-aarch64-bootloader.inc

meta-arm-bsp/recipes-devtools/gem5/gem5-aarch64-native/0001-scons-Add-MARSHAL_XXFLAGS_EXTRA-for-the-marshal-object.patch

@@ -0,0 +1,85 @@
+From 1303d0497bad151f9389ee30c37dc5f9fe325f6e Mon Sep 17 00:00:00 2001
+From: Giacomo Travaglini <giacomo.travaglini@arm.com>
+Date: Thu, 04 Jun 2020 12:45:52 +0100
+Subject: [PATCH] scons: Add MARSHAL_XXFLAGS_EXTRA for the marshal object
+
+We already provide to the user the CCFLAGS_EXTRA, LDFLAGS_EXTRA
+variables to pass flags to scons when compiling/linking gem5.
+Those variables are not passed to the marshal object.
+We add an extra pair:
+
+MARSHAL_CCFLAGS_EXTRA, MARSHAL_LDFLAGS_EXTRA
+
+to add flag injection capabilities to the marshal object.
+
+The patch is also renaming base_py_env to marshal_env.
+This happens for 2 reasons:
+
+1) At the moment the marshal compilation is the only task
+making use of the base python environment.
+
+2) Consistency with the EXTRA variable names added with this patch.
+I could have named them as BASE_XXFLAGS_EXTRA, but it seems too much
+generic and users might be confused by that, as they might think
+the BASE_XXFLAGS_EXTRA is a subset of the XXFLAGS_EXTRA so that
+setting it will affect gem5 compilation as well.
+
+Change-Id: I3e420caa897059455ff8f35462db2b38da050e93
+Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
+---
+
+diff --git a/SConstruct b/SConstruct
+index 3a03af4..5a66bba 100755
+--- a/SConstruct
++++ b/SConstruct
+@@ -276,6 +276,8 @@
+     ('CXX', 'C++ compiler', environ.get('CXX', main['CXX'])),
+     ('CCFLAGS_EXTRA', 'Extra C and C++ compiler flags', ''),
+     ('LDFLAGS_EXTRA', 'Extra linker flags', ''),
++    ('MARSHAL_CCFLAGS_EXTRA', 'Extra C and C++ marshal compiler flags', ''),
++    ('MARSHAL_LDFLAGS_EXTRA', 'Extra marshal linker flags', ''),
+     ('PYTHON_CONFIG', 'Python config binary to use',
+      [ 'python2.7-config', 'python-config', 'python3-config' ]),
+     ('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
+@@ -734,7 +736,9 @@
+ 
+ main.Prepend(CPPPATH=Dir('ext/pybind11/include/'))
+ # Bare minimum environment that only includes python
+-base_py_env = main.Clone()
++marshal_env = main.Clone()
++marshal_env.Append(CCFLAGS='$MARSHAL_CCFLAGS_EXTRA')
++marshal_env.Append(LINKFLAGS='$MARSHAL_LDFLAGS_EXTRA')
+ 
+ # On Solaris you need to use libsocket for socket ops
+ if not conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
+@@ -1285,7 +1289,7 @@
+     # to the configured variables.  It returns a list of environments,
+     # one for each variant build (debug, opt, etc.)
+     SConscript('src/SConscript', variant_dir=variant_path,
+-               exports=['env', 'base_py_env'])
++               exports=['env', 'marshal_env'])
+ 
+ # base help text
+ Help('''
+diff --git a/src/SConscript b/src/SConscript
+index 7cd628a..aa233c8 100644
+--- a/src/SConscript
++++ b/src/SConscript
+@@ -1140,7 +1140,7 @@
+ # Build a small helper that marshals the Python code using the same
+ # version of Python as gem5. This is in an unorthodox location to
+ # avoid building it for every variant.
+-py_marshal = base_py_env.Program('marshal', 'python/marshal.cc')[0]
++py_marshal = marshal_env.Program('marshal', 'python/marshal.cc')[0]
+ 
+ # Embed python files.  All .py files that have been indicated by a
+ # PySource() call in a SConscript need to be embedded into the M5
+@@ -1196,7 +1196,7 @@
+     code.write(str(target[0]))
+ 
+ for source in PySource.all:
+-    base_py_env.Command(source.cpp, [ py_marshal, source.tnode ],
++    marshal_env.Command(source.cpp, [ py_marshal, source.tnode ],
+                         MakeAction(embedPyFile, Transform("EMBED PY")))
+     Source(source.cpp, tags=source.tags, add_tags='python')
+ 

meta-arm-bsp/recipes-devtools/gem5/gem5-aarch64-native/0002-arch-arm-Introduce-HavePACExt-helper.patch

@@ -0,0 +1,55 @@
+Upstream-Status: Backport [https://gem5.googlesource.com/public/gem5/+/6d15745532df2dd306ecc15bd0e9f79914be1682]
+Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
+
+From 6d15745532df2dd306ecc15bd0e9f79914be1682 Mon Sep 17 00:00:00 2001
+From: Giacomo Travaglini <giacomo.travaglini@arm.com>
+Date: Tue, 25 Aug 2020 12:15:17 +0100
+Subject: [PATCH] arch-arm: Introduce HavePACExt helper
+
+This will check for presence of pointer authentication extension.
+According to the reference manual, Pointer authentication is
+implemented if the value of at least one of
+
+ID_AA64ISAR1_EL1.{APA, API, GPA, GPI}
+
+is not 0b0000.
+
+Change-Id: I4e98e65758e8edc953794e5b618d2c6c3f6000ae
+Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
+Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33454
+Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
+Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
+Tested-by: kokoro <noreply+kokoro@google.com>
+---
+
+diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
+index ad0a3da..a189c4a 100644
+--- a/src/arch/arm/utility.cc
++++ b/src/arch/arm/utility.cc
+@@ -315,6 +315,14 @@
+ }
+ 
+ bool
++HavePACExt(ThreadContext *tc)
++{
++    AA64ISAR1 id_aa64isar1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
++    return id_aa64isar1.api | id_aa64isar1.apa |
++        id_aa64isar1.gpi | id_aa64isar1.gpa;
++}
++
++bool
+ HaveVirtHostExt(ThreadContext *tc)
+ {
+     AA64MMFR1 id_aa64mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
+diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
+index f00f606..f17ebc5 100644
+--- a/src/arch/arm/utility.hh
++++ b/src/arch/arm/utility.hh
+@@ -151,6 +151,7 @@
+     return opModeToEL((OperatingMode) (uint8_t)cpsr.mode);
+ }
+ 
++bool HavePACExt(ThreadContext *tc);
+ bool HaveVirtHostExt(ThreadContext *tc);
+ bool HaveSecureEL2Ext(ThreadContext *tc);
+ bool IsSecureEL2Enabled(ThreadContext *tc);

meta-arm-bsp/recipes-devtools/gem5/gem5-aarch64-native/0003-arch-arm-Check-if-PAC-is-implemented-before-executing-insts.patch

@@ -0,0 +1,174 @@
+Upstream-Status: Backport [https://gem5.googlesource.com/public/gem5/+/b50d61fb9ff5d94f401af98bb0b7f8e25d21d012]
+Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
+
+From b50d61fb9ff5d94f401af98bb0b7f8e25d21d012 Mon Sep 17 00:00:00 2001
+From: Giacomo Travaglini <giacomo.travaglini@arm.com>
+Date: Tue, 25 Aug 2020 13:10:23 +0100
+Subject: [PATCH] arch-arm: Check if PAC is implemented before executing insts
+
+If Armv8.3-PAuth (PAC) extension is not supported, most instrucions
+will trigger an Undefined Instruction fault; except for a group of
+them living in the HINT space; those should be treated as NOP.
+
+Change-Id: Idec920ed15e0310ec9132a3cb3701cdb7e7cf9d1
+Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
+Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33455
+Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
+Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
+Tested-by: kokoro <noreply+kokoro@google.com>
+---
+
+diff --git a/src/arch/arm/isa/insts/pauth.isa b/src/arch/arm/isa/insts/pauth.isa
+index 4c5b371..4806e6a 100644
+--- a/src/arch/arm/isa/insts/pauth.isa
++++ b/src/arch/arm/isa/insts/pauth.isa
+@@ -1,5 +1,6 @@
+ // -*- mode:c++ -*-
+ 
++// Copyright (c) 2020 ARM Limited
+ // Copyright (c) 2020 Metempsy Technology Consulting
+ // All rights reserved
+ //
+@@ -41,20 +42,39 @@
+     decoder_output = ""
+     exec_output = ""
+ 
++    def pacEnabledCode(hint):
++        if hint:
++            code = """
++                if (!HavePACExt(xc->tcBase())) {
++                    return NoFault;
++                }
++                """
++        else:
++            code = """
++                if (!HavePACExt(xc->tcBase())) {
++                    return std::make_shared<UndefinedInstruction>(
++                        machInst, true);
++                }
++                """
++        return code
+ 
+-    def buildPauthObject(mnem, templateBase, opcode, optArgs=[]):
++    def buildPauthObject(mnem, templateBase, opcode, hint, optArgs=[]):
+         global header_output, decoder_output, exec_output
+-        pac_code = '''//uint64_t val = 0;
+-                uint64_t res;
+-                fault = %(op)s(xc->tcBase(), %(op1)s, %(op2)s, &res);
+-                XDest = res;
+-                '''
++        pac_code = '''
++            %(enabled)s
++
++            uint64_t res;
++            fault = %(op)s(xc->tcBase(), %(op1)s, %(op2)s, &res);
++            XDest = res;
++            '''
+         if templateBase=='DataX2Reg':
+-            code = pac_code % {"op1": 'Op164',
++            code = pac_code % {"enabled": pacEnabledCode(hint),
++                               "op1": 'Op164',
+                                "op2": 'Op264',
+                                "op":  opcode }
+         else:
+-            code = pac_code % {"op1": 'XDest',
++            code = pac_code % {"enabled": pacEnabledCode(hint),
++                               "op1": 'XDest',
+                                "op2": 'Op164',
+                                "op":  opcode }
+ 
+@@ -63,13 +83,15 @@
+         decoder_output += eval(templateBase + "Constructor").subst(iop)
+         exec_output += BasicExecute.subst(iop)
+ 
+-    def buildXPauthObject(mnem, optArgs=[]):
++    def buildXPauthObject(mnem, hint, optArgs=[]):
+         global header_output, decoder_output, exec_output
+         templateBase = "XPauthOpRegReg"
+ 
+-        code =  'uint64_t res;\n'\
+-                'fault = stripPAC(xc->tcBase(), XDest, data, &res);\n'
+-        code += 'XDest = res;'
++        code = pacEnabledCode(hint) + """
++            uint64_t res;
++            fault = stripPAC(xc->tcBase(), XDest, data, &res);
++            XDest = res;
++            """
+         regoptype = 'RegOp'
+ 
+         iop = InstObjParams(mnem, mnem, regoptype, code, optArgs)
+@@ -78,42 +100,42 @@
+         exec_output += BasicExecute.subst(iop)
+ 
+ 
+-    buildPauthObject("Pacda",  "DataX1Reg", 'addPACDA')
+-    buildPauthObject("Pacdza", "DataX1Reg", 'addPACDA')
+-    buildPauthObject("Pacdb",  "DataX1Reg", 'addPACDB')
+-    buildPauthObject("Pacdzb", "DataX1Reg", 'addPACDB')
+-    buildPauthObject("Pacga",  "DataX2Reg", 'addPACGA')
++    buildPauthObject("Pacda",  "DataX1Reg", 'addPACDA', hint=False)
++    buildPauthObject("Pacdza", "DataX1Reg", 'addPACDA', hint=False)
++    buildPauthObject("Pacdb",  "DataX1Reg", 'addPACDB', hint=False)
++    buildPauthObject("Pacdzb", "DataX1Reg", 'addPACDB', hint=False)
++    buildPauthObject("Pacga",  "DataX2Reg", 'addPACGA', hint=False)
+ 
+-    buildPauthObject("Pacia",     "DataX1Reg", 'addPACIA')
+-    buildPauthObject("Pacia1716", "DataX1Reg", 'addPACIA')
+-    buildPauthObject("Paciasp",   "DataX1Reg", 'addPACIA')
+-    buildPauthObject("Paciaz",    "DataX1Reg", 'addPACIA')
+-    buildPauthObject("Paciza",    "DataX1Reg", 'addPACIA')
++    buildPauthObject("Pacia",     "DataX1Reg", 'addPACIA', hint=False)
++    buildPauthObject("Pacia1716", "DataX1Reg", 'addPACIA', hint=True)
++    buildPauthObject("Paciasp",   "DataX1Reg", 'addPACIA', hint=True)
++    buildPauthObject("Paciaz",    "DataX1Reg", 'addPACIA', hint=True)
++    buildPauthObject("Paciza",    "DataX1Reg", 'addPACIA', hint=False)
+ 
+-    buildPauthObject("Pacib",     "DataX1Reg", 'addPACIB')
+-    buildPauthObject("Pacib1716", "DataX1Reg", 'addPACIB')
+-    buildPauthObject("Pacibsp",   "DataX1Reg", 'addPACIB')
+-    buildPauthObject("Pacibz",    "DataX1Reg", 'addPACIB')
+-    buildPauthObject("Pacizb",    "DataX1Reg", 'addPACIB')
++    buildPauthObject("Pacib",     "DataX1Reg", 'addPACIB', hint=False)
++    buildPauthObject("Pacib1716", "DataX1Reg", 'addPACIB', hint=True)
++    buildPauthObject("Pacibsp",   "DataX1Reg", 'addPACIB', hint=True)
++    buildPauthObject("Pacibz",    "DataX1Reg", 'addPACIB', hint=True)
++    buildPauthObject("Pacizb",    "DataX1Reg", 'addPACIB', hint=False)
+ 
+-    buildPauthObject("Autda",     "DataX1Reg", 'authDA')
+-    buildPauthObject("Autdza",    "DataX1Reg", 'authDA')
+-    buildPauthObject("Autdb",     "DataX1Reg", 'authDB')
+-    buildPauthObject("Autdzb",    "DataX1Reg", 'authDB')
++    buildPauthObject("Autda",     "DataX1Reg", 'authDA', hint=False)
++    buildPauthObject("Autdza",    "DataX1Reg", 'authDA', hint=False)
++    buildPauthObject("Autdb",     "DataX1Reg", 'authDB', hint=False)
++    buildPauthObject("Autdzb",    "DataX1Reg", 'authDB', hint=False)
+ 
+-    buildPauthObject("Autia",     "DataX1Reg", 'authIA')
+-    buildPauthObject("Autia1716", "DataX1Reg", 'authIA')
+-    buildPauthObject("Autiasp",   "DataX1Reg", 'authIA')
+-    buildPauthObject("Autiaz",    "DataX1Reg", 'authIA')
+-    buildPauthObject("Autiza",    "DataX1Reg", 'authIA')
++    buildPauthObject("Autia",     "DataX1Reg", 'authIA', hint=False)
++    buildPauthObject("Autia1716", "DataX1Reg", 'authIA', hint=True)
++    buildPauthObject("Autiasp",   "DataX1Reg", 'authIA', hint=True)
++    buildPauthObject("Autiaz",    "DataX1Reg", 'authIA', hint=True)
++    buildPauthObject("Autiza",    "DataX1Reg", 'authIA', hint=False)
+ 
+-    buildPauthObject("Autib",     "DataX1Reg", 'authIB')
+-    buildPauthObject("Autib1716", "DataX1Reg", 'authIB')
+-    buildPauthObject("Autibsp",   "DataX1Reg", 'authIB')
+-    buildPauthObject("Autibz",    "DataX1Reg", 'authIB')
+-    buildPauthObject("Autizb",    "DataX1Reg", 'authIB')
++    buildPauthObject("Autib",     "DataX1Reg", 'authIB', hint=False)
++    buildPauthObject("Autib1716", "DataX1Reg", 'authIB', hint=True)
++    buildPauthObject("Autibsp",   "DataX1Reg", 'authIB', hint=True)
++    buildPauthObject("Autibz",    "DataX1Reg", 'authIB', hint=True)
++    buildPauthObject("Autizb",    "DataX1Reg", 'authIB', hint=False)
+ 
+-    buildXPauthObject("Xpacd")
+-    buildXPauthObject("Xpaci")
+-    buildXPauthObject("Xpaclri")
++    buildXPauthObject("Xpacd", hint=False)
++    buildXPauthObject("Xpaci", hint=False)
++    buildXPauthObject("Xpaclri", hint=True)
+ }};

meta-arm-bsp/recipes-devtools/gem5/gem5-aarch64-native_20.bb

@@ -0,0 +1,35 @@
+# gem5 simulator source and checksum information
+
+LIC_FILES_CHKSUM = "file://COPYING;md5=2d9514d69d8abf88b6e9125e759bf0ab \
+                    file://LICENSE;md5=a585e2893cee63d16a1d8bc16c6297ec"
+
+SRC_URI = "git://gem5.googlesource.com/public/gem5;protocol=https;nobranch=1 \
+           file://0001-scons-Add-MARSHAL_XXFLAGS_EXTRA-for-the-marshal-object.patch \
+           file://0002-arch-arm-Introduce-HavePACExt-helper.patch \
+           file://0003-arch-arm-Check-if-PAC-is-implemented-before-executing-insts.patch \
+          "
+RELEASE_TAG = "v20.0.0.1"
+SRCREV = "332a9de33db603e0aefedae1e05134db4257ea3e"
+
+PV = "${RELEASE_TAG}"
+
+S = "${WORKDIR}/git"
+
+BPN = "gem5-aarch64-native"
+
+require gem5-aarch64-native.inc
+require gem5-native.inc
+
+# Get rid of compiler errors when building protobuf
+GEM5_SCONS_ARGS_append = " CCFLAGS_EXTRA='-Wno-error=unused-variable' --verbose"
+
+# Get rid of linker errors and have a faster link process
+GEM5_SCONS_ARGS_append = " LDFLAGS_EXTRA='${BUILD_LDFLAGS}' \
+MARSHAL_LDFLAGS_EXTRA='${BUILD_LDFLAGS}' --force-lto "
+
+do_compile_prepend() {
+    # Gem5 expect to have python in the path (can be python2 or 3)
+    # Create a link named python to python3
+    real=$(which ${PYTHON})
+    ln -snf $real $(dirname $real)/python
+}

meta-arm-bsp/recipes-devtools/gem5/gem5-aarch64-native_git.bb

@@ -1,26 +0,0 @@
-# gem5 simulator source and checksum information
-
-LIC_FILES_CHKSUM = "file://COPYING;md5=2d9514d69d8abf88b6e9125e759bf0ab \
-                    file://LICENSE;md5=a585e2893cee63d16a1d8bc16c6297ec"
-
-# The recipe is currently using a version in the release staging branch of gem5
-# until version 20 is released
-SRC_URI = "git://gem5.googlesource.com/public/gem5;protocol=https;branch=release-staging-v20.0.0.0"
-
-PV = "git${SRCPV}"
-
-S = "${WORKDIR}/git"
-
-SRCREV = "0bc5d77ed27e0765953d93c2376a4b4aea675a01"
-
-BPN = "gem5-aarch64-native"
-
-require gem5-aarch64-native.inc
-require gem5-native.inc
-
-do_compile_prepend() {
-    # Gem5 expect to have python in the path (can be python2 or 3)
-    # Create a link named python to python3
-    real=$(which ${PYTHON})
-    ln -snf $real $(dirname $real)/python
-}

meta-arm-bsp/recipes-devtools/gem5/gem5-native.inc

@@ -30,12 +30,6 @@ DEPENDS += "python3-six-native protobuf-native hdf5-native pkgconfig-native \
 
 EXTRA_OESCONS = "${GEM5_SCONS_ARGS}"
 
-do_compile_prepend() {
-    # We need to use the proper native libraries when executing
-    # compiled applications
-    export LD_LIBRARY_PATH="${STAGING_LIBDIR_NATIVE}"
-}
-
 do_install() {
 
     install -d ${D}${datadir}/gem5

meta-arm-bsp/recipes-kernel/linux/arm-platforms-kmeta/bsp/arm-platforms/gem5-arm64/gem5-arm64-drm.cfg

@@ -1,5 +1,4 @@
 CONFIG_DRM=y
-CONFIG_DRM_ARM=y
 CONFIG_DRM_HDLCD=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y

meta-arm-bsp/recipes-kernel/linux/files/dts/arm/fvp-base-gicv3-psci-common-custom.dtsi

@@ -1,264 +0,0 @@
-/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/memreserve/ 0x80000000 0x00010000;
-
-/include/ "rtsm_ve-motherboard-nomap.dtsi"
-
-/ {
-	model = "FVP Base";
-	compatible = "arm,vfp-base", "arm,vexpress";
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	aliases {
-		serial0 = &v2m_serial0;
-		serial1 = &v2m_serial1;
-		serial2 = &v2m_serial2;
-		serial3 = &v2m_serial3;
-	};
-
-	psci {
-		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
-		method = "smc";
-		cpu_suspend = <0xc4000001>;
-		cpu_off = <0x84000002>;
-		cpu_on = <0xc4000003>;
-		sys_poweroff = <0x84000008>;
-		sys_reset = <0x84000009>;
-	};
-
-	cpus {
-		#address-cells = <2>;
-		#size-cells = <0>;
-
-		cpu-map {
-			cluster0 {
-				core0 {
-					cpu = <&CPU0>;
-				};
-				core1 {
-					cpu = <&CPU1>;
-				};
-				core2 {
-					cpu = <&CPU2>;
-				};
-				core3 {
-					cpu = <&CPU3>;
-				};
-			};
-
-			cluster1 {
-				core0 {
-					cpu = <&CPU4>;
-				};
-				core1 {
-					cpu = <&CPU5>;
-				};
-				core2 {
-					cpu = <&CPU6>;
-				};
-				core3 {
-					cpu = <&CPU7>;
-				};
-			};
-		};
-
-		idle-states {
-			entry-method = "arm,psci";
-
-			CPU_SLEEP_0: cpu-sleep-0 {
-				compatible = "arm,idle-state";
-				local-timer-stop;
-				arm,psci-suspend-param = <0x0010000>;
-				entry-latency-us = <40>;
-				exit-latency-us = <100>;
-				min-residency-us = <150>;
-			};
-
-			CLUSTER_SLEEP_0: cluster-sleep-0 {
-				compatible = "arm,idle-state";
-				local-timer-stop;
-				arm,psci-suspend-param = <0x1010000>;
-				entry-latency-us = <500>;
-				exit-latency-us = <1000>;
-				min-residency-us = <2500>;
-			};
-		};
-
-		CPU0:cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x0>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU1:cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x1>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU2:cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x2>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU3:cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x3>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU4:cpu@100 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x100>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU5:cpu@101 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x101>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU6:cpu@102 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x102>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		CPU7:cpu@103 {
-			device_type = "cpu";
-			compatible = "arm,armv8";
-			reg = <0x0 0x103>;
-			enable-method = "psci";
-			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
-			next-level-cache = <&L2_0>;
-		};
-
-		L2_0: l2-cache0 {
-			compatible = "cache";
-		};
-	};
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0x00000000 0x80000000 0 0x7F000000>,
-		      <0x00000008 0x80000000 0 0x80000000>;
-	};
-
-	gic: interrupt-controller@2f000000 {
-		compatible = "arm,gic-v3";
-		#interrupt-cells = <3>;
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		interrupt-controller;
-		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
-		      <0x0 0x2f100000 0 0x200000>,	// GICR
-		      <0x0 0x2c000000 0 0x2000>,	// GICC
-		      <0x0 0x2c010000 0 0x2000>,	// GICH
-		      <0x0 0x2c02f000 0 0x2000>;	// GICV
-		interrupts = <1 9 4>;
-
-		its: its@2f020000 {
-			compatible = "arm,gic-v3-its";
-			msi-controller;
-			reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
-		};
-	};
-
-	timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xff01>,
-			     <1 14 0xff01>,
-			     <1 11 0xff01>,
-			     <1 10 0xff01>;
-		clock-frequency = <100000000>;
-	};
-
-	timer@2a810000 {
-			compatible = "arm,armv7-timer-mem";
-			reg = <0x0 0x2a810000 0x0 0x10000>;
-			clock-frequency = <100000000>;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-			frame@2a830000 {
-				frame-number = <1>;
-				interrupts = <0 26 4>;
-				reg = <0x0 0x2a830000 0x0 0x10000>;
-			};
-	};
-
-	pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <0 60 4>,
-			     <0 61 4>,
-			     <0 62 4>,
-			     <0 63 4>;
-	};
-
-	smb@8000000 {
-		compatible = "simple-bus";
-
-		#address-cells = <2>;
-		#size-cells = <1>;
-		ranges = <0 0 0 0x08000000 0x04000000>,
-			 <1 0 0 0x14000000 0x04000000>,
-			 <2 0 0 0x18000000 0x04000000>,
-			 <3 0 0 0x1c000000 0x04000000>,
-			 <4 0 0 0x0c000000 0x04000000>,
-			 <5 0 0 0x10000000 0x04000000>;
-	};
-
-	panels {
-		panel {
-			compatible	= "panel";
-			mode		= "XVGA";
-			refresh		= <60>;
-			xres		= <1024>;
-			yres		= <768>;
-			pixclock	= <15748>;
-			left_margin	= <152>;
-			right_margin	= <48>;
-			upper_margin	= <23>;
-			lower_margin	= <3>;
-			hsync_len	= <104>;
-			vsync_len	= <4>;
-			sync		= <0>;
-			vmode		= "FB_VMODE_NONINTERLACED";
-			tim2		= "TIM2_BCD", "TIM2_IPC";
-			cntl		= "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
-			caps		= "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
-			bpp		= <16>;
-		};
-	};
-
-};

meta-arm-bsp/recipes-kernel/linux/files/dts/arm/fvp-base-gicv3-psci-custom.dts

@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/include/ "fvp-base-gicv3-psci-common-custom.dtsi"

meta-arm-bsp/recipes-kernel/linux/files/dts/arm/rtsm_ve-motherboard-nomap.dtsi

@@ -1,282 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * ARM Ltd. Fast Models
- *
- * Versatile Express (VE) system model
- * Motherboard component
- *
- * VEMotherBoard.lisa
- *
- * This is a duplicate of rtsm_ve-motherboard.dtsi but not
- * using interrupt-map as this is not properly supported in
- * xen right now
- */
-/ {
-	smb@8000000 {
-		motherboard {
-			arm,v2m-memory-map = "rs1";
-			compatible = "arm,vexpress,v2m-p1", "simple-bus";
-			#address-cells = <2>; /* SMB chipselect number and offset */
-			#size-cells = <1>;
-			ranges;
-
-			flash@0,00000000 {
-				compatible = "arm,vexpress-flash", "cfi-flash";
-				reg = <0 0x00000000 0x04000000>,
-				      <4 0x00000000 0x04000000>;
-				bank-width = <4>;
-			};
-
-			v2m_video_ram: vram@2,00000000 {
-				compatible = "arm,vexpress-vram";
-				reg = <2 0x00000000 0x00800000>;
-			};
-
-			ethernet@2,02000000 {
-				compatible = "smsc,lan91c111";
-				reg = <2 0x02000000 0x10000>;
-				interrupts = <0 15 4>;
-			};
-
-			v2m_clk24mhz: clk24mhz {
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <24000000>;
-				clock-output-names = "v2m:clk24mhz";
-			};
-
-			v2m_refclk1mhz: refclk1mhz {
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <1000000>;
-				clock-output-names = "v2m:refclk1mhz";
-			};
-
-			v2m_refclk32khz: refclk32khz {
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-frequency = <32768>;
-				clock-output-names = "v2m:refclk32khz";
-			};
-
-			iofpga@3,00000000 {
-				compatible = "simple-bus";
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0 3 0 0x200000>;
-
-				v2m_sysreg: sysreg@10000 {
-					compatible = "arm,vexpress-sysreg";
-					reg = <0x010000 0x1000>;
-					gpio-controller;
-					#gpio-cells = <2>;
-				};
-
-				v2m_sysctl: sysctl@20000 {
-					compatible = "arm,sp810", "arm,primecell";
-					reg = <0x020000 0x1000>;
-					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
-					clock-names = "refclk", "timclk", "apb_pclk";
-					#clock-cells = <1>;
-					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
-					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
-					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
-				};
-
-				aaci@40000 {
-					compatible = "arm,pl041", "arm,primecell";
-					reg = <0x040000 0x1000>;
-					interrupts = <0 11 4>;
-					clocks = <&v2m_clk24mhz>;
-					clock-names = "apb_pclk";
-				};
-
-				mmci@50000 {
-					compatible = "arm,pl180", "arm,primecell";
-					reg = <0x050000 0x1000>;
-					interrupts = <0 9 4 0 10 4>;
-					cd-gpios = <&v2m_sysreg 0 0>;
-					wp-gpios = <&v2m_sysreg 1 0>;
-					max-frequency = <12000000>;
-					vmmc-supply = <&v2m_fixed_3v3>;
-					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-					clock-names = "mclk", "apb_pclk";
-				};
-
-				kmi@60000 {
-					compatible = "arm,pl050", "arm,primecell";
-					reg = <0x060000 0x1000>;
-					interrupts = <0 12 4>;
-					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-					clock-names = "KMIREFCLK", "apb_pclk";
-				};
-
-				kmi@70000 {
-					compatible = "arm,pl050", "arm,primecell";
-					reg = <0x070000 0x1000>;
-					interrupts = <0 13 4>;
-					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-					clock-names = "KMIREFCLK", "apb_pclk";
-				};
-
-				v2m_serial0: uart@90000 {
-					compatible = "arm,pl011", "arm,primecell";
-					reg = <0x090000 0x1000>;
-					interrupts = <0 5 4>;
-					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-					clock-names = "uartclk", "apb_pclk";
-				};
-
-				v2m_serial1: uart@a0000 {
-					compatible = "arm,pl011", "arm,primecell";
-					reg = <0x0a0000 0x1000>;
-					interrupts = <0 6 4>;
-					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-					clock-names = "uartclk", "apb_pclk";
-				};
-
-				v2m_serial2: uart@b0000 {
-					compatible = "arm,pl011", "arm,primecell";
-					reg = <0x0b0000 0x1000>;
-					interrupts = <0 7 4>;
-					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-					clock-names = "uartclk", "apb_pclk";
-				};
-
-				v2m_serial3: uart@c0000 {
-					compatible = "arm,pl011", "arm,primecell";
-					reg = <0x0c0000 0x1000>;
-					interrupts = <0 8 4>;
-					clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
-					clock-names = "uartclk", "apb_pclk";
-				};
-
-				wdt@f0000 {
-					compatible = "arm,sp805", "arm,primecell";
-					reg = <0x0f0000 0x1000>;
-					interrupts = <0 0 4>;
-					clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
-					clock-names = "wdogclk", "apb_pclk";
-				};
-
-				v2m_timer01: timer@110000 {
-					compatible = "arm,sp804", "arm,primecell";
-					reg = <0x110000 0x1000>;
-					interrupts = <0 2 4>;
-					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
-					clock-names = "timclken1", "timclken2", "apb_pclk";
-				};
-
-				v2m_timer23: timer@120000 {
-					compatible = "arm,sp804", "arm,primecell";
-					reg = <0x120000 0x1000>;
-					interrupts = <0 3 4>;
-					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
-					clock-names = "timclken1", "timclken2", "apb_pclk";
-				};
-
-				rtc@170000 {
-					compatible = "arm,pl031", "arm,primecell";
-					reg = <0x170000 0x1000>;
-					interrupts = <0 4 4>;
-					clocks = <&v2m_clk24mhz>;
-					clock-names = "apb_pclk";
-				};
-
-				clcd@1f0000 {
-					compatible = "arm,pl111", "arm,primecell";
-					reg = <0x1f0000 0x1000>;
-					interrupt-names = "combined";
-					interrupts = <0 14 4>;
-					clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
-					clock-names = "clcdclk", "apb_pclk";
-					arm,pl11x,framebuffer = <0x18000000 0x00180000>;
-					memory-region = <&v2m_video_ram>;
-					max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
-
-					port {
-						v2m_clcd_pads: endpoint {
-							remote-endpoint = <&v2m_clcd_panel>;
-							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
-						};
-					};
-
-					panel {
-						compatible = "panel-dpi";
-
-						port {
-							v2m_clcd_panel: endpoint {
-								remote-endpoint = <&v2m_clcd_pads>;
-							};
-						};
-
-						panel-timing {
-							clock-frequency = <63500127>;
-							hactive = <1024>;
-							hback-porch = <152>;
-							hfront-porch = <48>;
-							hsync-len = <104>;
-							vactive = <768>;
-							vback-porch = <23>;
-							vfront-porch = <3>;
-							vsync-len = <4>;
-						};
-					};
-				};
-
-				virtio-block@130000 {
-					compatible = "virtio,mmio";
-					reg = <0x130000 0x200>;
-					interrupts = <0 42 4>;
-				};
-			};
-
-			v2m_fixed_3v3: v2m-3v3 {
-				compatible = "regulator-fixed";
-				regulator-name = "3V3";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-always-on;
-			};
-
-			mcc {
-				compatible = "arm,vexpress,config-bus";
-				arm,vexpress,config-bridge = <&v2m_sysreg>;
-
-				v2m_oscclk1: oscclk1 {
-					/* CLCD clock */
-					compatible = "arm,vexpress-osc";
-					arm,vexpress-sysreg,func = <1 1>;
-					freq-range = <23750000 63500000>;
-					#clock-cells = <0>;
-					clock-output-names = "v2m:oscclk1";
-				};
-
-				reset {
-					compatible = "arm,vexpress-reset";
-					arm,vexpress-sysreg,func = <5 0>;
-				};
-
-				muxfpga {
-					compatible = "arm,vexpress-muxfpga";
-					arm,vexpress-sysreg,func = <7 0>;
-				};
-
-				shutdown {
-					compatible = "arm,vexpress-shutdown";
-					arm,vexpress-sysreg,func = <8 0>;
-				};
-
-				reboot {
-					compatible = "arm,vexpress-reboot";
-					arm,vexpress-sysreg,func = <9 0>;
-				};
-
-				dvimode {
-					compatible = "arm,vexpress-dvimode";
-					arm,vexpress-sysreg,func = <11 0>;
-				};
-			};
-		};
-	};
-};

meta-arm-bsp/recipes-kernel/linux/files/dts/gem5-arm64/armv8_gem5_v2_1cpu.dts

@@ -1,95 +0,0 @@
-/*
- * Copyright (c) 2015-2016 ARM Limited
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
- */
-
-/dts-v1/;
-
-/memreserve/ 0x80000000 0x00010000;
-
-/include/ "vexpress_gem5_v2.dtsi"
-
-/ {
-	model = "V2P-AARCH64";
-	compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0 0x80000000 0x4 0x00000000>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-        cpu@0 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 0 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-	};
-
-	virt-encoder {
-		compatible = "drm,virtual-encoder";
-		port {
-			dp0_virt_input: endpoint@0 {
-				remote-endpoint = <&dp0_output>;
-			};
-		};
-
-		display-timings {
-			native-mode = <&timing0>;
-
-			timing0: timing_1080p60 {
-				/* 1920x1080-60 */
-				clock-frequency = <148500000>;
-				hactive = <1920>;
-				vactive = <1080>;
-				hfront-porch = <148>;
-				hback-porch = <88>;
-				hsync-len = <44>;
-				vfront-porch = <36>;
-				vback-porch = <4>;
-				vsync-len = <5>;
-			};
-		};
-	};
-};
-
-&dp0 {
-	status = "ok"
-
-	port {
-		dp0_output: endpoint@0 {
-			remote-endpoint = <&dp0_virt_input>;
-		};
-	};
-};

meta-arm-bsp/recipes-kernel/linux/files/dts/gem5-arm64/armv8_gem5_v2_2cpu.dts

@@ -1,103 +0,0 @@
-/*
- * Copyright (c) 2015-2016 ARM Limited
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
- */
-
-/dts-v1/;
-
-/memreserve/ 0x80000000 0x00010000;
-
-/include/ "vexpress_gem5_v2.dtsi"
-
-/ {
-	model = "V2P-AARCH64";
-	compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0 0x80000000 0x4 0x00000000>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-        cpu@0 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 0 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@1 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 1 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-	};
-
-	virt-encoder {
-		compatible = "drm,virtual-encoder";
-		port {
-			dp0_virt_input: endpoint@0 {
-				remote-endpoint = <&dp0_output>;
-			};
-		};
-
-		display-timings {
-			native-mode = <&timing0>;
-
-			timing0: timing_1080p60 {
-				/* 1920x1080-60 */
-				clock-frequency = <148500000>;
-				hactive = <1920>;
-				vactive = <1080>;
-				hfront-porch = <148>;
-				hback-porch = <88>;
-				hsync-len = <44>;
-				vfront-porch = <36>;
-				vback-porch = <4>;
-				vsync-len = <5>;
-			};
-		};
-	};
-};
-
-&dp0 {
-	status = "ok"
-
-	port {
-		dp0_output: endpoint@0 {
-			remote-endpoint = <&dp0_virt_input>;
-		};
-	};
-};

meta-arm-bsp/recipes-kernel/linux/files/dts/gem5-arm64/armv8_gem5_v2_4cpu.dts

@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2015-2016 ARM Limited
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
- */
-
-/dts-v1/;
-
-/memreserve/ 0x80000000 0x00010000;
-
-/include/ "vexpress_gem5_v2.dtsi"
-
-/ {
-	model = "V2P-AARCH64";
-	compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0 0x80000000 0x4 0x00000000>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-        cpu@0 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 0 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@1 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 1 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@2 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 2 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@3 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 3 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-	};
-
-	virt-encoder {
-		compatible = "drm,virtual-encoder";
-		port {
-			dp0_virt_input: endpoint@0 {
-				remote-endpoint = <&dp0_output>;
-			};
-		};
-
-		display-timings {
-			native-mode = <&timing0>;
-
-			timing0: timing_1080p60 {
-				/* 1920x1080-60 */
-				clock-frequency = <148500000>;
-				hactive = <1920>;
-				vactive = <1080>;
-				hfront-porch = <148>;
-				hback-porch = <88>;
-				hsync-len = <44>;
-				vfront-porch = <36>;
-				vback-porch = <4>;
-				vsync-len = <5>;
-			};
-		};
-	};
-};
-
-&dp0 {
-	status = "ok"
-
-	port {
-		dp0_output: endpoint@0 {
-			remote-endpoint = <&dp0_virt_input>;
-		};
-	};
-};

meta-arm-bsp/recipes-kernel/linux/files/dts/gem5-arm64/armv8_gem5_v2_8cpu.dts

@@ -1,151 +0,0 @@
-/*
- * Copyright (c) 2015-2016 ARM Limited
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
- */
-
-/dts-v1/;
-
-/memreserve/ 0x80000000 0x00010000;
-
-/include/ "vexpress_gem5_v2.dtsi"
-
-/ {
-	model = "V2P-AARCH64";
-	compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
-
-	memory@80000000 {
-		device_type = "memory";
-		reg = <0 0x80000000 0x4 0x00000000>;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-        cpu@0 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 0 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@1 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 1 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@2 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 2 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@3 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 3 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@4 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 4 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@5 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 5 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@6 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 6 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-        cpu@7 {
-            device_type = "cpu";
-            compatible = "gem5,armv8", "arm,armv8";
-            reg = < 7 >;
-            enable-method = "spin-table";
-            cpu-release-addr = <0 0x8000fff8>;
-        };
-
-	};
-
-	virt-encoder {
-		compatible = "drm,virtual-encoder";
-		port {
-			dp0_virt_input: endpoint@0 {
-				remote-endpoint = <&dp0_output>;
-			};
-		};
-
-		display-timings {
-			native-mode = <&timing0>;
-
-			timing0: timing_1080p60 {
-				/* 1920x1080-60 */
-				clock-frequency = <148500000>;
-				hactive = <1920>;
-				vactive = <1080>;
-				hfront-porch = <148>;
-				hback-porch = <88>;
-				hsync-len = <44>;
-				vfront-porch = <36>;
-				vback-porch = <4>;
-				vsync-len = <5>;
-			};
-		};
-	};
-};
-
-&dp0 {
-	status = "ok"
-
-	port {
-		dp0_output: endpoint@0 {
-			remote-endpoint = <&dp0_virt_input>;
-		};
-	};
-};

meta-arm-bsp/recipes-kernel/linux/files/dts/gem5-arm64/vexpress_gem5_v2.dtsi

@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2015-2018 ARM Limited
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
- */
-
-/include/ "vexpress_gem5_v2_base.dtsi"
-
-/ {
-	/* The display processor needs custom configuration to setup its
-	 * output ports. Disable it by default in the platform until the
-	 * DT bindings have stabilize.
-	 */
-	dp0: hdlcd@2b000000 {
-		compatible = "arm,hdlcd";
-		reg = <0x0 0x2b000000 0x0 0x1000>;
-		interrupts = <0 63 4>;
-		clocks = <&osc_pxl>;
-		clock-names = "pxlclk";
-		status = "disabled";
-	};
-};

meta-arm-bsp/recipes-kernel/linux/files/dts/gem5-arm64/vexpress_gem5_v2_base.dtsi

@@ -1,202 +0,0 @@
-/*
- * Copyright (c) 2015-2017, 2019 ARM Limited
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Andreas Sandberg
- */
-
-/ {
-	arm,hbi = <0x0>;
-	arm,vexpress,site = <0xf>;
-	interrupt-parent = <&gic>;
-	#address-cells = <2>;
-	#size-cells = <2>;
-
-	gic: interrupt-controller@2c000000 {
-		compatible = "arm,gic-v3";
-		#interrupt-cells = <0x3>;
-		#address-cells = <0x2>;
-		ranges;
-		interrupt-controller;
-		redistributor-stride = <0x0 0x40000>; // 256kB stride
-		reg = <0x0 0x2c000000 0x0 0x10000
-		       0x0 0x2c010000 0x0 0x2000000 // room for 128 redistributors using 128K each (256K strided...)
-		       0x0 0x0 0x0 0x0>;
-		interrupts = <1 9 0xf04>;
-		#size-cells = <0x2>;
-		linux,phandle = <0x1>;
-		phandle = <0x1>;
-
-		gic-its@2e010000 {
-			compatible = "arm,gic-v3-its";
-			msi-controller;
-			#msi-cells = <1>;
-			reg = <0x0 0x2e010000 0 0x20000>;
-		};
-	};
-
-	timer {
-		compatible = "arm,cortex-a15-timer",
-			     "arm,armv7-timer";
-		interrupts = <1 13 0xf08>,
-		             <1 14 0xf08>,
-			     <1 11 0xf08>,
-		             <1 10 0xf08>;
-		clocks = <&osc_sys>;
-		clock-names="apb_pclk";
-	};
-
-	pci {
-		compatible = "pci-host-ecam-generic";
-		device_type = "pci";
-		#address-cells = <0x3>;
-		#size-cells = <0x2>;
-		#interrupt-cells = <0x1>;
-
-		reg = <0x0 0x30000000 0x0 0x10000000>;
-
-		ranges = <0x01000000 0x0 0x00000000  0x0 0x2f000000  0x0 0x00010000>,
-		         <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;
-
-	/*
-	  child unit address, #cells = #address-cells
-	  child interrupt specifier, #cells = #interrupt-cells (INTA = 1, INTB = 2, INTC = 3 and INTD = 4)
-	  interrupt-parent, phandle
-	  parent unit address, #cells = #address-cells@gic
-	  parent interrupt specifier, #cells = #interrupt-cells@gic
-	*/
-	interrupt-map = <0x0    0x0 0x0  0x1  &gic  0x0 0x0  0x0 0x44 0x1
-		         0x800  0x0 0x0  0x1  &gic  0x0 0x0  0x0 0x45 0x1
-		         0x1000 0x0 0x0  0x1  &gic  0x0 0x0  0x0 0x46 0x1
-		         0x1800 0x0 0x0  0x1  &gic  0x0 0x0  0x0 0x47 0x1>;
-
-	interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
-	dma-coherent;
-	};
-
-	kmi@1c060000 {
-		compatible = "arm,pl050", "arm,primecell";
-		reg = <0x0 0x1c060000 0x0 0x1000>;
-		interrupts = <0 12 4>;
-		clocks = <&v2m_clk24mhz>, <&osc_smb>;
-		clock-names = "KMIREFCLK", "apb_pclk";
-	};
-
-	kmi@1c070000 {
-		compatible = "arm,pl050", "arm,primecell";
-		reg = <0x0 0x1c070000 0x0 0x1000>;
-		interrupts = <0 13 4>;
-		clocks = <&v2m_clk24mhz>, <&osc_smb>;
-		clock-names = "KMIREFCLK", "apb_pclk";
-	};
-
-	uart0: uart@1c090000 {
-		compatible = "arm,pl011", "arm,primecell";
-		reg = <0x0 0x1c090000 0x0 0x1000>;
-		interrupts = <0 5 4>;
-		clocks = <&osc_peripheral>, <&osc_smb>;
-		clock-names = "uartclk", "apb_pclk";
-	};
-
-	rtc@1c170000 {
-		compatible = "arm,pl031", "arm,primecell";
-		reg = <0x0 0x1c170000 0x0 0x1000>;
-		interrupts = <0 4 4>;
-		clocks = <&osc_smb>;
-		clock-names = "apb_pclk";
-	};
-
-	v2m_clk24mhz: clk24mhz {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <24000000>;
-		clock-output-names = "v2m:clk24mhz";
-	};
-
-
-	v2m_sysreg: sysreg@1c010000 {
-		compatible = "arm,vexpress-sysreg";
-		reg = <0 0x1c010000 0x0 0x1000>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-
-	vio@1c130000 {
-		compatible = "virtio,mmio";
-		reg = <0 0x1c130000 0x0 0x1000>;
-		interrupts = <0 42 4>;
-	};
-
-	vio@1c140000 {
-		compatible = "virtio,mmio";
-		reg = <0 0x1c140000 0x0 0x1000>;
-		interrupts = <0 43 4>;
-	};
-
-	dcc {
-		compatible = "arm,vexpress,config-bus";
-		arm,vexpress,config-bridge = <&v2m_sysreg>;
-
-		osc_pxl: osc@5 {
-			compatible = "arm,vexpress-osc";
-			arm,vexpress-sysreg,func = <1 5>;
-			freq-range = <23750000 1000000000>;
-			#clock-cells = <0>;
-			clock-output-names = "oscclk5";
-		};
-
-		osc_smb: osc@6 {
-			compatible = "arm,vexpress-osc";
-			arm,vexpress-sysreg,func = <1 6>;
-			freq-range = <20000000 50000000>;
-			#clock-cells = <0>;
-			clock-output-names = "oscclk6";
-		};
-
-		osc_sys: osc@7 {
-			compatible = "arm,vexpress-osc";
-			arm,vexpress-sysreg,func = <1 7>;
-			freq-range = <20000000 60000000>;
-			#clock-cells = <0>;
-			clock-output-names = "oscclk7";
-		};
-	};
-
-
-	mcc {
-		compatible = "arm,vexpress,config-bus";
-		arm,vexpress,config-bridge = <&v2m_sysreg>;
-		arm,vexpress,site = <0>;
-
-		osc_peripheral: osc@2 {
-			compatible = "arm,vexpress-osc";
-			arm,vexpress-sysreg,func = <1 2>;
-			freq-range = <24000000 24000000>;
-			#clock-cells = <0>;
-			clock-output-names = "v2m:oscclk2";
-		};
-	};
-};

meta-arm-bsp/recipes-kernel/linux/files/fvp-base-dts.patch

@@ -0,0 +1,578 @@
+Add DTS files which are not yet upstream. In the future these will be provided by TF-A.
+
+Upstream-Status: Inappropriate
+Signed-off-by: Anders Dellien <anders.dellien@arm.com
+
+diff --git a/arch/arm64/boot/dts/arm/fvp-base-gicv3-psci-common-custom.dtsi b/arch/arm64/boot/dts/arm/fvp-base-gicv3-psci-common-custom.dtsi
+new file mode 100644
+index 000000000000..f4601c7f99f8
+--- /dev/null
++++ b/arch/arm64/boot/dts/arm/fvp-base-gicv3-psci-common-custom.dtsi
+@@ -0,0 +1,264 @@
++/*
++ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ */
++
++/memreserve/ 0x80000000 0x00010000;
++
++/include/ "rtsm_ve-motherboard-nomap.dtsi"
++
++/ {
++       model = "FVP Base";
++       compatible = "arm,vfp-base", "arm,vexpress";
++       interrupt-parent = <&gic>;
++       #address-cells = <2>;
++       #size-cells = <2>;
++
++       aliases {
++               serial0 = &v2m_serial0;
++               serial1 = &v2m_serial1;
++               serial2 = &v2m_serial2;
++               serial3 = &v2m_serial3;
++       };
++
++       psci {
++               compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
++               method = "smc";
++               cpu_suspend = <0xc4000001>;
++               cpu_off = <0x84000002>;
++               cpu_on = <0xc4000003>;
++               sys_poweroff = <0x84000008>;
++               sys_reset = <0x84000009>;
++       };
++
++       cpus {
++               #address-cells = <2>;
++               #size-cells = <0>;
++
++               cpu-map {
++                       cluster0 {
++                               core0 {
++                                       cpu = <&CPU0>;
++                               };
++                               core1 {
++                                       cpu = <&CPU1>;
++                               };
++                               core2 {
++                                       cpu = <&CPU2>;
++                               };
++                               core3 {
++                                       cpu = <&CPU3>;
++                               };
++                       };
++
++                       cluster1 {
++                               core0 {
++                                       cpu = <&CPU4>;
++                               };
++                               core1 {
++                                       cpu = <&CPU5>;
++                               };
++                               core2 {
++                                       cpu = <&CPU6>;
++                               };
++                               core3 {
++                                       cpu = <&CPU7>;
++                               };
++                       };
++               };
++
++               idle-states {
++                       entry-method = "arm,psci";
++
++                       CPU_SLEEP_0: cpu-sleep-0 {
++                               compatible = "arm,idle-state";
++                               local-timer-stop;
++                               arm,psci-suspend-param = <0x0010000>;
++                               entry-latency-us = <40>;
++                               exit-latency-us = <100>;
++                               min-residency-us = <150>;
++                       };
++
++                       CLUSTER_SLEEP_0: cluster-sleep-0 {
++                               compatible = "arm,idle-state";
++                               local-timer-stop;
++                               arm,psci-suspend-param = <0x1010000>;
++                               entry-latency-us = <500>;
++                               exit-latency-us = <1000>;
++                               min-residency-us = <2500>;
++                       };
++               };
++
++               CPU0:cpu@0 {
++                       device_type = "cpu";
++                       compatible = "arm,armv8";
++                       reg = <0x0 0x0>;
++                       enable-method = "psci";
++                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
++                       next-level-cache = <&L2_0>;
++               };
++
++               CPU1:cpu@1 {
++                       device_type = "cpu";
++                       compatible = "arm,armv8";
++                       reg = <0x0 0x1>;
++                       enable-method = "psci";
++                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
++                       next-level-cache = <&L2_0>;
++               };
++
++               CPU2:cpu@2 {
++                       device_type = "cpu";
++                       compatible = "arm,armv8";
++                       reg = <0x0 0x2>;
++                       enable-method = "psci";
++                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
++                       next-level-cache = <&L2_0>;
++               };
++
++               CPU3:cpu@3 {
++                       device_type = "cpu";
++                       compatible = "arm,armv8";
++                       reg = <0x0 0x3>;
++                       enable-method = "psci";
++                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
++                       next-level-cache = <&L2_0>;
++               };
++
++               CPU4:cpu@100 {
++                       device_type = "cpu";
++                       compatible = "arm,armv8";
++                       reg = <0x0 0x100>;
++                       enable-method = "psci";
++                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
++                       next-level-cache = <&L2_0>;
++               };
++
++               CPU5:cpu@101 {
++                       device_type = "cpu";
++                       compatible = "arm,armv8";
++                       reg = <0x0 0x101>;
++                       enable-method = "psci";
++                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
++                       next-level-cache = <&L2_0>;
++               };
++
++               CPU6:cpu@102 {
++                       device_type = "cpu";
++                       compatible = "arm,armv8";
++                       reg = <0x0 0x102>;
++                       enable-method = "psci";
++                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
++                       next-level-cache = <&L2_0>;
++               };
++
++               CPU7:cpu@103 {
++                       device_type = "cpu";
++                       compatible = "arm,armv8";
++                       reg = <0x0 0x103>;
++                       enable-method = "psci";
++                       cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
++                       next-level-cache = <&L2_0>;
++               };
++
++               L2_0: l2-cache0 {
++                       compatible = "cache";
++               };
++       };
++
++       memory@80000000 {
++               device_type = "memory";
++               reg = <0x00000000 0x80000000 0 0x7F000000>,
++                     <0x00000008 0x80000000 0 0x80000000>;
++       };
++
++       gic: interrupt-controller@2f000000 {
++               compatible = "arm,gic-v3";
++               #interrupt-cells = <3>;
++               #address-cells = <2>;
++               #size-cells = <2>;
++               ranges;
++               interrupt-controller;
++               reg = <0x0 0x2f000000 0 0x10000>,       // GICD
++                     <0x0 0x2f100000 0 0x200000>,      // GICR
++                     <0x0 0x2c000000 0 0x2000>,        // GICC
++                     <0x0 0x2c010000 0 0x2000>,        // GICH
++                     <0x0 0x2c02f000 0 0x2000>;        // GICV
++               interrupts = <1 9 4>;
++
++               its: its@2f020000 {
++                       compatible = "arm,gic-v3-its";
++                       msi-controller;
++                       reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
++               };
++       };
++
++       timer {
++               compatible = "arm,armv8-timer";
++               interrupts = <1 13 0xff01>,
++                            <1 14 0xff01>,
++                            <1 11 0xff01>,
++                            <1 10 0xff01>;
++               clock-frequency = <100000000>;
++       };
++
++       timer@2a810000 {
++                       compatible = "arm,armv7-timer-mem";
++                       reg = <0x0 0x2a810000 0x0 0x10000>;
++                       clock-frequency = <100000000>;
++                       #address-cells = <2>;
++                       #size-cells = <2>;
++                       ranges;
++                       frame@2a830000 {
++                               frame-number = <1>;
++                               interrupts = <0 26 4>;
++                               reg = <0x0 0x2a830000 0x0 0x10000>;
++                       };
++       };
++
++       pmu {
++               compatible = "arm,armv8-pmuv3";
++               interrupts = <0 60 4>,
++                            <0 61 4>,
++                            <0 62 4>,
++                            <0 63 4>;
++       };
++
++       smb@8000000 {
++               compatible = "simple-bus";
++
++               #address-cells = <2>;
++               #size-cells = <1>;
++               ranges = <0 0 0 0x08000000 0x04000000>,
++                        <1 0 0 0x14000000 0x04000000>,
++                        <2 0 0 0x18000000 0x04000000>,
++                        <3 0 0 0x1c000000 0x04000000>,
++                        <4 0 0 0x0c000000 0x04000000>,
++                        <5 0 0 0x10000000 0x04000000>;
++       };
++
++       panels {
++               panel {
++                       compatible      = "panel";
++                       mode            = "XVGA";
++                       refresh         = <60>;
++                       xres            = <1024>;
++                       yres            = <768>;
++                       pixclock        = <15748>;
++                       left_margin     = <152>;
++                       right_margin    = <48>;
++                       upper_margin    = <23>;
++                       lower_margin    = <3>;
++                       hsync_len       = <104>;
++                       vsync_len       = <4>;
++                       sync            = <0>;
++                       vmode           = "FB_VMODE_NONINTERLACED";
++                       tim2            = "TIM2_BCD", "TIM2_IPC";
++                       cntl            = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
++                       caps            = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
++                       bpp             = <16>;
++               };
++       };
++
++};
+diff --git a/arch/arm64/boot/dts/arm/fvp-base-gicv3-psci-custom.dts b/arch/arm64/boot/dts/arm/fvp-base-gicv3-psci-custom.dts
+new file mode 100644
+index 000000000000..984dbca90126
+--- /dev/null
++++ b/arch/arm64/boot/dts/arm/fvp-base-gicv3-psci-custom.dts
+@@ -0,0 +1,9 @@
++/*
++ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
++ *
++ * SPDX-License-Identifier: BSD-3-Clause
++ */
++
++/dts-v1/;
++
++/include/ "fvp-base-gicv3-psci-common-custom.dtsi"
+diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-nomap.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-nomap.dtsi
+new file mode 100644
+index 000000000000..a94f7cb863a2
+--- /dev/null
++++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-nomap.dtsi
+@@ -0,0 +1,282 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * ARM Ltd. Fast Models
++ *
++ * Versatile Express (VE) system model
++ * Motherboard component
++ *
++ * VEMotherBoard.lisa
++ *
++ * This is a duplicate of rtsm_ve-motherboard.dtsi but not
++ * using interrupt-map as this is not properly supported in
++ * xen right now
++ */
++/ {
++       smb@8000000 {
++               motherboard {
++                       arm,v2m-memory-map = "rs1";
++                       compatible = "arm,vexpress,v2m-p1", "simple-bus";
++                       #address-cells = <2>; /* SMB chipselect number and offset */
++                       #size-cells = <1>;
++                       ranges;
++
++                       flash@0,00000000 {
++                               compatible = "arm,vexpress-flash", "cfi-flash";
++                               reg = <0 0x00000000 0x04000000>,
++                                     <4 0x00000000 0x04000000>;
++                               bank-width = <4>;
++                       };
++
++                       v2m_video_ram: vram@2,00000000 {
++                               compatible = "arm,vexpress-vram";
++                               reg = <2 0x00000000 0x00800000>;
++                       };
++
++                       ethernet@2,02000000 {
++                               compatible = "smsc,lan91c111";
++                               reg = <2 0x02000000 0x10000>;
++                               interrupts = <0 15 4>;
++                       };
++
++                       v2m_clk24mhz: clk24mhz {
++                               compatible = "fixed-clock";
++                               #clock-cells = <0>;
++                               clock-frequency = <24000000>;
++                               clock-output-names = "v2m:clk24mhz";
++                       };
++
++                       v2m_refclk1mhz: refclk1mhz {
++                               compatible = "fixed-clock";
++                               #clock-cells = <0>;
++                               clock-frequency = <1000000>;
++                               clock-output-names = "v2m:refclk1mhz";
++                       };
++
++                       v2m_refclk32khz: refclk32khz {
++                               compatible = "fixed-clock";
++                               #clock-cells = <0>;
++                               clock-frequency = <32768>;
++                               clock-output-names = "v2m:refclk32khz";
++                       };
++
++                       iofpga@3,00000000 {
++                               compatible = "simple-bus";
++                               #address-cells = <1>;
++                               #size-cells = <1>;
++                               ranges = <0 3 0 0x200000>;
++
++                               v2m_sysreg: sysreg@10000 {
++                                       compatible = "arm,vexpress-sysreg";
++                                       reg = <0x010000 0x1000>;
++                                       gpio-controller;
++                                       #gpio-cells = <2>;
++                               };
++
++                               v2m_sysctl: sysctl@20000 {
++                                       compatible = "arm,sp810", "arm,primecell";
++                                       reg = <0x020000 0x1000>;
++                                       clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
++                                       clock-names = "refclk", "timclk", "apb_pclk";
++                                       #clock-cells = <1>;
++                                       clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
++                                       assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
++                                       assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
++                               };
++
++                               aaci@40000 {
++                                       compatible = "arm,pl041", "arm,primecell";
++                                       reg = <0x040000 0x1000>;
++                                       interrupts = <0 11 4>;
++                                       clocks = <&v2m_clk24mhz>;
++                                       clock-names = "apb_pclk";
++                               };
++
++                               mmci@50000 {
++                                       compatible = "arm,pl180", "arm,primecell";
++                                       reg = <0x050000 0x1000>;
++                                       interrupts = <0 9 4 0 10 4>;
++                                       cd-gpios = <&v2m_sysreg 0 0>;
++                                       wp-gpios = <&v2m_sysreg 1 0>;
++                                       max-frequency = <12000000>;
++                                       vmmc-supply = <&v2m_fixed_3v3>;
++                                       clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
++                                       clock-names = "mclk", "apb_pclk";
++                               };
++
++                               kmi@60000 {
++                                       compatible = "arm,pl050", "arm,primecell";
++                                       reg = <0x060000 0x1000>;
++                                       interrupts = <0 12 4>;
++                                       clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
++                                       clock-names = "KMIREFCLK", "apb_pclk";
++                               };
++
++                               kmi@70000 {
++                                       compatible = "arm,pl050", "arm,primecell";
++                                       reg = <0x070000 0x1000>;
++                                       interrupts = <0 13 4>;
++                                       clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
++                                       clock-names = "KMIREFCLK", "apb_pclk";
++                               };
++
++                               v2m_serial0: uart@90000 {
++                                       compatible = "arm,pl011", "arm,primecell";
++                                       reg = <0x090000 0x1000>;
++                                       interrupts = <0 5 4>;
++                                       clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
++                                       clock-names = "uartclk", "apb_pclk";
++                               };
++
++                               v2m_serial1: uart@a0000 {
++                                       compatible = "arm,pl011", "arm,primecell";
++                                       reg = <0x0a0000 0x1000>;
++                                       interrupts = <0 6 4>;
++                                       clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
++                                       clock-names = "uartclk", "apb_pclk";
++                               };
++
++                               v2m_serial2: uart@b0000 {
++                                       compatible = "arm,pl011", "arm,primecell";
++                                       reg = <0x0b0000 0x1000>;
++                                       interrupts = <0 7 4>;
++                                       clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
++                                       clock-names = "uartclk", "apb_pclk";
++                               };
++
++                               v2m_serial3: uart@c0000 {
++                                       compatible = "arm,pl011", "arm,primecell";
++                                       reg = <0x0c0000 0x1000>;
++                                       interrupts = <0 8 4>;
++                                       clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
++                                       clock-names = "uartclk", "apb_pclk";
++                               };
++
++                               wdt@f0000 {
++                                       compatible = "arm,sp805", "arm,primecell";
++                                       reg = <0x0f0000 0x1000>;
++                                       interrupts = <0 0 4>;
++                                       clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
++                                       clock-names = "wdogclk", "apb_pclk";
++                               };
++
++                               v2m_timer01: timer@110000 {
++                                       compatible = "arm,sp804", "arm,primecell";
++                                       reg = <0x110000 0x1000>;
++                                       interrupts = <0 2 4>;
++                                       clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
++                                       clock-names = "timclken1", "timclken2", "apb_pclk";
++                               };
++
++                               v2m_timer23: timer@120000 {
++                                       compatible = "arm,sp804", "arm,primecell";
++                                       reg = <0x120000 0x1000>;
++                                       interrupts = <0 3 4>;
++                                       clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
++                                       clock-names = "timclken1", "timclken2", "apb_pclk";
++                               };
++
++                               rtc@170000 {
++                                       compatible = "arm,pl031", "arm,primecell";
++                                       reg = <0x170000 0x1000>;
++                                       interrupts = <0 4 4>;
++                                       clocks = <&v2m_clk24mhz>;
++                                       clock-names = "apb_pclk";
++                               };
++
++                               clcd@1f0000 {
++                                       compatible = "arm,pl111", "arm,primecell";
++                                       reg = <0x1f0000 0x1000>;
++                                       interrupt-names = "combined";
++                                       interrupts = <0 14 4>;
++                                       clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
++                                       clock-names = "clcdclk", "apb_pclk";
++                                       arm,pl11x,framebuffer = <0x18000000 0x00180000>;
++                                       memory-region = <&v2m_video_ram>;
++                                       max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
++
++                                       port {
++                                               v2m_clcd_pads: endpoint {
++                                                       remote-endpoint = <&v2m_clcd_panel>;
++                                                       arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
++                                               };
++                                       };
++
++                                       panel {
++                                               compatible = "panel-dpi";
++
++                                               port {
++                                                       v2m_clcd_panel: endpoint {
++                                                               remote-endpoint = <&v2m_clcd_pads>;
++                                                       };
++                                               };
++
++                                               panel-timing {
++                                                       clock-frequency = <63500127>;
++                                                       hactive = <1024>;
++                                                       hback-porch = <152>;
++                                                       hfront-porch = <48>;
++                                                       hsync-len = <104>;
++                                                       vactive = <768>;
++                                                       vback-porch = <23>;
++                                                       vfront-porch = <3>;
++                                                       vsync-len = <4>;
++                                               };
++                                       };
++                               };
++
++                               virtio-block@130000 {
++                                       compatible = "virtio,mmio";
++                                       reg = <0x130000 0x200>;
++                                       interrupts = <0 42 4>;
++                               };
++                       };
++
++                       v2m_fixed_3v3: v2m-3v3 {
++                               compatible = "regulator-fixed";
++                               regulator-name = "3V3";
++                               regulator-min-microvolt = <3300000>;
++                               regulator-max-microvolt = <3300000>;
++                               regulator-always-on;
++                       };
++
++                       mcc {
++                               compatible = "arm,vexpress,config-bus";
++                               arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++                               v2m_oscclk1: oscclk1 {
++                                       /* CLCD clock */
++                                       compatible = "arm,vexpress-osc";
++                                       arm,vexpress-sysreg,func = <1 1>;
++                                       freq-range = <23750000 63500000>;
++                                       #clock-cells = <0>;
++                                       clock-output-names = "v2m:oscclk1";
++                               };
++
++                               reset {
++                                       compatible = "arm,vexpress-reset";
++                                       arm,vexpress-sysreg,func = <5 0>;
++                               };
++
++                               muxfpga {
++                                       compatible = "arm,vexpress-muxfpga";
++                                       arm,vexpress-sysreg,func = <7 0>;
++                               };
++
++                               shutdown {
++                                       compatible = "arm,vexpress-shutdown";
++                                       arm,vexpress-sysreg,func = <8 0>;
++                               };
++
++                               reboot {
++                                       compatible = "arm,vexpress-reboot";
++                                       arm,vexpress-sysreg,func = <9 0>;
++                               };
++
++                               dvimode {
++                                       compatible = "arm,vexpress-dvimode";
++                                       arm,vexpress-sysreg,func = <11 0>;
++                               };
++                       };
++               };
++       };
++};

meta-arm-bsp/recipes-kernel/linux/files/gem5-dts.patch

@@ -0,0 +1,757 @@
+Add DTS files which are not yet upstream.
+
+Upstream-Status: Pending
+Signed-off-by: Bertrand Marquis <bertrand.marquis@arm.com>
+
+diff --git a/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_1cpu.dts b/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_1cpu.dts
+new file mode 100644
+index 000000000000..0e59fdf89054
+--- /dev/null
++++ b/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_1cpu.dts
+@@ -0,0 +1,95 @@
++/*
++ * Copyright (c) 2015-2016 ARM Limited
++ * All rights reserved
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are
++ * met: redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer;
++ * redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution;
++ * neither the name of the copyright holders nor the names of its
++ * contributors may be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * Authors: Andreas Sandberg
++ */
++
++/dts-v1/;
++
++/memreserve/ 0x80000000 0x00010000;
++
++/include/ "vexpress_gem5_v2.dtsi"
++
++/ {
++	model = "V2P-AARCH64";
++	compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
++
++	memory@80000000 {
++		device_type = "memory";
++		reg = <0 0x80000000 0x4 0x00000000>;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++        cpu@0 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 0 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++	};
++
++	virt-encoder {
++		compatible = "drm,virtual-encoder";
++		port {
++			dp0_virt_input: endpoint@0 {
++				remote-endpoint = <&dp0_output>;
++			};
++		};
++
++		display-timings {
++			native-mode = <&timing0>;
++
++			timing0: timing_1080p60 {
++				/* 1920x1080-60 */
++				clock-frequency = <148500000>;
++				hactive = <1920>;
++				vactive = <1080>;
++				hfront-porch = <148>;
++				hback-porch = <88>;
++				hsync-len = <44>;
++				vfront-porch = <36>;
++				vback-porch = <4>;
++				vsync-len = <5>;
++			};
++		};
++	};
++};
++
++&dp0 {
++	status = "ok";
++
++	port {
++		dp0_output: endpoint@0 {
++			remote-endpoint = <&dp0_virt_input>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_2cpu.dts b/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_2cpu.dts
+new file mode 100644
+index 000000000000..441d3df2a16f
+--- /dev/null
++++ b/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_2cpu.dts
+@@ -0,0 +1,103 @@
++/*
++ * Copyright (c) 2015-2016 ARM Limited
++ * All rights reserved
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are
++ * met: redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer;
++ * redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution;
++ * neither the name of the copyright holders nor the names of its
++ * contributors may be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * Authors: Andreas Sandberg
++ */
++
++/dts-v1/;
++
++/memreserve/ 0x80000000 0x00010000;
++
++/include/ "vexpress_gem5_v2.dtsi"
++
++/ {
++	model = "V2P-AARCH64";
++	compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
++
++	memory@80000000 {
++		device_type = "memory";
++		reg = <0 0x80000000 0x4 0x00000000>;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++        cpu@0 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 0 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@1 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 1 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++	};
++
++	virt-encoder {
++		compatible = "drm,virtual-encoder";
++		port {
++			dp0_virt_input: endpoint@0 {
++				remote-endpoint = <&dp0_output>;
++			};
++		};
++
++		display-timings {
++			native-mode = <&timing0>;
++
++			timing0: timing_1080p60 {
++				/* 1920x1080-60 */
++				clock-frequency = <148500000>;
++				hactive = <1920>;
++				vactive = <1080>;
++				hfront-porch = <148>;
++				hback-porch = <88>;
++				hsync-len = <44>;
++				vfront-porch = <36>;
++				vback-porch = <4>;
++				vsync-len = <5>;
++			};
++		};
++	};
++};
++
++&dp0 {
++	status = "ok";
++
++	port {
++		dp0_output: endpoint@0 {
++			remote-endpoint = <&dp0_virt_input>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_4cpu.dts b/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_4cpu.dts
+new file mode 100644
+index 000000000000..2d0311a5f893
+--- /dev/null
++++ b/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_4cpu.dts
+@@ -0,0 +1,119 @@
++/*
++ * Copyright (c) 2015-2016 ARM Limited
++ * All rights reserved
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are
++ * met: redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer;
++ * redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution;
++ * neither the name of the copyright holders nor the names of its
++ * contributors may be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * Authors: Andreas Sandberg
++ */
++
++/dts-v1/;
++
++/memreserve/ 0x80000000 0x00010000;
++
++/include/ "vexpress_gem5_v2.dtsi"
++
++/ {
++	model = "V2P-AARCH64";
++	compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
++
++	memory@80000000 {
++		device_type = "memory";
++		reg = <0 0x80000000 0x4 0x00000000>;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++        cpu@0 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 0 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@1 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 1 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@2 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 2 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@3 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 3 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++	};
++
++	virt-encoder {
++		compatible = "drm,virtual-encoder";
++		port {
++			dp0_virt_input: endpoint@0 {
++				remote-endpoint = <&dp0_output>;
++			};
++		};
++
++		display-timings {
++			native-mode = <&timing0>;
++
++			timing0: timing_1080p60 {
++				/* 1920x1080-60 */
++				clock-frequency = <148500000>;
++				hactive = <1920>;
++				vactive = <1080>;
++				hfront-porch = <148>;
++				hback-porch = <88>;
++				hsync-len = <44>;
++				vfront-porch = <36>;
++				vback-porch = <4>;
++				vsync-len = <5>;
++			};
++		};
++	};
++};
++
++&dp0 {
++	status = "ok";
++
++	port {
++		dp0_output: endpoint@0 {
++			remote-endpoint = <&dp0_virt_input>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_8cpu.dts b/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_8cpu.dts
+new file mode 100644
+index 000000000000..ba94d0746958
+--- /dev/null
++++ b/arch/arm64/boot/dts/gem5-arm64/armv8_gem5_v2_8cpu.dts
+@@ -0,0 +1,151 @@
++/*
++ * Copyright (c) 2015-2016 ARM Limited
++ * All rights reserved
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are
++ * met: redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer;
++ * redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution;
++ * neither the name of the copyright holders nor the names of its
++ * contributors may be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * Authors: Andreas Sandberg
++ */
++
++/dts-v1/;
++
++/memreserve/ 0x80000000 0x00010000;
++
++/include/ "vexpress_gem5_v2.dtsi"
++
++/ {
++	model = "V2P-AARCH64";
++	compatible = "arm,vexpress,v2p-aarch64", "arm,vexpress";
++
++	memory@80000000 {
++		device_type = "memory";
++		reg = <0 0x80000000 0x4 0x00000000>;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++        cpu@0 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 0 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@1 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 1 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@2 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 2 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@3 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 3 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@4 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 4 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@5 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 5 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@6 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 6 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++        cpu@7 {
++            device_type = "cpu";
++            compatible = "gem5,armv8", "arm,armv8";
++            reg = < 7 >;
++            enable-method = "spin-table";
++            cpu-release-addr = <0 0x8000fff8>;
++        };
++
++	};
++
++	virt-encoder {
++		compatible = "drm,virtual-encoder";
++		port {
++			dp0_virt_input: endpoint@0 {
++				remote-endpoint = <&dp0_output>;
++			};
++		};
++
++		display-timings {
++			native-mode = <&timing0>;
++
++			timing0: timing_1080p60 {
++				/* 1920x1080-60 */
++				clock-frequency = <148500000>;
++				hactive = <1920>;
++				vactive = <1080>;
++				hfront-porch = <148>;
++				hback-porch = <88>;
++				hsync-len = <44>;
++				vfront-porch = <36>;
++				vback-porch = <4>;
++				vsync-len = <5>;
++			};
++		};
++	};
++};
++
++&dp0 {
++	status = "ok";
++
++	port {
++		dp0_output: endpoint@0 {
++			remote-endpoint = <&dp0_virt_input>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/gem5-arm64/vexpress_gem5_v2.dtsi b/arch/arm64/boot/dts/gem5-arm64/vexpress_gem5_v2.dtsi
+new file mode 100644
+index 000000000000..e53e6e84b301
+--- /dev/null
++++ b/arch/arm64/boot/dts/gem5-arm64/vexpress_gem5_v2.dtsi
+@@ -0,0 +1,46 @@
++/*
++ * Copyright (c) 2015-2018 ARM Limited
++ * All rights reserved
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are
++ * met: redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer;
++ * redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution;
++ * neither the name of the copyright holders nor the names of its
++ * contributors may be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * Authors: Andreas Sandberg
++ */
++
++/include/ "vexpress_gem5_v2_base.dtsi"
++
++/ {
++	/* The display processor needs custom configuration to setup its
++	 * output ports. Disable it by default in the platform until the
++	 * DT bindings have stabilize.
++	 */
++	dp0: hdlcd@2b000000 {
++		compatible = "arm,hdlcd";
++		reg = <0x0 0x2b000000 0x0 0x1000>;
++		interrupts = <0 63 4>;
++		clocks = <&osc_pxl>;
++		clock-names = "pxlclk";
++		status = "disabled";
++	};
++};
+diff --git a/arch/arm64/boot/dts/gem5-arm64/vexpress_gem5_v2_base.dtsi b/arch/arm64/boot/dts/gem5-arm64/vexpress_gem5_v2_base.dtsi
+new file mode 100644
+index 000000000000..eba0db2526df
+--- /dev/null
++++ b/arch/arm64/boot/dts/gem5-arm64/vexpress_gem5_v2_base.dtsi
+@@ -0,0 +1,202 @@
++/*
++ * Copyright (c) 2015-2017, 2019 ARM Limited
++ * All rights reserved
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are
++ * met: redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer;
++ * redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution;
++ * neither the name of the copyright holders nor the names of its
++ * contributors may be used to endorse or promote products derived from
++ * this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * Authors: Andreas Sandberg
++ */
++
++/ {
++	arm,hbi = <0x0>;
++	arm,vexpress,site = <0xf>;
++	interrupt-parent = <&gic>;
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	gic: interrupt-controller@2c000000 {
++		compatible = "arm,gic-v3";
++		#interrupt-cells = <0x3>;
++		#address-cells = <0x2>;
++		ranges;
++		interrupt-controller;
++		redistributor-stride = <0x0 0x40000>; // 256kB stride
++		reg = <0x0 0x2c000000 0x0 0x10000
++		       0x0 0x2c010000 0x0 0x2000000 // room for 128 redistributors using 128K each (256K strided...)
++		       0x0 0x0 0x0 0x0>;
++		interrupts = <1 9 0xf04>;
++		#size-cells = <0x2>;
++		linux,phandle = <0x1>;
++		phandle = <0x1>;
++
++		gic-its@2e010000 {
++			compatible = "arm,gic-v3-its";
++			msi-controller;
++			#msi-cells = <1>;
++			reg = <0x0 0x2e010000 0 0x20000>;
++		};
++	};
++
++	timer {
++		compatible = "arm,cortex-a15-timer",
++			     "arm,armv7-timer";
++		interrupts = <1 13 0xf08>,
++		             <1 14 0xf08>,
++			     <1 11 0xf08>,
++		             <1 10 0xf08>;
++		clocks = <&osc_sys>;
++		clock-names="apb_pclk";
++	};
++
++	pci {
++		compatible = "pci-host-ecam-generic";
++		device_type = "pci";
++		#address-cells = <0x3>;
++		#size-cells = <0x2>;
++		#interrupt-cells = <0x1>;
++
++		reg = <0x0 0x30000000 0x0 0x10000000>;
++
++		ranges = <0x01000000 0x0 0x00000000  0x0 0x2f000000  0x0 0x00010000>,
++		         <0x02000000 0x0 0x40000000  0x0 0x40000000  0x0 0x40000000>;
++
++	/*
++	  child unit address, #cells = #address-cells
++	  child interrupt specifier, #cells = #interrupt-cells (INTA = 1, INTB = 2, INTC = 3 and INTD = 4)
++	  interrupt-parent, phandle
++	  parent unit address, #cells = #address-cells@gic
++	  parent interrupt specifier, #cells = #interrupt-cells@gic
++	*/
++	interrupt-map = <0x0    0x0 0x0  0x1  &gic  0x0 0x0  0x0 0x44 0x1
++		         0x800  0x0 0x0  0x1  &gic  0x0 0x0  0x0 0x45 0x1
++		         0x1000 0x0 0x0  0x1  &gic  0x0 0x0  0x0 0x46 0x1
++		         0x1800 0x0 0x0  0x1  &gic  0x0 0x0  0x0 0x47 0x1>;
++
++	interrupt-map-mask = <0x001800 0x0 0x0 0x0>;
++	dma-coherent;
++	};
++
++	kmi@1c060000 {
++		compatible = "arm,pl050", "arm,primecell";
++		reg = <0x0 0x1c060000 0x0 0x1000>;
++		interrupts = <0 12 4>;
++		clocks = <&v2m_clk24mhz>, <&osc_smb>;
++		clock-names = "KMIREFCLK", "apb_pclk";
++	};
++
++	kmi@1c070000 {
++		compatible = "arm,pl050", "arm,primecell";
++		reg = <0x0 0x1c070000 0x0 0x1000>;
++		interrupts = <0 13 4>;
++		clocks = <&v2m_clk24mhz>, <&osc_smb>;
++		clock-names = "KMIREFCLK", "apb_pclk";
++	};
++
++	uart0: uart@1c090000 {
++		compatible = "arm,pl011", "arm,primecell";
++		reg = <0x0 0x1c090000 0x0 0x1000>;
++		interrupts = <0 5 4>;
++		clocks = <&osc_peripheral>, <&osc_smb>;
++		clock-names = "uartclk", "apb_pclk";
++	};
++
++	rtc@1c170000 {
++		compatible = "arm,pl031", "arm,primecell";
++		reg = <0x0 0x1c170000 0x0 0x1000>;
++		interrupts = <0 4 4>;
++		clocks = <&osc_smb>;
++		clock-names = "apb_pclk";
++	};
++
++	v2m_clk24mhz: clk24mhz {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <24000000>;
++		clock-output-names = "v2m:clk24mhz";
++	};
++
++
++	v2m_sysreg: sysreg@1c010000 {
++		compatible = "arm,vexpress-sysreg";
++		reg = <0 0x1c010000 0x0 0x1000>;
++		gpio-controller;
++		#gpio-cells = <2>;
++	};
++
++	vio@1c130000 {
++		compatible = "virtio,mmio";
++		reg = <0 0x1c130000 0x0 0x1000>;
++		interrupts = <0 42 4>;
++	};
++
++	vio@1c140000 {
++		compatible = "virtio,mmio";
++		reg = <0 0x1c140000 0x0 0x1000>;
++		interrupts = <0 43 4>;
++	};
++
++	dcc {
++		compatible = "arm,vexpress,config-bus";
++		arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++		osc_pxl: osc@5 {
++			compatible = "arm,vexpress-osc";
++			arm,vexpress-sysreg,func = <1 5>;
++			freq-range = <23750000 1000000000>;
++			#clock-cells = <0>;
++			clock-output-names = "oscclk5";
++		};
++
++		osc_smb: osc@6 {
++			compatible = "arm,vexpress-osc";
++			arm,vexpress-sysreg,func = <1 6>;
++			freq-range = <20000000 50000000>;
++			#clock-cells = <0>;
++			clock-output-names = "oscclk6";
++		};
++
++		osc_sys: osc@7 {
++			compatible = "arm,vexpress-osc";
++			arm,vexpress-sysreg,func = <1 7>;
++			freq-range = <20000000 60000000>;
++			#clock-cells = <0>;
++			clock-output-names = "oscclk7";
++		};
++	};
++
++
++	mcc {
++		compatible = "arm,vexpress,config-bus";
++		arm,vexpress,config-bridge = <&v2m_sysreg>;
++		arm,vexpress,site = <0>;
++
++		osc_peripheral: osc@2 {
++			compatible = "arm,vexpress-osc";
++			arm,vexpress-sysreg,func = <1 2>;
++			freq-range = <24000000 24000000>;
++			#clock-cells = <0>;
++			clock-output-names = "v2m:oscclk2";
++		};
++	};
++};

meta-arm-bsp/recipes-kernel/linux/files/tc0/defconfig

@@ -0,0 +1,906 @@
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_PSI=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_BLK_CGROUP=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_BPF=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_TUNE=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_FHANDLE is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_BPF_JIT_ALWAYS_ON=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_ALPINE=y
+CONFIG_ARCH_BCM2835=y
+CONFIG_ARCH_BCM_IPROC=y
+CONFIG_ARCH_BERLIN=y
+CONFIG_ARCH_BRCMSTB=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_K3=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_LG1K=y
+CONFIG_ARCH_HISI=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_ARCH_MESON=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_SEATTLE=y
+CONFIG_ARCH_SYNQUACER=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R8A7795=y
+CONFIG_ARCH_R8A7796=y
+CONFIG_ARCH_R8A77965=y
+CONFIG_ARCH_R8A77970=y
+CONFIG_ARCH_R8A77980=y
+CONFIG_ARCH_R8A77990=y
+CONFIG_ARCH_R8A77995=y
+CONFIG_ARCH_STRATIX10=y
+CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_SPRD=y
+CONFIG_ARCH_THUNDER=y
+CONFIG_ARCH_THUNDER2=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_XGENE=y
+CONFIG_ARCH_ZX=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_PCI=y
+CONFIG_PCI_IOV=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_PCI_AARDVARK=y
+CONFIG_PCI_TEGRA=y
+CONFIG_PCIE_RCAR=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_XGENE=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCIE_ROCKCHIP_HOST=m
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_HISI=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCIE_ARMADA_8K=y
+CONFIG_PCIE_KIRIN=y
+CONFIG_PCIE_HISI_STB=y
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_SCHED_MC=y
+CONFIG_NUMA=y
+CONFIG_SECCOMP=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_XEN=y
+CONFIG_ARM64_SW_TTBR0_PAN=y
+CONFIG_RANDOMIZE_BASE=y
+CONFIG_COMPAT=y
+CONFIG_HIBERNATION=y
+CONFIG_PM_DEBUG=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
+CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_TEGRA186_CPUFREQ=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_RASPBERRYPI_FIRMWARE=y
+CONFIG_EFI_CAPSULE_LOADER=y
+CONFIG_ACPI=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64_CE=m
+CONFIG_CRYPTO_SHA3_ARM64=m
+CONFIG_CRYPTO_SM3_ARM64_CE=m
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
+CONFIG_CRYPTO_CRC32_ARM64_CE=m
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_AES_ARM64_BS=m
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_MEMORY_FAILURE=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_CMA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_INTERFACE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_NET_IPVTI=y
+CONFIG_INET_ESP=y
+CONFIG_INET_UDP_DIAG=y
+CONFIG_INET_DIAG_DESTROY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_VTI=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
+CONFIG_NETFILTER_XT_TARGET_CT=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_SECURITY=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_RPFILTER=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_L2TP=y
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_NETEM=y
+CONFIG_NET_SCH_INGRESS=y
+CONFIG_NET_CLS_U32=y
+CONFIG_NET_CLS_BPF=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_BPF_JIT=y
+CONFIG_BT=m
+CONFIG_BT_HIDP=m
+# CONFIG_BT_HS is not set
+# CONFIG_BT_LE is not set
+CONFIG_BT_LEDS=y
+# CONFIG_BT_DEBUGFS is not set
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_CFG80211=m
+CONFIG_MAC80211=m
+CONFIG_MAC80211_LEDS=y
+CONFIG_RFKILL=m
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=32
+CONFIG_HISILICON_LPC=y
+CONFIG_SIMPLE_PM_BUS=y
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_DENALI_DT=y
+CONFIG_MTD_NAND_MARVELL=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_NVME=m
+CONFIG_SRAM=y
+CONFIG_UID_SYS_STATS=y
+CONFIG_EEPROM_AT25=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_HISI_SAS=y
+CONFIG_SCSI_HISI_SAS_PCI=y
+CONFIG_SCSI_UFSHCD=m
+CONFIG_SCSI_UFSHCD_PLATFORM=m
+CONFIG_SCSI_UFS_QCOM=m
+CONFIG_SCSI_UFS_HISI=m
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_AHCI_XGENE=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_SATA_SIL24=y
+CONFIG_SATA_RCAR=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_SNAPSHOT=y
+CONFIG_DM_UEVENT=y
+CONFIG_DM_VERITY=y
+CONFIG_DM_VERITY_FEC=y
+CONFIG_DM_BOW=y
+CONFIG_NETDEVICES=y
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_TUN=y
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=y
+CONFIG_AMD_XGBE=y
+CONFIG_NET_XGENE=y
+CONFIG_ATL1C=m
+CONFIG_MACB=y
+CONFIG_THUNDER_NIC_PF=y
+CONFIG_HIX5HD2_GMAC=y
+CONFIG_HNS_DSAF=y
+CONFIG_HNS_ENET=y
+CONFIG_E1000E=y
+CONFIG_IGB=y
+CONFIG_IGBVF=y
+CONFIG_MVNETA=y
+CONFIG_MVPP2=y
+CONFIG_SKY2=y
+CONFIG_QCOM_EMAC=m
+CONFIG_RAVB=y
+CONFIG_SMC91X=y
+CONFIG_SMSC911X=y
+CONFIG_SNI_AVE=y
+CONFIG_SNI_NETSEC=y
+CONFIG_STMMAC_ETH=m
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_AT803X_PHY=m
+CONFIG_MARVELL_PHY=m
+CONFIG_MARVELL_10G_PHY=m
+CONFIG_MESON_GXL_PHY=m
+CONFIG_MICREL_PHY=y
+CONFIG_REALTEK_PHY=m
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_PPP=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_MPPE=y
+CONFIG_PPTP=y
+CONFIG_PPPOL2TP=y
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_RTL8152=y
+CONFIG_USB_LAN78XX=m
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_SR9800=m
+CONFIG_USB_NET_SMSC75XX=m
+CONFIG_USB_NET_SMSC95XX=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_ATH10K=m
+CONFIG_ATH10K_PCI=m
+CONFIG_BRCMFMAC=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_PCIE=m
+CONFIG_WL18XX=m
+CONFIG_WLCORE_SDIO=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_ADC=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_CROS_EC=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=y
+CONFIG_JOYSTICK_XPAD_FF=y
+CONFIG_JOYSTICK_XPAD_LEDS=y
+CONFIG_INPUT_TABLET=y
+CONFIG_TABLET_USB_ACECAD=y
+CONFIG_TABLET_USB_AIPTEK=y
+CONFIG_TABLET_USB_GTCO=y
+CONFIG_TABLET_USB_HANWANG=y
+CONFIG_TABLET_USB_KBTAB=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PM8941_PWRKEY=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_INPUT_HISI_POWERKEY=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_BCM2835AUX=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_MT6577=y
+CONFIG_SERIAL_8250_UNIPHIER=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MESON=y
+CONFIG_SERIAL_MESON_CONSOLE=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_TEGRA=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS_I2C_INFINEON=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_BCM2835=m
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_MESON=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_PXA=y
+CONFIG_I2C_QUP=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SH_MOBILE=y
+CONFIG_I2C_TEGRA=y
+CONFIG_I2C_UNIPHIER_F=y
+CONFIG_I2C_VERSATILE=y
+CONFIG_I2C_RCAR=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SPI=y
+CONFIG_SPI_ARMADA_3700=y
+CONFIG_SPI_BCM2835=m
+CONFIG_SPI_BCM2835AUX=m
+CONFIG_SPI_MESON_SPICC=m
+CONFIG_SPI_MESON_SPIFC=m
+CONFIG_SPI_ORION=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_QUP=y
+CONFIG_SPI_S3C64XX=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_SPMI=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_MAX77620=y
+CONFIG_PINCTRL_IPQ8074=y
+CONFIG_PINCTRL_MSM8916=y
+CONFIG_PINCTRL_MSM8994=y
+CONFIG_PINCTRL_MSM8996=y
+CONFIG_PINCTRL_QDF2XXX=y
+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
+CONFIG_PINCTRL_MT7622=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_MB86S7X=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_RCAR=y
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_GPIO_XGENE=y
+CONFIG_GPIO_XGENE_SB=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_MAX77620=y
+CONFIG_POWER_AVS=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_SYSCON_REBOOT_MODE=y
+CONFIG_BATTERY_SBS=m
+CONFIG_BATTERY_BQ27XXX=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_RASPBERRYPI_HWMON=m
+CONFIG_SENSORS_INA2XX=m
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_ROCKCHIP_THERMAL=m
+CONFIG_RCAR_GEN3_THERMAL=y
+CONFIG_ARMADA_THERMAL=y
+CONFIG_BRCMSTB_THERMAL=m
+CONFIG_EXYNOS_THERMAL=y
+CONFIG_TEGRA_BPMP_THERMAL=m
+CONFIG_QCOM_TSENS=y
+CONFIG_UNIPHIER_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_S3C2410_WATCHDOG=y
+CONFIG_MESON_GXBB_WATCHDOG=m
+CONFIG_MESON_WATCHDOG=m
+CONFIG_RENESAS_WDT=y
+CONFIG_UNIPHIER_WATCHDOG=y
+CONFIG_BCM2835_WDT=y
+CONFIG_MFD_BD9571MWV=y
+CONFIG_MFD_AXP20X_RSB=y
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_CHARDEV=m
+CONFIG_MFD_EXYNOS_LPASS=m
+CONFIG_MFD_HI6421_PMIC=y
+CONFIG_MFD_HI655X_PMIC=y
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_SPMI_PMIC=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BD9571MWV=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_HI6421V530=y
+CONFIG_REGULATOR_HI655X=y
+CONFIG_REGULATOR_MAX77620=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_SMD_RPM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_VCTRL=m
+CONFIG_RC_CORE=m
+CONFIG_RC_DECODERS=y
+CONFIG_RC_DEVICES=y
+CONFIG_IR_MESON=m
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+# CONFIG_DVB_NET is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
+CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
+CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
+CONFIG_VIDEO_RENESAS_FCP=m
+CONFIG_VIDEO_RENESAS_VSP1=m
+CONFIG_DRM=y
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_I2C_NXP_TDA998X=y
+CONFIG_DRM_HDLCD=y
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_VIRT_ENCODER=y
+CONFIG_DRM_EXYNOS=m
+CONFIG_DRM_EXYNOS5433_DECON=y
+CONFIG_DRM_EXYNOS7_DECON=y
+CONFIG_DRM_EXYNOS_DSI=y
+# CONFIG_DRM_EXYNOS_DP is not set
+CONFIG_DRM_EXYNOS_HDMI=y
+CONFIG_DRM_EXYNOS_MIC=y
+CONFIG_DRM_ROCKCHIP=m
+CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_CDN_DP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_DRM_RCAR_DU=m
+CONFIG_DRM_RCAR_LVDS=m
+CONFIG_DRM_TEGRA=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_I2C_ADV7511=m
+CONFIG_DRM_VC4=m
+CONFIG_DRM_HISI_HIBMC=m
+CONFIG_DRM_HISI_KIRIN=m
+CONFIG_DRM_MESON=m
+CONFIG_FB_ARMCLCD=y
+CONFIG_BACKLIGHT_GENERIC=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_BCM2835_SOC_I2S=m
+CONFIG_SND_SOC_ROCKCHIP=m
+CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
+CONFIG_SND_SOC_ROCKCHIP_RT5645=m
+CONFIG_SND_SOC_RK3399_GRU_SOUND=m
+CONFIG_SND_SOC_SAMSUNG=y
+CONFIG_SND_SOC_RCAR=m
+CONFIG_SND_SOC_AK4613=m
+CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_AUDIO_GRAPH_CARD=m
+CONFIG_HIDRAW=y
+CONFIG_UHID=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_ACRUX=y
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_PRODIKEYS=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=y
+CONFIG_HID_ELECOM=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_HOLTEK=y
+CONFIG_HID_KEYTOUCH=y
+CONFIG_HID_KYE=y
+CONFIG_HID_UCLOGIC=y
+CONFIG_HID_WALTOP=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LCPOWER=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_LOGITECH_DJ=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_ORTEK=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_PICOLCD=y
+CONFIG_HID_PRIMAX=y
+CONFIG_HID_ROCCAT=y
+CONFIG_HID_SAITEK=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SPEEDLINK=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_HID_WACOM=y
+CONFIG_HID_WIIMOTE=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_HID_ZYDACRON=y
+CONFIG_USB_HIDDEV=y
+CONFIG_I2C_HID=m
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_OTG=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_TEGRA=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_EXYNOS=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_EXYNOS=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_RENESAS_USBHS=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_HSIC_USB3503=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=m
+CONFIG_USB_RENESAS_USB3=m
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_UEVENT=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_ACC=y
+CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y
+CONFIG_USB_CONFIGFS_F_MIDI=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMC_SDHCI_F_SDH30=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_SPI=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_HI3798CV200=y
+CONFIG_MMC_DW_K3=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MMC_BCM2835=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_EDAC=y
+CONFIG_EDAC_GHES=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_RK808=m
+CONFIG_RTC_DRV_S5M=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_CROS_EC=y
+CONFIG_RTC_DRV_S3C=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_RTC_DRV_ARMADA38X=y
+CONFIG_RTC_DRV_TEGRA=y
+CONFIG_RTC_DRV_XGENE=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_BCM2835=m
+CONFIG_K3_DMA=y
+CONFIG_MV_XOR_V2=y
+CONFIG_PL330_DMA=y
+CONFIG_TEGRA20_APB_DMA=y
+CONFIG_QCOM_BAM_DMA=y
+CONFIG_QCOM_HIDMA_MGMT=y
+CONFIG_QCOM_HIDMA=y
+CONFIG_RCAR_DMAC=y
+CONFIG_RENESAS_USB_DMAC=m
+CONFIG_VFIO=y
+CONFIG_VFIO_PCI=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+CONFIG_STAGING=y
+CONFIG_ASHMEM=y
+CONFIG_ION=y
+CONFIG_CROS_EC_I2C=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_S2MPS11=y
+CONFIG_CLK_QORIQ=y
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_QCOM_CLK_SMD_RPM=y
+CONFIG_IPQ_GCC_8074=y
+CONFIG_MSM_GCC_8916=y
+CONFIG_MSM_GCC_8994=y
+CONFIG_MSM_MMCC_8996=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_ARM_MHU=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_BCM2835_MBOX=y
+CONFIG_QCOM_APCS_IPC=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_TEGRA_IOMMU_SMMU=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_QCOM_IOMMU=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
+CONFIG_RPMSG_QCOM_SMD=y
+CONFIG_RASPBERRYPI_POWER=y
+CONFIG_QCOM_SMEM=y
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_QCOM_SMP2P=y
+CONFIG_QCOM_SMSM=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+CONFIG_ARCH_TEGRA_132_SOC=y
+CONFIG_ARCH_TEGRA_210_SOC=y
+CONFIG_ARCH_TEGRA_186_SOC=y
+CONFIG_ARCH_TEGRA_194_SOC=y
+CONFIG_ARCH_K3_AM6_SOC=y
+CONFIG_SOC_TI=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_EXTCON_USBC_CROS_EC=y
+CONFIG_MEMORY=y
+CONFIG_IIO=y
+CONFIG_EXYNOS_ADC=y
+CONFIG_ROCKCHIP_SARADC=m
+CONFIG_IIO_CROS_EC_SENSORS_CORE=m
+CONFIG_IIO_CROS_EC_SENSORS=m
+CONFIG_IIO_CROS_EC_LIGHT_PROX=m
+CONFIG_IIO_CROS_EC_BARO=m
+CONFIG_PWM=y
+CONFIG_PWM_BCM2835=m
+CONFIG_PWM_CROS_EC=m
+CONFIG_PWM_MESON=m
+CONFIG_PWM_RCAR=m
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_SAMSUNG=y
+CONFIG_PWM_TEGRA=m
+CONFIG_PHY_XGENE=y
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_HI6220_USB=y
+CONFIG_PHY_HISTB_COMBPHY=y
+CONFIG_PHY_HISI_INNO_USB2=y
+CONFIG_PHY_MVEBU_CP110_COMPHY=y
+CONFIG_PHY_QCOM_QMP=m
+CONFIG_PHY_QCOM_USB_HS=y
+CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_RCAR_GEN3_USB3=m
+CONFIG_PHY_ROCKCHIP_EMMC=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_PCIE=m
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_TEGRA_XUSB=y
+CONFIG_HISI_PMU=y
+CONFIG_QCOM_L2_PMU=y
+CONFIG_QCOM_L3_PMU=y
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_QCOM_QFPROM=y
+CONFIG_ROCKCHIP_EFUSE=y
+CONFIG_UNIPHIER_EFUSE=y
+CONFIG_MESON_EFUSE=m
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXT4_ENCRYPTION=y
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_F2FS_FS=y
+CONFIG_F2FS_FS_SECURITY=y
+CONFIG_F2FS_FS_ENCRYPTION=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_QFMT_V2=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=m
+CONFIG_OVERLAY_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_EFIVAR_FS=y
+CONFIG_SDCARD_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_RAM=y
+CONFIG_9P_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_HARDENED_USERCOPY=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_PANIC_TIMEOUT=5
+CONFIG_SCHEDSTATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_MEMTEST=y

meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc

@@ -8,7 +8,18 @@
 FILESEXTRAPATHS_prepend := "${THISDIR}:${THISDIR}/files:"
 
 # Arm platforms kmeta
-SRC_URI += "file://arm-platforms-kmeta;type=kmeta;name=arm-platforms-kmeta;destsuffix=arm-platforms-kmeta"
+SRC_URI_KMETA = "file://arm-platforms-kmeta;type=kmeta;name=arm-platforms-kmeta;destsuffix=arm-platforms-kmeta"
+SRC_URI_append_foundation-armv8 = " ${SRC_URI_KMETA}"
+SRC_URI_append_fvp-base = " ${SRC_URI_KMETA}"
+SRC_URI_append_juno = " ${SRC_URI_KMETA}"
+SRC_URI_append_gem5-arm64 = " ${SRC_URI_KMETA}"
+SRCREV_arm-platforms-kmeta = "6147e82375aa9df8f2a162d42ea6406c79c854c5"
+
+#
+# Cortex-A5 DesignStart KMACHINE
+#
+COMPATIBLE_MACHINE_a5ds = "a5ds"
+KMACHINE_a5ds = "a5ds"
 
 #
 # FVP FOUNDATION KMACHINE
@@ -21,12 +32,7 @@ KMACHINE_foundation-armv8 = "fvp"
 #
 COMPATIBLE_MACHINE_fvp-base = "fvp-base"
 KMACHINE_fvp-base = "fvp"
-SRC_URI_append_fvp-base = " file://dts/arm;subdir=add-files"
-
-do_patch_append_fvp-base() {
-    tar -C ${WORKDIR}/add-files/dts -cf - arm | \
-        tar -C arch/arm64/boot/dts -xf -
-}
+SRC_URI_append_fvp-base = " file://fvp-base-dts.patch"
 
 #
 # Juno KMACHINE
@@ -39,9 +45,4 @@ KMACHINE_juno = "juno"
 #
 COMPATIBLE_MACHINE_gem5-arm64 = "gem5-arm64"
 KMACHINE_gem5-arm64 = "gem5-arm64"
-SRC_URI_append_gem5-arm64 = " file://dts/gem5-arm64;subdir=add-files"
-
-do_patch_append_gem5-arm64() {
-    tar -C ${WORKDIR}/add-files/dts -cf - gem5-arm64 | \
-        tar -C arch/arm64/boot/dts -xf -
-}
+SRC_URI_append_gem5-arm64 = " file://gem5-dts.patch"

meta-arm-bsp/recipes-kernel/linux/linux-arm64-ack-4.19/tc0/0001-drm-Add-component-aware-simple-encoder.patch

@@ -0,0 +1,368 @@
+From 6fd66138c44107786879d0adebe78ca94cf6292f Mon Sep 17 00:00:00 2001
+From: Liviu Dudau <Liviu.Dudau@arm.com>
+Date: Wed, 1 Apr 2020 12:10:14 +0100
+Subject: [PATCH 1/2] drm: Add component-aware simple encoder
+
+This is a simple DRM encoder that gets its connector timings information
+from a OF subnode in the device tree and exposes that as a "discovered"
+panel. It can be used together with component-based DRM drivers in an
+emulated environment where no real encoder or connector hardware exists
+and the display output is configured outside the kernel.
+
+Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
+[Backported to gem5's 4.3 kernel]
+Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
+[Ported to gem5's 4.9 kernel. Added dep. on VIDEOMODE_HELPERS.]
+Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
+[Ported to gem5's 4.14 kernel.]
+Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
+Upstream-Status: Backport
+Signed-off-by: Teo Couprie Diaz <teo.coupriediaz@arm.com>
+---
+ drivers/gpu/drm/Kconfig               |  10 ++
+ drivers/gpu/drm/Makefile              |   3 +
+ drivers/gpu/drm/drm_virtual_encoder.c | 297 ++++++++++++++++++++++++++++++++++
+ 3 files changed, 310 insertions(+)
+ create mode 100644 drivers/gpu/drm/drm_virtual_encoder.c
+
+diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
+index e44e567..6e95357 100644
+--- a/drivers/gpu/drm/Kconfig
++++ b/drivers/gpu/drm/Kconfig
+@@ -255,6 +255,16 @@ config DRM_VKMS
+ 
+ 	  If M is selected the module will be called vkms.
+ 
++config DRM_VIRT_ENCODER
++	tristate "Virtual OF-based encoder"
++	depends on DRM && OF
++	select VIDEOMODE_HELPERS
++	help
++	  Choose this option to get a virtual encoder and its associated
++	  connector that will use the device tree to read the display
++	  timings information. If M is selected the module will be called
++	  drm_vencoder.
++
+ source "drivers/gpu/drm/exynos/Kconfig"
+ 
+ source "drivers/gpu/drm/rockchip/Kconfig"
+diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
+index a6771ce..733ad62 100644
+--- a/drivers/gpu/drm/Makefile
++++ b/drivers/gpu/drm/Makefile
+@@ -46,6 +46,9 @@ drm_kms_helper-$(CONFIG_DRM_DP_CEC) += drm_dp_cec.o
+ obj-$(CONFIG_DRM_KMS_HELPER) += drm_kms_helper.o
+ obj-$(CONFIG_DRM_DEBUG_SELFTEST) += selftests/
+ 
++drm_vencoder-y := drm_virtual_encoder.o
++obj-$(CONFIG_DRM_VIRT_ENCODER) += drm_vencoder.o
++
+ obj-$(CONFIG_DRM)	+= drm.o
+ obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
+ obj-$(CONFIG_DRM_PANEL_ORIENTATION_QUIRKS) += drm_panel_orientation_quirks.o
+diff --git a/drivers/gpu/drm/drm_virtual_encoder.c b/drivers/gpu/drm/drm_virtual_encoder.c
+new file mode 100644
+index 00000000..2e2c51d
+--- /dev/null
++++ b/drivers/gpu/drm/drm_virtual_encoder.c
+@@ -0,0 +1,297 @@
++/*
++ * Copyright (C) 2016 ARM Limited
++ * Author: Liviu Dudau <Liviu.Dudau@arm.com>
++ *
++ * Dummy encoder and connector that use the OF to "discover" the attached
++ * display timings. Can be used in situations where the encoder and connector's
++ * functionality are emulated and no setup steps are needed, or to describe
++ * attached panels for which no driver exists but can be used without
++ * additional hardware setup.
++ *
++ * The encoder also uses the component framework so that it can be a quick
++ * replacement for existing drivers when testing in an emulated environment.
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ */
++
++#include <drm/drmP.h>
++#include <drm/drm_crtc.h>
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_of.h>
++#include <linux/component.h>
++#include <video/display_timing.h>
++#include <video/of_display_timing.h>
++#include <video/videomode.h>
++
++struct drm_virt_priv {
++	struct drm_connector connector;
++	struct drm_encoder encoder;
++	struct display_timings *timings;
++};
++
++#define connector_to_drm_virt_priv(x) \
++	container_of(x, struct drm_virt_priv, connector)
++
++#define encoder_to_drm_virt_priv(x) \
++	container_of(x, struct drm_virt_priv, encoder)
++
++static void drm_virtcon_destroy(struct drm_connector *connector)
++{
++	struct drm_virt_priv *conn = connector_to_drm_virt_priv(connector);
++
++	drm_connector_cleanup(connector);
++	display_timings_release(conn->timings);
++}
++
++static enum drm_connector_status
++drm_virtcon_detect(struct drm_connector *connector, bool force)
++{
++	return connector_status_connected;
++}
++
++static const struct drm_connector_funcs drm_virtcon_funcs = {
++	.reset = drm_atomic_helper_connector_reset,
++	.detect	= drm_virtcon_detect,
++	.fill_modes = drm_helper_probe_single_connector_modes,
++	.destroy = drm_virtcon_destroy,
++	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
++	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
++};
++
++static int drm_virtcon_get_modes(struct drm_connector *connector)
++{
++	struct drm_virt_priv *conn = connector_to_drm_virt_priv(connector);
++	struct display_timings *timings = conn->timings;
++	int i;
++
++	for (i = 0; i < timings->num_timings; i++) {
++		struct drm_display_mode *mode = drm_mode_create(connector->dev);
++		struct videomode vm;
++
++		if (videomode_from_timings(timings, &vm, i))
++			break;
++
++		drm_display_mode_from_videomode(&vm, mode);
++		mode->type = DRM_MODE_TYPE_DRIVER;
++		if (timings->native_mode == i)
++			mode->type = DRM_MODE_TYPE_PREFERRED;
++
++		drm_mode_set_name(mode);
++		drm_mode_probed_add(connector, mode);
++	}
++
++	return i;
++}
++
++static int drm_virtcon_mode_valid(struct drm_connector *connector,
++				   struct drm_display_mode *mode)
++{
++	return MODE_OK;
++}
++
++struct drm_encoder *drm_virtcon_best_encoder(struct drm_connector *connector)
++{
++	struct drm_virt_priv *priv = connector_to_drm_virt_priv(connector);
++
++	return &priv->encoder;
++}
++
++struct drm_encoder *
++drm_virtcon_atomic_best_encoder(struct drm_connector *connector,
++				 struct drm_connector_state *connector_state)
++{
++	struct drm_virt_priv *priv = connector_to_drm_virt_priv(connector);
++
++	return &priv->encoder;
++}
++
++static const struct drm_connector_helper_funcs drm_virtcon_helper_funcs = {
++	.get_modes = drm_virtcon_get_modes,
++	.mode_valid = drm_virtcon_mode_valid,
++	.best_encoder = drm_virtcon_best_encoder,
++	.atomic_best_encoder = drm_virtcon_atomic_best_encoder,
++};
++
++static void drm_vencoder_destroy(struct drm_encoder *encoder)
++{
++	drm_encoder_cleanup(encoder);
++}
++
++static const struct drm_encoder_funcs drm_vencoder_funcs = {
++	.destroy = drm_vencoder_destroy,
++};
++
++static void drm_vencoder_dpms(struct drm_encoder *encoder, int mode)
++{
++	/* nothing needed */
++}
++
++static bool drm_vencoder_mode_fixup(struct drm_encoder *encoder,
++				    const struct drm_display_mode *mode,
++				    struct drm_display_mode *adjusted_mode)
++{
++	/* nothing needed */
++	return true;
++}
++
++static void drm_vencoder_prepare(struct drm_encoder *encoder)
++{
++	drm_vencoder_dpms(encoder, DRM_MODE_DPMS_OFF);
++}
++
++static void drm_vencoder_commit(struct drm_encoder *encoder)
++{
++	drm_vencoder_dpms(encoder, DRM_MODE_DPMS_ON);
++}
++
++static void drm_vencoder_mode_set(struct drm_encoder *encoder,
++				  struct drm_display_mode *mode,
++				  struct drm_display_mode *adjusted_mode)
++{
++	/* nothing needed */
++}
++
++static const struct drm_encoder_helper_funcs drm_vencoder_helper_funcs = {
++	.dpms		= drm_vencoder_dpms,
++	.mode_fixup	= drm_vencoder_mode_fixup,
++	.prepare	= drm_vencoder_prepare,
++	.commit		= drm_vencoder_commit,
++	.mode_set	= drm_vencoder_mode_set,
++};
++
++static int drm_vencoder_bind(struct device *dev, struct device *master,
++			     void *data)
++{
++	struct drm_encoder *encoder;
++	struct drm_virt_priv *con;
++	struct drm_connector *connector;
++	struct drm_device *drm = data;
++	u32 crtcs = 0;
++	int ret;
++
++	con = devm_kzalloc(dev, sizeof(*con), GFP_KERNEL);
++	if (!con)
++		return -ENOMEM;
++
++	dev_set_drvdata(dev, con);
++	connector = &con->connector;
++	encoder = &con->encoder;
++
++	if (dev->of_node) {
++		struct drm_bridge *bridge;
++		crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
++		bridge = of_drm_find_bridge(dev->of_node);
++		if (bridge) {
++			ret = drm_bridge_attach(encoder, bridge, NULL);
++			if (ret) {
++				DRM_ERROR("Failed to initialize bridge\n");
++				return ret;
++			}
++		}
++		con->timings = of_get_display_timings(dev->of_node);
++		if (!con->timings) {
++			dev_err(dev, "failed to get display panel timings\n");
++			return ENXIO;
++		}
++	}
++
++	/* If no CRTCs were found, fall back to the old encoder's behaviour */
++	if (crtcs == 0) {
++		dev_warn(dev, "Falling back to first CRTC\n");
++		crtcs = 1 << 0;
++	}
++
++	encoder->possible_crtcs = crtcs ? crtcs : 1;
++	encoder->possible_clones = 0;
++
++	ret = drm_encoder_init(drm, encoder, &drm_vencoder_funcs,
++			       DRM_MODE_ENCODER_VIRTUAL, NULL);
++	if (ret)
++		goto encoder_init_err;
++
++	drm_encoder_helper_add(encoder, &drm_vencoder_helper_funcs);
++
++	/* bogus values, pretend we're a 24" screen for DPI calculations */
++	connector->display_info.width_mm = 519;
++	connector->display_info.height_mm = 324;
++	connector->interlace_allowed = false;
++	connector->doublescan_allowed = false;
++	connector->polled = 0;
++
++	ret = drm_connector_init(drm, connector, &drm_virtcon_funcs,
++				 DRM_MODE_CONNECTOR_VIRTUAL);
++	if (ret)
++		goto connector_init_err;
++
++	drm_connector_helper_add(connector, &drm_virtcon_helper_funcs);
++
++	drm_connector_register(connector);
++
++	ret = drm_connector_attach_encoder(connector, encoder);
++	if (ret)
++		goto attach_err;
++
++	return ret;
++
++attach_err:
++	drm_connector_unregister(connector);
++	drm_connector_cleanup(connector);
++connector_init_err:
++	drm_encoder_cleanup(encoder);
++encoder_init_err:
++	display_timings_release(con->timings);
++
++	return ret;
++};
++
++static void drm_vencoder_unbind(struct device *dev, struct device *master,
++				void *data)
++{
++	struct drm_virt_priv *con = dev_get_drvdata(dev);
++
++	drm_connector_unregister(&con->connector);
++	drm_connector_cleanup(&con->connector);
++	drm_encoder_cleanup(&con->encoder);
++	display_timings_release(con->timings);
++}
++
++static const struct component_ops drm_vencoder_ops = {
++	.bind = drm_vencoder_bind,
++	.unbind = drm_vencoder_unbind,
++};
++
++static int drm_vencoder_probe(struct platform_device *pdev)
++{
++	return component_add(&pdev->dev, &drm_vencoder_ops);
++}
++
++static int drm_vencoder_remove(struct platform_device *pdev)
++{
++	component_del(&pdev->dev, &drm_vencoder_ops);
++	return 0;
++}
++
++static const struct of_device_id drm_vencoder_of_match[] = {
++	{ .compatible = "drm,virtual-encoder", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, drm_vencoder_of_match);
++
++static struct platform_driver drm_vencoder_driver = {
++	.probe = drm_vencoder_probe,
++	.remove = drm_vencoder_remove,
++	.driver = {
++		.name = "drm_vencoder",
++		.of_match_table = drm_vencoder_of_match,
++	},
++};
++
++module_platform_driver(drm_vencoder_driver);
++
++MODULE_AUTHOR("Liviu Dudau");
++MODULE_DESCRIPTION("Virtual DRM Encoder");
++MODULE_LICENSE("GPL v2");
+-- 
+2.7.4
+

meta-arm-bsp/recipes-kernel/linux/linux-arm64-ack-4.19/tc0/0002-swap-red-and-blue-colors-in-HDLCD-driver.patch

@@ -0,0 +1,43 @@
+From 064807d22a0a2865a930d4cc48b61f917f4bf15f Mon Sep 17 00:00:00 2001
+From: Anders Dellien <anders.dellien@arm.com>
+Date: Fri, 17 Apr 2020 16:06:03 +0100
+Subject: [PATCH 2/2] swap red and blue colors in HDLCD driver
+
+The HDLCD drivers is configured to use BGR888 but Android needs
+RGB888 - so we need to swap the red and blue components.
+
+Change-Id: Ib47ddff9280a53757925f6c1b1f373089d038025
+Signed-off-by: Anders Dellien<anders.dellien@arm.com>
+Upstream-Status: Inappropriate [Color swap needed for TC0 only]
+Signed-off-by: Teo Couprie Diaz <teo.coupriediaz@arm.com>
+---
+ drivers/gpu/drm/arm/hdlcd_crtc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
+index e69d996..a46ba4f 100644
+--- a/drivers/gpu/drm/arm/hdlcd_crtc.c
++++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
+@@ -110,15 +110,15 @@ static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
+ 	 * pixel is outside the visible frame area or when there is a
+ 	 * buffer underrun.
+ 	 */
+-	hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
++	hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->blue.offset |
+ #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
+ 		    0x00ff0000 |	/* show underruns in red */
+ #endif
+-		    ((format->red.length & 0xf) << 8));
++		    ((format->blue.length & 0xf) << 8));
+ 	hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
+ 		    ((format->green.length & 0xf) << 8));
+-	hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
+-		    ((format->blue.length & 0xf) << 8));
++	hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->red.offset |
++		    ((format->red.length & 0xf) << 8));
+ 
+ 	return 0;
+ }
+-- 
+2.7.4
+

meta-arm-bsp/recipes-kernel/linux/linux-arm64-ack-tc0.inc

@@ -0,0 +1,15 @@
+#
+# TC0 MACHINE specific configurations
+#
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/linux-arm64-ack-4.19:${THISDIR}/files:"
+
+SRC_URI_append = " \
+    file://defconfig \
+    file://0001-drm-Add-component-aware-simple-encoder.patch \
+    file://0002-swap-red-and-blue-colors-in-HDLCD-driver.patch \
+    "
+
+KCONFIG_MODE = "--alldefconfig"
+
+COMPATIBLE_MACHINE = "tc0"

meta-arm-bsp/recipes-kernel/linux/linux-arm64-ack_4.19.bbappend

@@ -0,0 +1,6 @@
+# Machine specific configurations
+
+MACHINE_ACK_REQUIRE ?= ""
+MACHINE_ACK_REQUIRE_tc0 = "linux-arm64-ack-tc0.inc"
+
+require ${MACHINE_ACK_REQUIRE}

meta-arm-bsp/recipes-kernel/linux/linux-linaro-arm_4.19.bbappend

@@ -1,3 +1,3 @@
 # Add support for Arm Platforms (boards or simulators)
 
-require linux-yocto-arm-platforms.inc
+require linux-arm-platforms.inc

meta-arm-bsp/recipes-kernel/linux/linux-linaro-arm_5.4.bb

@@ -11,10 +11,11 @@ COMPATIBLE_MACHINE ?= "invalid"
 # KBRANCH is set to n1sdp by default as there is no master branch on the repository
 KBRANCH = "n1sdp"
 
-SRC_URI = "git://git.linaro.org/landing-teams/working/arm/kernel-release.git;branch=${KBRANCH}; \
+SRC_URI = "git://git.linaro.org/landing-teams/working/arm/kernel-release.git;nobranch=1 \
            file://0001-menuconfig-mconf-cfg-Allow-specification-of-ncurses-location.patch \
           "
 LIC_FILES_CHKSUM = "file://COPYING;md5=bbea815ee2795b2f4230826c0c6b8814"
 
-SRCREV = "${AUTOREV}"
+# Refer to commit TAG N1SDP-2020.03.26 since it will not get force pushed
+SRCREV = "137cccb0843e63b031acf67d1ca4f6447b8c417c"
 LINUX_VERSION ?= "${PV}"

meta-arm-bsp/recipes-kernel/linux/linux-stable_%.bbappend

@@ -0,0 +1,3 @@
+# Add support for Arm Platforms (boards or simulators)
+
+require linux-arm-platforms.inc

meta-arm-bsp/recipes-kernel/linux/linux-upstream-arm-platforms.inc

@@ -1,24 +0,0 @@
-DESCRIPTION = "Linux Kernel based on upstream tree"
-SECTION = "kernel"
-LICENSE = "GPLv2"
-SRCREV_FORMAT = "kernel"
-
-require recipes-kernel/linux/linux-yocto.inc
-
-KERNEL_VERSION_SANITY_SKIP = "1"
-
-S = "${WORKDIR}/git"
-
-# Override do_kernel_configme to avoid kernel being assembled into a linux-yocto
-# style kernel
-# https://www.yoctoproject.org/docs/latest/ref-manual/ref-manual.html#ref-tasks-kernel_configme
-do_kernel_configme[noexec] = "1"
-
-# Make sure no branch is defined since here we track a specific version
-KBRANCH = ""
-
-LIC_FILES_CHKSUM = "file://COPYING;md5=bbea815ee2795b2f4230826c0c6b8814"
-
-SRC_URI = "\
-        git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux;protocol=https;nobranch=1 \
-        "

meta-arm-bsp/recipes-kernel/linux/linux-upstream-arm_5.3.bb

@@ -1,8 +0,0 @@
-# Add support for Upstream Kernel for Arm Platforms (boards or simulators)
-
-SUMMARY = "Linux Kernel Upstream, supported by Arm/Linaro"
-
-require recipes-kernel/linux/linux-upstream-arm-platforms.inc
-
-SRCREV = "v${PV}"
-LINUX_VERSION ?= "${PV}"

meta-arm-bsp/recipes-kernel/linux/linux-yocto_5.4.bbappend

@@ -1,3 +1,3 @@
 # Add support for Arm Platforms (boards or simulators)
 
-require linux-yocto-arm-platforms.inc
+require linux-arm-platforms.inc

meta-arm-toolchain/recipes-devtools/external-arm-toolchain/gcc-aarch64-none-elf_9.2-2019.12.bb

@@ -0,0 +1,17 @@
+# Copyright (C) 2020 Texas Instruments Inc.
+# Released under the MIT license (see COPYING.MIT for the terms)
+
+require gcc-x86host.inc
+
+SUMMARY = "Baremetal GCC for Aarch64 processors"
+LICENSE = "GPL-3.0-with-GCC-exception & GPLv3"
+
+LIC_FILES_CHKSUM = "file://share/doc/gcc/GNU-Free-Documentation-License.html;md5=cc1e9a49a59ce7e6ae5ef37cd16eca0c"
+
+PROVIDES = "virtual/aarch64-none-elf-gcc"
+
+SRC_URI = "https://developer.arm.com/-/media/Files/downloads/gnu-a/${PV}/binrel/gcc-arm-${PV}-x86_64-${BINNAME}.tar.xz"
+
+SRC_URI[sha256sum] = "36d2cbe7c2984f2c20f562ac2f3ba524c59151adfa8ee10f1326c88de337b6d1"
+
+S = "${WORKDIR}/gcc-arm-${PV}-x86_64-${BINNAME}"

meta-arm-toolchain/recipes-devtools/external-arm-toolchain/gcc-arm-none-eabi_9-2019-q4-major.bb

@@ -0,0 +1,16 @@
+# Copyright (C) 2019 Garmin Ltd. or its subsidiaries
+# Released under the MIT license (see COPYING.MIT for the terms)
+
+require gcc-x86host.inc
+
+SUMMARY = "Baremetal GCC for ARM-R and ARM-M processors"
+LICENSE = "GPL-3.0-with-GCC-exception & GPLv3"
+
+LIC_FILES_CHKSUM = "file://share/doc/gcc-arm-none-eabi/license.txt;md5=c18349634b740b7b95f2c2159af888f5"
+
+PROVIDES = "virtual/arm-none-eabi-gcc"
+
+SRC_URI = "https://developer.arm.com/-/media/Files/downloads/gnu-rm/9-2019q4/${BPN}-${PV}-x86_64-linux.tar.bz2"
+
+SRC_URI[md5sum] = "fe0029de4f4ec43cf7008944e34ff8cc"
+SRC_URI[sha256sum] = "bcd840f839d5bf49279638e9f67890b2ef3a7c9c7a9b25271e83ec4ff41d177a"

meta-arm-toolchain/recipes-devtools/external-arm-toolchain/gcc-x86host.inc

@@ -0,0 +1,24 @@
+COMPATIBLE_HOST = "x86_64.*-linux"
+
+FILES_${PN} = "${datadir} ${bindir}"
+
+BINNAME = "${@d.getVar("BPN").strip("gcc-")}"
+
+do_install() {
+    install -d ${D}${datadir}/${BINNAME}/
+    cp -r ${S}/. ${D}${datadir}/
+
+    install -d ${D}${bindir}
+    # Symlink all executables into bindir
+    for f in ${D}${datadir}/bin/${BINNAME}-*; do
+        lnr $f ${D}${bindir}/$(basename $f)
+    done
+}
+
+INSANE_SKIP_${PN} = "already-stripped libdir staticdev file-rdeps"
+
+INHIBIT_SYSROOT_STRIP = "1"
+INHIBIT_PACKAGE_STRIP = "1"
+INHIBIT_PACKAGE_DEBUG_SPLIT = "1"
+
+BBCLASSEXTEND = "native nativesdk"

meta-arm-toolchain/recipes-devtools/gcc/gcc-arm-8.2.inc

@@ -2,6 +2,7 @@ require recipes-devtools/gcc/gcc-common.inc
 
 BASEPV = "8.2"
 PV = "arm-${BASEPV}"
+CVE_VERSION = "${BASEPV}"
 
 MMYY = "19.01"
 RELEASE = "20${MMYY}"

meta-arm-toolchain/recipes-devtools/gcc/gcc-arm-8.3.inc

@@ -2,6 +2,7 @@ require recipes-devtools/gcc/gcc-common.inc
 
 BASEPV = "8.3"
 PV = "arm-${BASEPV}"
+CVE_VERSION = "${BASEPV}"
 
 MMYY = "19.03"
 RELEASE = "20${MMYY}"

meta-arm-toolchain/recipes-devtools/gcc/gcc-arm-9.2.inc

@@ -3,6 +3,7 @@ require recipes-devtools/gcc/gcc-common.inc
 # Third digit in PV should be incremented after a minor release
 
 PV = "arm-9.2"
+CVE_VERSION = "9.2"
 
 # BINV should be incremented to a revision after a minor gcc release
 

meta-arm/README.md

@@ -0,0 +1 @@
+See ../README.md

meta-arm/conf/layer.conf

@@ -11,6 +11,6 @@ BBFILE_PRIORITY_meta-arm = "6"
 
 LAYERDEPENDS_meta-arm = " \
     core \
-    meta-python \
+    arm-toolchain \
 "
 LAYERSERIES_COMPAT_meta-arm = "warrior zeus dunfell"

meta-arm/recipes-bsp/scp-firmware/scp-firmware.inc

@@ -0,0 +1,73 @@
+SUMMARY = "SCP and MCP Firmware"
+
+PROVIDES += "virtual/control-processor-firmware"
+
+SCP_BUILD_RELEASE   ?= "1"
+SCP_COMPILE_VERBOSE ?= "0"
+SCP_PLATFORM        ?= "invalid"
+SCP_COMPILER        ?= "arm-none-eabi"
+SCP_LOG_LEVEL       ?= "WARN"
+
+DEPENDS += "virtual/arm-none-eabi-gcc-native"
+
+SCP_BUILD_STR = "${@bb.utils.contains('SCP_BUILD_RELEASE', '1', 'release', 'debug', d)}"
+SCP_COMP_STR  = "${@bb.utils.contains('SCP_COMPILE_VERBOSE', '0', '', 'V=1', d)}"
+
+inherit python3native
+inherit deploy
+
+B = "${WORKDIR}/build"
+S = "${WORKDIR}/src"
+
+# Allow platform specific copying of only scp or both scp & mcp, default to both
+FW_TARGETS ?= "scp mcp"
+
+COMPATIBLE_MACHINE ?= "invalid"
+
+LDFLAGS[unexport] = "1"
+
+# The gcc-arm-none-eabi version does not support -fmacro-prefix-max
+DEBUG_PREFIX_MAP_pn-scp = "\
+    -fdebug-prefix-map=${WORKDIR}=/usr/src/debug/${PN}/${EXTENDPE}${PV}-${PR} \
+    -fdebug-prefix-map=${STAGING_DIR_HOST}= \
+    -fdebug-prefix-map=${STAGING_DIR_NATIVE}= \
+"
+
+# No configure
+do_configure[noexec] = "1"
+
+EXTRA_OEMAKE = "${SCP_COMP_STR} \
+                BUILD_PATH='${B}' \
+                PRODUCT='${SCP_PLATFORM}' \
+                MODE='${SCP_BUILD_STR}' \
+                LOG_LEVEL='${SCP_LOG_LEVEL}' \
+                CC='${SCP_COMPILER}-gcc' \
+                AR='${SCP_COMPILER}-ar' \
+                SIZE='${SCP_COMPILER}-size' \
+                OBJCOPY='${SCP_COMPILER}-objcopy' \
+                "
+
+do_compile() {
+    oe_runmake -C "${S}" ${EXTRA_OEMAKE}
+}
+do_compile[cleandirs] += "${B}"
+
+do_install() {
+     install -d ${D}/firmware
+     for FW in ${FW_TARGETS}; do
+        for TYPE in ramfw romfw; do
+           install -D "${B}/product/${SCP_PLATFORM}/${FW}_${TYPE}/release/bin/${FW}_${TYPE}.bin" "${D}/firmware/"
+        done
+     done
+}
+
+FILES_${PN} = "/firmware"
+SYSROOT_DIRS += "/firmware"
+# Skip QA check for relocations in .text of elf binaries
+INSANE_SKIP_${PN} = "textrel"
+
+do_deploy() {
+    # Copy the images to deploy directory
+    cp -rf ${D}/firmware/* ${DEPLOYDIR}/
+}
+addtask deploy after do_install

meta-arm/recipes-bsp/scp-firmware/scp-firmware_git.bb

@@ -0,0 +1,20 @@
+DESCRIPTION = "Firmware for SCP and MCP software reference implementation"
+HOMEPAGE = "https://github.com/ARM-software/SCP-firmware"
+
+LICENSE = "BSD-3-Clause & Apache-2.0"
+
+# SCP
+LIC_FILES_CHKSUM = "file://license.md;beginline=5;md5=9db9e3d2fb8d9300a6c3d15101b19731"
+# CMSIS
+LIC_FILES_CHKSUM += "file://cmsis/LICENSE.txt;md5=e3fc50a88d0a364313df4b21ef20c29e"
+
+SRC_URI = "\
+    git://github.com/ARM-software/SCP-firmware.git;protocol=https;name=scp;destsuffix=src;nobranch=1 \
+    git://github.com/ARM-software/CMSIS_5.git;protocol=https;name=cmsis;destsuffix=src/cmsis;lfs=0;nobranch=1 \
+"
+
+SRCREV_scp    = "fd7c83561a7d76c7681d5d017fb23aa3664c028c"
+SRCREV_cmsis  = "refs/tags/5.2.0"
+SRCREV_FORMAT = "scp_cmsis"
+
+require scp-firmware.inc

meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc

@@ -5,7 +5,7 @@ PROVIDES = "virtual/trusted-firmware-a"
 
 PACKAGE_ARCH = "${MACHINE_ARCH}"
 
-inherit deploy nopackages
+inherit deploy
 
 COMPATIBLE_MACHINE ?= "invalid"
 
@@ -35,7 +35,7 @@ SRC_URI_MBEDTLS ??= ""
 # This should be set to MBEDTLS LIC FILES checksum
 LIC_FILES_CHKSUM_MBEDTLS ??= ""
 # add MBEDTLS to our sources if activated
-SRC_URI += "${@bb.utils.contains('TFA_MBEDTLS', '1', '${SRC_URI_MBEDTLS}', '', d)}"
+SRC_URI_append = " ${@bb.utils.contains('TFA_MBEDTLS', '1', '${SRC_URI_MBEDTLS}', '', d)}"
 # add mbed TLS chksum
 LIC_FILES_CHKSUM += "${@bb.utils.contains('TFA_MBEDTLS', '1', '${LIC_FILES_CHKSUM_MBEDTLS}', '', d)}"
 # add mbed TLS to version
@@ -71,6 +71,8 @@ do_configure[noexec] = "1"
 # We need openssl for fiptool
 DEPENDS_append = " dtc-native openssl-native"
 
+EXTRA_OEMAKE += "V=1"
+
 # Add platform parameter
 EXTRA_OEMAKE += "BUILD_BASE=${B} PLAT=${TFA_PLATFORM}"
 
@@ -98,12 +100,15 @@ EXTRA_OEMAKE += "${@bb.utils.contains('TFA_UBOOT', '1', 'BL33=${DEPLOY_DIR_IMAGE
 do_compile() {
     cd ${S}
 
-    # These changes are needed to have the fiptool compiling and executing properly
-    sed -i '/^LDLIBS/ s,$, \-L${RECIPE_SYSROOT_NATIVE}${libdir},' ${S}/tools/fiptool/Makefile
-    sed -i '/^INCLUDE_PATHS/ s,$, \-I${RECIPE_SYSROOT_NATIVE}${includedir},' ${S}/tools/fiptool/Makefile
-    export LD_LIBRARY_PATH=${STAGING_DIR_NATIVE}${libdir}:$LD_LIBRARY_PATH
+    # These changes are needed to have the native tools compiling and executing properly
+    sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile
+    sed -i '/^INCLUDE_PATHS/ s,$, \$\{BUILD_CFLAGS},' ${S}/tools/fiptool/Makefile
+    sed -i 's^OPENSSL_DIR.*=.*$^OPENSSL_DIR = ${STAGING_DIR_NATIVE}/${prefix_native}^' ${S}/tools/*/Makefile
 
-    oe_runmake ${TFA_BUILD_TARGET}
+    # Currently there are races if you build all the targets at once in parallel
+    for T in ${TFA_BUILD_TARGET}; do
+        oe_runmake $T
+    done
 }
 do_compile[cleandirs] = "${B}"
 
@@ -116,7 +121,7 @@ do_install() {
 
     install -d -m 755 ${D}/firmware
     for atfbin in ${TFA_INSTALL_TARGET}; do
-        processes="0"
+        processed="0"
         if [ "$atfbin" = "all" ]; then
             # Target all is not handled by default
             bberror "all as TFA_INSTALL_TARGET is not handled by do_install"
@@ -130,25 +135,29 @@ do_install() {
             install -m 0644 $BUILD_PLAT/$atfbin.bin \
                 ${D}/firmware/$atfbin-${TFA_PLATFORM}.bin
             ln -sf $atfbin-${TFA_PLATFORM}.bin ${D}/firmware/$atfbin.bin
-            processes="1"
+            processed="1"
         fi
         if [ -f $BUILD_PLAT/$atfbin/$atfbin.elf ]; then
             echo "Install $atfbin.elf"
             install -m 0644 $BUILD_PLAT/$atfbin/$atfbin.elf \
                 ${D}/firmware/$atfbin-${TFA_PLATFORM}.elf
             ln -sf $atfbin-${TFA_PLATFORM}.elf ${D}/firmware/$atfbin.elf
-            processes="1"
+            processed="1"
         fi
         if [ -f $BUILD_PLAT/$atfbin ]; then
             echo "Install $atfbin"
             install -m 0644 $BUILD_PLAT/$atfbin \
                 ${D}/firmware/$atfbin-${TFA_PLATFORM}
             ln -sf $atfbin-${TFA_PLATFORM} ${D}/firmware/$atfbin
-            processes="1"
+            processed="1"
         fi
-
-        if [ "$atfbin" = "dtbs" ]; then
-            echo "dtbs install, skipped"
+        if [ -f ${BUILD_DIR}/fdts/$atfbin.dtb ]; then
+            echo "Install $atfbin.dtb"
+            install -m 0644 "${BUILD_DIR}/fdts/$atfbin.dtb" \
+                "${D}/firmware/$atfbin.dtb"
+            processed="1"
+        elif [ "$atfbin" = "dtbs" ]; then
+            echo "dtbs install, skipped: set dtbs in TFA_INSTALL_TARGET"
         elif [ -f ${B}/tools/$atfbin/$atfbin ]; then
             echo "Tools $atfbin install, skipped"
         elif [ "$processed" = "0" ]; then
@@ -158,7 +167,10 @@ do_install() {
     done
 }
 
+FILES_${PN} = "/firmware"
 SYSROOT_DIRS += "/firmware"
+# Skip QA check for relocations in .text of elf binaries
+INSANE_SKIP_${PN} = "textrel"
 
 do_deploy() {
     cp -rf ${D}/firmware/* ${DEPLOYDIR}/

meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.1.bb

@@ -24,7 +24,7 @@ SRC_URI[tfa.sha256sum] = "7c4c00a4f28d3cfbb235fd1a1fb28c4d2fc1d657c9301686e7d882
 # Those are used in trusted-firmware-a.inc if TFA_MBEDTLS is set to 1
 #
 
-SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls"
+SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls;branch=mbedtls-2.16"
 
 # mbed TLS v2.16.2
 SRCREV_mbedtls = "d81c11b8ab61fd5b2da8133aa73c5fe33a0633eb"

meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.2.bb

@@ -24,7 +24,7 @@ SRC_URI[tfa.sha256sum] = "7c4c00a4f28d3cfbb235fd1a1fb28c4d2fc1d657c9301686e7d882
 # Those are used in trusted-firmware-a.inc if TFA_MBEDTLS is set to 1
 #
 
-SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls"
+SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls;branch=mbedtls-2.16"
 
 # mbed TLS v2.16.2
 SRCREV_mbedtls = "d81c11b8ab61fd5b2da8133aa73c5fe33a0633eb"

meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.3.bb

@@ -24,7 +24,7 @@ SRC_URI[tfa.sha256sum] = "7c4c00a4f28d3cfbb235fd1a1fb28c4d2fc1d657c9301686e7d882
 # Those are used in trusted-firmware-a.inc if TFA_MBEDTLS is set to 1
 #
 
-SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls"
+SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls;branch=mbedtls-2.18"
 
 # mbed TLS v2.18.1
 SRCREV_mbedtls = "ca933c7e0c9e84738b168b6b0feb89af4183a60a"

meta-arm/recipes-bsp/trusted-firmware-m/trusted-firmware-m_1.0.bb

@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2020 Arm Limited
+#
+
+SUMMARY = "Trusted Firmware for Cortex-M"
+DESCRIPTION = "Trusted Firmware-M"
+HOMEPAGE = "https://git.trustedfirmware.org/trusted-firmware-m.git"
+PROVIDES = "virtual/trusted-firmware-m"
+
+# TF-Mv1.0
+SRCREV_tfm = "TF-Mv1.0"
+LICENSE = "BSD-3-Clause & Apachev2"
+
+LIC_FILES_CHKSUM ?= "file://license.rst;md5=07f368487da347f3c7bd0fc3085f3afa"
+LIC_FILES_CHKSUM += "file://../mbed-crypto/LICENSE;md5=302d50a6369f5f22efdb674db908167a"
+LIC_FILES_CHKSUM += "file://../mbedtls/LICENSE;md5=302d50a6369f5f22efdb674db908167a"
+LIC_FILES_CHKSUM += "file://../CMSIS_5/LICENSE.txt;md5=c4082b6c254c9fb71136710391d9728b"
+
+SRC_URI  = "git://git.trustedfirmware.org/trusted-firmware-m.git;protocol=https;branch=master;name=tfm;destsuffix=${S}"
+SRC_URI += "git://github.com/ARMmbed/mbed-crypto.git;protocol=https;branch=development;name=mbed-crypto;destsuffix=${S}/../mbed-crypto"
+SRC_URI += "git://github.com/ARMmbed/mbedtls.git;protocol=https;branch=mbedtls-2.7;name=mbedtls;destsuffix=${S}/../mbedtls"
+SRC_URI += "https://github.com/ARM-software/CMSIS_5/releases/download/5.5.0/ARM.CMSIS.5.5.0.pack;name=cmsis;subdir=${S}/../CMSIS_5;downloadfilename=ARM.CMSIS.5.5.0.zip"
+
+SRC_URI[cmsis.md5sum] = "73b6cf6b4ab06ac099478e6cf983c08e"
+SRC_URI[cmsis.sha256sum] = "fc6e46c77de29ed05ef3bfd4846a2da49b024bc8854c876ac053aaa8d348ac52"
+
+SRCREV_FORMAT ?= "tfm_mbed-crypto_mbedtls_cmsis"
+SRCREV_mbed-crypto ?= "mbedcrypto-3.0.1"
+SRCREV_mbedtls ?= "mbedtls-2.7.14"
+SRCREV_cmsis ?= "5.5.0"
+
+inherit python3native deploy
+
+TFM_DEPENDS ?= ""
+DEPENDS += "${TFM_DEPENDS}"
+DEPENDS += "cmake-native"
+DEPENDS += "python3-cryptography-native python3-pyasn1-native"
+DEPENDS += "python3-jinja2-native python3-cbor-native python3-pyyaml-native"
+
+S = "${WORKDIR}/git/tfm"
+B = "${S}/build"
+
+COMPATIBLE_MACHINE ?= "invalid"
+
+# Build for debug (set TFA_DEBUG to 1 to activate)
+TFM_DEBUG ?= "0"
+# Set target config
+TFM_CONFIG ?= "ConfigDefault.cmake"
+# Platform must be set for each machine
+TFM_PLATFORM ?= "invalid"
+
+# Uncomment, or copy these lines to your local.conf to use the Arm Clang compiler
+# from meta-arm-toolchain.
+# Please make sure to check the applicable license beforehand!
+#LICENSE_FLAGS_WHITELIST = "armcompiler_armcompiler-native"
+#TFM_COMPILER = "ARMCLANG"
+# For most targets, it is required to set and export the following LICENSE variables for the armcompiler:
+# ARM_TOOL_VARIANT, ARMLMD_LICENSE_FILE, LM_LICENSE_FILE
+
+# Setting GCC as the default TF-M compiler
+TFM_COMPILER ?= "GNUARM"
+DEPENDS += "${@'armcompiler-native' if d.getVar('TFM_COMPILER', True) == 'ARMCLANG' else 'gcc-arm-none-eabi-native'}"
+
+# Add platform parameters
+EXTRA_OECMAKE += "-DTARGET_PLATFORM=${TFM_PLATFORM}"
+
+# Add compiler parameters
+EXTRA_OECMAKE += "-DCOMPILER=${TFM_COMPILER}"
+
+# Handle TFM_DEBUG parameter
+EXTRA_OECMAKE += "${@bb.utils.contains('TFM_DEBUG', '1', '-DCMAKE_BUILD_TYPE=Debug', '', d)}"
+EXTRA_OECMAKE += "-DPROJ_CONFIG=${S}/configs/${TFM_CONFIG}"
+
+# Let the Makefile handle setting up the CFLAGS and LDFLAGS as it is a standalone application
+CFLAGS[unexport] = "1"
+LDFLAGS[unexport] = "1"
+AS[unexport] = "1"
+LD[unexport] = "1"
+
+# This is needed because CMSIS_5 source package originally has .pack extension not .zip
+# and bitbake checks this dependency based on file extension
+do_unpack[depends] += "unzip-native:do_populate_sysroot"
+
+do_configure[prefuncs] += "do_check_config"
+do_check_config() {
+    if [ ! -f "${S}/configs/${TFM_CONFIG}" ]; then
+        bbfatal "Couldn't find config file '${TFM_CONFIG}' in '${S}/configs/'"
+    fi
+}
+
+do_configure() {
+    cd ${S}
+    python3 "tools/tfm_parse_manifest_list.py"
+
+    if [ ! -d "${B}" ]
+    then
+        install -d ${B}
+    else
+        rm -f ${B}/CMakeCache.txt
+    fi
+
+    cd ${B}
+    cmake -G"Unix Makefiles" --build ${S} ${EXTRA_OECMAKE}
+}
+
+do_compile() {
+    if [ -d "${B}" ]
+    then
+        oe_runmake -C ${B} install
+    else
+        bbfatal "TF-M CMake not generated!"
+    fi
+}
+
+do_install() {
+    if [ ! -d "${B}/install/outputs" ]
+    then
+        bbfatal "Output not found in '${B}/install/outputs'!"
+    fi
+
+    install -d -m 755 ${D}/firmware
+    cd ${B}/install/outputs
+    for dir in *;do
+        install -D -p -m 0644 $dir/* -t ${D}/firmware/$dir/
+    done
+}
+
+FILES_${PN} = "/firmware"
+SYSROOT_DIRS += "/firmware"
+# Skip QA check for relocations in .text of elf binaries
+INSANE_SKIP_${PN} = "textrel"
+
+addtask deploy after do_install
+do_deploy() {
+    cp -rf ${D}/firmware/* ${DEPLOYDIR}/
+}

meta-arm/recipes-bsp/uefi/edk2-firmware.inc

@@ -0,0 +1,84 @@
+SUMMARY = "UEFI EDK2 Firmware"
+
+PROVIDES += "virtual/uefi-firmware"
+
+EDK2_BUILD_RELEASE   ?= "0"
+EDK2_PLATFORM        ?= "invalid"
+EDK2_PLATFORM_DSC    ?= ""
+EDK2_BIN_NAME        ?= ""
+EDK2_ARCH            ?= ""
+
+EDK2_BUILD_MODE = "${@bb.utils.contains('EDK2_BUILD_RELEASE', '1', 'RELEASE', 'DEBUG', d)}"
+
+DEPENDS += "util-linux-native iasl-native"
+
+inherit python3native
+inherit deploy
+
+B = "${WORKDIR}/build"
+S = "${WORKDIR}/git"
+
+COMPATIBLE_MACHINE ?= "invalid"
+
+LDFLAGS[unexport] = "1"
+
+# No configure
+do_configure[noexec] = "1"
+
+# Set variables as per envsetup
+export GCC5_AARCH64_PREFIX = "${STAGING_BINDIR_TOOLCHAIN}/${TARGET_PREFIX}"
+export PACKAGES_PATH       = "${S}/edk2:${S}/edk2/edk2-platforms"
+export WORKSPACE           = "${S}/edk2"
+export EDK_TOOLS_PATH      = "${WORKSPACE}/BaseTools"
+export PYTHON_COMMAND      = "${PYTHON}"
+export CONF_PATH           = "${WORKSPACE}/Conf"
+
+export BTOOLS_PATH = "${EDK_TOOLS_PATH}/BinWrappers/PosixLike"
+
+python __anonymous() {
+    # If GCC Version is greater than 4 then pass GCC5
+    # set GCC5 by default
+    d.setVar('GCC_VER', 'GCC5')
+
+    # Otherwise pass the corresponding version
+    G = d.getVar('GCCVERSION',True).split(".")
+    gcc_vlist = ['1', '2', '3', '4']
+    if G[0] in gcc_vlist:
+        d.setVar('GCC_VER', 'GCC'+G[0])
+}
+
+do_compile() {
+    sed -i -e 's:-I \.\.:-I \.\. ${BUILD_CFLAGS} :' ${EDK_TOOLS_PATH}/Source/C/Makefiles/header.makefile
+    sed -i -e 's: -luuid: -luuid ${BUILD_LDFLAGS}:g' ${EDK_TOOLS_PATH}/Source/C/*/GNUmakefile
+
+    # Copy the templates as we don't run envsetup
+    cp ${EDK_TOOLS_PATH}/Conf/build_rule.template ${WORKSPACE}/Conf/build_rule.txt
+    cp ${EDK_TOOLS_PATH}/Conf/tools_def.template ${WORKSPACE}/Conf/tools_def.txt
+    cp ${EDK_TOOLS_PATH}/Conf/target.template ${WORKSPACE}/Conf/target.txt
+
+    # Build basetools
+    oe_runmake -C ${S}/edk2/BaseTools
+
+    PATH="${WORKSPACE}:${BTOOLS_PATH}:$PATH" \
+    "${S}/edk2/BaseTools/BinWrappers/PosixLike/build" \
+       -a "${EDK2_ARCH}" \
+       -b ${EDK2_BUILD_MODE} \
+       -t ${GCC_VER} \
+       -p "${S}/edk2/edk2-platforms/Platform/ARM/${EDK2_PLATFORM_DSC}"
+}
+
+do_install() {
+    install -d ${D}/firmware
+    install "${S}/edk2/Build/${EDK2_PLATFORM}/${EDK2_BUILD_MODE}_${GCC_VER}/FV/${EDK2_BIN_NAME}" "${D}/firmware/uefi.bin"
+}
+
+FILES_${PN} = "/firmware"
+SYSROOT_DIRS += "/firmware"
+# Skip QA check for relocations in .text of elf binaries
+INSANE_SKIP_${PN} = "textrel"
+
+do_deploy() {
+    # Copy the images to deploy directory
+    cp -rf ${D}/firmware/* ${DEPLOYDIR}/
+}
+addtask deploy after do_install

meta-arm/recipes-bsp/uefi/edk2-firmware_git.bb

@@ -0,0 +1,19 @@
+DESCRIPTION = "UEFI EDK2 Firmware for Arm reference platforms"
+HOMEPAGE = "https://github.com/tianocore/edk2"
+
+LICENSE = "BSD-2-Clause-Patent"
+
+# EDK2
+LIC_FILES_CHKSUM = "file://edk2/License.txt;md5=2b415520383f7964e96700ae12b4570a"
+# EDK2 Platforms
+LIC_FILES_CHKSUM += "file://edk2/edk2-platforms/License.txt;md5=2b415520383f7964e96700ae12b4570a"
+
+SRC_URI ?= "\
+    git://github.com/tianocore/edk2.git;name=edk2;destsuffix=${S}/edk2;nobranch=1 \
+    git://github.com/tianocore/edk2-platforms.git;name=edk2-platforms;destsuffix=${S}/edk2/edk2-platforms;nobranch=1 \
+"
+SRCREV_edk2           ?= "6ff7c838d09224dd4e4c9b5b93152d8db1b19740"
+SRCREV_edk2-platforms ?= "ed4cc8059ec551032f0d8b8c172e9ec19214a638"
+SRCREV_FORMAT         = "edk2_edk2-platforms"
+
+require edk2-firmware.inc

meta-arm/recipes-devtools/fiptool/fiptool-native_2.3.bb

@@ -0,0 +1,29 @@
+# Firmware Image Package (FIP)
+# It is a packaging format used by TF-A to package the
+# firmware images in a single binary.
+
+DESCRIPTION = "fiptool - Trusted Firmware tool for packaging"
+LICENSE = "BSD-3-Clause"
+
+SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;destsuffix=fiptool-${PV};protocol=https;"
+LIC_FILES_CHKSUM = "file://docs/license.rst;md5=189505435dbcdcc8caa63c46fe93fa89"
+
+# Use fiptool from TF-A v2.3
+SRCREV = "ecd27ad85f1eba29f6bf92c39dc002c85b07dad5"
+
+DEPENDS += "openssl-native"
+
+inherit native
+
+do_compile () {
+    # These changes are needed to have the fiptool compiling and executing properly
+    sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile
+    sed -i '/^INCLUDE_PATHS/ s,$, \$\{BUILD_CFLAGS},' ${S}/tools/fiptool/Makefile
+
+    oe_runmake fiptool
+}
+
+do_install () {
+    install -d ${D}${bindir}/
+    install -m 0755 tools/fiptool/fiptool ${D}${bindir}
+}

meta-arm/recipes-kernel/linux/linux-arm64-ack_4.19.bb

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2020 Arm Limited
+#
+
+
+DESCRIPTION = "Linux Android Common Kernel"
+SECTION = "kernel"
+LICENSE = "GPLv2"
+LIC_FILES_CHKSUM = "file://${S}/COPYING;md5=bbea815ee2795b2f4230826c0c6b8814"
+
+require recipes-kernel/linux/linux-yocto.inc
+
+COMPATIBLE_MACHINE ?= "invalid"
+
+ARCH = "arm64"
+
+SRC_URI = " \
+    git://android.googlesource.com/kernel/common.git;protocol=https;branch=android-4.19-q-release \
+    "
+
+# ASB-2020-06-05_4.19-q-release tag commit
+SRCREV = "ebd43352dd92e56f14a4985a3c99de767fc8f9cf"
+
+S = "${WORKDIR}/git"
+
+LINUX_VERSION ?= "${PV}"
+KERNEL_VERSION_SANITY_SKIP = "1"
+KBRANCH = ""

meta-arm/recipes-security/optee/optee-os_git.bb

@@ -10,7 +10,7 @@ PV = "3.8.0+git${SRCPV}"
 inherit deploy python3native
 require optee.inc
 
-DEPENDS = "python3-pycrypto-native python3-pyelftools-native python3-pycryptodomex-native"
+DEPENDS = "python3-pycryptodome-native python3-pycryptodomex-native python3-pyelftools-native"
 
 SRCREV = "023e33656e2c9557ce50ad63a98b2e2c9b51c118"
 SRC_URI = " \