arm-bsp/documentation: corstone1000: 2022.11.10 RC: update the change log

Aligning the change log with the latest Corstone1000 SW updates. Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>
arm-bsp/documentation: corstone1000: 2022.11.10 RC: update the release notes
2026-07-17 16:17:09 +00:00 · 2022-11-10 11:07:20 -05:00 · 2022-11-10 11:07:20 -05:00 · 2022-11-10 11:07:20 -05:00 · 2022-11-08 08:18:55 -05:00 · 2022-11-07 14:05:39 -05:00
77 changed files with 4340 additions and 156 deletions
@@ -242,3 +242,18 @@ metrics:
  script:
    - kas shell --update --force-checkout ci/base.yml --command \
      "$CI_PROJECT_DIR/ci/patchreview $CI_PROJECT_DIR/meta-* --verbose --metrics $CI_PROJECT_DIR/metrics.txt"
+
+documentation:
+  extends: .setup
+  script:
+    - |
+      sudo pip3 install -r meta-arm-bsp/documentation/requirements.txt
+      for CONF in meta-*/documentation/*/conf.py ; do
+        SOURCE_DIR=$(dirname $CONF)
+        MACHINE=$(basename $SOURCE_DIR)
+        sphinx-build -vW $SOURCE_DIR build-docs/$MACHINE
+      done
+      test -d build-docs/
+  artifacts:
+    paths:
+      - build-docs/
@@ -5,7 +5,7 @@ distro: poky

 defaults:
  repos:
-    refspec: master
+    refspec: langdale

 repos:
  meta-arm:
@@ -26,13 +26,7 @@ env:

 local_conf_header:
  base: |
-    BB_SERVER_TIMEOUT = "60"
    CONF_VERSION = "2"
-    BB_NUMBER_THREADS = "16"
-    PARALLEL_MAKE = "-j16"
-    XZ_MEMLIMIT = "25%"
-    XZ_THREADS = "16"
-    ZSTD_THREADS = "16"
    LICENSE_FLAGS_ACCEPTED += "Arm-FVP-EULA"
  setup: |
    PACKAGE_CLASSES = "package_ipk"
@@ -4,6 +4,7 @@ header:
 repos:
  meta-clang:
    url: https://github.com/kraj/meta-clang
+    refspec: master

 local_conf_header:
  clang: |
@@ -5,7 +5,7 @@ distro: poky-tiny

 defaults:
  repos:
-    refspec: master
+    refspec: langdale

 repos:
  meta-arm:
@@ -16,7 +16,6 @@ repos:

  poky:
    url: https://git.yoctoproject.org/git/poky
-    refspec: master
    layers:
      meta:
      meta-poky:
@@ -24,7 +23,6 @@ repos:

  meta-openembedded:
    url: https://git.openembedded.org/meta-openembedded
-    refspec: master
    layers:
      meta-oe:
      meta-python:
@@ -42,3 +42,9 @@ FVP_TERMINALS[host.host_terminal_1] ?= "Secure World Console"
 FVP_TERMINALS[se.secenc_terminal] ?= "Secure Enclave Console"
 FVP_TERMINALS[extsys0.extsys_terminal] ?= "Cortex M3"

+# MMC card configuration
+FVP_CONFIG[board.msd_mmc.card_type] ?= "SDHC"
+FVP_CONFIG[board.msd_mmc.p_fast_access] ?= "0"
+FVP_CONFIG[board.msd_mmc.diagnostics] ?= "2"
+FVP_CONFIG[board.msd_mmc.p_max_block_count] ?= "0xFFFF"
+FVP_CONFIG[board.msd_config.pl180_fifo_depth] ?= "16"
@@ -10,10 +10,10 @@ require conf/machine/include/arm/arch-armv8a.inc
 TUNE_FEATURES = "aarch64"

 PREFERRED_VERSION_u-boot ?= "2022.04"
-PREFERRED_VERSION_linux-yocto ?= "5.15%"
-PREFERRED_VERSION_linux-yocto-rt ?= "5.15%"

 # FVP u-boot configuration
 UBOOT_MACHINE = "vexpress_aemv8a_semi_defconfig"

 KERNEL_IMAGETYPE = "Image"
+
+FVP_CONFIG[bp.virtio_rng.enabled] ?= "1"
@@ -9,8 +9,6 @@ require conf/machine/include/arm/armv8r/arch-armv8r64.inc
 EXTRA_IMAGEDEPENDS += "boot-wrapper-aarch64"

 PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto"
-PREFERRED_VERSION_linux-yocto ?= "5.15%"
-PREFERRED_VERSION_linux-yocto-rt ?= "5.15%"
 PREFERRED_VERSION_u-boot ?= "2022.07"

 KERNEL_IMAGETYPE = "Image"
@@ -0,0 +1,164 @@
+..
+ # Copyright (c) 2022, Arm Limited.
+ #
+ # SPDX-License-Identifier: MIT
+
+##########
+Change Log
+##########
+
+This document contains a summary of the new features, changes and
+fixes in each release of Corstone-1000 software stack.
+
+******************
+Version 2022.11.10
+******************
+
+Changes
+=======
+
+- Booting the External System (Cortex-M3) with RTX RTOS
+- Adding MHU communication between the HOST (Cortex-A35) and the External System
+- Adding a Linux application to test the External System
+- Adding ESRT (EFI System Resource Table) support
+- Upgrading the SW stack recipes
+- Upgrades for the U-Boot FF-A driver and MM communication
+
+Corstone-1000 components versions
+=======================================
+
+-------------------------------------------+------------+
+| arm-ffa-tee                               | 1.1.1      |
+-------------------------------------------+------------+
+| arm-ffa-user                              | 5.0.0      |
+-------------------------------------------+------------+
+| corstone1000-external-sys-tests           | 1.0        |
+-------------------------------------------+------------+
+| external-system                           | 0.1.0      |
+-------------------------------------------+------------+
+| linux-yocto                               | 5.19       |
+-------------------------------------------+------------+
+| u-boot                                    | 2022.07    |
+-------------------------------------------+------------+
+| optee-client                              | 3.18.0     |
+-------------------------------------------+------------+
+| optee-os                                  | 3.18.0     |
+-------------------------------------------+------------+
+| trusted-firmware-a                        | 2.7.0      |
+-------------------------------------------+------------+
+| trusted-firmware-m                        | 1.6.0      |
+-------------------------------------------+------------+
+| ts-newlib                                 | 4.1.0      |
+-------------------------------------------+------------+
+| ts-psa-{crypto, iat, its. ps}-api-test    | 451aa087a4 |
+-------------------------------------------+------------+
+| ts-sp-{se-proxy, smm-gateway}             | 3d4956770f |
+-------------------------------------------+------------+
+
+Yocto distribution components versions
+=======================================
+
+-------------------------------------------+---------------------+
+| meta-arm                                  | langdale            |
+-------------------------------------------+---------------------+
+| poky                                      | langdale            |
+-------------------------------------------+---------------------+
+| meta-openembedded                         | langdale            |
+-------------------------------------------+---------------------+
+| busybox                                   | 1.35.0              |
+-------------------------------------------+---------------------+
+| musl                                      | 1.2.3+git37e18b7bf3 |
+-------------------------------------------+---------------------+
+| gcc-arm-none-eabi-native                  | 11.2-2022.02        |
+-------------------------------------------+---------------------+
+| gcc-cross-aarch64                         | 12.2                |
+-------------------------------------------+---------------------+
+| openssl                                   | 3.0.5               |
+-------------------------------------------+---------------------+
+
+******************
+Version 2022.04.04
+******************
+
+Changes
+=======
+- Linux distro openSUSE, raw image installation and boot in the FVP.
+- SCT test support in FVP.
+- Manual capsule update support in FVP.
+
+******************
+Version 2022.02.25
+******************
+
+Changes
+=======
+- Building and running psa-arch-tests on Corstone-1000 FVP
+- Enabled smm-gateway partition in Trusted Service on Corstone-1000 FVP
+- Enabled MHU driver in Trusted Service on Corstone-1000 FVP
+- Enabled OpenAMP support in SE proxy SP on Corstone-1000 FVP
+
+******************
+Version 2022.02.21
+******************
+
+Changes
+=======
+- psa-arch-tests: recipe is dropped and merged into the secure-partitons recipe.
+- psa-arch-tests: The tests are align with latest tfm version for psa-crypto-api suite.
+
+******************
+Version 2022.01.18
+******************
+
+Changes
+=======
+- psa-arch-tests: change master to main for psa-arch-tests
+- U-Boot: fix null pointer exception for get_image_info
+- TF-M: fix capsule instability issue for Corstone-1000
+
+******************
+Version 2022.01.07
+******************
+
+Changes
+=======
+- Corstone-1000: fix SystemReady-IR ACS test (SCT, FWTS) failures.
+- U-Boot: send bootcomplete event to secure enclave.
+- U-Boot: support populating Corstone-1000 image_info to ESRT table.
+- U-Boot: add ethernet device and enable configs to support bootfromnetwork SCT.
+
+******************
+Version 2021.12.15
+******************
+
+Changes
+=======
+- Enabling Corstone-1000 FPGA support on:
+  - Linux 5.10
+  - OP-TEE 3.14
+  - Trusted Firmware-A 2.5
+  - Trusted Firmware-M 1.5
+- Building and running psa-arch-tests
+- Adding openamp support in SE proxy SP
+- OP-TEE: adding smm-gateway partition
+- U-Boot: introducing Arm FF-A and MM support
+
+******************
+Version 2021.10.29
+******************
+
+Changes
+=======
+- Enabling Corstone-1000 FVP support on:
+  - Linux 5.10
+  - OP-TEE 3.14
+  - Trusted Firmware-A 2.5
+  - Trusted Firmware-M 1.4
+- Linux kernel: enabling EFI, adding FF-A debugfs driver, integrating ARM_FFA_TRANSPORT.
+- U-Boot: Extending EFI support
+- python3-imgtool: adding recipe for Trusted-firmware-m
+- python3-imgtool: adding the Yocto recipe used in signing host images (based on MCUBOOT format)
+
+--------------
+
+*Copyright (c) 2022, Arm Limited. All rights reserved.*
@@ -0,0 +1,52 @@
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'corstone1000'
+copyright = '2020-2022, Arm Limited'
+author = 'Arm Limited'
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store', 'docs/infra']
+
+
+# -- Options for HTML output -------------------------------------------------
+
+# The theme to use for HTML and HTML Help pages.  See the documentation for
+# a list of builtin themes.
+#
+html_theme = 'sphinx_rtd_theme'
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+#html_static_path = ['_static']
@@ -0,0 +1,16 @@
+..
+ # Copyright (c) 2022, Arm Limited.
+ #
+ # SPDX-License-Identifier: MIT
+
+################
+ARM Corstone1000
+################
+
+.. toctree::
+   :maxdepth: 1
+
+   software-architecture
+   user-guide
+   release-notes
+   change-log
@@ -0,0 +1,159 @@
+..
+ # Copyright (c) 2022, Arm Limited.
+ #
+ # SPDX-License-Identifier: MIT
+
+#############
+Release notes
+#############
+
+**************************
+Release notes - 2022.11.10
+**************************
+
+Known Issues or Limitations
+---------------------------
+ - The external-system can not be reset individually on (or using) AN550_v1 FPGA release. However, the system-wide reset still applies to the external-system.
+ - FPGA supports Linux distro install and boot through installer. However, FVP only supports openSUSE raw image installation and boot.
+ - Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide can not boot on Corstone-1000 (i.e. user may experience timeouts or boot hang).
+ - Below SCT FAILURE is a known issues in the FVP:
+   UEFI Compliant - Boot from network protocols must be implemented -- FAILURE
+ - Known limitations regarding ACS tests: The behavior after running ACS tests on FVP is not consistent.  Both behaviors are expected and are valid;
+   The system might boot till the Linux prompt. Or, the system might wait after finishing the ACS tests.
+   In both cases, the system executes the entire test suite and writes the results as stated in the user guide.
+
+Platform Support
+-----------------
+ - This software release is tested on Corstone-1000 FPGA version AN550_v1
+   https://developer.arm.com/downloads/-/download-fpga-images
+ - This software release is tested on Corstone-1000 Fast Model platform (FVP) version 11.19_21
+   https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
+
+**************************
+Release notes - 2022.04.04
+**************************
+
+Known Issues or Limitations
+---------------------------
+ - FPGA support Linux distro install and boot through installer. However,
+   FVP only support openSUSE raw image installation and boot.
+ - Due to the performance uplimit of MPS3 FPGA and FVP, some Linux distros like Fedora Rawhide
+   cannot boot on Corstone-1000 (i.e. user may experience timeouts or boot hang).
+ - Below SCT FAILURE is a known issues in the FVP:
+   UEFI Compliant - Boot from network protocols must be implemented -- FAILURE
+
+Platform Support
+-----------------
+ - This software release is tested on Corstone-1000 FPGA version AN550_v1
+ - This software release is tested on Corstone-1000 Fast Model platform (FVP) version 11.17_23
+   https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
+
+**************************
+Release notes - 2022.02.25
+**************************
+
+Known Issues or Limitations
+---------------------------
+ - The following tests only work on Corstone-1000 FPGA: ACS tests (SCT, FWTS,
+   BSA), manual capsule update test, Linux distro install and boot.
+
+Platform Support
+----------------
+ - This software release is tested on Corstone-1000 FPGA version AN550_v1
+ - This software release is tested on Corstone-1000 Fast Model platform (FVP) version 11.17_23
+   https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
+
+Release notes - 2022.02.21
+--------------------------
+
+Known Issues or Limitations
+---------------------------
+ - The following tests only work on Corstone-1000 FPGA: ACS tests (SCT, FWTS,
+   BSA), manual capsule update test, Linux distro install and boot, psa-arch-test.
+
+Platform Support
+----------------
+ - This software release is tested on Corstone-1000 FPGA version AN550_v1
+ - This software release is tested on Corstone-1000 Fast Model platform (FVP) version 11.16.21
+   https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
+
+Release notes - 2022.01.18
+--------------------------
+
+Known Issues or Limitations
+---------------------------
+
+ - Before running each SystemReady-IR tests: ACS tests (SCT, FWTS, BSA), manual
+   capsule update test, Linux distro install and boot, etc., the SecureEnclave
+   flash must be cleaned. See user-guide "Clean Secure Flash Before Testing"
+   section.
+
+Release notes - 2021.12.15
+--------------------------
+
+Software Features
+------------------
+The following components are present in the release:
+
+ - Yocto version Honister
+ - Linux kernel version 5.10
+ - U-Boot 2021.07
+ - OP-TEE version 3.14
+ - Trusted Firmware-A 2.5
+ - Trusted Firmware-M 1.5
+ - OpenAMP 347397decaa43372fc4d00f965640ebde042966d
+ - Trusted Services a365a04f937b9b76ebb2e0eeade226f208cbc0d2
+
+
+Platform Support
+----------------
+ - This software release is tested on Corstone-1000 FPGA version AN550_v1
+ - This software release is tested on Corstone-1000 Fast Model platform (FVP) version 11.16.21
+   https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
+
+Known Issues or Limitations
+---------------------------
+ - The following tests only work on Corstone-1000 FPGA: ACS tests (SCT, FWTS,
+   BSA), manual capsule update test, Linux distro install and boot, and
+   psa-arch-tests.
+ - Only the manual capsule update from UEFI shell is supported on FPGA.
+ - Due to flash size limitation and to support A/B banks,the wic image provided
+   by the user should be smaller than 15MB.
+ - The failures in PSA Arch Crypto Test are known limitations with crypto
+   library. It requires further investigation. The user can refer to `PSA Arch Crypto Test Failure Analysis In TF-M V1.5 Release <https://developer.trustedfirmware.org/w/tf_m/release/psa_arch_crypto_test_failure_analysis_in_tf-m_v1.5_release/>`__
+   for the reason for each failing test.
+
+
+Release notes - 2021.10.29
+--------------------------
+
+Software Features
+-----------------
+This initial release of Corstone-1000 supports booting Linux on the Cortex-A35
+and TF-M/MCUBOOT in the Secure Enclave. The following components are present in
+the release:
+
+ - Linux kernel version 5.10
+ - U-Boot 2021.07
+ - OP-TEE version 3.14
+ - Trusted Firmware-A 2.5
+ - Trusted Firmware-M 1.4
+
+Platform Support
+----------------
+ - This Software release is tested on Corstone-1000 Fast Model platform (FVP) version 11.16.21
+   https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
+
+Known Issues or Limitations
+---------------------------
+ - No software support for external system(Cortex M3)
+ - No communication established between A35 and M0+
+ - Very basic functionality of booting Secure Enclave, Trusted Firmware-A , OP-TEE , u-boot and Linux are performed
+
+Support
+-------
+For support email: support-subsystem-iot@arm.com
+
+--------------
+
+*Copyright (c) 2022, Arm Limited. All rights reserved.*
@@ -0,0 +1,239 @@
+..
+ # Copyright (c) 2022, Arm Limited.
+ #
+ # SPDX-License-Identifier: MIT
+
+######################
+Software architecture
+######################
+
+
+*****************
+ARM corstone1000
+*****************
+
+ARM corstone1000 is a reference solution for IoT devices. It is part of
+Total Solution for IoT which consists of hardware and software reference
+implementation.
+
+Corstone1000 software plus hardware reference solution is PSA Level-2 ready
+certified (`PSA L2 Ready`_) as well as System Ready IR certified(`SRIR cert`_).
+More information on the corstone1000 subsystem product and design can be
+found at:
+`Arm corstone1000 Software`_ and `Arm corstone1000 Technical Overview`_.
+
+This readme explicitly focuses on the software part of the solution and
+provides internal details on the software components. The reference
+software package of the platform can be retrieved following instructions
+present in the user-guide document.
+
+***************
+Design Overview
+***************
+
+The software architecture of corstone1000 platform is a reference
+implementation of Platform Security Architecture (`PSA`_) which provides
+framework to build secure IoT devices.
+
+The base system architecture of the platform is created from three
+different tyes of systems: Secure Enclave, Host and External System.
+Each subsystem provides different functionality to overall SoC.
+
+
+.. image:: images/CorstoneSubsystems.png
+   :width: 720
+   :alt: CorstoneSubsystems
+
+
+The Secure Enclave System, provides PSA Root of Trust (RoT) and
+cryptographic functions. It is based on an Cortex-M0+ processor,
+CC312 Cryptographic Accelerator and peripherals, such as watchdog and
+secure flash. Software running on the Secure Enclave is isolated via
+hardware for enhanced security. Communication with the Secure Encalve
+is achieved using Message Hnadling Units (MHUs) and shared memory.
+On system power on, the Secure Enclaves boots first. Its software
+comprises of two boot loading stages, both based on mcuboot, and
+TrustedFirmware-M(`TF-M`_) as runtime software. The software design on 
+Secure Enclave follows Firmware Framework for M class
+processor (`FF-M`_) specification.
+
+The Host System is based on ARM Cotex-A35 processor with standardized
+peripherals to allow for the booting of a Linux OS. The Cortex-A35 has
+the TrustZone technology that allows secure and non-secure security
+states in the processor. The software design in the Host System follows
+Firmware Framework for A class procseeor (`FF-A`_) specification.
+The boot process follows Trusted Boot Base Requirement (`TBBR`_).
+The Host Subsystem is taken out of reset by the Secure Enclave system
+during its final stages of the initialization. The Host subsystem runs
+FF-A Secure Partitions(based on `Trusted Services`_) and OPTEE-OS
+(`OPTEE-OS`_) in the secure world, and u-boot(`u-boot repo`_) and
+linux (`linux repo`_) in the non-secure world. The communication between
+non-secure and the secure world is performed via FF-A messages.
+
+An external system is intended to implement use-case specific
+functionality. The system is based on Cortex-M3 and run RTX RTOS.
+Communictaion between external system and Host(cortex-A35) is performed
+using MHU as transport mechanism and rpmsg messaging system.
+
+Overall, the corstone1000 architecture is designed to cover a range
+of Power, Performance, and Area (PPA) applications, and enable extension
+for use-case specific applications, for example, sensors, cloud
+connectivitiy, and edge computing.
+
+*****************
+Secure Boot Chain
+*****************
+
+For the security of a device, it is essential that only authorized
+software should run on the device. The corstone1000 boot uses a
+Secure Boot Chain process where an already authenticated image verifies
+and loads the following software in the chain. For the boot chain
+process to work, the start of the chain should be trusted, forming the
+Root of Trust (RoT) of the device. The RoT of the device is immutable in
+nature and encoded into the device by the device owner before it
+is deployed into the field. In Corstone1000, the BL1 image of the secure
+enclave and content of the CC312 OTP (One Time Programmable) memory
+forms the RoT. The BL1 image exists in ROM (Read Only Memory).
+
+.. image:: images/SecureBootChain.png
+   :width: 870
+   :alt: SecureBootChain
+
+It is a lengthy chain to boot the software on corstone1000. On power on,
+the secure enclave starts executing BL1 code from the ROM which is the RoT
+of the device. Authentication of an image involves the steps listed below:
+
+- Load image from flash to dynamic RAM.
+- The public key present in the image header is validated by comparing with the hash. Depending on the image, the hash of the public key is either stored in the OTP or part of the software which is being already verfied in the previous stages.
+- The image is validated using the public key.
+
+In the secure enclave, BL1 authenticates the BL2 and passes the execution
+control. BL2 authenticates the initial boot loader of the host (Host BL2)
+and TF-M. The execution control is now passed to TF-M. TF-M being the run
+time executable of secure enclaves initializes itself and, in the end,
+brings the host CPU out of rest. The host follows the boot standard defined
+in the `TBBR`_ to authenticate the secure and non-secure software.
+
+***************
+Secure Services
+***************
+
+corstone1000 is unique in providing a secure environment to run a secure
+workload. The platform has Trustzone technology in the Host subsystem but
+it also has hardware isolated secure enclave environment to run such secure
+workloads. In corstone1000, known Secure Services such as Crypto, Protected
+Storage, Internal Trusted Storage and Attestation are available via PSA
+Functional APIs in TF-M. There is no difference for a user communicating to
+these services which are running on a secure enclave instead of the
+secure world of the host subsystem. The below diagram presents the data
+flow path for such calls.
+
+
+.. image:: images/SecureServices.png
+   :width: 930
+   :alt: SecureServices
+
+
+The SE Proxy SP (Secure Enclave Proxy Secure Partition) is a proxy partition
+managed by OPTEE which forwards such calls to the secure enclave. The
+solution relies on OpenAMP which uses shared memory and MHU interrupts as
+a doorbell for communication between two cores. corstone1000 implements
+isolation level 2. Cortex-M0+ MPU (Memory Protection Unit) is used to implement
+isolation level 2.
+
+For a user to define its own secure service, both the options of the host
+secure world or secure encalve are available. It's a trade-off between
+lower latency vs higher security. Services running on a secure enclave are
+secure by real hardware isolation but have a higher latency path. In the
+second scenario, the services running on the secure world of the host
+subsystem have lower latency but virtual hardware isolation created by
+Trustzone technology.
+
+
+**********************
+Secure Firmware Update
+**********************
+
+Apart from always booting the authorized images, it is also essential that
+the device only accepts the authorized images in the firmware update
+process. corstone1000 supports OTA (Over the Air) firmware updates and
+follows Platform Security Firmware Update sepcification (`FWU`_).
+
+As standardized into `FWU`_, the external flash is divided into two
+banks of which one bank has currently running images and the other bank is
+used for staging new images.  There are four updatable units, i.e. Secure
+Enclave's BL2 and TF-M, and Host's FIP (Firmware Image Package) and Kernel
+Image. The new images are accepted in the form of a UEFI capsule.
+
+
+.. image:: images/ExternalFlash.png
+   :width: 690
+   :alt: ExternalFlash
+
+
+The Metadata Block in the flash has the below firmware update state machine.
+TF-M runs an OTA service that is responsible for accepting and updating the
+images in the flash. The communication between the UEFI Capsule update
+subsystem and the OTA service follows the same data path explained above.
+The OTA service writes the new images to the passive bank after successful
+capsule verification. It changes the state of the system to trial state and
+triggers the reset. Boot loaders in Secure Enclave and Host read the Metadata
+block to get the information on the boot bank. In the successful trial stage,
+the acknowledgment from the host moves the state of the system from trial to
+regular. Any failure in the trial stage or system hangs leads to a system
+reset. This is made sure by the use of watchdog hardware. The Secure Enclave's
+BL1 has the logic to identify multiple resets and eventually switch back to the
+previous good bank. The ability to revert to the previous bank is crucial to
+guarantee the availability of the device.
+
+
+.. image:: images/SecureFirmwareUpdate.png
+   :width: 430
+   :alt: SecureFirmwareUpdate
+
+
+
+******************************
+UEFI Runtime Support in u-boot
+******************************
+
+Implementation of UEFI boottime and runtime APIs require variable storage.
+In corstone1000, these UEFI variables are stored in the Protected Storage
+service. The below diagram presents the data flow to store UEFI variables.
+The u-boot implementation of the UEFI subsystem uses the FF-A driver to
+communicate with the SMM Service in the secure world. The backend of the
+SMM service uses the proxy PS from the SE Proxy SP. From there on, the PS
+calls are forwarded to the secure enclave as explained above.
+
+
+.. image:: images/UEFISupport.png
+   :width: 590
+   :alt: UEFISupport
+
+
+***************
+References
+***************
+`ARM corstone1000 Search`_
+`Arm security features`_
+
+--------------
+
+*Copyright (c) 2022, Arm Limited. All rights reserved.*
+
+.. _Arm corstone1000 Technical Overview: https://developer.arm.com/documentation/102360/0000
+.. _Arm corstone1000 Software: https://developer.arm.com/Tools%20and%20Software/Corstone-1000%20Software
+.. _Arm corstone1000 Search: https://developer.arm.com/search#q=corstone-1000
+.. _Arm security features: https://www.arm.com/architecture/security-features/platform-security
+.. _linux repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/
+.. _FF-A: https://developer.arm.com/documentation/den0077/latest
+.. _FF-M: https://developer.arm.com/-/media/Files/pdf/PlatformSecurityArchitecture/Architect/DEN0063-PSA_Firmware_Framework-1.0.0-2.pdf?revision=2d1429fa-4b5b-461a-a60e-4ef3d8f7f4b4&hash=3BFD6F3E687F324672F18E5BE9F08EDC48087C93
+.. _FWU: https://developer.arm.com/documentation/den0118/a/
+.. _OPTEE-OS: https://github.com/OP-TEE/optee_os
+.. _PSA: https://www.psacertified.org/
+.. _PSA L2 Ready: https://www.psacertified.org/products/corstone-1000/
+.. _SRIR cert: https://armkeil.blob.core.windows.net/developer/Files/pdf/certificate-list/arm-systemready-ir-certification-arm-corstone-1000.pdf
+.. _TBBR: https://developer.arm.com/documentation/den0006/latest
+.. _TF-M: https://www.trustedfirmware.org/projects/tf-m/
+.. _Trusted Services: https://www.trustedfirmware.org/projects/trusted-services/
+.. _u-boot repo: https://github.com/u-boot/u-boot.git
@@ -0,0 +1,12 @@
+# Copyright (c) 2022, Arm Limited.
+#
+# SPDX-License-Identifier: MIT
+
+# Read The Docs specific
+jinja2==3.1.1
+
+# Required to build the documentation
+sphinx==4.5.0
+sphinx_rtd_theme==1.0.0
+sphinx-copybutton==0.5.0
+docutils==0.17.1
@@ -3,6 +3,7 @@ From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
 Date: Fri, 29 Apr 2022 20:07:50 +0100
 Subject: [PATCH] tc: increase heap pages

+Upstream-Status: Pending
 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
 ---
 /BUILD.gn | 2 +-
@@ -0,0 +1,359 @@
+From 6ab17eeb8225cdf4afc6956c9a2774d60866c36d Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Mon, 28 Mar 2022 05:16:50 +0100
+Subject: [PATCH 1/6] corstone1000: platform secure test framework
+
+Change-Id: Ib781927f0add93ec9c06515d251e79518ee1db6e
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+Upstream-Status: Accepted [TF-Mv1.7.0]
+---
+ .../arm/corstone1000/Native_Driver/firewall.c |  15 ++
+ .../arm/corstone1000/Native_Driver/firewall.h |   5 +
+ .../ci_regression_tests/CMakeLists.txt        |  45 +++++
+ .../corstone1000/ci_regression_tests/s_test.c | 186 ++++++++++++++++++
+ .../corstone1000/ci_regression_tests/s_test.h |  30 +++
+ .../ci_regression_tests/s_test_config.cmake   |   8 +
+ 6 files changed, 289 insertions(+)
+ create mode 100644 platform/ext/target/arm/corstone1000/ci_regression_tests/CMakeLists.txt
+ create mode 100644 platform/ext/target/arm/corstone1000/ci_regression_tests/s_test.c
+ create mode 100644 platform/ext/target/arm/corstone1000/ci_regression_tests/s_test.h
+ create mode 100644 platform/ext/target/arm/corstone1000/ci_regression_tests/s_test_config.cmake
+
+diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/firewall.c b/platform/ext/target/arm/corstone1000/Native_Driver/firewall.c
+index 788cc3ec92..356b85e9d5 100755
+--- a/platform/ext/target/arm/corstone1000/Native_Driver/firewall.c
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/firewall.c
+@@ -293,6 +293,21 @@ void fc_enable_mpl(enum rgn_mpe_t mpe, enum rgn_mpl_t mpl)
+         ptr->rgn_mpl3 |= (mpl & RGN_MPL_EN_MASK);
+ }
+ 
+void fc_read_mpl(enum rgn_mpe_t mpe, enum rgn_mpl_t* mpl)
+{
+    struct _firewall_pe_rwe_reg_map_t *ptr =
+         (struct _firewall_pe_rwe_reg_map_t *)fw_data.rwe_ptr;
+    if (mpe == RGN_MPE0)
+        *mpl = (ptr->rgn_mpl0 & RGN_MPL_EN_MASK);
+    else if (mpe == RGN_MPE1)
+        *mpl = (ptr->rgn_mpl1 & RGN_MPL_EN_MASK);
+    else if (mpe == RGN_MPE2)
+        *mpl = (ptr->rgn_mpl2 & RGN_MPL_EN_MASK);
+    else if (mpe == RGN_MPE3)
+        *mpl = (ptr->rgn_mpl3 & RGN_MPL_EN_MASK);
+}
+
+
+ void fc_disable_mpl(enum rgn_mpe_t mpe, enum rgn_mpl_t mpl)
+ {
+     struct _firewall_pe_rwe_reg_map_t *ptr =
+diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/firewall.h b/platform/ext/target/arm/corstone1000/Native_Driver/firewall.h
+index 48c86725ef..17afe6a92f 100755
+--- a/platform/ext/target/arm/corstone1000/Native_Driver/firewall.h
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/firewall.h
+@@ -247,6 +247,11 @@ void fc_init_mpl(enum rgn_mpe_t mpe);
+  */
+ void fc_enable_mpl(enum rgn_mpe_t mpe, enum rgn_mpl_t mpl);
+ 
+/**
+ * \brief Reads Master Permission List in the selected Firewall Component
+ */
+void fc_read_mpl(enum rgn_mpe_t mpe, enum rgn_mpl_t* mpl);
+
+ /**
+  * \brief Disables Master Permission List in the selected Firewall Component
+  */
+diff --git a/platform/ext/target/arm/corstone1000/ci_regression_tests/CMakeLists.txt b/platform/ext/target/arm/corstone1000/ci_regression_tests/CMakeLists.txt
+new file mode 100644
+index 0000000000..70e1c20e4e
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/ci_regression_tests/CMakeLists.txt
+@@ -0,0 +1,45 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2021-22, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+cmake_policy(SET CMP0079 NEW)
+
+include(${CMAKE_CURRENT_SOURCE_DIR}/s_test_config.cmake)
+
+####################### Secure #################################################
+
+add_library(corstone1000_test_s STATIC EXCLUDE_FROM_ALL)
+
+target_sources(corstone1000_test_s
+    PRIVATE
+        ${CMAKE_CURRENT_SOURCE_DIR}/s_test.c
+        ../Native_Driver/firewall.c
+)
+
+target_include_directories(corstone1000_test_s
+    PRIVATE
+        ${CMAKE_CURRENT_SOURCE_DIR}
+        ../Device/Include
+        ../Native_Driver
+)
+
+# Example test links tfm_test_suite_extra_common to use related interface
+target_link_libraries(corstone1000_test_s
+    PRIVATE
+        tfm_test_suite_extra_common
+        tfm_log
+)
+
+target_compile_definitions(corstone1000_test_s
+    PRIVATE
+        $<$<BOOL:${PLATFORM_IS_FVP}>:PLATFORM_IS_FVP>
+)
+
+# The corstone1000_test_s library is linked by tfm_test_suite_extra_s
+target_link_libraries(tfm_test_suite_extra_s
+    PRIVATE
+        corstone1000_test_s
+)
+diff --git a/platform/ext/target/arm/corstone1000/ci_regression_tests/s_test.c b/platform/ext/target/arm/corstone1000/ci_regression_tests/s_test.c
+new file mode 100644
+index 0000000000..963f46d2ab
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/ci_regression_tests/s_test.c
+@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2021-22, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "s_test.h"
+#include "platform_base_address.h"
+#include "firewall.h"
+#include "tfm_log_raw.h"
+
+#define DISABLED_TEST 0
+
+enum host_firewall_host_comp_id_t {
+  HOST_FCTRL = (0x00u),
+  COMP_SYSPERIPH,
+  COMP_DBGPERIPH,
+  COMP_AONPERIPH,
+  COMP_XNVM,
+  COMP_CVM,
+  COMP_HOSTCPU,
+  COMP_EXTSYS0,
+  COMP_EXTSYS1,
+  COMP_EXPSLV0,
+  COMP_EXPSLV1,
+  COMP_EXPMST0,
+  COMP_EXPMST1,
+  COMP_OCVM,
+  COMP_DEBUG,
+};
+
+const struct extra_tests_t plat_s_t = {
+    .test_entry = s_test,
+    .expected_ret = EXTRA_TEST_SUCCESS
+};
+
+static int test_host_firewall_status(void)
+{
+    enum fw_lockdown_status_t status;
+    uint32_t any_component_id = 2;
+
+    fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, any_component_id);
+    status = fw_get_lockdown_status();
+    if (status != FW_LOCKED) {
+        tfm_log_printf("FAIL: %s.\n\r", __func__);
+        return EXTRA_TEST_FAILED;
+    }
+
+    tfm_log_printf("PASS: %s\n\r", __func__);
+    return EXTRA_TEST_SUCCESS;
+}
+
+static int test_host_firewall_external_flash_configurations(void)
+{
+    enum rgn_mpl_t mpl_rights = 0;
+    enum rgn_mpl_t expected_rights = 0;
+
+#if !(PLATFORM_IS_FVP)
+    /* External flash */
+    fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_EXPMST0);
+    fc_select_region(3);
+    fc_read_mpl(RGN_MPE0, &mpl_rights);
+    expected_rights = (RGN_MPL_ANY_MST_MASK | RGN_MPL_SECURE_READ_MASK |
+                                              RGN_MPL_SECURE_WRITE_MASK);
+    if (mpl_rights != expected_rights) {
+        tfm_log_printf("FAIL1: %s.\n\r", __func__);
+        return EXTRA_TEST_FAILED;
+    }
+    /* XIP Permissions */
+    fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_XNVM);
+    fc_select_region(1);
+    fc_read_mpl(RGN_MPE0, &mpl_rights);
+    expected_rights = (RGN_MPL_ANY_MST_MASK |
+                              RGN_MPL_SECURE_READ_MASK |
+                              RGN_MPL_NONSECURE_READ_MASK);
+    if (mpl_rights != expected_rights) {
+        tfm_log_printf("FAIL2: %s.\n\r", __func__);
+        return EXTRA_TEST_FAILED;
+    }
+#else
+    /* Enable the below test when FVP Host Firewall is configured. */
+    /*
+    fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_XNVM);
+    fc_select_region(1);
+    fc_read_mpl(RGN_MPE0, &mpl_rights);
+    tfm_log_printf("mpl rights = %d\n\r", mpl_rights);
+    expected_rights = (RGN_MPL_ANY_MST_MASK |
+                  RGN_MPL_SECURE_READ_MASK |
+                  RGN_MPL_SECURE_WRITE_MASK |
+                  RGN_MPL_NONSECURE_READ_MASK |
+                  RGN_MPL_NONSECURE_WRITE_MASK);
+    if (mpl_rights != expected_rights) {
+        tfm_log_printf("FAIL1: %s.\n\r", __func__);
+        return EXTRA_TEST_FAILED;
+    }
+    */
+#endif
+
+    tfm_log_printf("PASS: %s\n\r", __func__);
+    return EXTRA_TEST_SUCCESS;
+}
+
+static int test_host_firewall_secure_flash_configurations(void)
+{
+    enum rgn_mpl_t mpl_rights = 0;
+    enum rgn_mpl_t expected_rights = 0;
+
+#if !(PLATFORM_IS_FVP)
+    /* External flash */
+    fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_EXPMST1);
+    fc_select_region(1);
+    fc_read_mpl(RGN_MPE0, &mpl_rights);
+    expected_rights = (RGN_MPL_ANY_MST_MASK | RGN_MPL_SECURE_READ_MASK |
+                                              RGN_MPL_SECURE_WRITE_MASK);
+    if (mpl_rights != expected_rights) {
+        tfm_log_printf("FAIL: %s.\n\r", __func__);
+        return EXTRA_TEST_FAILED;
+    }
+#endif
+
+    tfm_log_printf("PASS: %s\n\r", __func__);
+    return EXTRA_TEST_SUCCESS;
+}
+
+static int test_bir_programming(void)
+{
+    /* BIR is expected to bhaive like write once register */
+
+    volatile uint32_t *bir_base = (uint32_t *)CORSTONE1000_HOST_BIR_BASE;
+
+    bir_base[0] = 0x1;
+    bir_base[0] = 0x2;
+    if (bir_base[0] != 0x1) {
+        tfm_log_printf("FAIL: %s : (%u)\n\r", __func__, bir_base[0]);
+        return EXTRA_TEST_FAILED;
+    }
+
+    tfm_log_printf("PASS: %s\n\r", __func__);
+    return EXTRA_TEST_SUCCESS;
+}
+
+int32_t s_test(void)
+{
+    int status;
+    int failures = 0;
+
+#if (DISABLED_TEST == 1)
+    status = test_host_firewall_status();
+    if (status) {
+        failures++;
+    }
+#endif
+
+    status = test_host_firewall_secure_flash_configurations();
+    if (status) {
+        failures++;
+    }
+
+    status = test_host_firewall_external_flash_configurations();
+    if (status) {
+        failures++;
+    }
+
+#if (DISABLED_TEST == 1)
+    status = test_bir_programming();
+    if (status) {
+        failures++;
+    }
+#endif
+
+    if (failures) {
+        tfm_log_printf("Not all platform test could pass: failures=%d\n\r", failures);
+        return EXTRA_TEST_FAILED;
+    }
+
+    tfm_log_printf("ALL_PASS: corstone1000 platform test cases passed.\n\r");
+    return EXTRA_TEST_SUCCESS;
+}
+
+int32_t extra_tests_init(struct extra_tests_t *internal_test_t)
+{
+    /* Add platform init code here. */
+
+    return register_extra_tests(internal_test_t, &plat_s_t);
+}
+diff --git a/platform/ext/target/arm/corstone1000/ci_regression_tests/s_test.h b/platform/ext/target/arm/corstone1000/ci_regression_tests/s_test.h
+new file mode 100644
+index 0000000000..8aff4d679c
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/ci_regression_tests/s_test.h
+@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021-22, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __S_TESTS_H__
+#define __S_TESTS_H__
+
+#include "extra_tests_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+const struct extra_tests_t plat_s_t;
+
+/**
+ * \brief Platform specific secure test function.
+ *
+ * \returns Returns error code as specified in \ref int32_t
+ */
+int32_t s_test(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __S_TESTS_H__ */
+diff --git a/platform/ext/target/arm/corstone1000/ci_regression_tests/s_test_config.cmake b/platform/ext/target/arm/corstone1000/ci_regression_tests/s_test_config.cmake
+new file mode 100644
+index 0000000000..bb8d26bf1c
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/ci_regression_tests/s_test_config.cmake
+@@ -0,0 +1,8 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2021-22, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+############ Define secure test specific cmake configurations here #############
+-- 
+2.25.1
+
@@ -0,0 +1,77 @@
+From 6fd49ab55c3419429e437845864c5bb2d731da29 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Mon, 25 Apr 2022 05:26:38 +0100
+Subject: [PATCH 2/6] corstone1000: make external system support optional
+
+The commits introduce build time variables to make
+external system support in the platform optional.
+
+Change-Id: I593014e0da4ac553c105c66ae55f6fd83ffe427e
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+Upstream-Status: Accepted [TF-Mv1.7.0]
+---
+ .../ext/target/arm/corstone1000/CMakeLists.txt    |  1 +
+ platform/ext/target/arm/corstone1000/config.cmake |  1 +
+ .../target/arm/corstone1000/tfm_hal_multi_core.c  | 15 +++++++++++++++
+ 3 files changed, 17 insertions(+)
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index 16bc708964..39d7b03455 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -97,6 +97,7 @@ target_compile_definitions(platform_s
+     PRIVATE
+         $<$<BOOL:${PLATFORM_IS_FVP}>:PLATFORM_IS_FVP>
+         $<$<BOOL:${TEST_S}>:TEST_S>
+        $<$<BOOL:${EXTERNAL_SYSTEM_SUPPORT}>:EXTERNAL_SYSTEM_SUPPORT>
+ )
+ 
+ #========================= Platform BL2 =======================================#
+diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
+index e5f91108ee..a3399db318 100644
+--- a/platform/ext/target/arm/corstone1000/config.cmake
+++ b/platform/ext/target/arm/corstone1000/config.cmake
+@@ -21,6 +21,7 @@ set(CRYPTO_HW_ACCELERATOR               ON         CACHE BOOL     "Whether to en
+ set(CRYPTO_NV_SEED                      OFF        CACHE BOOL     "Use stored NV seed to provide entropy")
+ set(TFM_CRYPTO_TEST_ALG_CFB             OFF        CACHE BOOL     "Test CFB cryptography mode")
+ set(NS                                  FALSE      CACHE BOOL     "Whether to build NS app")
+set(EXTERNAL_SYSTEM_SUPPORT             OFF        CACHE BOOL     "Whether to include external system support.")
+ 
+ # FVP is not integrated/tested with CC312.
+ if (${PLATFORM_IS_FVP})
+diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+index 8e1b455086..8622844d91 100644
+--- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+@@ -16,6 +16,16 @@
+ #define HOST_CPU_PE0_CONFIG_OFFSET 0x010
+ #define AA64nAA32_MASK (1 << 3)
+ 
+#ifdef EXTERNAL_SYSTEM_SUPPORT
+void tfm_external_system_boot()
+{
+    volatile uint32_t *ext_sys_reset_ctl_reg = (uint32_t *)(CORSTONE1000_EXT_SYS_RESET_REG);
+
+    /* de-assert CPU_WAIT signal*/
+    *ext_sys_reset_ctl_reg = 0x0;
+}
+#endif
+
+ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
+ {
+     /* Switch the shared flash to XiP mode for the host */
+@@ -53,6 +63,11 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
+     *reset_ctl_reg = 0;
+ 
+     (void) start_addr;
+
+#ifdef EXTERNAL_SYSTEM_SUPPORT
+    /*release EXT SYS out of reset*/
+    tfm_external_system_boot();
+#endif
+ }
+ 
+ void tfm_hal_wait_for_ns_cpu_ready(void)
+-- 
+2.25.1
+
@@ -0,0 +1,298 @@
+From 2e56f2601249243f2fb3ba67caf9febe4bfc8371 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Tue, 26 Apr 2022 20:17:13 +0100
+Subject: [PATCH 3/6] corstone1000: enable secure enclave run without host
+ binaries
+
+In TEST_S configuration, the build disables part of the code which
+assumes that the host binaries are present in the flash. This change
+will allow secure enclave's part of the platforms software to build
+and run without the host support. The configuration can be used to run
+CI and test secure enclave software independently.
+
+Change-Id: I29325750a3bea270fe5b3b8b47932a7071a59482
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+Upstream-Status: Accepted [TF-Mv1.7.0]
+---
+ .../ext/target/arm/corstone1000/readme.rst    | 88 +++++++++++++++----
+ .../target/arm/corstone1000/CMakeLists.txt    |  8 +-
+ .../arm/corstone1000/bl1/CMakeLists.txt       |  2 +-
+ .../target/arm/corstone1000/bl2_flash_map.c   |  2 +
+ .../target/arm/corstone1000/boot_hal_bl2.c    |  2 +
+ .../ext/target/arm/corstone1000/config.cmake  | 11 ++-
+ .../arm/corstone1000/partition/flash_layout.h |  2 +-
+ .../arm/corstone1000/tfm_hal_multi_core.c     |  2 +
+ 8 files changed, 94 insertions(+), 23 deletions(-)
+
+diff --git a/docs/platform/ext/target/arm/corstone1000/readme.rst b/docs/platform/ext/target/arm/corstone1000/readme.rst
+index 94b58ac6fc..10c9c58f78 100644
+--- a/docs/platform/ext/target/arm/corstone1000/readme.rst
+++ b/docs/platform/ext/target/arm/corstone1000/readme.rst
+@@ -7,22 +7,27 @@ Introduction
+ ************
+ 
+ The ARM's Corstone-1000 platform is a reference implementation of PSA FF-M
+-architecture where NSPE and SPE environments are partitioned into
+architecture where NSPE and SPE environments are partitioned/isolated into
+ Cortex-A35 and Cortex-M0+ respectively.
+ 
+ Cortex-M0+ acting as Secure Enclave is the Root-of-trust of SoC. Its
+-software comprises of two boot loading stages, i.e. Bl1 and Bl2, based on
+-mcuboot, and TF-M as run time software. Cortex-A35, also referred as host,
+-is completely treated as non-secure from the Secure Enclave perspective.
+software comprises of two boot loading stages, i.e. Bl1 and Bl2 (based on
+mcuboot) and TF-M as run time software. Cortex-A35, also referred as host,
+is treated as non-secure from the Secure Enclave perspective.
+ The Cortex-A35 is brought out of rest by Secure Enclave in aarch64 bit mode,
+ and boots the software ecosystem based on linux, u-boot, UEFI run time
+-services, TF-A and Optee.
+services, TF-A, Secure Partitions and Optee.
+ 
+ The communication between NSPE and SPE is based on PSA IPC protocol running on
+-top of OpenAMP.
+top of FF-A/OpenAMP.
+ 
+ The secure enclave subsystem has ARM's CC-312 (Crypto Cell) hardware to
+-accelerate cryptographic operations.
+accelerate cryptographic operations. Additionaly, platform supports Secure Debug
+using SDC-600 as the communication interface between host debugger and platform
+target. The platform has the build option to enable secure debug protocol to
+unlock debug ports during boot time. The protocol is based on ARM's ADAC
+(Authenticated Debug Access Control) standard.
+
+ 
+ ***********
+ System boot
+@@ -33,23 +38,76 @@ System boot
+ - BL1 load, verifies and transfer execution to BL2 which is again based on mcuboot.
+ - BL2 loads and verifies TF-M and host's initial boot loader image.
+ - BL2 transfer the execution to the TF-M.
+-- During TF-M initialization, the host is reset.
+- During TF-M initialization, the host is taken out of rest.
+- Hashes of the keys used for image verification are stored in the OTP memory.
+ 
+ *****
+ Build
+ *****
+ 
+-.. code-block::
+Platform solution
+=================
+
+The platform binaries are build using Yocto. Below is the user guide:
+
+`Arm Corstone-1000 User Guide`_
+
+Secure Test
+===========
+
+This section can be used to test the secure enclave software indedendently from
+the host. The below configuration builds the secure enclave binaries with CI test
+frame integrated. On boot, secure enclave softwares stack is brought up, and
+CI tests starts executing at the end of the initialization process. In the
+below configuration, host software support is disabled, and meant only
+to test/verify the secure enclave softwares.
+
+FVP
+---
+ 
+-    cmake -B build/ -S <tf-m-root>/ -DCMAKE_BUILD_TYPE=Debug -DTFM_TOOLCHAIN_FILE=<tf-m-root>/toolchain_GNUARM.cmake -DTFM_PLATFORM=arm/corstone1000
+- Download Corstone-1000 FVP from : `Arm Ecosystem FVPs`_
+- Install FVP by running the shell script.
+- Running of the binary will boot secure enclave software stack and at the end all CI test
+  from tf-m-test along with platform specific tests are executed.
+
+.. code-block:: bash
+
+    cmake -B build/ -S <tf-m-root>/ -DCMAKE_BUILD_TYPE=Debug -DTFM_TOOLCHAIN_FILE=<tf-m-root>/toolchain_GNUARM.cmake -DTFM_PLATFORM=arm/corstone1000 -DPLATFORM_IS_FVP=TRUE -DTEST_NS=OFF -DTEST_S=ON -DEXTRA_S_TEST_SUITES_PATHS=<tf-m-root>/trusted-firmware-m/platform/ext/target/arm/corstone1000/ci_regression_tests/
+     cmake --build build -- install
+    cd ./build/install/outputs/
+    cat bl2_signed.bin bl2_signed.bin tfm_s_signed.bin > cs1000.bin
+    cd <path-to-FVP-installation>/models/Linux64_GCC-9.3/
+    ./FVP_Corstone-1000 -C board.flashloader0.fname="none" -C se.trustedBootROMloader.fname="./<path-to-build-dir>/install/outputs/bl1.bin" -C board.xnvm_size=64 -C se.trustedSRAM_config=6 -C se.BootROM_config="3" -C board.smsc_91c111.enabled=0  -C board.hostbridge.userNetworking=true --data board.flash0=./<path-to-build-dir>/install/outputs/cs1000.bin@0x68100000 -C diagnostics=4 -C disable_visualisation=true -C board.se_flash_size=8192 -C diagnostics=4  -C disable_visualisation=true
+
+FPGA
+----
+ 
+-The binaries will be installed inside:
+- Follow the above pointed platform user guide to setup the FPGA board.
+- Use the BL1 generated from the below commands to place it inside FPGA board SD Card.
+- Use the cs1000.bin created from the below commands to place it inside FPGA board SD Card.
+
+.. code-block:: bash
+
+    cmake -B build/ -S <tf-m-root>/ -DCMAKE_BUILD_TYPE=Debug -DTFM_TOOLCHAIN_FILE=<tf-m-root>/toolchain_GNUARM.cmake -DTFM_PLATFORM=arm/corstone1000 -DTEST_NS=OFF -DTEST_S=ON -DEXTRA_S_TEST_SUITES_PATHS=<tf-m-root>/trusted-firmware-m/platform/ext/target/arm/corstone1000/ci_regression_tests/ -DTEST_S_PS=OFF -DTEST_S_PLATFORM=OFF
+    cmake --build build -- install
+    cd ./build/install/outputs/
+    cat bl2_signed.bin bl2_signed.bin tfm_s_signed.bin > cs1000.bin
+    cp bl1.bin <path-to-FPGA-SD-CARD>/SOFTWARE/
+    cp cs1000.bin <path-to-FPGA-SD-CARD>/SOFTWARE/
+ 
+-.. code-block::
+FPGA build can not compile all the CI tests into a single build as it exceeds
+the available RAM size. So there is a need to select few tests but not all.
+The above configuration disable build of -DTEST_S_PS and -DTEST_S_PLATFORM.
+Other test configurations are:
+ 
+-    ./build/install/outputs/ARM/CORSTONE1000
+- -DTEST_S_ATTESTATION=ON/OFF
+- -DTEST_S_AUDIT=ON/OFF
+- -DTEST_S_CRYPTO=ON/OFF
+- -DTEST_S_ITS=ON/OFF
+- -DTEST_S_PS=ON/OFF
+- -DTEST_S_PLATFORM=ON/OFF
+ 
+---------------
+*Copyright (c) 2021-2022, Arm Limited. All rights reserved.*
+ 
+-*Copyright (c) 2021, Arm Limited. All rights reserved.*
+.. _Arm Ecosystem FVPs: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
+.. _Arm Corstone-1000 User Guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/CORSTONE1000-2022.04.19/docs/embedded-a/corstone1000/user-guide.rst
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index 39d7b03455..81522c7cf0 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -18,7 +18,7 @@ target_include_directories(platform_region_defs
+ 
+ target_compile_definitions(platform_region_defs
+     INTERFACE
+-        $<$<BOOL:${TEST_S}>:TEST_S>
+        $<$<BOOL:${TFM_S_REG_TEST}>:TFM_S_REG_TEST>
+ )
+ #========================= Platform common defs ===============================#
+ 
+@@ -75,7 +75,7 @@ target_sources(platform_s
+         $<$<BOOL:TFM_PARTITION_PLATFORM>:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c>
+         fw_update_agent/uefi_capsule_parser.c
+         fw_update_agent/fwu_agent.c
+-        $<$<BOOL:${TEST_S}>:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg.c>
+        $<$<BOOL:${TFM_S_REG_TEST}>:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg.c>
+ )
+ 
+ if (PLATFORM_IS_FVP)
+@@ -96,7 +96,7 @@ endif()
+ target_compile_definitions(platform_s
+     PRIVATE
+         $<$<BOOL:${PLATFORM_IS_FVP}>:PLATFORM_IS_FVP>
+-        $<$<BOOL:${TEST_S}>:TEST_S>
+        $<$<BOOL:${TFM_S_REG_TEST}>:TFM_S_REG_TEST>
+         $<$<BOOL:${EXTERNAL_SYSTEM_SUPPORT}>:EXTERNAL_SYSTEM_SUPPORT>
+ )
+ 
+@@ -136,7 +136,7 @@ endif()
+ target_compile_definitions(platform_bl2
+     PRIVATE
+         $<$<BOOL:${PLATFORM_IS_FVP}>:PLATFORM_IS_FVP>
+-        $<$<BOOL:${TEST_S}>:TEST_S>
+        $<$<BOOL:${TFM_S_REG_TEST}>:TFM_S_REG_TEST>
+ )
+ 
+ # boot_hal_bl2.c is compiled as part of 'bl2' target and not inside
+diff --git a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+index 369695f148..d39c5ae91d 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+@@ -291,7 +291,7 @@ target_compile_definitions(signing_layout_for_bl2
+     PRIVATE
+         MCUBOOT_IMAGE_NUMBER=${BL1_IMAGE_NUMBER}
+         BL1
+-        $<$<BOOL:${TEST_S}>:TEST_S>
+        $<$<BOOL:${TFM_S_REG_TEST}>:TFM_S_REG_TEST>
+ )
+ 
+ target_include_directories(signing_layout_for_bl2
+diff --git a/platform/ext/target/arm/corstone1000/bl2_flash_map.c b/platform/ext/target/arm/corstone1000/bl2_flash_map.c
+index 6bffa274df..0a6a592d94 100644
+--- a/platform/ext/target/arm/corstone1000/bl2_flash_map.c
+++ b/platform/ext/target/arm/corstone1000/bl2_flash_map.c
+@@ -38,6 +38,7 @@ struct flash_area flash_map[] = {
+         .fa_off = FLASH_AREA_1_OFFSET,
+         .fa_size = FLASH_AREA_1_SIZE,
+     },
+#ifndef TFM_S_REG_TEST
+     {
+         .fa_id = FLASH_AREA_2_ID,
+         .fa_device_id = FLASH_DEVICE_ID,
+@@ -52,6 +53,7 @@ struct flash_area flash_map[] = {
+         .fa_off = FLASH_INVALID_OFFSET,
+         .fa_size = FLASH_INVALID_SIZE,
+     },
+#endif
+ };
+ 
+ const int flash_map_entry_num = ARRAY_SIZE(flash_map);
+diff --git a/platform/ext/target/arm/corstone1000/boot_hal_bl2.c b/platform/ext/target/arm/corstone1000/boot_hal_bl2.c
+index 792e06f81e..134315a17b 100644
+--- a/platform/ext/target/arm/corstone1000/boot_hal_bl2.c
+++ b/platform/ext/target/arm/corstone1000/boot_hal_bl2.c
+@@ -100,10 +100,12 @@ int32_t boot_platform_init(void)
+         return 1;
+     }
+ 
+#ifndef TFM_S_REG_TEST
+     result = fill_bl2_flash_map_by_parsing_fips(BANK_0_PARTITION_OFFSET);
+     if (result) {
+         return 1;
+     }
+#endif
+ 
+     result = FLASH_DEV_NAME.Initialize(NULL);
+     if (result != ARM_DRIVER_OK) {
+diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
+index a3399db318..a6a1a33c42 100644
+--- a/platform/ext/target/arm/corstone1000/config.cmake
+++ b/platform/ext/target/arm/corstone1000/config.cmake
+@@ -13,8 +13,15 @@ set(DEFAULT_MCUBOOT_FLASH_MAP           OFF        CACHE BOOL     "Whether to us
+ set(MCUBOOT_UPGRADE_STRATEGY            "RAM_LOAD" CACHE STRING   "Upgrade strategy when multiple boot images are loaded")
+ set(MCUBOOT_SECURITY_COUNTER_S          "1"      CACHE STRING    "Security counter for S image. auto sets it to IMAGE_VERSION_S")
+ 
+-set(TFM_ISOLATION_LEVEL                 2          CACHE STRING   "Isolation level")
+-set(MCUBOOT_IMAGE_NUMBER                2          CACHE STRING   "Whether to combine S and NS into either 1 image, or sign each separately")
+if (TEST_S OR TEST_S_ATTESTATION OR TEST_S_AUDIT OR TEST_S_CRYPTO OR TEST_S_ITS OR TEST_S_PS OR TEST_S_PLATFORM OR EXTRA_S_TEST_SUITES_PATHS)
+  # Test configuration: host images are not needed and work only with isolation level 1
+  set(MCUBOOT_IMAGE_NUMBER                1          CACHE STRING   "Whether to combine S and NS into either 1 image, or sign each separately")
+  set(TFM_ISOLATION_LEVEL                 1          CACHE STRING   "Isolation level")
+else()
+  set(MCUBOOT_IMAGE_NUMBER                2          CACHE STRING   "Whether to combine S and NS into either 1 image, or sign each separately")
+  set(TFM_ISOLATION_LEVEL                 2          CACHE STRING   "Isolation level")
+endif()
+
+ set(TFM_MULTI_CORE_TOPOLOGY             ON         CACHE BOOL     "Whether to build for a dual-cpu architecture")
+ set(TFM_PLAT_SPECIFIC_MULTI_CORE_COMM   ON         CACHE BOOL     "Whether to use a platform specific inter core communication instead of mailbox in dual-cpu topology")
+ set(CRYPTO_HW_ACCELERATOR               ON         CACHE BOOL     "Whether to enable the crypto hardware accelerator on supported platforms")
+diff --git a/platform/ext/target/arm/corstone1000/partition/flash_layout.h b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+index aa5a8fe463..b0319bb319 100644
+--- a/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+++ b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+@@ -119,7 +119,7 @@
+  *
+  */
+ #define SE_BL2_PARTITION_SIZE           (0x19000)    /* 100 KB */
+-#ifdef TEST_S
+#ifdef TFM_S_REG_TEST
+ #define TFM_PARTITION_SIZE              (0x61C00)    /* 391 KB */
+ #else
+ #define TFM_PARTITION_SIZE              (0x5E000)    /* 376 KB */
+diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+index 8622844d91..1146ffe22a 100644
+--- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+@@ -31,6 +31,7 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
+     /* Switch the shared flash to XiP mode for the host */
+     Select_XIP_Mode_For_Shared_Flash();
+ 
+#ifndef TFM_S_REG_TEST
+     volatile uint32_t *bir_base = (uint32_t *)CORSTONE1000_HOST_BIR_BASE;
+ 
+     /* Program Boot Instruction Register to jump to BL2 (TF-A) base address
+@@ -68,6 +69,7 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
+     /*release EXT SYS out of reset*/
+     tfm_external_system_boot();
+ #endif
+#endif /* !TFM_S_REG_TEST */
+ }
+ 
+ void tfm_hal_wait_for_ns_cpu_ready(void)
+-- 
+2.25.1
+
@@ -0,0 +1,72 @@
+From f3686dfb8fb97cb42c3d4f8ee2d7aa736d5cb760 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Wed, 3 Aug 2022 15:50:27 +0100
+Subject: [PATCH 4/6] Platform Partition: Allow configuration of input and
+ output buffer
+
+The change makes input and output buffer size macros used by
+the platform partition to be configured by cmake. This will
+allow platforms to set the buffer size accordingly.
+
+Change-Id: Ia492ce02f8744b0157228d9be51a9ec5b7c88ef6
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+Upstream-Status: Accepted [TF-Mv1.7.0]
+---
+ config/config_default.cmake                  | 2 ++
+ secure_fw/partitions/platform/CMakeLists.txt | 6 ++++++
+ secure_fw/partitions/platform/platform_sp.c  | 9 +++++++--
+ 3 files changed, 15 insertions(+), 2 deletions(-)
+
+diff --git a/config/config_default.cmake b/config/config_default.cmake
+index 3112b707bc..497c972dc9 100755
+--- a/config/config_default.cmake
+++ b/config/config_default.cmake
+@@ -141,6 +141,8 @@ set(ATTEST_INCLUDE_OPTIONAL_CLAIMS      ON          CACHE BOOL      "Include opt
+ set(ATTEST_INCLUDE_COSE_KEY_ID          OFF         CACHE BOOL      "Include COSE key-id in initial attestation token")
+ 
+ set(TFM_PARTITION_PLATFORM              ON          CACHE BOOL      "Enable Platform partition")
+set(PLATFORM_SERVICE_INPUT_BUFFER_SIZE  64          CACHE STRING    "Size of input buffer in platform service.")
+set(PLATFORM_SERVICE_OUTPUT_BUFFER_SIZE 64          CACHE STRING    "Size of output buffer in platform service.")
+ 
+ set(TFM_PARTITION_AUDIT_LOG             OFF         CACHE BOOL      "Enable Audit Log partition")
+ 
+diff --git a/secure_fw/partitions/platform/CMakeLists.txt b/secure_fw/partitions/platform/CMakeLists.txt
+index 4b37cd780c..3070f89d6d 100644
+--- a/secure_fw/partitions/platform/CMakeLists.txt
+++ b/secure_fw/partitions/platform/CMakeLists.txt
+@@ -47,6 +47,12 @@ target_link_libraries(tfm_psa_rot_partition_platform
+         tfm_spm
+ )
+ 
+target_compile_definitions(tfm_psa_rot_partition_platform
+    PRIVATE
+        INPUT_BUFFER_SIZE=${PLATFORM_SERVICE_INPUT_BUFFER_SIZE}
+        OUTPUT_BUFFER_SIZE=${PLATFORM_SERVICE_OUTPUT_BUFFER_SIZE}
+)
+
+ ############################ Secure API ########################################
+ 
+ target_sources(tfm_sprt
+diff --git a/secure_fw/partitions/platform/platform_sp.c b/secure_fw/partitions/platform/platform_sp.c
+index 673cb0ee06..87bd434720 100644
+--- a/secure_fw/partitions/platform/platform_sp.c
+++ b/secure_fw/partitions/platform/platform_sp.c
+@@ -38,8 +38,13 @@ static const int32_t nv_counter_access_map[NV_COUNTER_MAP_SIZE] = {
+ #include "psa/service.h"
+ #include "region_defs.h"
+ 
+-#define INPUT_BUFFER_SIZE  64
+-#define OUTPUT_BUFFER_SIZE 64
+#ifndef INPUT_BUFFER_SIZE
+#define INPUT_BUFFER_SIZE      64
+#endif
+
+#ifndef OUTPUT_BUFFER_SIZE
+#define OUTPUT_BUFFER_SIZE     64
+#endif
+ 
+ typedef enum tfm_platform_err_t (*plat_func_t)(const psa_msg_t *msg);
+ #endif /* TFM_PSA_API */
+-- 
+2.25.1
+
@@ -0,0 +1,573 @@
+From 9d70628b7dc1dbc3c1ac7f4f3c0f6aa6b237510d Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Wed, 6 Jul 2022 11:19:39 +0100
+Subject: [PATCH 5/6] corstone1000: support for UEFI FMP image Information
+
+The commit provides the support for UEFI FMP (Firmware Management
+Protocol) SET and GET Image info APIs.
+
+The APIs to SET and GET image info is implemented. In current design,
+SET is called by secure encalve and GET is called by the host.
+
+FMP image information is initialized on every boot and retained
+in SRAM. The updatable values of the FMP are stored in private
+metadata section of the flash.
+
+Change-Id: Iaf0b4a13a9c24f05e4a32509e61a8b96ee8e9e4b
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+Upstream-Status: Accepted [TF-Mv1.7.0]
+---
+ .../target/arm/corstone1000/CMakeLists.txt    |   2 +
+ .../ext/target/arm/corstone1000/config.cmake  |   8 +-
+ .../corstone1000/fw_update_agent/fwu_agent.c  |  61 ++++-
+ .../corstone1000/fw_update_agent/fwu_agent.h  |   3 +
+ .../corstone1000/fw_update_agent/uefi_fmp.c   | 240 ++++++++++++++++++
+ .../corstone1000/fw_update_agent/uefi_fmp.h   |  56 ++++
+ .../include/corstone1000_ioctl_requests.h     |  14 +-
+ .../services/src/tfm_platform_system.c        |   9 +
+ 8 files changed, 374 insertions(+), 19 deletions(-)
+ create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/uefi_fmp.c
+ create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/uefi_fmp.h
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index 81522c7cf0..3602312a3a 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -76,6 +76,8 @@ target_sources(platform_s
+         fw_update_agent/uefi_capsule_parser.c
+         fw_update_agent/fwu_agent.c
+         $<$<BOOL:${TFM_S_REG_TEST}>:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg.c>
+        fw_update_agent/uefi_fmp.c
+        $<$<NOT:$<BOOL:${PLATFORM_DEFAULT_OTP}>>:${PLATFORM_DIR}/ext/accelerator/cc312/otp_cc312.c>
+ )
+ 
+ if (PLATFORM_IS_FVP)
+diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
+index a6a1a33c42..ab0fe17ba8 100644
+--- a/platform/ext/target/arm/corstone1000/config.cmake
+++ b/platform/ext/target/arm/corstone1000/config.cmake
+@@ -50,7 +50,9 @@ else()
+     set(PLATFORM_PSA_ADAC_SECURE_DEBUG      FALSE        CACHE BOOL      "Whether to use psa-adac secure debug.")
+ endif()
+ 
+-set(DEFAULT_MCUBOOT_SECURITY_COUNTERS   OFF          CACHE BOOL      "Whether to use the default security counter configuration defined by TF-M project")
+set(DEFAULT_MCUBOOT_SECURITY_COUNTERS       OFF          CACHE BOOL      "Whether to use the default security counter configuration defined by TF-M project")
+ 
+-set(PS_ENCRYPTION                       OFF          CACHE BOOL      "Enable encryption for Protected Storage partition")
+-set(PS_ROLLBACK_PROTECTION              OFF          CACHE BOOL      "Enable rollback protection for Protected Storage partition")
+set(PS_ENCRYPTION                           OFF          CACHE BOOL      "Enable encryption for Protected Storage partition")
+set(PS_ROLLBACK_PROTECTION                  OFF          CACHE BOOL      "Enable rollback protection for Protected Storage partition")
+
+set(PLATFORM_SERVICE_OUTPUT_BUFFER_SIZE     256          CACHE STRING    "Size of output buffer in platform service.")
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index 3abb5dd0dc..72a5fc9c1d 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -18,6 +18,7 @@
+ #include "platform_description.h"
+ #include "tfm_plat_nv_counters.h"
+ #include "tfm_plat_defs.h"
+#include "uefi_fmp.h"
+ 
+ /* Properties of image in a bank */
+ struct fwu_image_properties {
+@@ -84,6 +85,11 @@ struct fwu_private_metadata {
+        /* staged nv_counter: temprary location before written to the otp */
+        uint32_t nv_counter[NR_OF_IMAGES_IN_FW_BANK];
+ 
+       /* FMP information */
+       uint32_t fmp_version;
+       uint32_t fmp_last_attempt_version;
+       uint32_t fmp_last_attempt_status;
+
+ } __packed;
+ 
+ #define MAX_BOOT_ATTEMPTS_PER_BANK 3
+@@ -278,7 +284,7 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
+ {
+     enum fwu_agent_error_t ret;
+     struct fwu_private_metadata priv_metadata;
+-    uint32_t image_version = 0;
+    uint32_t image_version = FWU_IMAGE_INITIAL_VERSION;
+ 
+     FWU_LOG_MSG("%s: enter\n\r", __func__);
+ 
+@@ -302,8 +308,8 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
+     memset(&_metadata, 0, sizeof(struct fwu_metadata));
+ 
+     _metadata.version = 1;
+-    _metadata.active_index = 0;
+-    _metadata.previous_active_index = 1;
+    _metadata.active_index = BANK_0;
+    _metadata.previous_active_index = BANK_1;
+ 
+     /* bank 0 is the place where images are located at the
+      * start of device lifecycle */
+@@ -339,6 +345,10 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
+     priv_metadata.boot_index = BANK_0;
+     priv_metadata.boot_attempted = 0;
+ 
+    priv_metadata.fmp_version = FWU_IMAGE_INITIAL_VERSION;
+    priv_metadata.fmp_last_attempt_version = FWU_IMAGE_INITIAL_VERSION;
+    priv_metadata.fmp_last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS;
+
+     ret = private_metadata_write(&priv_metadata);
+     if (ret) {
+         return ret;
+@@ -540,9 +550,25 @@ enum fwu_agent_error_t corstone1000_fwu_flash_image(void)
+                                 &image_bank_offset);
+         switch(image_index) {
+             case IMAGE_ALL:
+
+                 ret = flash_full_capsule(&_metadata, capsule_info.image[i],
+                                          capsule_info.size[i],
+                                          capsule_info.version[i]);
+
+                if (ret != FWU_AGENT_SUCCESS) {
+
+                    priv_metadata.fmp_last_attempt_version = capsule_info.version[i];
+                    priv_metadata.fmp_last_attempt_status = LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL;
+
+                    private_metadata_write(&priv_metadata);
+
+                    fmp_set_image_info(&full_capsule_image_guid,
+                            priv_metadata.fmp_version,
+                            priv_metadata.fmp_last_attempt_version,
+                            priv_metadata.fmp_last_attempt_status);
+                }
+
+
+                 break;
+             default:
+                 FWU_LOG_MSG("%s: sent image not recognized\n\r", __func__);
+@@ -866,17 +892,42 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+ 
+     current_state = get_fwu_agent_state(&_metadata, &priv_metadata);
+     if (current_state == FWU_AGENT_STATE_REGULAR) {
+
+         ret = FWU_AGENT_SUCCESS; /* nothing to be done */
+
+        fmp_set_image_info(&full_capsule_image_guid,
+                priv_metadata.fmp_version,
+                priv_metadata.fmp_last_attempt_version,
+                priv_metadata.fmp_last_attempt_status);
+
+         goto out;
+
+     } else if (current_state != FWU_AGENT_STATE_TRIAL) {
+         FWU_ASSERT(0);
+     }
+ 
+     if (_metadata.active_index != priv_metadata.boot_index) {
+
+         /* firmware update failed, revert back to previous bank */
+
+        priv_metadata.fmp_last_attempt_version =
+         _metadata.img_entry[IMAGE_0].img_props[_metadata.active_index].version;
+
+        priv_metadata.fmp_last_attempt_status = LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL;
+
+         ret = fwu_select_previous(&_metadata, &priv_metadata);
+
+     } else {
+
+         /* firmware update successful */
+
+        priv_metadata.fmp_version =
+         _metadata.img_entry[IMAGE_0].img_props[_metadata.active_index].version;
+        priv_metadata.fmp_last_attempt_version =
+         _metadata.img_entry[IMAGE_0].img_props[_metadata.active_index].version;
+
+        priv_metadata.fmp_last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS;
+
+         ret = fwu_accept_image(&full_capsule_image_guid, &_metadata,
+                                 &priv_metadata);
+         if (!ret) {
+@@ -886,6 +937,10 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+ 
+     if (ret == FWU_AGENT_SUCCESS) {
+         disable_host_ack_timer();
+        fmp_set_image_info(&full_capsule_image_guid,
+                priv_metadata.fmp_version,
+                priv_metadata.fmp_last_attempt_version,
+                priv_metadata.fmp_last_attempt_status);
+     }
+ 
+ out:
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+index 57b07e8d2c..aa18179024 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+@@ -30,6 +30,9 @@ enum fwu_agent_error_t {
+                 }                                                              \
+ 
+ 
+/* Version used for the very first image of the device. */
+#define FWU_IMAGE_INITIAL_VERSION 0
+
+ enum fwu_agent_error_t fwu_metadata_provision(void);
+ enum fwu_agent_error_t fwu_metadata_init(void);
+ 
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_fmp.c b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_fmp.c
+new file mode 100644
+index 0000000000..ce576e1794
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_fmp.c
+@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <string.h>
+#include <stdbool.h>
+#include "cmsis.h"
+#include "uefi_fmp.h"
+
+/* The count will increase when partial update is supported.
+ * At present, only full WIC is considered as updatable image.
+ */
+#define NUMBER_OF_FMP_IMAGES 1
+#define NO_OF_FMP_VARIABLES_PER_IMAGE   6
+
+#define UEFI_ARCHITECTURE_64
+
+#ifdef UEFI_ARCHITECTURE_64
+typedef uint64_t uefi_ptr_t;
+typedef uint64_t efi_uintn_t;
+#else
+typedef uint32_t uefi_ptr_t;
+typedef uint32_t efi_uintn_t;
+#endif
+
+/* Below macro definations and struct declarations taken from UEFI spec 2.9 */
+
+/*
+ * Image Attribute Definitions
+ */
+#define IMAGE_ATTRIBUTE_IMAGE_UPDATABLE            0x00000001
+#define IMAGE_ATTRIBUTE_RESET_REQUIRED             0x00000002
+#define IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED    0x00000004
+#define IMAGE_ATTRIBUTE_IN_USE                     0x00000008
+#define IMAGE_ATTRIBUTE_UEFI_IMAGE                 0x00000010
+#define IMAGE_ATTRIBUTE_DEPENDENCY                 0x00000020
+
+typedef uint32_t DescriptorVersion_t;
+typedef uint32_t DescriptorSize_t;
+typedef uint8_t DescriptorCount_t;
+
+typedef __PACKED_STRUCT {
+    uint8_t ImageIndex;
+    struct efi_guid ImageTypeId;
+    uint64_t ImageId;
+    uefi_ptr_t PtrImageIdName;
+    uint32_t Version;
+    uefi_ptr_t PtrVersionName;
+    efi_uintn_t Size;
+    uint64_t AttributesSupported;
+    uint64_t AttributesSetting;
+    uint64_t Compatibilities;
+    /* Introduced with DescriptorVersion 2+ */
+    uint32_t LowestSupportedImageVersion;
+    /* Introduced with DescriptorVersion 3+ */
+    uint32_t LastAttemptVersion;
+    uint32_t LastAttemptStatus;
+    uint64_t HardwareInstance;
+    /* Introduced with DescriptorVersion 4+ */
+    uefi_ptr_t PtrDependencies;
+} EFI_FIRMWARE_IMAGE_DESCRIPTOR;
+
+typedef __PACKED_STRUCT {
+    DescriptorVersion_t DescriptorVersion;
+    DescriptorSize_t DescriptorsSize;
+    DescriptorCount_t DescriptorCount;
+    EFI_FIRMWARE_IMAGE_DESCRIPTOR ImageDescriptor;
+    uint16_t *ImageName;
+    uint32_t ImageNameSize;
+    uint16_t *ImageVersionName;
+    uint32_t ImageVersionNameSize;
+} EFI_FIRMWARE_MANAGEMENT_PROTOCOL_IMAGE_INFO;
+
+
+static uint16_t corstone_image_name0[] = { 'C', 'O', 'R', 'S', 'T', 'O', 'N', 'E', '1', '0', '0', '0', '_', 'W', 'I', 'C', '\0' };
+static uint16_t corstone_version_name0[] = { 'C', 'O', 'R', 'S', 'T', 'O', 'N', 'E', '1', '0', '0', '0', '_', 'B', 'E', 'S', 'T', '\0'};
+
+static EFI_FIRMWARE_MANAGEMENT_PROTOCOL_IMAGE_INFO fmp_info[NUMBER_OF_FMP_IMAGES];
+
+extern struct efi_guid full_capsule_image_guid;
+
+static bool is_fmp_info_initialized = false;
+
+static void init_fmp_info(void)
+{
+    memset(fmp_info, 0,
+     sizeof(EFI_FIRMWARE_MANAGEMENT_PROTOCOL_IMAGE_INFO) * NUMBER_OF_FMP_IMAGES);
+
+    /* Fill information for the WIC.
+     * Add further details when partial image is supported.
+     */
+
+    fmp_info[0].DescriptorVersion = 4;
+    fmp_info[0].DescriptorCount = NUMBER_OF_FMP_IMAGES;
+    fmp_info[0].DescriptorsSize =
+                 sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR) +
+                 sizeof(corstone_image_name0) + sizeof(corstone_version_name0);
+
+    fmp_info[0].ImageDescriptor.ImageIndex = 1;
+
+    memcpy(&fmp_info[0].ImageDescriptor.ImageTypeId, &full_capsule_image_guid,
+            sizeof(struct efi_guid));
+
+    fmp_info[0].ImageDescriptor.ImageId = 1;
+    fmp_info[0].ImageDescriptor.Version = FWU_IMAGE_INITIAL_VERSION;
+    fmp_info[0].ImageDescriptor.AttributesSupported = 1;
+    fmp_info[0].ImageDescriptor.AttributesSetting = (
+            IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | IMAGE_ATTRIBUTE_RESET_REQUIRED);
+    fmp_info[0].ImageDescriptor.LowestSupportedImageVersion =
+            FWU_IMAGE_INITIAL_VERSION;
+    fmp_info[0].ImageDescriptor.LastAttemptVersion = FWU_IMAGE_INITIAL_VERSION;
+    fmp_info[0].ImageDescriptor.LastAttemptStatus = LAST_ATTEMPT_STATUS_SUCCESS;
+
+    fmp_info[0].ImageName = corstone_image_name0;
+    fmp_info[0].ImageNameSize = sizeof(corstone_image_name0);
+    fmp_info[0].ImageVersionName = corstone_version_name0;
+    fmp_info[0].ImageVersionNameSize = sizeof(corstone_version_name0);
+
+    is_fmp_info_initialized = true;
+
+    return;
+}
+
+enum fwu_agent_error_t fmp_set_image_info(struct efi_guid *guid,
+                     uint32_t current_version, uint32_t attempt_version,
+                     uint32_t last_attempt_status)
+{
+    enum fwu_agent_error_t status = FWU_AGENT_ERROR;
+
+    FWU_LOG_MSG("%s:%d Enter\n\r", __func__, __LINE__);
+
+    if (is_fmp_info_initialized == false) {
+        init_fmp_info();
+    }
+
+    for (int i = 0; i < NUMBER_OF_FMP_IMAGES; i++) {
+        if ((memcmp(guid, &fmp_info[i].ImageDescriptor.ImageTypeId,
+                        sizeof(struct efi_guid))) == 0)
+        {
+            FWU_LOG_MSG("FMP image update: image id = %u\n\r",
+                                    fmp_info[i].ImageDescriptor.ImageId);
+            fmp_info[i].ImageDescriptor.Version = current_version;
+            fmp_info[i].ImageDescriptor.LastAttemptVersion = attempt_version;
+            fmp_info[i].ImageDescriptor.LastAttemptStatus = last_attempt_status;
+            FWU_LOG_MSG("FMP image update: status = %u"
+                            "version=%u last_attempt_version=%u.\n\r",
+                            last_attempt_status, current_version,
+                            attempt_version);
+            status = FWU_AGENT_SUCCESS;
+            break;
+        }
+    }
+
+    FWU_LOG_MSG("%s:%d Exit.\n\r", __func__, __LINE__);
+    return status;
+}
+
+
+#define NO_OF_FMP_VARIABLES    (NUMBER_OF_FMP_IMAGES * NO_OF_FMP_VARIABLES_PER_IMAGE)
+
+static enum fwu_agent_error_t pack_image_info(void *buffer, uint32_t size)
+{
+    typedef __PACKED_STRUCT {
+        uint32_t variable_count;
+        uint32_t variable_size[NO_OF_FMP_VARIABLES];
+        uint8_t variable[];
+    } packed_buffer_t;
+
+    packed_buffer_t *packed_buffer = buffer;
+    int runner = 0;
+    int index = 0;
+    int current_size = sizeof(packed_buffer_t);
+    int size_requirement_1 = 0;
+    int size_requirement_2 = 0;
+
+    if (size < current_size) {
+        FWU_LOG_MSG("%s:%d Buffer too small.\n\r", __func__, __LINE__);
+        return FWU_AGENT_ERROR;
+    }
+
+    packed_buffer->variable_count = NO_OF_FMP_VARIABLES;
+
+    for (int i = 0; i < NUMBER_OF_FMP_IMAGES; i++) {
+
+       packed_buffer->variable_size[index++] = sizeof(DescriptorVersion_t);
+       packed_buffer->variable_size[index++] = sizeof(DescriptorSize_t);
+       packed_buffer->variable_size[index++] = sizeof(DescriptorCount_t);
+       packed_buffer->variable_size[index++] = sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR);
+       packed_buffer->variable_size[index++] = fmp_info[i].ImageNameSize;
+       packed_buffer->variable_size[index++] = fmp_info[i].ImageVersionNameSize;
+
+       size_requirement_1 = sizeof(DescriptorVersion_t) + sizeof(DescriptorSize_t) +
+              sizeof(DescriptorCount_t) + sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR);
+
+       size_requirement_2 = fmp_info[i].ImageNameSize + fmp_info[i].ImageVersionNameSize;
+
+       current_size += size_requirement_1 + size_requirement_2;
+
+       if (size < current_size) {
+           FWU_LOG_MSG("%s:%d Buffer too small.\n\r", __func__, __LINE__);
+           return FWU_AGENT_ERROR;
+       }
+
+       FWU_LOG_MSG("%s:%d ImageInfo size = %u, ImageName size = %u, "
+               "ImageVersionName size = %u\n\r", __func__, __LINE__,
+               sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR), fmp_info[i].ImageNameSize,
+               fmp_info[i].ImageVersionNameSize);
+   
+       memcpy(&packed_buffer->variable[runner], &fmp_info[i], size_requirement_1);
+       runner += size_requirement_1;
+   
+       memcpy(&packed_buffer->variable[runner], fmp_info[i].ImageName,
+                                       fmp_info[i].ImageNameSize);
+       runner += fmp_info[i].ImageNameSize;
+   
+       memcpy(&packed_buffer->variable[runner], fmp_info[i].ImageVersionName,
+                                       fmp_info[i].ImageVersionNameSize);
+       runner += fmp_info[i].ImageVersionNameSize;
+
+    }
+
+    return FWU_AGENT_SUCCESS;
+}
+
+enum fwu_agent_error_t fmp_get_image_info(void *buffer, uint32_t size)
+{
+    enum fwu_agent_error_t status;
+
+    FWU_LOG_MSG("%s:%d Enter\n\r", __func__, __LINE__);
+
+    status = pack_image_info(buffer, size);
+
+    FWU_LOG_MSG("%s:%d Exit\n\r", __func__, __LINE__);
+
+    return status;
+}
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_fmp.h b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_fmp.h
+new file mode 100644
+index 0000000000..d876bd7cff
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_fmp.h
+@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef UEFI_FMP_H
+#define UEFI_FMP_H
+
+
+#include <stdint.h>
+#include "fwu_agent.h"
+#include "../fip_parser/external/uuid.h"
+
+/*
+ * Last Attempt Status Value
+ */
+
+#define LAST_ATTEMPT_STATUS_SUCCESS                                     0x00000000
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL                          0x00000001
+#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES                0x00000002
+#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION                     0x00000003
+#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT                        0x00000004
+#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR                            0x00000005
+#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC                            0x00000006
+#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT                          0x00000007
+#define LAST_ATTEMPT_STATUS_ERROR_UNSATISFIED_DEPENDENCIES              0x00000008
+/* The LastAttemptStatus values of 0x1000 - 0x4000 are reserved for vendor usage. */
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MIN         0x00001000
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL_VENDOR_RANGE_MAX         0x00004000
+
+
+
+/*
+ * Updates FMP information for the image matched by guid.
+ *
+ * guid : guid of the image
+ * current_version: current versions for the image
+ * attempt_version: attempted versions for the image
+ *
+ */
+enum fwu_agent_error_t fmp_set_image_info(struct efi_guid *guid,
+                     uint32_t current_version, uint32_t attempt_version,
+                     uint32_t last_attempt_status);
+
+/*
+ * Return fmp image information for all the updable images.
+ *
+ * buffer : pointer to the out buffer
+ * size : size of the buffer
+ *
+ */
+enum fwu_agent_error_t fmp_get_image_info(void *buffer, uint32_t size);
+
+#endif /* UEFI_FMP_H */
+diff --git a/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h b/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h
+index 8ac67346b6..c5f3537e9d 100644
+--- a/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h
+++ b/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h
+@@ -14,19 +14,7 @@
+ enum corstone1000_ioctl_id_t {
+    IOCTL_CORSTONE1000_FWU_FLASH_IMAGES = 0,
+    IOCTL_CORSTONE1000_FWU_HOST_ACK,
+   IOCTL_CORSTONE1000_FMP_GET_IMAGE_INFO,
+ };
+ 
+-
+-typedef struct corstone1000_ioctl_in_params {
+-
+-    uint32_t ioctl_id;
+-
+-} corstone1000_ioctl_in_params_t;
+-
+-typedef struct corstone1000_ioctl_out_params {
+-
+-    int32_t result;
+-
+-} corstone1000_ioctl_out_params_t;
+-
+ #endif /* CORSTONE1000_IOCTL_REQUESTS_H */
+diff --git a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+index 5b3f3e14a2..41305ed966 100644
+--- a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+++ b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+@@ -9,6 +9,7 @@
+ #include "platform_description.h"
+ #include "corstone1000_ioctl_requests.h"
+ #include "fwu_agent.h"
+#include "uefi_fmp.h"
+ 
+ void tfm_platform_hal_system_reset(void)
+ {
+@@ -36,6 +37,14 @@ enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
+             corstone1000_fwu_host_ack();
+             break;
+ 
+        case IOCTL_CORSTONE1000_FMP_GET_IMAGE_INFO:
+            if (out_vec == NULL) {
+                ret = TFM_PLATFORM_ERR_INVALID_PARAM;
+                break;
+            }
+            fmp_get_image_info(out_vec[0].base, out_vec[0].len);
+            break;
+
+         default:
+             ret = TFM_PLATFORM_ERR_NOT_SUPPORTED;
+             break;
+-- 
+2.25.1
+
@@ -0,0 +1,51 @@
+From 492c887c8dff97ea1b8a11b4e729620d3744ac38 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Mon, 30 May 2022 12:38:23 +0100
+Subject: [PATCH 6/6] corstone1000: remove two partition configuration
+
+Previously to run tf-m test, a larger partition was created
+which allowed all default test binaries to be included.
+The patch revert the change because any partition might
+not be enough to hold all test binaries in the future.
+So its better to run few test at a time instead of creating
+a larger partition.
+
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+Change-Id: I223fe45f2de014dbcadc6ac12c321c524701116a
+Upstream-Status: Accepted [TF-Mv1.7.0]
+---
+ platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt       | 1 -
+ platform/ext/target/arm/corstone1000/partition/flash_layout.h | 4 ----
+ 2 files changed, 5 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+index d39c5ae91d..f1ae1ebd47 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+@@ -291,7 +291,6 @@ target_compile_definitions(signing_layout_for_bl2
+     PRIVATE
+         MCUBOOT_IMAGE_NUMBER=${BL1_IMAGE_NUMBER}
+         BL1
+-        $<$<BOOL:${TFM_S_REG_TEST}>:TFM_S_REG_TEST>
+ )
+ 
+ target_include_directories(signing_layout_for_bl2
+diff --git a/platform/ext/target/arm/corstone1000/partition/flash_layout.h b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+index b0319bb319..50a0a11fc8 100644
+--- a/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+++ b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+@@ -119,11 +119,7 @@
+  *
+  */
+ #define SE_BL2_PARTITION_SIZE           (0x19000)    /* 100 KB */
+-#ifdef TFM_S_REG_TEST
+-#define TFM_PARTITION_SIZE              (0x61C00)    /* 391 KB */
+-#else
+ #define TFM_PARTITION_SIZE              (0x5E000)    /* 376 KB */
+-#endif
+ #define FIP_PARTITION_SIZE              (0x200000)   /* 2 MB */
+ #define KERNEL_PARTITION_SIZE           (0xC00000)   /* 12 MB */
+ 
+-- 
+2.25.1
+
@@ -0,0 +1,27 @@
+From 5be42e1c05205209fc3988f0df30a02da95c2448 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Wed, 2 Nov 2022 00:12:35 +0000
+Subject: [PATCH] corstone1000: adjust PS asset configuration
+
+Adjust protected storage asset configuration to be more inline
+with the one in trusted service side, that would make thinks
+work when testing and using more than the default variables.
+
+Upstream-Status: Pending
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ platform/ext/target/arm/corstone1000/config.cmake | 1 ++
+ 1 file changed, 1 insertions(+)
+
+diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
+index ab0fe17ba886..c2b4b646e6b0 100644
+--- a/platform/ext/target/arm/corstone1000/config.cmake
+++ b/platform/ext/target/arm/corstone1000/config.cmake
+@@ -56,3 +56,4 @@ set(PS_ENCRYPTION                           OFF          CACHE BOOL      "Enable
+ set(PS_ROLLBACK_PROTECTION                  OFF          CACHE BOOL      "Enable rollback protection for Protected Storage partition")
+ 
+ set(PLATFORM_SERVICE_OUTPUT_BUFFER_SIZE     256          CACHE STRING    "Size of output buffer in platform service.")
+set(PS_NUM_ASSETS                           "40"        CACHE STRING    "The maximum number of assets to be stored in the Protected Storage area")
+-- 
+2.38.1
+
@@ -11,22 +11,6 @@ TFM_PLATFORM_IS_FVP ?= "FALSE"
 EXTRA_OECMAKE += "-DPLATFORM_IS_FVP=${TFM_PLATFORM_IS_FVP}"
 EXTRA_OECMAKE += "-DCC312_LEGACY_DRIVER_API_ENABLED=OFF"

-SRCBRANCH_tfm = "master"
-SRC_URI  = "git://git.trustedfirmware.org/TF-M/trusted-firmware-m.git;protocol=https;branch=${SRCBRANCH_tfm};name=tfm;destsuffix=git/tfm \
-            git://git.trustedfirmware.org/TF-M/tf-m-tests.git;protocol=https;branch=master;name=tfm-tests;destsuffix=git/tf-m-tests \
-            git://github.com/ARMmbed/mbedtls.git;protocol=https;branch=master;name=mbedtls;destsuffix=git/mbedtls \
-            git://github.com/mcu-tools/mcuboot.git;protocol=https;branch=main;name=mcuboot;destsuffix=git/mcuboot \
-            "
-
-# Bumping the SHA of TFM is required as multiple changes are needed in the TFM to support the ESRT 
-# The most crucial change needed is TFM support for UEFI FMP Image Information 
-SRCREV_tfm = "b065a6b28cc6c692b99e4f7e9387d96f51bf4d07"
-SRCREV_mbedtls = "869298bffeea13b205343361b7a7daf2b210e33d"
-SRCREV_mcuboot = "c657cbea75f2bb1faf1fceacf972a0537a8d26dd"
-SRCREV_tfm-tests = "3e6c52b4b255e4b1343ba6a257a77fa7a976e8fb"
-PV .= "+git${SRCPV}"
-SRCREV_FORMAT ?= "tfm"
-
 # libmetal
 LICENSE += "& BSD-3-Clause"
 LIC_FILES_CHKSUM += "file://../libmetal/LICENSE.md;md5=fe0b8a4beea8f0813b606d15a3df3d3c"
@@ -41,16 +25,17 @@ SRC_URI += "git://github.com/OpenAMP/open-amp.git;protocol=https;branch=main;nam
 SRCREV_openamp = "347397decaa43372fc4d00f965640ebde042966d"
 EXTRA_OECMAKE += "-DLIBOPENAMP_SRC_PATH=${S}/../openamp -DLIBOPENAMP_BIN_PATH=${B}/libopenamp-build"

-# Secure Debug ADAC
-LICENSE += "& BSD-3-Clause"
-LIC_FILES_CHKSUM += "file://../psa-adac/license.rst;md5=07f368487da347f3c7bd0fc3085f3afa"
-SRC_URI += "git://git.trustedfirmware.org/shared/psa-adac.git;protocol=https;branch=master;name=psa-adac;destsuffix=git/psa-adac"
-SRCREV_psa-adac = "427923cc0152578d536fb2065154d5d0dd874910"
-# Secure debug is disabled by default
-EXTRA_OECMAKE += "-DPLATFORM_PSA_ADAC_SECURE_DEBUG=OFF"
-EXTRA_OECMAKE += "-DPLATFORM_PSA_ADAC_SOURCE_PATH=${S}/../psa-adac -DPLATFORM_PSA_ADAC_BUILD_PATH=${B}/libpsa-adac-build"
-
-DEPENDS += "trusted-firmware-a"
+# Apply the necessary changes for supporting FMP image info
+FILESEXTRAPATHS:prepend := "${THISDIR}/corstone1000:"
+SRC_URI:append:corstone1000 = " \
+        file://0001-corstone1000-platform-secure-test-framework.patch             \
+        file://0002-corstone1000-make-external-system-support-optional.patch      \
+        file://0003-corstone1000-enable-secure-enclave-run-without-host-.patch    \
+        file://0004-Platform-Partition-Allow-configuration-of-input-and-.patch    \
+        file://0005-corstone1000-support-for-UEFI-FMP-image-Information.patch     \
+        file://0006-corstone1000-remove-two-partition-configuration.patch         \
+        file://0007-corstone1000-adjust-PS-asset-configuration.patch              \
+      "

 do_install() {
  install -D -p -m 0644 ${B}/install/outputs/tfm_s_signed.bin ${D}/firmware/tfm_s_signed.bin
@@ -0,0 +1,182 @@
+From 6cb8e5f83d53357fbc6e58c2c5c5a3450654f9e6 Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Wed, 19 Oct 2022 17:51:10 +0100
+Subject: [PATCH] arm_ffa: add support for 32-bit direct messaging
+
+add 32-bit mode for FFA_MSG_SEND_DIRECT_REQ and FFA_MSG_SEND_DIRECT_RESP
+
+Tested-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ cmd/armffa.c                       |  2 +-
+ drivers/firmware/arm-ffa/core.c    | 17 ++++++++++++++---
+ drivers/firmware/arm-ffa/sandbox.c |  2 +-
+ include/arm_ffa.h                  |  2 +-
+ lib/efi_loader/efi_capsule.c       |  2 +-
+ lib/efi_loader/efi_setup.c         |  2 +-
+ lib/efi_loader/efi_variable_tee.c  |  2 +-
+ test/dm/ffa.c                      |  6 +++---
+ 8 files changed, 23 insertions(+), 12 deletions(-)
+
+diff --git a/cmd/armffa.c b/cmd/armffa.c
+index 9b56e8a830..9842b99181 100644
+--- a/cmd/armffa.c
+++ b/cmd/armffa.c
+@@ -129,7 +129,7 @@ int  do_ffa_msg_send_direct_req(struct cmd_tbl *cmdtp, int flag, int argc,
+ 		return -EINVAL;
+ 	}
+ 
+-	ret = ffa_bus_ops_get()->sync_send_receive(part_id, &msg);
+	ret = ffa_bus_ops_get()->sync_send_receive(part_id, &msg, 1);
+ 	if (ret == 0) {
+ 		u8 cnt;
+ 
+diff --git a/drivers/firmware/arm-ffa/core.c b/drivers/firmware/arm-ffa/core.c
+index caba10caae..ba1ba59937 100644
+--- a/drivers/firmware/arm-ffa/core.c
+++ b/drivers/firmware/arm-ffa/core.c
+@@ -1032,6 +1032,7 @@ static int ffa_cache_partitions_info(void)
+  * ffa_msg_send_direct_req - FFA_MSG_SEND_DIRECT_{REQ,RESP} handler function
+  * @dst_part_id: destination partition ID
+  * @msg: pointer to the message data preallocated by the client (in/out)
+ * @is_smc64: select 64-bit or 32-bit FF-A ABI
+  *
+  * This is the runtime function that implements FFA_MSG_SEND_DIRECT_{REQ,RESP}
+  * FF-A functions.
+@@ -1048,10 +1049,12 @@ static int ffa_cache_partitions_info(void)
+  *
+  * 0 on success. Otherwise, failure
+  */
+-static int __ffa_runtime ffa_msg_send_direct_req(u16 dst_part_id, struct ffa_send_direct_data *msg)
+static int __ffa_runtime ffa_msg_send_direct_req(u16 dst_part_id, struct ffa_send_direct_data *msg,
+						 u8 is_smc64)
+ {
+ 	ffa_value_t res = {0};
+ 	int ffa_errno;
+	u64 req_mode, resp_mode;
+ 
+ 	if (!ffa_priv_data || !ffa_priv_data->invoke_ffa_fn)
+ 		return -EINVAL;
+@@ -1060,8 +1063,16 @@ static int __ffa_runtime ffa_msg_send_direct_req(u16 dst_part_id, struct ffa_sen
+ 	if (!ffa_priv_data->partitions.count || !ffa_priv_data->partitions.descs)
+ 		return -ENODEV;
+ 
+	if(is_smc64) {
+		req_mode = FFA_SMC_64(FFA_MSG_SEND_DIRECT_REQ);
+		resp_mode = FFA_SMC_64(FFA_MSG_SEND_DIRECT_RESP);
+	} else {
+		req_mode = FFA_SMC_32(FFA_MSG_SEND_DIRECT_REQ);
+		resp_mode = FFA_SMC_32(FFA_MSG_SEND_DIRECT_RESP);
+	}
+
+ 	ffa_priv_data->invoke_ffa_fn((ffa_value_t){
+-			.a0 = FFA_SMC_64(FFA_MSG_SEND_DIRECT_REQ),
+			.a0 = req_mode,
+ 			.a1 = PREP_SELF_ENDPOINT_ID(ffa_priv_data->id) |
+ 				PREP_PART_ENDPOINT_ID(dst_part_id),
+ 			.a2 = 0,
+@@ -1083,7 +1094,7 @@ static int __ffa_runtime ffa_msg_send_direct_req(u16 dst_part_id, struct ffa_sen
+ 		return 0;
+ 	}
+ 
+-	if (res.a0 == FFA_SMC_64(FFA_MSG_SEND_DIRECT_RESP)) {
+	if (res.a0 == resp_mode){
+ 		/*
+ 		 * Message sent with response
+ 		 * extract the return data
+diff --git a/drivers/firmware/arm-ffa/sandbox.c b/drivers/firmware/arm-ffa/sandbox.c
+index 16e1fdc809..8e8549441d 100644
+--- a/drivers/firmware/arm-ffa/sandbox.c
+++ b/drivers/firmware/arm-ffa/sandbox.c
+@@ -430,7 +430,7 @@ static int sandbox_ffa_sp_valid(u16 part_id)
+  * @{a0-a7} , res: The SMC call arguments and return structure.
+  *
+  * This is the function that emulates FFA_MSG_SEND_DIRECT_{REQ,RESP}
+- * FF-A functions.
+ * FF-A functions. Only SMC 64-bit is supported in Sandbox.
+  *
+  * Emulating interrupts is not supported. So, FFA_RUN and FFA_INTERRUPT are not supported.
+  * In case of success FFA_MSG_SEND_DIRECT_RESP is returned with default pattern data (0xff).
+diff --git a/include/arm_ffa.h b/include/arm_ffa.h
+index 665413a0c5..4a7c59ff28 100644
+--- a/include/arm_ffa.h
+++ b/include/arm_ffa.h
+@@ -97,7 +97,7 @@ struct __packed ffa_send_direct_data {
+ struct ffa_bus_ops {
+ 	int (*partition_info_get)(const char *uuid_str,
+ 				  u32 *parts_size, struct ffa_partition_info *buffer);
+-	int (*sync_send_receive)(u16 dst_part_id, struct ffa_send_direct_data *msg);
+	int (*sync_send_receive)(u16 dst_part_id, struct ffa_send_direct_data *msg, u8 is_smc64);
+ 	int (*rxtx_unmap)(void);
+ };
+ 
+diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
+index 65e2fc8296..c479c53d04 100644
+--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
+@@ -591,7 +591,7 @@ static int __efi_runtime efi_corstone1000_buffer_ready_event(u32 capsule_image_s
+ 	msg.data1 = PREP_SEPROXY_SVC_ID(CORSTONE1000_SEPROXY_UPDATE_SVC_ID) |
+ 		PREP_SEPROXY_EVT(CORSTONE1000_BUFFER_READY_EVT); /* w4 */
+ 
+-	return ffa_bus_ops_get()->sync_send_receive(CORSTONE1000_SEPROXY_PART_ID, &msg);
+	return ffa_bus_ops_get()->sync_send_receive(CORSTONE1000_SEPROXY_PART_ID, &msg, 0);
+ }
+ #endif
+ 
+diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
+index 6ccda175ff..416af8d663 100644
+--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
+@@ -153,7 +153,7 @@ static int efi_corstone1000_uboot_efi_started_event(void)
+ 	msg.data1 = PREP_SEPROXY_SVC_ID(CORSTONE1000_SEPROXY_UPDATE_SVC_ID) |
+ 			PREP_SEPROXY_EVT(CORSTONE1000_UBOOT_EFI_STARTED_EVT); /* w4 */
+ 
+-	return ffa_bus_ops_get()->sync_send_receive(CORSTONE1000_SEPROXY_PART_ID, &msg);
+	return ffa_bus_ops_get()->sync_send_receive(CORSTONE1000_SEPROXY_PART_ID, &msg, 0);
+ }
+ #endif
+ 
+diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c
+index 7d9d577281..05f3c02911 100644
+--- a/lib/efi_loader/efi_variable_tee.c
+++ b/lib/efi_loader/efi_variable_tee.c
+@@ -201,7 +201,7 @@ static int __efi_runtime ffa_notify_mm_sp(void)
+ 
+ 	msg.data0 = FFA_SHARED_MM_BUFFER_OFFSET; /* x3 */
+ 
+-	ret = ffa_bus_ops_get()->sync_send_receive(mm_sp_id, &msg);
+	ret = ffa_bus_ops_get()->sync_send_receive(mm_sp_id, &msg, 1);
+ 	if (ret != 0)
+ 		return ret;
+ 
+diff --git a/test/dm/ffa.c b/test/dm/ffa.c
+index 052d5fc3f4..14b19cf71e 100644
+--- a/test/dm/ffa.c
+++ b/test/dm/ffa.c
+@@ -170,7 +170,7 @@ static int  test_ffa_msg_send_direct_req(u16 part_id, struct unit_test_state *ut
+ 	struct ffa_send_direct_data msg = {0};
+ 	u8 cnt;
+ 
+-	ut_assertok(ffa_bus_ops_get()->sync_send_receive(part_id, &msg));
+	ut_assertok(ffa_bus_ops_get()->sync_send_receive(part_id, &msg, 1));
+ 
+ 	for (cnt = 0; cnt < sizeof(struct ffa_send_direct_data) / sizeof(u64); cnt++)
+ 		ut_assertok(((u64 *)&msg)[cnt] != 0xffffffffffffffff);
+@@ -380,12 +380,12 @@ static int dm_test_ffa_nack(struct unit_test_state *uts)
+ 	ut_assertok(count != SANDBOX_SP_COUNT_PER_VALID_SERVICE);
+ 
+ 	/* send data to an invalid partition */
+-	ret = ffa_bus_ops_get()->sync_send_receive(part_id, &msg);
+	ret = ffa_bus_ops_get()->sync_send_receive(part_id, &msg, 1);
+ 	ut_assertok(ret != -EINVAL);
+ 
+ 	/* send data to a valid partition */
+ 	part_id = prvdata->partitions.descs[0].info.id;
+-	ret = ffa_bus_ops_get()->sync_send_receive(part_id, &msg);
+	ret = ffa_bus_ops_get()->sync_send_receive(part_id, &msg, 1);
+ 	ut_assertok(ret != 0);
+ 
+ 	return CMD_RET_SUCCESS;
+-- 
+2.17.1
@@ -48,7 +48,8 @@ SRC_URI:append:corstone1000 = " \
        file://0028-Introduce-external-sys-driver-to-device-tree.patch \
        file://0029-Add-mhu-and-rpmsg-client-to-u-boot-device-tree.patch \
        file://0030-arm-corstone1000-esrt-support.patch \
-      "
+        file://0031-ffa-add-support-for-32-bit-direct-messaging.patch  \
+        "

 #
 # FVP BASE
@@ -0,0 +1,29 @@
+From b443c8efd563dc372c60e7ad9f52aeddf7c13706 Mon Sep 17 00:00:00 2001
+From: Anton Antonov <Anton.Antonov@arm.com>
+Date: Mon, 7 Nov 2022 11:37:51 +0000
+Subject: [PATCH] arm64: dts: fvp: Enable virtio-rng support
+
+The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17.
+Enable it since Yocto includes a recipe for a newer FVP version.
+
+Upstream-Status: Inappropriate [Yocto specific]
+Signed-off-by: Anton Antonov <Anton.Antonov@arm.com>
+---
+ arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
+index ec2d5280a30b..acafdcbf1063 100644
+--- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi
+@@ -26,7 +26,6 @@ virtio@200000 {
+ 					compatible = "virtio,mmio";
+ 					reg = <0x200000 0x200>;
+ 					interrupts = <46>;
+-					status = "disabled";
+ 				};
+ 			};
+ 		};
+-- 
+2.25.1
+
@@ -36,7 +36,6 @@ SRC_URI:append:corstone500 = " \
 # Corstone1000 KMACHINE
 #
 FILESEXTRAPATHS:prepend:corstone1000 := "${ARMBSPFILESPATHS}"
-FILESEXTRAPATHS:prepend:corstone1000 := "${ARMFILESPATHS}"
 COMPATIBLE_MACHINE:corstone1000 = "${MACHINE}"
 KCONFIG_MODE:corstone1000 = "--alldefconfig"
 KMACHINE:corstone1000 = "corstone1000"
@@ -70,6 +69,7 @@ KERNEL_FEATURES:corstone1000 = ""
 COMPATIBLE_MACHINE:fvp-base = "fvp-base"
 KMACHINE:fvp-base = "fvp"
 FILESEXTRAPATHS:prepend:fvp-base := "${ARMBSPFILESPATHS}"
+SRC_URI:append:fvp-base = " file://0001-arm64-dts-fvp-Enable-virtio-rng-support.patch"

 #
 # FVP BASE ARM32 KMACHINE
@@ -115,7 +115,6 @@ COMPATIBLE_MACHINE:n1sdp = "n1sdp"
 KBUILD_DEFCONFIG:n1sdp = "defconfig"
 KCONFIG_MODE:n1sdp = "--alldefconfig"
 FILESEXTRAPATHS:prepend:n1sdp := "${ARMBSPFILESPATHS}"
-FILESEXTRAPATHS:prepend:n1sdp := "${ARMFILESPATHS}"
 SRC_URI:append:n1sdp = " \
    file://0001-iommu-arm-smmu-v3-workaround-for-ATC_INV_SIZE_ALL-in.patch \
    file://0002-n1sdp-pci_quirk-add-acs-override-for-PCI-devices.patch \
@@ -13,7 +13,8 @@ it around as necessary, and handling (most of) the new choices.
 Signed-off-by: Robin Murphy <robin.murphy@arm.com>
 Link: https://lore.kernel.org/r/e58b495bcc7deec3882be4bac910ed0bf6979674.1638530442.git.robin.murphy@arm.com
 Signed-off-by: Will Deacon <will@kernel.org>
-Upstream-Status = Backport [https://lore.kernel.org/r/e58b495bcc7deec3882be4bac910ed0bf6979674.1638530442.git.robin.murphy@arm.com]
+
+Upstream-Status: Backport [https://lore.kernel.org/r/e58b495bcc7deec3882be4bac910ed0bf6979674.1638530442.git.robin.murphy@arm.com]
 Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
 ---
@@ -1,7 +1,7 @@
-From 7c9589c4bb056db5e1696f2a777891ab235b1b63 Mon Sep 17 00:00:00 2001
+From 13de79cd4f0d25b812e5f4ad4a19bc075496be83 Mon Sep 17 00:00:00 2001
 From: Vishnu Banavath <vishnu.banavath@arm.com>
 Date: Fri, 3 Dec 2021 16:36:51 +0000
-Subject: [PATCH 01/19] Add openamp to SE proxy deployment
+Subject: [PATCH 01/20] Add openamp to SE proxy deployment

 Openamp is required to communicate between secure partitions(running on
 Cortex-A) and trusted-firmware-m(running on Cortex-M).
@@ -283,5 +283,5 @@ index 000000000000..449f35f4fda4
 +set_property(TARGET openamp PROPERTY IMPORTED_LOCATION "${OPENAMP_INSTALL_DIR}/lib/${CMAKE_STATIC_LIBRARY_PREFIX}open_amp${CMAKE_STATIC_LIBRARY_SUFFIX}")
 +set_property(TARGET openamp PROPERTY INTERFACE_INCLUDE_DIRECTORIES "${OPENAMP_INSTALL_DIR}/include")
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From e4ccb92f8de94a82edd3548d62c853790ae36bd1 Mon Sep 17 00:00:00 2001
+From 28aedac78016e5063ebd675a43e6c3655f87b442 Mon Sep 17 00:00:00 2001
 From: Vishnu Banavath <vishnu.banavath@arm.com>
 Date: Fri, 3 Dec 2021 18:00:46 +0000
-Subject: [PATCH 02/19] Implement mhu driver and the OpenAmp conversion layer.
+Subject: [PATCH 02/20] Implement mhu driver and the OpenAmp conversion layer.

 This commit adds an mhu driver (v2.1 and v2) to the secure
 partition se_proxy and a conversion layer to communicate with
@@ -1087,5 +1087,5 @@ index 000000000000..bb778bb9719b
 +# include MHU driver
 +include(${TS_ROOT}/platform/drivers/arm/mhu_driver/component.cmake)
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From e187510a814b48b7b2e477a9913ee35b68522d06 Mon Sep 17 00:00:00 2001
+From 55394c4c9681af71b1ed7f7ebc7c44b2e1737113 Mon Sep 17 00:00:00 2001
 From: Vishnu Banavath <vishnu.banavath@arm.com>
 Date: Fri, 3 Dec 2021 19:00:54 +0000
-Subject: [PATCH 03/19] Add openamp rpc caller
+Subject: [PATCH 03/20] Add openamp rpc caller

 Upstream-Status: Pending
 Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
@@ -1192,5 +1192,5 @@ index d39873a0fe81..34fe5ff1b925 100644
 		# Stub service provider backends
 		"components/rpc/dummy"
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From 8c1bc5a7ae525d64802e2a06746f698f54cf07ca Mon Sep 17 00:00:00 2001
+From fb6d2f33e26c7b6ef88d552feca1f835da3f0df6 Mon Sep 17 00:00:00 2001
 From: Vishnu Banavath <vishnu.banavath@arm.com>
 Date: Fri, 3 Dec 2021 19:05:18 +0000
-Subject: [PATCH 04/19] add psa client definitions for ff-m
+Subject: [PATCH 04/20] add psa client definitions for ff-m

 Add PSA client definitions in common include to add future
 ff-m support.
@@ -294,5 +294,5 @@ index 000000000000..aaa973c6e987
 +
 +#endif /* __PSA_MANIFEST_SID_H__ */
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From e9778f726ed582360152f150301995b10d268aae Mon Sep 17 00:00:00 2001
+From 0311fc8f131fe7a2b0f4dd9988c610fda47394aa Mon Sep 17 00:00:00 2001
 From: Vishnu Banavath <vishnu.banavath@arm.com>
 Date: Fri, 3 Dec 2021 19:13:03 +0000
-Subject: [PATCH 05/19] Add common service component to ipc support
+Subject: [PATCH 05/20] Add common service component to ipc support

 Add support for inter processor communication for PSA
 including, the openamp client side structures lib.
@@ -291,5 +291,5 @@ index 34fe5ff1b925..dd0c5d00c21e 100644
 		"components/service/discovery/provider"
 		"components/service/discovery/provider/serializer/packed-c"
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From 0df82487a7a253c601ca20ca1bd64fbb9ed64230 Mon Sep 17 00:00:00 2001
+From ed4371d63cb52c121be9678bc225055944286c30 Mon Sep 17 00:00:00 2001
 From: Vishnu Banavath <vishnu.banavath@arm.com>
 Date: Fri, 3 Dec 2021 19:19:24 +0000
-Subject: [PATCH 06/19] Add secure storage ipc backend
+Subject: [PATCH 06/20] Add secure storage ipc backend

 Add secure storage ipc ff-m implementation which may use
 openamp as rpc to communicate with other processor.
@@ -519,5 +519,5 @@ index dd0c5d00c21e..cd51460406ca 100644
 		"components/service/attestation/provider"
 		"components/service/attestation/provider/serializer/packed-c"
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From 9c7f1e6a5eb9ab887e568cfa3c2003583d387bc9 Mon Sep 17 00:00:00 2001
+From d1377a5ed909e3a1d9caca56aeda262a80322a4b Mon Sep 17 00:00:00 2001
 From: Vishnu Banavath <vishnu.banavath@arm.com>
 Date: Fri, 3 Dec 2021 19:25:34 +0000
-Subject: [PATCH 07/19] Use secure storage ipc and openamp for se_proxy
+Subject: [PATCH 07/20] Use secure storage ipc and openamp for se_proxy

 Remove mock up backend for secure storage in se proxy
 deployment and use instead the secure storage ipc backend with
@@ -59,5 +59,5 @@ index acfb6e8873fa..57290056d614 100644
 	return secure_storage_provider_init(&ps_provider, backend);
 }
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From d9169d380366afc63af5d4bf02791aeb41f47897 Mon Sep 17 00:00:00 2001
+From 1b50ab6b6ff1c6f27ab320e18fb0d4aeb1122f0d Mon Sep 17 00:00:00 2001
 From: Satish Kumar <satish.kumar01@arm.com>
 Date: Sun, 12 Dec 2021 10:43:48 +0000
-Subject: [PATCH 08/19] Run psa-arch-test
+Subject: [PATCH 08/20] Run psa-arch-test

 Fixes needed to run psa-arch-test

@@ -68,5 +68,5 @@ index 4f6ba2a7d822..1fd6b40dc803 100644
 };
 
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From ee767c1ae857cfcc8b4bb520b2558091e253cf94 Mon Sep 17 00:00:00 2001
+From a6fba503ffddae004e23b32559212e749e8586f6 Mon Sep 17 00:00:00 2001
 From: Satish Kumar <satish.kumar01@arm.com>
 Date: Sun, 12 Dec 2021 10:57:17 +0000
-Subject: [PATCH 09/19] Use address instead of pointers
+Subject: [PATCH 09/20] Use address instead of pointers

 Since secure enclave is 32bit and we 64bit there is an issue
 in the protocol communication design that force us to handle
@@ -164,5 +164,5 @@ index a1f369db253e..bda442a61d5c 100644
 
 	(void)client_id;
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From afdeb8e098a1f2822adf2ea83ded8dd9e2d021ba Mon Sep 17 00:00:00 2001
+From b142f3c162fb1c28982d26b5ac2181ba79197a28 Mon Sep 17 00:00:00 2001
 From: Rui Miguel Silva <rui.silva@linaro.org>
 Date: Tue, 7 Dec 2021 11:50:00 +0000
-Subject: [PATCH 10/19] Add psa ipc attestation to se proxy
+Subject: [PATCH 10/20] Add psa ipc attestation to se proxy

 Implement attestation client API as psa ipc and include it to
 se proxy deployment.
@@ -16,12 +16,15 @@ Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
 .../reporter/psa_ipc/psa_ipc_attest_report.c  | 45 ++++++++++
 components/service/common/include/psa/sid.h   |  4 +
 .../se-proxy/common/service_proxy_factory.c   |  6 ++
- deployments/se-proxy/se-proxy.cmake           |  3 +-
- 7 files changed, 169 insertions(+), 1 deletion(-)
+ deployments/se-proxy/se-proxy.cmake           |  7 +-
+ ...ble-using-hard-coded-attestation-key.patch | 29 -------
+ external/psa_arch_tests/psa_arch_tests.cmake  |  4 -
+ 9 files changed, 171 insertions(+), 36 deletions(-)
 create mode 100644 components/service/attestation/client/psa_ipc/component.cmake
 create mode 100644 components/service/attestation/client/psa_ipc/iat_ipc_client.c
 create mode 100644 components/service/attestation/reporter/psa_ipc/component.cmake
 create mode 100644 components/service/attestation/reporter/psa_ipc/psa_ipc_attest_report.c
+ delete mode 100644 external/psa_arch_tests/0001-Disable-using-hard-coded-attestation-key.patch

 diff --git a/components/service/attestation/client/psa_ipc/component.cmake b/components/service/attestation/client/psa_ipc/component.cmake
 new file mode 100644
@@ -243,10 +246,10 @@ index 57290056d614..4b8cceccbe4d 100644
 	attest_provider_register_serializer(&attest_provider,
 		TS_RPC_ENCODING_PACKED_C, packedc_attest_provider_serializer_instance());
 diff --git a/deployments/se-proxy/se-proxy.cmake b/deployments/se-proxy/se-proxy.cmake
-index cd51460406ca..38d26821d44d 100644
+index cd51460406ca..3dbbc36c968d 100644
 --- a/deployments/se-proxy/se-proxy.cmake
 +++ b/deployments/se-proxy/se-proxy.cmake
-@@ -49,12 +49,13 @@ add_components(TARGET "se-proxy"
+@@ -49,14 +49,15 @@ add_components(TARGET "se-proxy"
 		"components/service/attestation/include"
 		"components/service/attestation/provider"
 		"components/service/attestation/provider/serializer/packed-c"
@@ -258,9 +261,63 @@ index cd51460406ca..38d26821d44d 100644
 		"components/rpc/dummy"
 		"components/rpc/common/caller"
 -		"components/service/attestation/reporter/stub"
- 		"components/service/attestation/key_mngr/stub"
- 		"components/service/crypto/backend/stub"
+-		"components/service/attestation/key_mngr/stub"
+-		"components/service/crypto/backend/stub"
+		"components/service/attestation/key_mngr/local"
+		"components/service/crypto/backend/psa_ipc"
 		"components/service/crypto/client/psa"
+ 		"components/service/secure_storage/backend/mock_store"
+ )
+diff --git a/external/psa_arch_tests/0001-Disable-using-hard-coded-attestation-key.patch b/external/psa_arch_tests/0001-Disable-using-hard-coded-attestation-key.patch
+deleted file mode 100644
+index 6664961ab662..000000000000
+--- a/external/psa_arch_tests/0001-Disable-using-hard-coded-attestation-key.patch
+++ /dev/null
+@@ -1,29 +0,0 @@
+-From dbd25f94eb62a9855bf342dd97503a49ea50f83e Mon Sep 17 00:00:00 2001
+-From: Gyorgy Szing <Gyorgy.Szing@arm.com>
+-Date: Tue, 8 Feb 2022 17:06:37 +0000
+-Subject: [PATCH 1/1] Disable using hard-coded attestation key
+-
+-Modify platform config to disable using a hard-coded attestation
+-key.
+-
+-Signed-off-by: Gyorgy Szing <Gyorgy.Szing@arm.com>
+----
+- api-tests/platform/targets/tgt_dev_apis_linux/nspe/pal_config.h | 2 +-
+- 1 file changed, 1 insertion(+), 1 deletion(-)
+-
+-diff --git a/api-tests/platform/targets/tgt_dev_apis_linux/nspe/pal_config.h b/api-tests/platform/targets/tgt_dev_apis_linux/nspe/pal_config.h
+-index 6112ba7..1cdf581 100755
+---- a/api-tests/platform/targets/tgt_dev_apis_linux/nspe/pal_config.h
+-+++ b/api-tests/platform/targets/tgt_dev_apis_linux/nspe/pal_config.h
+-@@ -60,7 +60,7 @@ typedef uint32_t            cfg_id_t;
+- #define CRYPTO_VERSION_BETA3
+- 
+- /* Use hardcoded public key */
+--#define PLATFORM_OVERRIDE_ATTEST_PK
+-+//#define PLATFORM_OVERRIDE_ATTEST_PK
+- 
+- /*
+-  * Include of PSA defined Header files
+--- 
+-2.17.1
+-
+diff --git a/external/psa_arch_tests/psa_arch_tests.cmake b/external/psa_arch_tests/psa_arch_tests.cmake
+index a8b77a1fc05e..1995df3e0b49 100644
+--- a/external/psa_arch_tests/psa_arch_tests.cmake
+++ b/external/psa_arch_tests/psa_arch_tests.cmake
+@@ -15,10 +15,6 @@ set(GIT_OPTIONS
+ 	GIT_REPOSITORY ${PSA_ARCH_TESTS_URL}
+ 	GIT_TAG ${PSA_ARCH_TESTS_REFSPEC}
+ 	GIT_SHALLOW FALSE
+-	PATCH_COMMAND git stash
+-		COMMAND git tag -f ts-before-am
+-		COMMAND git am ${CMAKE_CURRENT_LIST_DIR}/0001-Disable-using-hard-coded-attestation-key.patch
+-		COMMAND git reset ts-before-am
+ )
+ 
+ # Ensure list of defines is separated correctly
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From 94770f9660154bb1157e19c11fb706889a81ae73 Mon Sep 17 00:00:00 2001
+From 4240977f7c38950f5edb316bb08ae05cb7b99875 Mon Sep 17 00:00:00 2001
 From: Satish Kumar <satish.kumar01@arm.com>
 Date: Thu, 9 Dec 2021 14:11:06 +0000
-Subject: [PATCH 11/19] Setup its backend as openamp rpc using secure storage
+Subject: [PATCH 11/20] Setup its backend as openamp rpc using secure storage
 ipc implementation.

 Upstream-Status: Pending
@@ -159,5 +159,5 @@ index 4b8cceccbe4d..1110ac46bf8b 100644
 +        return secure_storage_provider_init(&its_provider, backend);
 }
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From 896b5009bb07c4b53541290e1712856063411107 Mon Sep 17 00:00:00 2001
+From 0b5d96b1a9f927dc141047600edf2249af7022c5 Mon Sep 17 00:00:00 2001
 From: Rui Miguel Silva <rui.silva@linaro.org>
 Date: Thu, 9 Dec 2021 14:17:39 +0000
-Subject: [PATCH 12/19] add psa ipc crypto backend
+Subject: [PATCH 12/20] add psa ipc crypto backend

 Add psa ipc crypto backend and attach it to se proxy
 deployment.
@@ -36,9 +36,8 @@ Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
 .../crypto/include/psa/crypto_client_struct.h |   8 +-
 .../service/crypto/include/psa/crypto_sizes.h |   2 +-
 .../se-proxy/common/service_proxy_factory.c   |  15 +-
- deployments/se-proxy/se-proxy.cmake           |   2 +-
 .../providers/arm/corstone1000/platform.cmake |   2 +
- 29 files changed, 2293 insertions(+), 11 deletions(-)
+ 28 files changed, 2292 insertions(+), 10 deletions(-)
 create mode 100644 components/service/crypto/backend/psa_ipc/component.cmake
 create mode 100644 components/service/crypto/backend/psa_ipc/crypto_ipc_backend.c
 create mode 100644 components/service/crypto/backend/psa_ipc/crypto_ipc_backend.h
@@ -2556,19 +2555,6 @@ index 1110ac46bf8b..7edeef8b434a 100644
 
 	return crypto_iface;
 }
-diff --git a/deployments/se-proxy/se-proxy.cmake b/deployments/se-proxy/se-proxy.cmake
-index 38d26821d44d..f647190d9559 100644
--- a/deployments/se-proxy/se-proxy.cmake
-+++ b/deployments/se-proxy/se-proxy.cmake
-@@ -57,7 +57,7 @@ add_components(TARGET "se-proxy"
- 		"components/rpc/dummy"
- 		"components/rpc/common/caller"
- 		"components/service/attestation/key_mngr/stub"
-		"components/service/crypto/backend/stub"
-+		"components/service/crypto/backend/psa_ipc"
- 		"components/service/crypto/client/psa"
- 		"components/service/secure_storage/backend/mock_store"
- )
 diff --git a/platform/providers/arm/corstone1000/platform.cmake b/platform/providers/arm/corstone1000/platform.cmake
 index bb778bb9719b..51e5faa3e4d8 100644
 --- a/platform/providers/arm/corstone1000/platform.cmake
@@ -2580,5 +2566,5 @@ index bb778bb9719b..51e5faa3e4d8 100644
 +
 +add_compile_definitions(MBEDTLS_ECP_DP_SECP521R1_ENABLED)
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From 6b8ebdeb8caa6326ae2a4befaf4410a7a54d4e02 Mon Sep 17 00:00:00 2001
+From 050be6fdfee656b0556766cc1db30f4c0ea87c79 Mon Sep 17 00:00:00 2001
 From: Julian Hall <julian.hall@arm.com>
 Date: Tue, 12 Oct 2021 15:45:41 +0100
-Subject: [PATCH 13/19] Add stub capsule update service components
+Subject: [PATCH 13/20] Add stub capsule update service components

 To facilitate development of a capsule update service provider,
 stub components are added to provide a starting point for an
@@ -338,7 +338,7 @@ index 298d407a2371..02aa7fe2550d 100644
 #ifdef __cplusplus
 }
 diff --git a/deployments/se-proxy/se-proxy.cmake b/deployments/se-proxy/se-proxy.cmake
-index f647190d9559..e35b0d0f610d 100644
+index 3dbbc36c968d..f0db2d43f443 100644
 --- a/deployments/se-proxy/se-proxy.cmake
 +++ b/deployments/se-proxy/se-proxy.cmake
@@ -51,6 +51,7 @@ add_components(TARGET "se-proxy"
@@ -432,5 +432,5 @@ index 000000000000..285d924186be
 +
 +#endif /* CAPSULE_UPDATE_PARAMETERS_H */
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From a71b26f867f1b4a08285d6da82528de6a54321f2 Mon Sep 17 00:00:00 2001
+From 229ec29154a4404426ad3083af68ca111a214e13 Mon Sep 17 00:00:00 2001
 From: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
 Date: Thu, 16 Dec 2021 21:31:40 +0000
-Subject: [PATCH 14/19] Configure storage size
+Subject: [PATCH 14/20] Configure storage size

 Upstream-Status: Pending
 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
@@ -10,7 +10,7 @@ Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
 1 file changed, 3 insertions(+), 2 deletions(-)

 diff --git a/components/service/smm_variable/backend/uefi_variable_store.c b/components/service/smm_variable/backend/uefi_variable_store.c
-index 715ccc3cb546..aeb8a22062b7 100644
+index 611e2e225c6b..6c3b9ed81c25 100644
 --- a/components/service/smm_variable/backend/uefi_variable_store.c
 +++ b/components/service/smm_variable/backend/uefi_variable_store.c
@@ -88,6 +88,7 @@ static efi_status_t check_name_terminator(
@@ -38,5 +38,5 @@ index 715ccc3cb546..aeb8a22062b7 100644
 
 	context->owner_id = owner_id;
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From 3cc9c417f12f005244530d8d706a6b7f3be35627 Mon Sep 17 00:00:00 2001
+From cf83184500703f9b4f2ac04be59cc7d624d8fd66 Mon Sep 17 00:00:00 2001
 From: Satish Kumar <satish.kumar01@arm.com>
 Date: Sun, 13 Feb 2022 09:01:10 +0000
-Subject: [PATCH 15/19] Fix: Crypto interface structure aligned with tf-m
+Subject: [PATCH 15/20] Fix: Crypto interface structure aligned with tf-m
 change.

 NO NEED TO RAISE PR: The PR for this FIX  is raied by Emek.
@@ -27,5 +27,5 @@ index c13c20e84131..ec25eaf868c7 100644
 							    *   AEAD until the API is
 							    *   restructured
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From c54afe45c1be25c4819b0f762cf03a24e6343ce5 Mon Sep 17 00:00:00 2001
+From 551d8722769fa2f2d2ac74adcb289333a9b03598 Mon Sep 17 00:00:00 2001
 From: Satish Kumar <satish.kumar01@arm.com>
 Date: Sun, 13 Feb 2022 09:49:51 +0000
-Subject: [PATCH 16/19] Integrate remaining psa-ipc client APIs.
+Subject: [PATCH 16/20] Integrate remaining psa-ipc client APIs.

 Upstream-Status: Pending
 Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
@@ -490,5 +490,5 @@ index e16f6e5450af..cc9279ee79f2 100644
 }
 #endif
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From b1ff44c650ae82f364a2f74059eeb280996dc4f8 Mon Sep 17 00:00:00 2001
+From 5a5e162e17c9decb04b3b2905a0fb604e8f06e91 Mon Sep 17 00:00:00 2001
 From: Satish Kumar <satish.kumar01@arm.com>
 Date: Mon, 14 Feb 2022 17:52:00 +0000
-Subject: [PATCH 17/19] Fix : update psa_set_key_usage_flags definition to the
+Subject: [PATCH 17/20] Fix : update psa_set_key_usage_flags definition to the
 latest from the tf-m

 Upstream-Status: Pending
@@ -36,5 +36,5 @@ index 1bc55e375eea..b4a7ed4b39d3 100644
 }
 
 -- 
-2.38.0
+2.38.1

@@ -1,9 +1,10 @@
-From a1da63a8c4d55d52321608a72129af49e0a498b2 Mon Sep 17 00:00:00 2001
+From 1a4d46fdc0b5745b9cfb0789e4b778111bd6dbbb Mon Sep 17 00:00:00 2001
 From: Satish Kumar <satish.kumar01@arm.com>
 Date: Mon, 14 Feb 2022 08:22:25 +0000
-Subject: [PATCH 18/19] Fixes in AEAD for psa-arch test 54 and 58.
+Subject: [PATCH 18/20] Fixes in AEAD for psa-arch test 54 and 58.

-Upstream-Status: Pending
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
 Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
 ---
@@ -116,5 +117,5 @@ index 0be266b52403..435fd3b523ce 100644
 
 /* Variable length input parameter tags */
 -- 
-2.38.0
+2.38.1

@@ -1,7 +1,7 @@
-From 07ad7e1f7ba06045bf331d5b73a6adf38a098fb7 Mon Sep 17 00:00:00 2001
+From c519bae79629bfe551d79cfeb4e7d8a059545145 Mon Sep 17 00:00:00 2001
 From: Rui Miguel Silva <rui.silva@linaro.org>
 Date: Tue, 11 Oct 2022 10:46:10 +0100
-Subject: [PATCH 19/19] plat: corstone1000: change default smm values
+Subject: [PATCH 19/20] plat: corstone1000: change default smm values

 Smm gateway uses SE proxy to route the calls for any NV
 storage so set the NV_STORE_SN.
@@ -33,5 +33,5 @@ index 51e5faa3e4d8..04b629a81906 100644
 +	SMM_GATEWAY_MAX_UEFI_VARIABLES=100
 +)
 -- 
-2.38.0
+2.38.1

@@ -0,0 +1,418 @@
+From 70cf374fb55f2d62ecbe28049253df33b42b6749 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Fri, 8 Jul 2022 09:48:06 +0100
+Subject: [PATCH 20/20] FMP Support in Corstone1000.
+
+The FMP support is used by u-boot to pupolate ESRT information
+for the kernel.
+
+The solution is platform specific and needs to be revisted.
+
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+Upstream-Status: Inappropriate [The solution is platform specific and needs to be revisted]
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ .../provider/capsule_update_provider.c        |   5 +
+ .../capsule_update/provider/component.cmake   |   1 +
+ .../provider/corstone1000_fmp_service.c       | 307 ++++++++++++++++++
+ .../provider/corstone1000_fmp_service.h       |  26 ++
+ 4 files changed, 339 insertions(+)
+ create mode 100644 components/service/capsule_update/provider/corstone1000_fmp_service.c
+ create mode 100644 components/service/capsule_update/provider/corstone1000_fmp_service.h
+
+diff --git a/components/service/capsule_update/provider/capsule_update_provider.c b/components/service/capsule_update/provider/capsule_update_provider.c
+index e133753f8560..991a2235cd73 100644
+--- a/components/service/capsule_update/provider/capsule_update_provider.c
+++ b/components/service/capsule_update/provider/capsule_update_provider.c
+@@ -11,6 +11,7 @@
+ #include <protocols/service/capsule_update/capsule_update_proto.h>
+ #include <protocols/rpc/common/packed-c/status.h>
+ #include "capsule_update_provider.h"
+#include "corstone1000_fmp_service.h"
+ 
+ 
+ #define CAPSULE_UPDATE_REQUEST (0x1)
+@@ -47,6 +48,8 @@ struct rpc_interface *capsule_update_provider_init(
+ 		rpc_interface = service_provider_get_rpc_interface(&context->base_provider);
+ 	}
+ 
+	provision_fmp_variables_metadata(context->client.caller);
+
+ 	return rpc_interface;
+ }
+ 
+@@ -85,6 +88,7 @@ static rpc_status_t event_handler(uint32_t opcode, struct rpc_caller *caller)
+ 		}
+ 		psa_call(caller,handle, PSA_IPC_CALL,
+ 			in_vec,IOVEC_LEN(in_vec), NULL, 0);
+		set_fmp_image_info(caller, handle);
+ 		break;
+ 
+ 		case KERNEL_STARTED_EVENT:
+@@ -99,6 +103,7 @@ static rpc_status_t event_handler(uint32_t opcode, struct rpc_caller *caller)
+ 		}
+ 		psa_call(caller,handle, PSA_IPC_CALL,
+ 			in_vec,IOVEC_LEN(in_vec), NULL, 0);
+		set_fmp_image_info(caller, handle);
+ 		break;
+ 		default:
+ 			EMSG("%s unsupported opcode", __func__);
+diff --git a/components/service/capsule_update/provider/component.cmake b/components/service/capsule_update/provider/component.cmake
+index 1d412eb234d9..6b0601494938 100644
+--- a/components/service/capsule_update/provider/component.cmake
+++ b/components/service/capsule_update/provider/component.cmake
+@@ -10,4 +10,5 @@ endif()
+ 
+ target_sources(${TGT} PRIVATE
+ 	"${CMAKE_CURRENT_LIST_DIR}/capsule_update_provider.c"
+	"${CMAKE_CURRENT_LIST_DIR}/corstone1000_fmp_service.c"
+ 	)
+diff --git a/components/service/capsule_update/provider/corstone1000_fmp_service.c b/components/service/capsule_update/provider/corstone1000_fmp_service.c
+new file mode 100644
+index 000000000000..6a7a47a7ed99
+--- /dev/null
+++ b/components/service/capsule_update/provider/corstone1000_fmp_service.c
+@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "corstone1000_fmp_service.h"
+#include <psa/client.h>
+#include <psa/sid.h>
+#include <psa/storage_common.h>
+#include <trace.h>
+
+#include <service/smm_variable/backend/variable_index.h>
+
+#define VARIABLE_INDEX_STORAGE_UID			(0x787)
+
+/**
+ * Variable attributes
+ */
+#define	EFI_VARIABLE_NON_VOLATILE				(0x00000001)
+#define	EFI_VARIABLE_BOOTSERVICE_ACCESS				(0x00000002)
+#define	EFI_VARIABLE_RUNTIME_ACCESS				(0x00000004)
+#define	EFI_VARIABLE_HARDWARE_ERROR_RECORD			(0x00000008)
+#define	EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS			(0x00000010)
+#define	EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS	(0x00000020)
+#define	EFI_VARIABLE_APPEND_WRITE				(0x00000040)
+#define	EFI_VARIABLE_MASK \
+	(EFI_VARIABLE_NON_VOLATILE | \
+	 EFI_VARIABLE_BOOTSERVICE_ACCESS | \
+	 EFI_VARIABLE_RUNTIME_ACCESS | \
+	 EFI_VARIABLE_HARDWARE_ERROR_RECORD | \
+	 EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS | \
+	 EFI_VARIABLE_APPEND_WRITE)
+
+#define FMP_VARIABLES_COUNT	6
+
+static struct variable_metadata fmp_variables_metadata[FMP_VARIABLES_COUNT] = {
+    {
+	{ 0x86c77a67, 0x0b97, 0x4633, \
+		{ 0xa1, 0x87, 0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7} },
+	/* name size = (variable_name + \0) * sizeof(u16) */
+	.name_size = 42, { 'F', 'm', 'p', 'D', 'e', 's', 'c', 'r', 'i', 'p', 't', 'o', 'r', 'V', 'e', 'r', 's', 'i', 'o', 'n' },
+	.attributes = EFI_VARIABLE_NON_VOLATILE, .uid = 0
+    },
+    {
+	{ 0x86c77a67, 0x0b97, 0x4633, \
+		{ 0xa1, 0x87, 0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7} },
+	/* name size = (variable_name + \0) * sizeof(u16) */
+	.name_size = 34, { 'F', 'm', 'p', 'I', 'm', 'a', 'g', 'e', 'I', 'n', 'f', 'o', 'S', 'i', 'z', 'e' },
+	.attributes = EFI_VARIABLE_NON_VOLATILE, .uid = 0
+    },
+    {
+	{ 0x86c77a67, 0x0b97, 0x4633, \
+		{ 0xa1, 0x87, 0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7} },
+	/* name size = (variable_name + \0) * sizeof(u16) */
+	.name_size = 38, { 'F', 'm', 'p', 'D', 'e', 's', 'c', 'r', 'i', 'p', 't', 'o', 'r', 'C', 'o', 'u', 'n', 't' },
+	.attributes = EFI_VARIABLE_NON_VOLATILE, .uid = 0
+    },
+    {
+	{ 0x86c77a67, 0x0b97, 0x4633, \
+		{ 0xa1, 0x87, 0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7} },
+	/* name size = (variable_name + \0) * sizeof(u16) */
+	.name_size = 26, { 'F', 'm', 'p', 'I', 'm', 'a', 'g', 'e', 'I', 'n', 'f', 'o' },
+	.attributes = EFI_VARIABLE_NON_VOLATILE, .uid = 0
+    },
+    {
+	{ 0x86c77a67, 0x0b97, 0x4633, \
+		{ 0xa1, 0x87, 0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7} },
+	/* name size = (variable_name + \0) * sizeof(u16) */
+	.name_size = 28, { 'F', 'm', 'p', 'I', 'm', 'a', 'g', 'e', 'N', 'a', 'm', 'e', '1' },
+	.attributes = EFI_VARIABLE_NON_VOLATILE, .uid = 0
+    },
+    {
+	{ 0x86c77a67, 0x0b97, 0x4633, \
+		{ 0xa1, 0x87, 0x49, 0x10, 0x4d, 0x06, 0x85, 0xc7} },
+	/* name size = (variable_name + \0) * sizeof(u16) */
+	.name_size = 32, { 'F', 'm', 'p', 'V', 'e', 'r', 's', 'i', 'o', 'n',  'N', 'a', 'm', 'e', '1' },
+	.attributes = EFI_VARIABLE_NON_VOLATILE, .uid = 0
+    },
+};
+
+static psa_status_t protected_storage_set(struct rpc_caller *caller,
+	psa_storage_uid_t uid, size_t data_length, const void *p_data)
+{
+	psa_status_t psa_status;
+	psa_storage_create_flags_t create_flags = PSA_STORAGE_FLAG_NONE;
+
+	struct psa_invec in_vec[] = {
+		{ .base = psa_ptr_to_u32(&uid), .len = sizeof(uid) },
+		{ .base = psa_ptr_const_to_u32(p_data), .len = data_length },
+		{ .base = psa_ptr_to_u32(&create_flags), .len = sizeof(create_flags) },
+	};
+
+	psa_status = psa_call(caller, TFM_PROTECTED_STORAGE_SERVICE_HANDLE, TFM_PS_ITS_SET,
+			      in_vec, IOVEC_LEN(in_vec), NULL, 0);
+	if (psa_status < 0)
+		EMSG("ipc_set: psa_call failed: %d", psa_status);
+
+	return psa_status;
+}
+
+static psa_status_t protected_storage_get(struct rpc_caller *caller,
+	psa_storage_uid_t uid, size_t data_size, void *p_data)
+{
+	psa_status_t psa_status;
+	uint32_t offset = 0;
+
+	struct psa_invec in_vec[] = {
+		{ .base = psa_ptr_to_u32(&uid), .len = sizeof(uid) },
+		{ .base = psa_ptr_to_u32(&offset), .len = sizeof(offset) },
+	};
+
+	struct psa_outvec out_vec[] = {
+		{ .base = psa_ptr_to_u32(p_data), .len = data_size },
+	};
+
+	psa_status = psa_call(caller, TFM_PROTECTED_STORAGE_SERVICE_HANDLE,
+			      TFM_PS_ITS_GET, in_vec, IOVEC_LEN(in_vec),
+			      out_vec, IOVEC_LEN(out_vec));
+
+	if (psa_status == PSA_SUCCESS && out_vec[0].len != data_size) {
+	    EMSG("Return size does not match with expected size.");
+	    return PSA_ERROR_BUFFER_TOO_SMALL;
+	}
+
+	return psa_status;
+}	
+
+static uint64_t name_hash(EFI_GUID *guid, size_t name_size,
+	const int16_t *name)
+{
+	/* Using djb2 hash by Dan Bernstein */
+	uint64_t hash = 5381;
+
+	/* Calculate hash over GUID */
+	hash = ((hash << 5) + hash) + guid->Data1;
+	hash = ((hash << 5) + hash) + guid->Data2;
+	hash = ((hash << 5) + hash) + guid->Data3;
+
+	for (int i = 0; i < 8; ++i) {
+
+		hash = ((hash << 5) + hash) + guid->Data4[i];
+	}   
+
+	/* Extend to cover name up to but not including null terminator */
+	for (int i = 0; i < name_size / sizeof(int16_t); ++i) {
+
+		if (!name[i]) break;
+		hash = ((hash << 5) + hash) + name[i];
+	}
+
+	return hash;
+}
+
+
+static void initialize_metadata(void)
+{
+    for (int i = 0; i < FMP_VARIABLES_COUNT; i++) {
+
+	fmp_variables_metadata[i].uid = name_hash(
+					&fmp_variables_metadata[i].guid,
+					fmp_variables_metadata[i].name_size,
+					fmp_variables_metadata[i].name);
+    }
+}
+
+
+void provision_fmp_variables_metadata(struct rpc_caller *caller)
+{
+    struct variable_metadata metadata;
+    psa_status_t status;
+    uint32_t dummy_values = 0xDEAD;
+
+    EMSG("Provisioning FMP metadata.");
+
+    initialize_metadata();
+
+    status = protected_storage_get(caller, VARIABLE_INDEX_STORAGE_UID,
+		sizeof(struct variable_metadata), &metadata);
+
+    if (status == PSA_SUCCESS) {
+	EMSG("UEFI variables store is already provisioned.");
+	return;
+    }
+
+    /* Provision FMP variables with dummy values. */
+    for (int i = 0; i < FMP_VARIABLES_COUNT; i++) {
+	protected_storage_set(caller, fmp_variables_metadata[i].uid,
+				sizeof(dummy_values), &dummy_values);
+    }
+
+    status = protected_storage_set(caller, VARIABLE_INDEX_STORAGE_UID,
+		    sizeof(struct variable_metadata) * FMP_VARIABLES_COUNT,
+		    fmp_variables_metadata);
+
+    if (status != EFI_SUCCESS) {
+	return;
+    }
+
+    EMSG("FMP metadata is provisioned");
+}
+
+typedef struct {
+    void *base;
+    int len;
+} variable_data_t;
+
+static variable_data_t fmp_variables_data[FMP_VARIABLES_COUNT];
+
+#define IMAGE_INFO_BUFFER_SIZE	256
+static char image_info_buffer[IMAGE_INFO_BUFFER_SIZE];
+#define IOCTL_CORSTONE1000_FMP_IMAGE_INFO	2
+
+static psa_status_t unpack_image_info(void *buffer, uint32_t size)
+{
+    typedef struct __attribute__ ((__packed__)) {
+	uint32_t variable_count;
+	uint32_t variable_size[FMP_VARIABLES_COUNT];
+	uint8_t variable[];
+    } packed_buffer_t;
+
+    packed_buffer_t *packed_buffer = buffer;
+    int runner = 0;
+
+    if (packed_buffer->variable_count != FMP_VARIABLES_COUNT) {
+	EMSG("Expected fmp varaibles = %u, but received = %u",
+		FMP_VARIABLES_COUNT, packed_buffer->variable_count);
+	return PSA_ERROR_PROGRAMMER_ERROR;
+    }
+
+    for (int i = 0; i < packed_buffer->variable_count; i++) {
+	EMSG("FMP variable %d : size %u", i, packed_buffer->variable_size[i]);
+	fmp_variables_data[i].base = &packed_buffer->variable[runner];
+	fmp_variables_data[i].len= packed_buffer->variable_size[i];
+	runner += packed_buffer->variable_size[i];
+    }
+
+    return PSA_SUCCESS;
+}
+
+static psa_status_t get_image_info(struct rpc_caller *caller,
+			   psa_handle_t platform_service_handle)
+{
+    psa_status_t status;
+    psa_handle_t handle;
+    uint32_t ioctl_id = IOCTL_CORSTONE1000_FMP_IMAGE_INFO;
+
+    struct psa_invec in_vec[] = {
+	{ .base = &ioctl_id, .len = sizeof(ioctl_id) },
+    };
+
+    struct psa_outvec out_vec[] = {
+	{ .base = image_info_buffer, .len = IMAGE_INFO_BUFFER_SIZE },
+    };
+
+    memset(image_info_buffer, 0, IMAGE_INFO_BUFFER_SIZE);
+
+    psa_call(caller, platform_service_handle, PSA_IPC_CALL,
+	     in_vec, IOVEC_LEN(in_vec), out_vec, IOVEC_LEN(out_vec));
+
+    status = unpack_image_info(image_info_buffer, IMAGE_INFO_BUFFER_SIZE);
+    if (status != PSA_SUCCESS) {
+	return status;
+    }
+
+    return PSA_SUCCESS;
+}
+
+static psa_status_t set_image_info(struct rpc_caller *caller)
+{
+    psa_status_t status;
+
+    for (int i = 0; i < FMP_VARIABLES_COUNT; i++) {
+	
+	status = protected_storage_set(caller,
+			fmp_variables_metadata[i].uid,
+			fmp_variables_data[i].len, fmp_variables_data[i].base);
+
+	if (status != PSA_SUCCESS) {
+
+            EMSG("FMP variable %d set unsuccessful", i);
+	    return status;
+	}
+
+        EMSG("FMP variable %d set success", i);
+    }
+
+    return PSA_SUCCESS;
+}
+
+void set_fmp_image_info(struct rpc_caller *caller,
+			psa_handle_t platform_service_handle)
+{
+    psa_status_t status;
+
+    status = get_image_info(caller, platform_service_handle);
+    if (status != PSA_SUCCESS) {
+	return;
+    }
+
+    status = set_image_info(caller);
+    if (status != PSA_SUCCESS) {
+	return;
+    }
+
+    return;
+}
+diff --git a/components/service/capsule_update/provider/corstone1000_fmp_service.h b/components/service/capsule_update/provider/corstone1000_fmp_service.h
+new file mode 100644
+index 000000000000..95fba2a04d5c
+--- /dev/null
+++ b/components/service/capsule_update/provider/corstone1000_fmp_service.h
+@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORSTONE1000_FMP_SERVICE_H
+#define CORSTONE1000_FMP_SERVICE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rpc_caller.h>
+#include <psa/client.h>
+
+void provision_fmp_variables_metadata(struct rpc_caller *caller);
+
+void set_fmp_image_info(struct rpc_caller *caller,
+		psa_handle_t platform_service_handle);
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif /* CORSTONE1000_FMP_SERVICE_H */
+-- 
+2.38.1
+
@@ -0,0 +1,35 @@
+From 6d3cac6f3a6e977e9330c9c06514a372ade170a2 Mon Sep 17 00:00:00 2001
+From: Emekcan <emekcan.aras@arm.com>
+Date: Wed, 2 Nov 2022 09:58:27 +0000
+Subject: [PATCH] smm_gateway: add checks for null attributes
+
+As par EDK-2 and EDK-2 test code, setVariable() with 0 
+attributes means a delete variable request. Currently, 
+smm gatway doesn't handle this scenario. This commit adds
+that support.
+
+Upstream-Status: Pending
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+---
+ components/service/smm_variable/backend/uefi_variable_store.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/components/service/smm_variable/backend/uefi_variable_store.c b/components/service/smm_variable/backend/uefi_variable_store.c
+index 6c3b9ed8..a691dc5d 100644
+--- a/components/service/smm_variable/backend/uefi_variable_store.c
+++ b/components/service/smm_variable/backend/uefi_variable_store.c
+@@ -202,9 +202,9 @@ efi_status_t uefi_variable_store_set_variable(
+ 		if (info->is_variable_set) {
+ 
+ 			/* It's a request to update to an existing variable */
+-			if (!(var->Attributes &
+			if (!(var->Attributes) || (!(var->Attributes &
+ 				(EFI_VARIABLE_APPEND_WRITE | EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS_MASK)) &&
+-				!var->DataSize) {
+				!var->DataSize)) {
+ 
+ 				/* It's a remove operation - for a remove, the variable
+ 				 * data must be removed from the storage backend before
+-- 
+2.17.1
+
@@ -0,0 +1,33 @@
+From 2aa665ad2cb13bc79b645db41686449a47593aab Mon Sep 17 00:00:00 2001
+From: Emekcan <emekcan.aras@arm.com>
+Date: Thu, 3 Nov 2022 17:43:40 +0000
+Subject: [PATCH] smm_gateway: GetNextVariableName Fix
+
+GetNextVariableName() should return EFI_BUFFER_TOO_SMALL 
+when NameSize is smaller than the actual NameSize. It 
+currently returns EFI_BUFFER_OUT_OF_RESOURCES due to setting
+max_name_len incorrectly. This fixes max_name_len error by
+replacing it with actual NameSize request by u-boot.
+
+Upstream-Status: Pending
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+---
+ .../service/smm_variable/provider/smm_variable_provider.c       | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/components/service/smm_variable/provider/smm_variable_provider.c b/components/service/smm_variable/provider/smm_variable_provider.c
+index a9679b7e..6a4b6fa7 100644
+--- a/components/service/smm_variable/provider/smm_variable_provider.c
+++ b/components/service/smm_variable/provider/smm_variable_provider.c
+@@ -197,7 +197,7 @@ static rpc_status_t get_next_variable_name_handler(void *context, struct call_re
+ 			efi_status = uefi_variable_store_get_next_variable_name(
+ 				&this_instance->variable_store,
+ 				(SMM_VARIABLE_COMMUNICATE_GET_NEXT_VARIABLE_NAME*)resp_buf->data,
+-				max_name_len,
+				((SMM_VARIABLE_COMMUNICATE_GET_NEXT_VARIABLE_NAME*)resp_buf->data)->NameSize,
+ 				&resp_buf->data_len);
+ 		}
+ 		else {
+-- 
+2.17.1
+
@@ -0,0 +1,230 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+
+From c1bcab09bb5b73e0f7131d9433f5e23c3943f007 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Sat, 11 Dec 2021 11:06:57 +0000
+Subject: [PATCH] corstone1000: port crypto config
+
+
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+%% original patch: 0002-corstone1000-port-crypto-config.patch
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ .../nspe/pal_crypto_config.h                  | 81 +++++++++++++++----
+ 1 file changed, 65 insertions(+), 16 deletions(-)
+
+diff --git a/api-tests/platform/targets/tgt_dev_apis_linux/nspe/pal_crypto_config.h b/api-tests/platform/targets/tgt_dev_apis_linux/nspe/pal_crypto_config.h
+index 218a94c69502..c6d4aadd8476 100755
+--- a/api-tests/platform/targets/tgt_dev_apis_linux/nspe/pal_crypto_config.h
+++ b/api-tests/platform/targets/tgt_dev_apis_linux/nspe/pal_crypto_config.h
+@@ -34,10 +34,14 @@
+  *
+  * Comment macros to disable the types
+  */
+#ifndef TF_M_PROFILE_SMALL
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_RSA
+ #define ARCH_TEST_RSA_1024
+ #define ARCH_TEST_RSA_2048
+ #define ARCH_TEST_RSA_3072
+#endif
+#endif
+ 
+ /**
+  * \def  ARCH_TEST_ECC
+@@ -50,11 +54,17 @@
+  * Requires: ARCH_TEST_ECC
+  * Comment macros to disable the curve
+  */
+#ifndef TF_M_PROFILE_SMALL
+ #define ARCH_TEST_ECC
+ #define ARCH_TEST_ECC_CURVE_SECP192R1
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_ECC_CURVE_SECP224R1
+#endif
+ #define ARCH_TEST_ECC_CURVE_SECP256R1
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_ECC_CURVE_SECP384R1
+#endif
+#endif
+ 
+ /**
+  * \def ARCH_TEST_AES
+@@ -78,10 +88,10 @@
+  *
+  * Comment macros to disable the types
+  */
+-#define ARCH_TEST_DES
+-#define ARCH_TEST_DES_1KEY
+-#define ARCH_TEST_DES_2KEY
+-#define ARCH_TEST_DES_3KEY
+//#define ARCH_TEST_DES
+//#define ARCH_TEST_DES_1KEY
+//#define ARCH_TEST_DES_2KEY
+//#define ARCH_TEST_DES_3KEY
+ 
+ /**
+  * \def  ARCH_TEST_RAW
+@@ -104,7 +114,7 @@
+  *
+  * Enable the ARC4 key type.
+  */
+-#define ARCH_TEST_ARC4
+//#define ARCH_TEST_ARC4
+ 
+ /**
+  * \def ARCH_TEST_CIPHER_MODE_CTR
+@@ -113,7 +123,11 @@
+  *
+  * Requires: ARCH_TEST_CIPHER
+  */
+#ifndef TF_M_PROFILE_SMALL
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_CIPHER_MODE_CTR
+#endif
+#endif
+ 
+ /**
+  * \def ARCH_TEST_CIPHER_MODE_CFB
+@@ -138,7 +152,11 @@
+  *
+  * Requires: ARCH_TEST_CIPHER, ARCH_TEST_AES, ARCH_TEST_CIPHER_MODE_CTR
+  */
+#ifndef TF_M_PROFILE_SMALL
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_CTR_AES
+#endif
+#endif
+ 
+ /**
+  * \def ARCH_TEST_CBC_AES
+@@ -157,7 +175,11 @@
+  *
+  * Comment macros to disable the types
+  */
+#ifndef TF_M_PROFILE_SMALL
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_CBC_NO_PADDING
+#endif
+#endif
+ 
+ /**
+  * \def ARCH_TEST_CFB_AES
+@@ -177,11 +199,15 @@
+  *
+  * Comment macros to disable the types
+  */
+#ifndef TF_M_PROFILE_SMALL
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_PKCS1V15
+ #define ARCH_TEST_RSA_PKCS1V15_SIGN
+ #define ARCH_TEST_RSA_PKCS1V15_SIGN_RAW
+ #define ARCH_TEST_RSA_PKCS1V15_CRYPT
+ #define ARCH_TEST_RSA_OAEP
+#endif
+#endif
+ 
+ /**
+  * \def ARCH_TEST_CBC_PKCS7
+@@ -190,7 +216,11 @@
+  *
+  * Comment macros to disable the types
+  */
+#ifndef TF_M_PROFILE_SMALL
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_CBC_PKCS7
+#endif
+#endif
+ 
+ /**
+  * \def ARCH_TEST_ASYMMETRIC_ENCRYPTION
+@@ -227,21 +257,27 @@
+  *
+  * Comment macros to disable the types
+  */
+-// #define ARCH_TEST_MD2
+-// #define ARCH_TEST_MD4
+-#define ARCH_TEST_MD5
+-#define ARCH_TEST_RIPEMD160
+-#define ARCH_TEST_SHA1
+//#define ARCH_TEST_MD2
+//#define ARCH_TEST_MD4
+//#define ARCH_TEST_MD5
+//#define ARCH_TEST_RIPEMD160
+//#define ARCH_TEST_SHA1
+#ifndef TF_M_PROFILE_SMALL
+ #define ARCH_TEST_SHA224
+#endif
+ #define ARCH_TEST_SHA256
+#ifndef TF_M_PROFILE_SMALL
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_SHA384
+ #define ARCH_TEST_SHA512
+-// #define ARCH_TEST_SHA512_224
+-// #define ARCH_TEST_SHA512_256
+-// #define ARCH_TEST_SHA3_224
+-// #define ARCH_TEST_SHA3_256
+-// #define ARCH_TEST_SHA3_384
+-// #define ARCH_TEST_SHA3_512
+#endif
+#endif
+//#define ARCH_TEST_SHA512_224
+//#define ARCH_TEST_SHA512_256
+//#define ARCH_TEST_SHA3_224
+//#define ARCH_TEST_SHA3_256
+//#define ARCH_TEST_SHA3_384
+//#define ARCH_TEST_SHA3_512
+ 
+ /**
+  * \def ARCH_TEST_HKDF
+@@ -270,7 +306,12 @@
+  *
+  * Comment macros to disable the types
+  */
+#ifndef TF_M_PROFILE_SMALL
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_CMAC
+#endif
+#endif
+//#define ARCH_TEST_GMAC
+ #define ARCH_TEST_HMAC
+ 
+ /**
+@@ -290,7 +331,11 @@
+  * Requires: ARCH_TEST_AES
+  *
+  */
+#ifndef TF_M_PROFILE_SMALL
+#ifndef TF_M_PROFILE_MEDIUM
+ #define ARCH_TEST_GCM
+#endif
+#endif
+ 
+ /**
+  * \def ARCH_TEST_TRUNCATED_MAC
+@@ -309,7 +354,9 @@
+  *
+  * Requires: ARCH_TEST_ECC
+  */
+#ifndef TF_M_PROFILE_SMALL
+ #define ARCH_TEST_ECDH
+#endif
+ 
+ /**
+  * \def ARCH_TEST_ECDSA
+@@ -317,7 +364,9 @@
+  * Enable the elliptic curve DSA library.
+  * Requires: ARCH_TEST_ECC
+  */
+#ifndef TF_M_PROFILE_SMALL
+ #define ARCH_TEST_ECDSA
+#endif
+ 
+ /**
+  * \def ARCH_TEST_DETERMINISTIC_ECDSA
+-- 
+2.38.0
+
@@ -0,0 +1,10 @@
+MACHINE_TS_REQUIRE ?= ""
+MACHINE_TS_REQUIRE:corstone1000 = "ts-corstone1000.inc"
+
+require ${MACHINE_TS_REQUIRE}
+
+
+EXTRA_OECMAKE:append:corstone1000 = "-DMM_COMM_BUFFER_ADDRESS=0x02000000 \
+                                    -DMM_COMM_BUFFER_PAGE_COUNT=1 \
+                                    "
+
@@ -1,28 +1,26 @@
 FILESEXTRAPATHS:prepend := "${THISDIR}/corstone1000:"

-SRC_URI:append = " \
-    file://0001-Add-openamp-to-SE-proxy-deployment.patch \
-    file://0002-Implement-mhu-driver-and-the-OpenAmp-conversion-laye.patch \
-    file://0003-Add-openamp-rpc-caller.patch \
-    file://0004-add-psa-client-definitions-for-ff-m.patch \
-    file://0005-Add-common-service-component-to-ipc-support.patch \
-    file://0006-Add-secure-storage-ipc-backend.patch \
-    file://0007-Use-secure-storage-ipc-and-openamp-for-se_proxy.patch \
-    file://0008-Run-psa-arch-test.patch \
-    file://0009-Use-address-instead-of-pointers.patch \
-    file://0010-Add-psa-ipc-attestation-to-se-proxy.patch \
-    file://0011-Setup-its-backend-as-openamp-rpc-using-secure-storag.patch \
-    file://0012-add-psa-ipc-crypto-backend.patch \
-    file://0013-Add-stub-capsule-update-service-components.patch \
-    file://0014-Configure-storage-size.patch \
-    file://0015-Fix-Crypto-interface-structure-aligned-with-tf-m-cha.patch \
-    file://0016-Integrate-remaining-psa-ipc-client-APIs.patch \
-    file://0017-Fix-update-psa_set_key_usage_flags-definition-to-the.patch \
-    file://0018-Fixes-in-AEAD-for-psa-arch-test-54-and-58.patch \
-    file://0019-plat-corstone1000-change-default-smm-values.patch \
-    "
-
-
-EXTRA_OECMAKE:append = "-DMM_COMM_BUFFER_ADDRESS="0x00000000 0x02000000" \
-    -DMM_COMM_BUFFER_PAGE_COUNT="1" \
+SRC_URI:append:corstone1000  = " \
+    file://0001-Add-openamp-to-SE-proxy-deployment.patch;patchdir=../trusted-services \
+    file://0002-Implement-mhu-driver-and-the-OpenAmp-conversion-laye.patch;patchdir=../trusted-services \
+    file://0003-Add-openamp-rpc-caller.patch;patchdir=../trusted-services \
+    file://0004-add-psa-client-definitions-for-ff-m.patch;patchdir=../trusted-services \
+    file://0005-Add-common-service-component-to-ipc-support.patch;patchdir=../trusted-services \
+    file://0006-Add-secure-storage-ipc-backend.patch;patchdir=../trusted-services \
+    file://0007-Use-secure-storage-ipc-and-openamp-for-se_proxy.patch;patchdir=../trusted-services \
+    file://0008-Run-psa-arch-test.patch;patchdir=../trusted-services \
+    file://0009-Use-address-instead-of-pointers.patch;patchdir=../trusted-services \
+    file://0010-Add-psa-ipc-attestation-to-se-proxy.patch;patchdir=../trusted-services \
+    file://0011-Setup-its-backend-as-openamp-rpc-using-secure-storag.patch;patchdir=../trusted-services;patchdir=../trusted-services \
+    file://0012-add-psa-ipc-crypto-backend.patch;patchdir=../trusted-services \
+    file://0013-Add-stub-capsule-update-service-components.patch;patchdir=../trusted-services \
+    file://0014-Configure-storage-size.patch;patchdir=../trusted-services \
+    file://0015-Fix-Crypto-interface-structure-aligned-with-tf-m-cha.patch;patchdir=../trusted-services;patchdir=../trusted-services \
+    file://0016-Integrate-remaining-psa-ipc-client-APIs.patch;patchdir=../trusted-services \
+    file://0017-Fix-update-psa_set_key_usage_flags-definition-to-the.patch;patchdir=../trusted-services;patchdir=../trusted-services \
+    file://0018-Fixes-in-AEAD-for-psa-arch-test-54-and-58.patch;patchdir=../trusted-services \
+    file://0019-plat-corstone1000-change-default-smm-values.patch;patchdir=../trusted-services \
+    file://0020-FMP-Support-in-Corstone1000.patch;patchdir=../trusted-services \
+    file://0021-smm_gateway-add-checks-for-null-attributes.patch;patchdir=../trusted-services \
+    file://0022-GetNextVariableName-Fix.patch;patchdir=../trusted-services \
    "
@@ -0,0 +1,7 @@
+FILESEXTRAPATHS:prepend := "${THISDIR}/corstone1000/psa-apitest:"
+
+include ts-corstone1000.inc
+
+SRC_URI:append:corstone1000  = " \
+    file://0001-corstone1000-port-crypto-config.patch;patchdir=../psatest \
+    "
@@ -0,0 +1 @@
+require ts-psa-api-test.inc
@@ -0,0 +1 @@
+require ts-psa-api-test.inc
@@ -0,0 +1 @@
+require ts-psa-api-test.inc
@@ -0,0 +1 @@
+require ts-psa-api-test.inc
@@ -2,3 +2,8 @@ MACHINE_TS_REQUIRE ?= ""
 MACHINE_TS_REQUIRE:corstone1000 = "ts-corstone1000.inc"

 require ${MACHINE_TS_REQUIRE}
+
+EXTRA_OECMAKE:append:corstone1000 = " -DMM_COMM_BUFFER_ADDRESS="0x00000000 0x02000000" \
+    -DMM_COMM_BUFFER_PAGE_COUNT="1" \
+    "
+
@@ -2,3 +2,8 @@ MACHINE_TS_REQUIRE ?= ""
 MACHINE_TS_REQUIRE:corstone1000 = "ts-corstone1000.inc"

 require ${MACHINE_TS_REQUIRE}
+
+EXTRA_OECMAKE:append:corstone1000 = " -DMM_COMM_BUFFER_ADDRESS="0x00000000 0x02000000" \
+    -DMM_COMM_BUFFER_PAGE_COUNT="1" \
+    "
+
@@ -10,6 +10,7 @@ Fixes
 noreturn void panic(const char *fmt, ...);
 ^

+Upstream-Status: Pending
 Signed-off-by: Khem Raj <raj.khem@gmail.com>

 ---
@@ -1,4 +1,4 @@
-FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:"
+FILESEXTRAPATHS:prepend := "${ARMFILESPATHS}"

 # Enable ARM-FFA transport
 SRC_URI:append = " \
@@ -0,0 +1,34 @@
+Take a patch from linux-yocto to fix buildpaths in perf's python module.
+
+Upstream-Status: Pending
+Signed-off-by: Ross Burton <ross.burton@arm.com>
+
+From b8cd0e429bf75b673c438a8277d4bc74327df992 Mon Sep 17 00:00:00 2001
+From: Tom Zanussi <tom.zanussi@intel.com>
+Date: Tue, 3 Jul 2012 13:07:23 -0500
+Subject: [PATCH] perf: change --root to --prefix for python install
+
+Otherwise we get the sysroot path appended to the build path, not what
+we want.
+
+Signed-off-by: Tom Zanussi <tom.zanussi@intel.com>
+---
+ tools/perf/Makefile.perf | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf
+index 8f738e11356d..ee945d8e3996 100644
+--- a/tools/perf/Makefile.perf
+++ b/tools/perf/Makefile.perf
+@@ -1022,7 +1022,7 @@ install-bin: install-tools install-tests install-traceevent-plugins
+ install: install-bin try-install-man
+ 
+ install-python_ext:
+-	$(PYTHON_WORD) util/setup.py --quiet install --root='/$(DESTDIR_SQ)'
+	$(PYTHON_WORD) util/setup.py --quiet install --prefix='$(DESTDIR_SQ)/usr'
+ 
+ # 'make install-doc' should call 'make -C Documentation install'
+ $(INSTALL_DOC_TARGETS):
+-- 
+2.34.1
+
@@ -8,6 +8,7 @@ SRC_URI = " \
    git://android.googlesource.com/kernel/common.git;protocol=https;branch=android13-5.15-lts \
    file://0001-lib-build_OID_registry-fix-reproducibility-issues.patch \
    file://0002-vt-conmakehash-improve-reproducibility.patch \
+    file://0001-perf-change-root-to-prefix-for-python-install.patch \
    "

 # tag: ASB-2022-05-05_13-5.15-93-ge8b3f31d7a60
@@ -1,4 +1,4 @@
-ARMFILESPATHS := "${THISDIR}/${PN}:"
+ARMFILESPATHS := "${THISDIR}/files:"

 COMPATIBLE_MACHINE:generic-arm64 = "generic-arm64"
 FILESEXTRAPATHS:prepend:generic-arm64 = "${ARMFILESPATHS}"
@@ -18,11 +18,9 @@ EXTRA_OECMAKE += "\
                  -DPSA_ARCH_TESTS_SOURCE_DIR=${WORKDIR}/git/psatest \
                 "

-# TS ships patches that need to be applied to psa-arch-tests
+# TS check if there are patches to apply to psa-arch-tests, if so apply them
 apply_ts_patch() {
-    for p in ${S}/external/psa_arch_tests/*.patch; do
-        patch -p1 -d ${WORKDIR}/git/psatest < ${p}
-    done
+    find ${S}/external/psa_arch_tests -type f -name '*.patch' -exec patch -p1 -d ${WORKDIR}/git/psatest -i {} \;
 }
 do_patch[postfuncs] += "apply_ts_patch"
Author	SHA1	Message	Date
Vishnu Banavath	ff9b6f29bf	arm-bsp/documentation: corstone1000: 2022.11.10 RC: update the change log Aligning the change log with the latest Corstone1000 SW updates. Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-10 11:07:20 -05:00
Vishnu Banavath	00ceaafc72	arm-bsp/documentation: corstone1000: 2022.11.10 RC: update the release notes Aligning the release notes with the latest Corstone1000 SW updates. Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-10 11:07:20 -05:00
Abdellatif El Khlifi	8185ca9c20	arm-bsp/documentation: corstone1000: 2022.11.10 RC: update the user guide Aligning the user guide with the latest Corstone1000 SW updates. Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-10 11:07:20 -05:00
Luca Fancellu	387f32242e	arm,arm-bsp/recipes-kernel: don't use PN in arm-ffa-transport.inc There are some cases where PN is not expanded into linux-yocto in the arm-ffa-transport.inc file required from linux-yocto_%.bbappend, because of the := usage, in those cases PN gets "defaultpkgname". To fix the issue, rename "linux-yocto" folder into "files" and adjust ARMFILESPATHS to point to that in linux-yocto_%.bbappend, prepend ARMFILESPATHS to FILESEXTRAPATHS in arm-ffa-transport.inc. Remove ARMFILESPATHS prepend from FILESEXTRAPATHS for corstone1000 in meta-arm-bsp, because the platform has always the "arm-ffa" in MACHINE_FEATURES, which causes ARMFILESPATHS to be prepended. While there, remove the FILESEXTRAPATHS prepend of ARMFILESPATHS for the n1sdp that will be added by arm-ffa-transport.inc only when needed. Signed-off-by: Luca Fancellu <luca.fancellu@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-08 08:18:55 -05:00
Ross Burton	dd5a968d3d	arm/linux-arm64-ack: fix buildpaths in the perf Python module Use --prefix instead of --root when installing the Python modules to ensure that build paths are not embedded in the compiled .pyc files. Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-07 14:05:39 -05:00
Anton Antonov	99e1bf8229	arm-bsp/fvp-base: Enable virtio-rng support and unset preferred 5.15 kernel Without virtio-rng enabled kernel 5.19 takes ages to finish random number generator initialisation which causes issues with ssh and other crypto related services. Signed-off-by: Anton Antonov <Anton.Antonov@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-07 11:00:12 -05:00
Emekcan	a41572a032	arm-bsp/trusted-services: Fix GetNextVariable max_name_len in smm gateway GetNextVariableName() should return EFI_BUFFER_TOO_SMALL when NameSize is smaller than the actual NameSize. It currently returns EFI_BUFFER_OUT_OF_RESOURCES due to setting max_name_len incorrectly. This fixes max_name_len error by replacing it with actual NameSize request by u-boot. Signed-off-by: Emekcan Aras <emekcan.aras@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-07 07:45:38 -05:00
Emekcan	5fd87e47f6	arm-bsp/trusted-services: add checks for null attributes in smm gateway As in EDK-2 and EDK-2 test code, setVariable() with 0 attributes means a delete variable requiest. Currently, smm gateway doesn't handle this scenario. This commit adds that support Signed-off-by: Emekcan Aras <emekcan.aras@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-07 07:45:38 -05:00
Rui Miguel Silva	8d35c5b539	arm-bsp/trusted-firmware-m: adjust ps assets for corstone1000 Enabling ESRT in trusted services increased the need for more assets at protected storage level, since we now save FMP data , capsule update, like Image Info as non volatile EFI variables. So, just change the default configuration for the corstone1000 to handle this. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-07 07:45:34 -05:00
Rui Miguel Silva	9e2de7dacc	arm-bsp/trusted-services: psa test setup corstone1000 Reorder patch list headers, move psa api test patch that should be applied to all psa api test from a crypto specific directory to a more generic "psa-apitest" directory. Create a inc file for the psa api test to make sure all out of tree patches from trusted services are applied to all test source directories, and move mm communicator buffer details to each SP, and finally set it up differently as it should/is expected to be at libts. With this setup all psa-api test for crypto and attestation passed. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-07 07:45:34 -05:00
Rui Miguel Silva	3651527f57	arm/trusted-services: check before applying patches At the apply ts patch stage, first check if they are patches to be applied. Because if not, this would break the apply patch stage with an error. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-11-07 07:45:34 -05:00
Ross Burton	4ee457693e	CI: track meta-openembedded's langdale branch Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-28 12:00:11 -04:00
Abdellatif El Khlifi	46e8092b6b	kas: corstone1000: set branches to langdale point poky/meta-openembedded to langdale Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-28 12:00:08 -04:00
Mohamed Omar Asaker	f312adf47b	arm-bsp/corstone1000: add msd configs for fvp Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-27 07:00:09 -04:00
Jon Mason	d3541b1e29	CI: Remove host bitbake variables Bitbake variables were being set in KAS for the unique Gitlab CI configuration being used internally. While this should not have been significantly detrimental for other setups, this shouldn't be necessary with proper runner setup. Removing them here to all for a more generic CI experience. Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 13:33:55 -04:00
Satish Kumar	952dee0de9	arm-bsp/trusted-service: corstone1000: esrt support Signed-off-by: Satish Kumar <satish.kumar01@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 13:33:55 -04:00
Mohamed Omar Asaker	9e17830b84	arm-bsp/trusted-firmware-m: corstone1000 support FMP image info Apply tfm patches to support FMP image info Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 13:33:55 -04:00
Mohamed Omar Asaker	bb02720fd7	Revert "arm-bsp/trusted-firmware-m: corstone1000: bump tfm SHA" This reverts commit `81181ed898`. Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 13:33:55 -04:00
Mohamed Omar Asaker	b4dfea8e28	Revert "arm-bsp/trusted-firmware-m: corstone1000: secure debug code checkout from yocto" This reverts commit `37ba0b162a`. Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 13:33:55 -04:00
Rui Miguel Silva	e4a5809373	arm-bsp/corstone1000: apply ts patch to psa crypto api test Apply shared patch to trusted services that is used to compile psa crypto api tests to include change in packed-c request message in the eaed update structure to be in sync with the serialize/deserialize in TS side. As at it, move the other corstone1000 specific patch file to meta-arm-bsp where it should be. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 13:33:55 -04:00
Ross Burton	72f0580f70	CI: add documentation job This job builds all of the Sphinx documentation it can find with fatal warnings enabled. Signed-off-by: Ross Burton <ross.burton@arm.com>	2022-10-24 12:02:01 -04:00
Vishnu Banavath	950372e99d	meta-arm-bsp/doc: add readthedocs for corstone1000 These changes are to add support for readthedocs for corstone1000 platform. readthedocs server traces any changes to to corstone1000 documents and will trigger a build which will generate html file which can will be rendered by corstone1000.docs.arm.com server Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 12:02:01 -04:00
Vishnu Banavath	0a7c6ae7e1	runfvp: corstone1000: add mmc card configuration These changes are to pass appropriate MMC card configuration to corstone1000 FVP. Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 12:02:01 -04:00
Ross Burton	bd01053121	arm-bsp/linux-arm64-ack: fix malformed Upstream-Status tag Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 12:02:01 -04:00
Ross Burton	062aef06c7	arm-bsp/hafnium: add missing Upstream-Status Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 12:02:01 -04:00
Ross Burton	0245e6609c	arm/hafnium: add missing Upstream-Status Signed-off-by: Ross Burton <ross.burton@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 12:02:01 -04:00
Rui Miguel Silva	a42ee82eda	arm/trusted-services: port crypto config Port crypto config to psa arch test api suite.This needs to move to arm-bsp since is corstone1000 specific configuration Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 12:02:01 -04:00
Mohamed Omar Asaker	be90d2e4b0	arm-bsp/u-boot: corstone1000: support 32bit ffa direct messaging Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-24 12:02:01 -04:00
Jon Mason	1935f51d0f	CI: fix to langdale Signed-off-by: Jon Mason <jon.mason@arm.com>	2022-10-19 14:30:01 -04:00