CI: only run pending-updates on master

This job takes a few minutes and isn't useful unless it's being ran for
master, or is being actively worked on.

Signed-off-by: Ross Burton <ross.burton@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>

.gitlab-ci.yml

@@ -1,4 +1,4 @@
-image: ${MIRROR_GHCR}/siemens/kas/kas:4.7
+image: ${MIRROR_GHCR}/siemens/kas/kas:4.4
 
 variables:
   # These are needed as the k8s executor doesn't respect the container
@@ -76,8 +76,7 @@ stages:
 
   artifacts:
     name: "logs"
-    when: on_failure
-    expire_in: 1 week
+    when: always
     paths:
       - $KAS_BUILD_DIR/tmp*/work*/**/temp/log.do_*.*
       - $KAS_BUILD_DIR/tmp*/work*/**/testimage/*
@@ -126,7 +125,7 @@ update-repos:
 #
 # Available options for building are (VIRT _must_ be last for ssh override)
 #  DISTRO: [poky, poky-altcfg, poky-tiny]
-#  KERNEL: [linux-yocto, linux-yocto-dev]
+#  KERNEL: [linux-yocto, linux-yocto-dev, linux-yocto-rt]
 #  TOOLCHAINS: [gcc, clang]
 #  TCLIBC: [glibc, musl]
 #  FIRMWARE: [u-boot, edk2]
@@ -271,11 +270,14 @@ qemuarm64-secureboot:
   extends: .build
   parallel:
     matrix:
-      - TOOLCHAINS: [gcc, clang]
+      - KERNEL: [linux-yocto, linux-yocto-rt]
+        TOOLCHAINS: [gcc, clang]
         TCLIBC: [glibc, musl]
         TS: [none, qemuarm64-secureboot-ts]
         TESTING: testimage
-      - UEFISB: [none, uefi-secureboot]
+      - TOOLCHAINS: [gcc, clang]
+        TS: [none, qemuarm64-secureboot-ts]
+        UEFISB: [none, uefi-secureboot]
         TESTING: testimage
       - KERNEL: linux-yocto-dev
         TESTING: testimage
@@ -284,15 +286,23 @@ qemuarm64:
   extends: .build
   parallel:
     matrix:
+      - DISTRO: poky
+        KERNEL: [linux-yocto, linux-yocto-rt]
+        TOOLCHAINS: [gcc, clang]
+        FIRMWARE: [u-boot, edk2]
+        TESTING: testimage
       - DISTRO: poky-tiny
         TESTING: testimage
       - VIRT: xen
+      - KERNEL: linux-yocto-dev
+        TESTING: testimage
 
 qemuarm-secureboot:
   extends: .build
   parallel:
     matrix:
-      - TOOLCHAINS: [gcc, clang]
+      - KERNEL: [linux-yocto, linux-yocto-rt]
+        TOOLCHAINS: [gcc, clang]
         TCLIBC: [glibc, musl]
         TESTING: testimage
       - DISTRO: [poky, poky-altcfg]
@@ -304,19 +314,23 @@ qemuarm:
   extends: .build
   parallel:
     matrix:
-      - TOOLCHAINS: [gcc, clang]
-        FIRMWARE: edk2
+      - DISTRO: poky
+        KERNEL: [linux-yocto, linux-yocto-rt]
+        TOOLCHAINS: [gcc, clang]
+        FIRMWARE: [u-boot, edk2]
         TESTING: testimage
       - DISTRO: poky-tiny
         TESTING: testimage
       - VIRT: xen
+      - KERNEL: linux-yocto-dev
+        TESTING: testimage
 
 qemuarmv5:
   extends: .build
   parallel:
     matrix:
       - DISTRO: poky
-        KERNEL: [linux-yocto, linux-yocto-dev]
+        KERNEL: [linux-yocto, linux-yocto-dev, linux-yocto-rt]
         TESTING: testimage
       - DISTRO: poky-tiny
         TESTING: testimage
@@ -325,7 +339,8 @@ sbsa-ref:
   extends: .build
   parallel:
     matrix:
-      - TOOLCHAINS: [gcc, clang]
+      - KERNEL: [linux-yocto, linux-yocto-rt]
+        TOOLCHAINS: [gcc, clang]
         TESTING: testimage
       - DISTRO: poky-altcfg
         TESTING: testimage

ci/base.yml

@@ -7,31 +7,21 @@ distro: poky
 
 defaults:
   repos:
-    branch: whinlatter
+    branch: walnascar
 
 repos:
-  bitbake:
-    url: https://git.openembedded.org/bitbake
-    branch: "2.16"
-    layers:
-      bitbake: disabled
-
-  core:
-    url: https://git.openembedded.org/openembedded-core
-    layers:
-      meta:
-
-  meta-yocto:
-    url: https://git.yoctoproject.org/meta-yocto
-    layers:
-      meta-poky:
-
   meta-arm:
     layers:
       meta-arm:
       meta-arm-bsp:
       meta-arm-toolchain:
 
+  poky:
+    url: https://git.yoctoproject.org/poky
+    layers:
+      meta:
+      meta-poky:
+
 env:
   BB_LOGCONFIG: ""
   TOOLCHAIN_DIR: ""
@@ -40,9 +30,13 @@ local_conf_header:
   base: |
     CONF_VERSION = "2"
     BB_SERVER_TIMEOUT = "300"
+  setup: |
+    PACKAGE_CLASSES = "package_ipk"
+    PACKAGECONFIG:remove:pn-qemu-system-native = "gtk+ sdl"
+    PACKAGECONFIG:append:pn-perf = " coresight"
     INHERIT += "rm_work"
   extrapackages: |
-    CORE_IMAGE_EXTRA_INSTALL += "perf"
+    CORE_IMAGE_EXTRA_INSTALL += "perf opencsd"
     CORE_IMAGE_EXTRA_INSTALL:append:aarch64 = " gator-daemon"
 
 machine: unset

ci/clang.yml

@@ -3,6 +3,10 @@
 header:
   version: 14
 
+repos:
+  meta-clang:
+    url: https://github.com/kraj/meta-clang
+
 local_conf_header:
   toolchain: |
-    PREFERRED_TOOLCHAIN_TARGET = "clang"
+    TOOLCHAIN = "clang"

ci/fvp-base-ts.yml

@@ -5,24 +5,23 @@ header:
   includes:
     - ci/fvp-base.yml
     - ci/meta-openembedded.yml
+    - ci/testimage.yml
 
 local_conf_header:
   trusted_services: |
     # Enable the needed test suites
-    TEST_SUITES:append = " trusted_services"
+    TEST_SUITES = " ping ssh trusted_services"
     # Include all Secure Partitions into the image
     MACHINE_FEATURES:append = " arm-ffa ts-crypto ts-storage ts-its"
     MACHINE_FEATURES:append = " ts-attestation ts-smm-gateway optee-spmc-test"
-    MACHINE_FEATURES:append = " ts-block-storage ts-fwu ts-logging"
-    MACHINE_FEATURES:append = " arm-branch-protection"
-    SMMGW_AUTH_VAR = "1"
+    MACHINE_FEATURES:append = " ts-block-storage ts-fwu"
     # Include TS demo/test tools into image
     IMAGE_INSTALL:append = " packagegroup-ts-tests"
     # Include TS PSA Arch tests into image
     IMAGE_INSTALL:append = " packagegroup-ts-tests-psa"
     CORE_IMAGE_EXTRA_INSTALL += "optee-test"
     # Set the TS environment
-    TS_ENV = "sp"
+    TS_ENV="sp"
     # Enable and configure semihosting
     FVP_CONFIG[cluster0.cpu0.semihosting-cwd] = "${DEPLOY_DIR_IMAGE}"
     FVP_CONFIG[cluster0.cpu1.semihosting-cwd] = "${DEPLOY_DIR_IMAGE}"

ci/fvp.yml

@@ -7,6 +7,3 @@ local_conf_header:
   testimagefvp: |
     LICENSE_FLAGS_ACCEPTED += "Arm-FVP-EULA"
     IMAGE_CLASSES += "fvpboot"
-  networking_failing_tests: |
-    # These tests currently fail as the wrong IP for the build host is used
-    TEST_SUITES:remove = "opkg dnf"

ci/gcc.yml

@@ -3,7 +3,7 @@
 header:
   version: 14
 
-#NOTE: This is the default.  This is only being added for completeness/clarity
+#NOTE: This is the default for poky.  This is only being added for completeness/clarity
 local_conf_header:
   toolchain: |
-    PREFERRED_TOOLCHAIN_TARGET = "gcc"
+    TOOLCHAIN = "gcc"

ci/genericarm64.yml

@@ -6,7 +6,7 @@ header:
     - ci/base.yml
 
 repos:
-  meta-yocto:
+  poky:
     layers:
       meta-yocto-bsp:
 

ci/qemuarm64-secureboot.yml

@@ -9,7 +9,6 @@ machine: qemuarm64-secureboot
 
 target:
   - core-image-base
-  - hafnium
 
 local_conf_header:
   optee: |

ci/selftest.yml

@@ -7,4 +7,3 @@ local_conf_header:
   setup: |
     BB_LOGCONFIG = ""
     SANITY_TESTED_DISTROS = ""
-    INHERIT:remove = "rm_work"

ci/sstate-mirror.yml

@@ -6,6 +6,6 @@ header:
 local_conf_header:
   sstate_mirror: |
     BB_HASHSERVE_UPSTREAM = "wss://hashserv.yoctoproject.org/ws"
-    SSTATE_MIRRORS = "file://.* http://sstate.yoctoproject.org/all/PATH;downloadfilename=PATH"
+    SSTATE_MIRRORS = "file://.* http://cdn.jsdelivr.net/yocto/sstate/all/PATH;downloadfilename=PATH"
     BB_HASHSERVE = "auto"
     BB_SIGNATURE_HANDLER = "OEEquivHash"

ci/testimage.yml

@@ -17,3 +17,5 @@ local_conf_header:
     IMAGE_FEATURES += "ssh-server-dropbear"
   sshkeys: |
     CORE_IMAGE_EXTRA_INSTALL += "ssh-pregen-hostkeys"
+  universally_failing_tests: |
+    TEST_SUITES:remove = "opkg"

ci/update-repos

@@ -23,6 +23,7 @@ repositories = (
     "https://git.yoctoproject.org/poky",
     "https://git.openembedded.org/meta-openembedded",
     "https://git.yoctoproject.org/meta-virtualization",
+    "https://github.com/kraj/meta-clang",
 )
 
 if __name__ == "__main__":

documentation/runfvp.md

@@ -59,16 +59,6 @@ There are recipes for common FVPs in meta-arm already, and writing new recipes i
 
 If `FVP_PROVIDER` is not set then it is assumed that `FVP_EXE` is installed on the host already.
 
-### `FVP_BINDIR`
-
-Optional parameter to configure the path of the FVP binary. For example, `fvp-base` uses path from the build host by default. This path can be customized by configuring like below.
-
-```
-FVP_BINDIR ?= "utilities/fvp/usr/bin"
-```
-
-Potential use case for this parameter configuration is to execute `runfvp` script without the need for bitbake environment initialization.
-
 ### `FVP_CONFIG`
 
 Parameters passed to the FVP with the `--parameter`/`-C` option.  These are expressed as variable flags so individual parameters can be altered easily. For example:

documentation/trusted-services.md

@@ -24,7 +24,6 @@ features for each [Secure Partition][^2] you would like to include:
 | se-proxy          | ts-se-proxy     |
 | smm-gateway       | ts-smm-gateway  |
 | spm-test[1-4]     | optee-spmc-test |
-| Logging           | ts-logging      |
 
 Other steps depend on your machine/platform definition:
 
@@ -58,18 +57,6 @@ Optionally for testing purposes you can add `packagegroup-ts-tests` into your im
   meta-arm also includes Trusted Service OEQA tests which can be used for automated testing.
 See `ci/trusted-services.yml` for an example how to include them into an image.
 
-## Configuration options
-
-Some TS recipes support yocto variables to set build configuration. These variables can be set in .conf files (machine
-specific or local.conf), or .bbappend files. 
-
-SmmGW SP recipe supports the following configuration variables
-
-| Variable name         | Type | Description                                                                                            |
-|-----------------------|------|--------------------------------------------------------------------------------------------------------|
-| SMMGW_AUTH_VAR        | Bool | Enable Authenticated variable support                                                                  |
-| SMMGW_INTERNAL_CRYPTO | Bool | Use MbedTLS build into SmmGW for authentication related crypto operations. Depends on SMMGW_AUTH_VAR=1 |
-
 
 ------
 [^1]: https://trusted-services.readthedocs.io/en/integration/overview/index.html

kas/corstone1000-a320.yml

@@ -1,19 +0,0 @@
-# yaml-language-server: $schema=https://raw.githubusercontent.com/siemens/kas/master/kas/schema-kas.json
-
-header:
-  version: 14
-
-local_conf_header:
-  a320: |
-    MACHINE_FEATURES += "cortexa320"
-    OVERRIDES .= ":cortexa320"
-
-repos:
-  meta-ethos:
-    url: https://gitlab.arm.com/iot/meta-ethos.git
-    branch: whinlatter
-    commit: b919565c36b89af2ba61cc28024da633a9fae0da
-  meta-sca:
-    url: https://github.com/priv-kweihmann/meta-sca.git
-    branch: master
-    commit: e68f1a9d17553a2a1b5b20962749f90482112a3f

kas/corstone1000-base.yml

@@ -5,36 +5,25 @@ distro: poky
 
 defaults:
   repos:
-    branch: master
+    branch: walnascar
 
 repos:
-  bitbake:
-    url: https://git.openembedded.org/bitbake
-    commit: 0dde1a3ff852be057be40d17f233ecca19e7b389
-    layers:
-      bitbake: disabled
-
-  core:
-    url: https://git.openembedded.org/openembedded-core
-    commit: 4bd920ad7d7279020ea6e561d0584ae70f33f751
-    layers:
-      meta:
-
-  meta-yocto:
-    url: https://git.yoctoproject.org/meta-yocto
-    commit: b3b659263566c4d2f2813190e72d93f8598a4c47
-    layers:
-      meta-poky:
-
   meta-arm:
     layers:
       meta-arm:
       meta-arm-bsp:
       meta-arm-toolchain:
 
+  poky:
+    url: https://git.yoctoproject.org/git/poky
+    commit: ee0d8d8a61d8e22a3dd00c32cde58ee6e8ec458f
+    layers:
+      meta:
+      meta-poky:
+
   meta-openembedded:
     url: https://git.openembedded.org/meta-openembedded
-    commit: fc0152e434307b98e1d16251f92ed81ac617c1db
+    commit: 2169c9afcc0945045bea49f58011080942d4ddb4
     layers:
       meta-oe:
       meta-python:
@@ -42,7 +31,7 @@ repos:
 
   meta-secure-core:
     url: https://github.com/wind-river/meta-secure-core.git
-    commit: 63209fb1500cee88d5d4d74669bce4b613c03ff7
+    commit: 423bc85b050594cc42fe3f2e0d0229960e70b94e
     layers:
       meta-secure-core-common:
       meta-signing-key:

kas/corstone1000-extsys.yml

@@ -4,6 +4,3 @@ header:
 local_conf_header:
   extsys: |
     MACHINE_FEATURES += "corstone1000-extsys"
-
-    # external system firmware
-    CORE_IMAGE_EXTRA_INSTALL:firmware += "external-system-elf"

kas/corstone1000-firmware-only.yml

@@ -10,7 +10,7 @@ local_conf_header:
     OVERRIDES .= ":firmware"
 
     # Need to ensure we build with a small libc
-    TCLIBC = "musl"
+    TCLIBC="musl"
 
   mass-storage: |
     # Ensure the Mass Storage device is absent

kas/corstone1000-image-configuration.yml

@@ -23,11 +23,6 @@ local_conf_header:
     INIT_MANAGER:firmware = "mdev-busybox"
     VIRTUAL-RUNTIME_init_manager:firmware = "busybox"
 
-    # This guarantees module auto-loading support at boot
-    # by adding /etc/init.d/modutils.sh and /etc/rcS.d/ files
-    CORE_IMAGE_EXTRA_INSTALL:append = " modutils-initscripts"
-    DISTRO_FEATURES:append = " sysvinit"
-
     # prevent the kernel image from being included in the intramfs rootfs
     PACKAGE_EXCLUDE:firmware += "kernel-image-*"
 
@@ -45,8 +40,10 @@ local_conf_header:
     CORE_IMAGE_EXTRA_INSTALL += "packagegroup-ts-tests-psa"
     CORE_IMAGE_EXTRA_INSTALL:firmware += "packagegroup-ts-tests-psa"
 
+    # external system firmware
+    CORE_IMAGE_EXTRA_INSTALL:firmware += "external-system-elf"
+
   capsule: |
-    # These variables are set here since they are not defined in the arm-systemready-firmware recipe or under multiconfig mode.
     CAPSULE_EXTENSION = "uefi.capsule"
-    CAPSULE_VERSION = "6"
-    CAPSULE_NAME = "${MACHINE}-v${CAPSULE_VERSION}"
+    CAPSULE_FW_VERSION = "6"
+    CAPSULE_NAME = "${MACHINE}-v${CAPSULE_FW_VERSION}"

meta-arm-bsp/conf/layer.conf

@@ -9,12 +9,11 @@ BBFILE_COLLECTIONS += "meta-arm-bsp"
 BBFILE_PATTERN_meta-arm-bsp = "^${LAYERDIR}/"
 BBFILE_PRIORITY_meta-arm-bsp = "5"
 
-LAYERSERIES_COMPAT_meta-arm-bsp = "walnascar whinlatter"
+LAYERSERIES_COMPAT_meta-arm-bsp = "styhead walnascar"
 
 LAYERDEPENDS_meta-arm-bsp = "core meta-arm"
 # This won't be used by layerindex-fetch, but works everywhere else
 LAYERDEPENDS_meta-arm-bsp:append:corstone1000 = " meta-python openembedded-layer efi-secure-boot"
-LAYERDEPENDS_meta-arm-bsp:append:corstone1000:cortexa320 = " meta-ethos"
 LAYERDEPENDS_meta-arm-bsp:append:musca-b1 = " meta-python"
 LAYERDEPENDS_meta-arm-bsp:append:musca-s1 = " meta-python"
 

meta-arm-bsp/conf/machine/corstone1000-fvp.conf

@@ -3,18 +3,10 @@
 #@DESCRIPTION: Machine configuration for Corstone1000 64-bit FVP
 require conf/machine/include/corstone1000.inc
 
-require ${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000-extsys', \
-    'conf/machine/include/corstone1000-extsys.inc', '', d)}
-
-require ${@bb.utils.contains('MACHINE_FEATURES', 'cortexa320', \
-    'conf/machine/include/corstone1000-a320.inc', '', d)}
-
 TFA_TARGET_PLATFORM = "fvp"
 
 TFM_PLATFORM_IS_FVP = "TRUE"
 
-CORSTONE_1000_TYPE = "CORSTONE_1000_TYPE_CORTEX_A35_FVP"
-
 # testimage config
 TEST_TARGET = "OEFVPTarget"
 TEST_TARGET_IP = "127.0.0.1:2222"
@@ -23,10 +15,10 @@ DEFAULT_TEST_SUITES:append = " fvp_boot fvp_devices"
 # FVP Config
 FVP_PROVIDER ?= "fvp-corstone1000-native"
 FVP_EXE ?= "FVP_Corstone-1000"
-FVP_EXE:cortexa320 = "FVP_Corstone-1000-A320"
 FVP_CONSOLES[default] = "host_terminal_0"
 FVP_CONSOLES[tf-a] = "host_terminal_1"
 FVP_CONSOLES[se] = "secenc_terminal"
+FVP_CONSOLES[extsys] = "extsys_terminal"
 
 #Disable Time Annotation
 FASTSIM_DISABLE_TA = "0"
@@ -49,11 +41,14 @@ FVP_CONFIG[se.cryptocell.USER_OTP_FILTERING_DISABLE] ?= "1"
 # Boot image
 FVP_DATA ?= "board.flash0=corstone1000-flash-firmware-image-${MACHINE}.wic@0x68000000"
 
+# External system (cortex-M3)
+FVP_CONFIG[extsys_harness0.extsys_flashloader.fname] ?= "es_flashfw.bin"
 
 # FVP Terminals
 FVP_TERMINALS[host.host_terminal_0] ?= "Normal World Console"
 FVP_TERMINALS[host.host_terminal_1] ?= "Secure World Console"
 FVP_TERMINALS[se.secenc_terminal] ?= "Secure Enclave Console"
+FVP_TERMINALS[extsys0.extsys_terminal] ?= "Cortex M3"
 
 # MMC card configuration
 FVP_CONFIG[board.msd_mmc.card_type] ?= "SDHC"

meta-arm-bsp/conf/machine/corstone1000-mps3.conf

@@ -6,7 +6,4 @@ require conf/machine/include/corstone1000.inc
 
 TFA_TARGET_PLATFORM = "fpga"
 
-# Unlike the FVP, MPS3 supports CoreSight
-MACHINE_FEATURES += "coresight"
-
-CORSTONE_1000_TYPE = "CORSTONE_1000_TYPE_CORTEX_A35_MPS3"
+PLATFORM_IS_FVP = "FALSE"

meta-arm-bsp/conf/machine/fvp-base.conf

@@ -6,12 +6,6 @@
 
 require conf/machine/include/arm/arch-armv8-5a.inc
 
-# Set variables here to make it easier to change Instruction Set Architectures
-# on the FVP Base machine, which should make it easier to test both the tunes
-# and the virtual hardware.  These variables are set via the DEFAULT_TUNE
-ARM_ISA_MAJOR = "${@int(d.getVar('ARMPKGARCH').split('v')[1][0])}"
-ARM_ISA_MINOR = "${@int(d.getVar('ARMPKGARCH')[d.getVar('ARMPKGARCH').find('-')+1]) if '-' in d.getVar('ARMPKGARCH') else 0 }"
-
 ARM_SYSTEMREADY_FIRMWARE = "trusted-firmware-a:do_deploy"
 ARM_SYSTEMREADY_ACS_CONSOLE = "default"
 EXTRA_IMAGEDEPENDS = "${ARM_SYSTEMREADY_FIRMWARE}"
@@ -23,6 +17,8 @@ IMAGE_FSTYPES += "wic"
 WKS_FILE ?= "efi-disk.wks.in"
 
 SERIAL_CONSOLES = "115200;ttyAMA0"
+# FIXME -  This is being upstreamed.  Remove once that has occurred.
+KERNEL_CONSOLE ?= "${@','.join(d.getVar('SERIAL_CONSOLES').split(' ')[0].split(';')[::-1]) or 'ttyS0'}"
 
 PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto"
 KERNEL_DTB_NAME = "fvp-base-revc.dtb"
@@ -61,12 +57,9 @@ FVP_CONFIG[cluster1.stage12_tlb_size] ?= "1024"
 FVP_CONFIG[bp.secureflashloader.fname] ?= "bl1-fvp.bin"
 FVP_CONFIG[bp.flashloader0.fname] ?= "fip-fvp.bin"
 FVP_CONFIG[bp.virtioblockdevice.image_path] ?= "${IMAGE_NAME}.wic"
-
-# FVP Base default is 8.0, so there is no has_arm_v8-0 for it.  However, this is needed for every version after.  So set this accordingly
-FVP_EXTRA_ARGS = "--parameter cluster0.has_arm_v${ARM_ISA_MAJOR}-${ARM_ISA_MINOR}=1 --parameter cluster1.has_arm_v${ARM_ISA_MAJOR}-${ARM_ISA_MINOR}=1"
-FVP_EXTRA_ARGS += "${@bb.utils.contains('TUNE_FEATURES', 'sve', '--parameter cluster0.has_sve=1 --parameter cluster1.has_sve=1', '', d)}"
-FVP_EXTRA_ARGS += "${@bb.utils.contains('TUNE_FEATURES', 'sve2', '--parameter cluster0.sve.has_sve2=1 --parameter cluster1.sve.has_sve2=1', '', d)}"
-
+# Set the baseline to ARMv8.5, as the default is 8.0.
+FVP_CONFIG[cluster0.has_arm_v8-5] = "1"
+FVP_CONFIG[cluster1.has_arm_v8-5] = "1"
 FVP_CONSOLES[default] = "terminal_0"
 FVP_TERMINALS[bp.terminal_0] ?= "Console"
 FVP_TERMINALS[bp.terminal_1] ?= ""

meta-arm-bsp/conf/machine/include/corstone1000-a320.inc

@@ -1,5 +0,0 @@
-ETHOSU_NUM_MACS ?= "256"
-
-FVP_CONFIG[host.ethosu.num_macs] = "${ETHOSU_NUM_MACS}"
-
-IMAGE_INSTALL:append = " arm-npu-ethosu"

meta-arm-bsp/conf/machine/include/corstone1000-extsys.inc

@@ -1,6 +0,0 @@
-
-FVP_CONSOLES[extsys] = "extsys_terminal"
-
-FVP_CONFIG[extsys_harness0.extsys_flashloader.fname] = "es_flashfw.bin"
-
-FVP_TERMINALS[extsys0.extsys_terminal] = "Cortex M3"

meta-arm-bsp/conf/machine/include/corstone1000.inc

@@ -1,23 +1,21 @@
-TUNE_FILE = "conf/machine/include/arm/armv8a/tune-cortexa35.inc"
-TUNE_FILE:cortexa320 = "conf/machine/include/arm/arch-armv9-2a.inc"
-require ${TUNE_FILE}
+require conf/machine/include/arm/armv8a/tune-cortexa35.inc
 
 MACHINEOVERRIDES =. "corstone1000:"
 
 # TF-M
-PREFERRED_VERSION_trusted-firmware-m ?= "2.2.1"
+PREFERRED_VERSION_trusted-firmware-m ?= "2.1.%"
 
 # TF-A
 TFA_PLATFORM = "corstone1000"
-PREFERRED_VERSION_trusted-firmware-a ?= "2.13.%"
-PREFERRED_VERSION_tf-a-tests ?= "2.13.%"
+PREFERRED_VERSION_trusted-firmware-a ?= "2.11.%"
+PREFERRED_VERSION_tf-a-tests ?= "2.10.%"
 
 TFA_BL2_BINARY = "bl2-corstone1000.bin"
 TFA_FIP_BINARY = "fip-corstone1000.bin"
 
 # optee
-PREFERRED_VERSION_optee-os ?= "4.7.%"
-PREFERRED_VERSION_optee-client ?= "4.7.%"
+PREFERRED_VERSION_optee-os ?= "4.4.%"
+PREFERRED_VERSION_optee-client ?= "4.4.%"
 
 # Trusted Services
 TS_PLATFORM = "arm/corstone1000"
@@ -25,8 +23,8 @@ TS_SP_SE_PROXY_CONFIG = "corstone1000"
 # Include smm-gateway and se-proxy SPs into optee-os binary
 MACHINE_FEATURES += "ts-smm-gateway ts-se-proxy"
 
-# U-Boot
-PREFERRED_VERSION_u-boot ?= "2025.04%"
+# u-boot
+PREFERRED_VERSION_u-boot ?= "2023.07%"
 MACHINE_FEATURES += "efi"
 EFI_PROVIDER ?= "grub-efi"
 
@@ -68,9 +66,4 @@ ARM_SYSTEMREADY_FIRMWARE = "${FIRMWARE_DEPLOYMENT}:do_deploy \
 ARM_SYSTEMREADY_ACS_CONSOLE ?= "default"
 
 # Workaround IMAGE_ROOTFS_EXTRA_SPACE being ignored when images are repacked
-IMAGE_ROOTFS_EXTRA_ARGS += "--extra-filesystem-space ${@${IMAGE_ROOTFS_EXTRA_SPACE}}K"
-
-# Enable Authenticated variable support in SmmGW
-SMMGW_AUTH_VAR = "1"
-# Use MbedTLS build into SmmGW for authentication related crypto operations.
-SMMGW_INTERNAL_CRYPTO = "1"
+IMAGE_ROOTFS_EXTRA_ARGS += "--extra-space ${@${IMAGE_ROOTFS_EXTRA_SPACE}}K"

meta-arm-bsp/conf/machine/juno.conf

@@ -8,7 +8,7 @@ TUNE_FEATURES = "aarch64"
 
 require conf/machine/include/arm/arch-armv8a.inc
 
-MACHINE_FEATURES = "usbhost usbgadget alsa screen wifi bluetooth optee pci coresight"
+MACHINE_FEATURES = "usbhost usbgadget alsa screen wifi bluetooth optee pci"
 
 KERNEL_IMAGETYPE = "Image.gz"
 KERNEL_DEVICETREE = "arm/juno.dtb arm/juno-r1.dtb arm/juno-r2.dtb"

meta-arm-bsp/conf/machine/sbsa-ref.conf

@@ -36,11 +36,11 @@ QB_MACHINE = "-machine sbsa-ref"
 QB_CPU = "-cpu neoverse-n2"
 QB_MEM = "-m 1024"
 QB_DEFAULT_FSTYPE = "wic.qcow2"
-QB_NETWORK_DEVICE = "-device e1000e,netdev=net0,mac=@MAC@"
+QB_NETWORK_DEVICE = "-device virtio-net-pci,netdev=net0,mac=@MAC@"
 QB_DRIVE_TYPE = "/dev/hd"
 QB_ROOTFS_OPT = "-drive file=@ROOTFS@,if=ide,format=qcow2"
 QB_DEFAULT_KERNEL = "none"
-QB_OPT_APPEND = "-device usb-tablet -device usb-kbd -drive if=pflash,format=raw,unit=0,readonly,file=@DEPLOY_DIR_IMAGE@/SBSA_FLASH0.fd -drive if=pflash,format=raw,unit=1,readonly,file=@DEPLOY_DIR_IMAGE@/SBSA_FLASH1.fd"
+QB_OPT_APPEND = "-device usb-tablet -device usb-kbd -pflash @DEPLOY_DIR_IMAGE@/SBSA_FLASH0.fd -pflash @DEPLOY_DIR_IMAGE@/SBSA_FLASH1.fd"
 QB_SERIAL_OPT = "-device virtio-serial-pci -chardev null,id=virtcon -device virtconsole,chardev=virtcon"
 QB_TCPSERIAL_OPT = "-device virtio-serial-pci -chardev socket,id=virtcon,port=@PORT@,host=127.0.0.1 -device virtconsole,chardev=virtcon"
 # sbsa-ref is a true virtual machine so can't use KVM

meta-arm-bsp/conf/machine/sgi575.conf

@@ -9,9 +9,6 @@ require conf/machine/include/arm/armv8-2a/tune-cortexa75.inc
 EXTRA_IMAGEDEPENDS += "virtual/control-processor-firmware"
 EXTRA_IMAGEDEPENDS += "trusted-firmware-a"
 
-# 2.13.0 removes support for sgi575
-PREFERRED_VERSION_trusted-firmware-a ?= "2.12.%"
-
 KERNEL_IMAGETYPE ?= "Image"
 PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto"
 SERIAL_CONSOLES = "115200;ttyAMA0"

meta-arm-bsp/documentation/corstone1000/change-log.rst

@@ -1,5 +1,5 @@
 ..
- # Copyright (c) 2022-2026, Arm Limited.
+ # Copyright (c) 2022-2025, Arm Limited.
  #
  # SPDX-License-Identifier: MIT
 
@@ -10,77 +10,6 @@ Change Log
 This document contains a summary of the new features, changes and
 fixes in each release of Corstone-1000 software stack.
 
-***************
-Version 2025.12
-***************
-
-Changes
-=======
-
-- Delivered end-to-end Cortex-A320 enablement across U-Boot, TF-A, TF-M, OP-TEE, Yocto machine layers, and documentation, including device-tree updates, MPIDR handling, and FVP model renaming.
-- Rolled out the PSA Firmware Update (DEN0118) pipeline: U-Boot capsule parsing, Bootloader Abstraction Layer in TF-M, ESRT exposure, and Trusted Services IPC bridges replacing legacy capsule code.
-- Hardened the new firmware update flow with EFI self-tests, metadata restructuring for partial and multi-image acceptance, and RSE-COMMS gating refinements.
-- Upgraded key firmware components (TF-A 2.13.0, TF-M 2.2.1, Trusted Services 1.2.0, OP-TEE OS 4.7.0) and introduced targeted test skips plus integer-only build modes to keep validation green.
-- Cleaned and renumbered downstream patch series across Trusted Services and TF-M while removing obsolete integrations to align with upstream baselines.
-- Refreshed release material and architecture guides to describe the A320 profile, PSA FWU behavior, and updated software stack.
-- Added KAS profiles, machine includes, and automated FVP selection logic to streamline developer workflows for the refreshed platform configuration.
-
-Corstone-1000 components versions
-=================================
-
-+-------------------------------------------+-------------------+
-| linux-yocto                               | 6.12.60           |
-+-------------------------------------------+-------------------+
-| u-boot                                    | 2025.04           |
-+-------------------------------------------+-------------------+
-| external-system                           | 0.1.0             |
-+-------------------------------------------+-------------------+
-| optee-client                              | 4.7.0             |
-+-------------------------------------------+-------------------+
-| optee-os                                  | 4.7.0             |
-+-------------------------------------------+-------------------+
-| trusted-firmware-a                        | 2.13.0            |
-+-------------------------------------------+-------------------+
-| trusted-firmware-m                        | 2.2.1             |
-+-------------------------------------------+-------------------+
-| libts                                     | v1.2.0            |
-+-------------------------------------------+-------------------+
-| ts-sp-{se-proxy, smm-gateway}             | v1.2.0            |
-+-------------------------------------------+-------------------+
-| ts-psa-{crypto, iat, its. ps}-api-test    | 74dc6646ff        |
-+-------------------------------------------+-------------------+
-
-Yocto distribution components versions
-======================================
-
-+-------------------------------------------+----------------+
-| meta-arm                                  | whinlatter     |
-+-------------------------------------------+----------------+
-| bitbake                                   | 0dde1a3ff8     |
-+-------------------------------------------+----------------+
-| meta-openembedded                         | fc0152e434     |
-+-------------------------------------------+----------------+
-| openembedded-core                         | 4bd920ad7d     |
-+-------------------------------------------+----------------+
-| meta-yocto                                | b3b6592635     |
-+-------------------------------------------+----------------+
-| meta-secure-core                          | 63209fb150     |
-+-------------------------------------------+----------------+
-| meta-ethos                                | aa2504a32f     |
-+-------------------------------------------+----------------+
-| meta-sca                                  | e68f1a9d17     |
-+-------------------------------------------+----------------+
-| busybox                                   | 1.37.0         |
-+-------------------------------------------+----------------+
-| musl                                      | 1.2.5          |
-+-------------------------------------------+----------------+
-| gcc-arm-none-eabi                         | 13.3.rel1      |
-+-------------------------------------------+----------------+
-| gcc-cross-aarch64                         | 15.2.0         |
-+-------------------------------------------+----------------+
-| openssl                                   | 3.5.4          |
-+-------------------------------------------+----------------+
-
 ***************
 Version 2025.05
 ***************
@@ -568,4 +497,4 @@ Changes
 
 --------------
 
-*Copyright (c) 2022-2026, Arm Limited. All rights reserved.*
+*Copyright (c) 2022-2024, Arm Limited. All rights reserved.*

meta-arm-bsp/documentation/corstone1000/index.rst

@@ -1,5 +1,5 @@
 ..
- # Copyright (c) 2022, 2024, 2026 Arm Limited.
+ # Copyright (c) 2022, 2024, Arm Limited.
  #
  # SPDX-License-Identifier: MIT
 

meta-arm-bsp/documentation/corstone1000/release-notes.rst

@@ -1,5 +1,5 @@
 ..
- # Copyright (c) 2022-2026, Arm Limited.
+ # Copyright (c) 2022-2025, Arm Limited.
  #
  # SPDX-License-Identifier: MIT
 
@@ -19,18 +19,6 @@ intended for safety-critical applications. Should Your Software or Your Hardware
 prove defective, you assume the entire cost of all necessary servicing, repair
 or correction.
 
-***********************
-Release notes - 2025.12
-***********************
-
-The same notes as the 2025.05 release still apply.
-
-Known Issues or Limitations
----------------------------
-
-- Corstone-1000 with Cortex-A320 FVP does not currently support Symmetric Multiprocessing
-- Corstone-1000 with Cortex-A320 FVP becomes unresponsive when the Linux kernel driver for the Ethos-U85 NPU loads automatically after a software reboot.
-
 ***********************
 Release notes - 2025.05
 ***********************
@@ -280,4 +268,4 @@ For all security issues, contact Arm by email at psirt@arm.com.
 
 --------------
 
-*Copyright (c) 2022-2026, Arm Limited. All rights reserved.*
+*Copyright (c) 2022-2023, Arm Limited. All rights reserved.*

meta-arm-bsp/documentation/corstone1000/software-architecture.rst

@@ -1,5 +1,5 @@
 ..
- # Copyright (c) 2022-2026, Arm Limited.
+ # Copyright (c) 2022-2025, Arm Limited.
  #
  # SPDX-License-Identifier: MIT
 
@@ -116,19 +116,6 @@ The Corstone-1000 architecture is designed to cover a range of
 `Power, Performance, and Area (PPA) <ppa-website_>`__ applications, and enable extension
 for use-case specific applications, for example, sensors, cloud connectivity, and edge computing.
 
-**************************************
-Corstone-1000 with Cortex-A320 Variant
-**************************************
-
-This variant of the Corstone-1000 platform replaces the Host System's Cortex-A35 processor
-with a Cortex-A320. In this configuration, the optional External System (previously a Cortex-M3)
-is replaced by an Arm Ethos-U85 Neural Processing Unit (NPU).
-The Ethos-U85 runs in the direct drive configuration, where the Host System is responsible for managing the NPU directly.
-
-.. image:: images/CorstoneA320Subsystems.png
-   :width: 720
-   :alt: CorstoneA320Subsystems
-
 *****************
 Secure Boot Chain
 *****************
@@ -328,49 +315,15 @@ Host Secure World experience lower latency, but rely on TrustZone technology for
 which offers comparatively less robust security.
 
 
-**************************
-PSA Secure Firmware Update
-**************************
-
-The Arm Corstone-1000 platform necessitates a robust, secure, and flexible firmware update mechanism
-including partial capsule update to ensure fielded devices can receive critical patches, feature enhancements,
-and security fixes without compromising system integrity. To meet these requirements, we have implemented the
-Platform Security Architecture (PSA) Firmware Update (FWU) framework on Corstone-1000, leveraging Trusted Firmware-M (TF-M)
-for the Secure Enclave, U-Boot as the host-side client on Cortex-A, and the UEFI capsule update mechanism for payload
-encapsulation. This design supports both the Fixed Virtual Platform (FVP) and the Field Programmable Gate Array (FPGA)
-targets, providing consistent behavior across simulation and silicon-based deployments. The Corstone-1000 supports FWU
-which complies with the `Platform Security Firmware Update for the A-profile Arm Architecture <platform-security-fwu-for-a-profile-pdf_>`__
-and `PSA Firmware Update IHI 0093 <psa-firmware-update-ihi-0093-api-reference-website_>`__
-specifications.
-
-To standardize and streamline capsule creation with multiple FMP payloads, the `EDK2 capsule generation tool <edk2-capsule-generation-tool-repository_>`__
-tool has been integrated into the meta-arm Yocto layer for Corstone‑1000. This integration involves defining
-build rules for generating UEFI capsules as part of the firmware image build process. Configuration parameters
-exposed in the recipe allow developers to specify the number of FMP payloads, target image GUIDs, version numbers etc.
-This capsule ensures that all update payloads conform to the UEFI FMP specification and are ready for
-validation and delivery by U‑Boot.
-
-The FWU solution for Corstone-1000 is composed of three primary domains:
-
-- Host System
-- Trusted Services intermediary
-- Secure Enclave
-
-Each domain has distinct responsibilities and communicates through standardized interfaces.
+**********************
+Secure Firmware Update
+**********************
 
 
-.. image:: images/SystemArchitecturePSAFirmwareUpdate.png
-   :width: 690
-   :alt: SystemArchitecturePSAFirmwareUpdate
-
-On the host side, U-Boot functions as the FWU client and orchestrates the update process from capsule retrieval to
-payload delivery based on `PSA FWU DEN0018 specification <psa-fwu-den0018-specification-website_>`__
-via Arm FF-A framework. The Trusted-Services SE Proxy secure partition serves as a gateway between the non-secure host
-environment and the Secure Enclave. The `PSA FWU service <ts-psa-fwu-service-website_>`__ running in the Trusted Services
-implementation forwards the data to the Secure Enclave via MHU-based PSA calls. Within the Secure Enclave, the PSA FWU
-Agent, conforming to `PSA Firmware Update IHI 0093 <psa-firmware-update-ihi-0093-api-reference-website_>`__ specification,
-orchestrates the actual flash programming, metadata management, and rollback protection mechanisms. The agent relies on a
-bespoke `shim layer <tfm-shim-layer-website_>`__ to abstract hardware‑specific flash operations and bootloader interactions.
+In addition to always booting authorized images, it is equally important that the device only accepts
+authorized (signed) images during the firmware update process. Corstone-1000 supports over-the-air (OTA)
+firmware updates and complies with the `Platform Security Firmware Update for the A-profile Arm Architecture <platform-security-fwu-for-a-profile-pdf_>`__ 
+specification.
 
 As defined in the specification, the external flash is divided into two banks: one bank holds the
 currently running images, while the other is used to stage new images.
@@ -383,55 +336,23 @@ New images are delivered and accepted in the form of UEFI capsules.
    :width: 690
    :alt: ExternalFlash
 
-When a FWU is initiated on Corstone-1000, the following sequence of operations takes place:
+When a firmware update is triggered, U-Boot begins by verifying the UEFI capsule by checking its signature,
+version number, and size. After successful verification, it signals the Secure Enclave, which then
+starts writing the capsule contents to flash memory.
 
-#. **Capsule Retrieval and Preparation**
+Once the write operation is complete, the Secure Enclave resets the entire system. The update process
+is tracked using a state machine stored in the Metadata Block within flash. TF-M runs an OTA service
+that is responsible for verifying and updating the images in the passive flash bank. Communication
+between the UEFI capsule update subsystem and the OTA service follows the same data path described
+earlier. After verifying the capsule, the OTA service writes the new images to the passive bank,
+updates the system state to 'trial,' and initiates a reset.
 
-   U-Boot on the host system retrieves the firmware capsule.
-   It validates the capsule header and parses the FMP (Firmware Management Protocol) descriptor list to identify the payloads to be updated.
-
-   For each FMP descriptor, U-Boot:
-
-   Splits the firmware payload into 4 KiB chunks.
-   Invokes the PSA_FWU_Update API for each chunk, transmitting the buffer address via the FF-A (Firmware Framework for Arm) shared memory interface.
-
-#. **Secure Transmission and Forwarding**
-
-   The PSA Firmware Update (FWU) service, running as part of Trusted Services, receives the chunks through Secure Partition Client (SPC) calls.
-   It forwards these chunks to the Secure Enclave using MHU-based PSA calls.
-
-#. **Flashing Within the Secure Enclave**
-
-   Inside the Secure Enclave, the PSA FWU Agent dispatches each chunk to the shim layer.
-
-   The shim layer:
-
-   Erases the corresponding sectors in the non-active flash bank.
-   Writes the received firmware chunks at the correct offsets.
-   During partial updates, it also copies static partitions from the active bank to the non-active one to maintain consistency.
-
-#. **Finalization and Boot Preparation**
-
-   After all chunks are successfully written:
-
-   The shim updates the firmware manifest and the EFI System Resource Table (ESRT) entries to reflect the new image version.
-   This step enables the bootloader to recognize the new firmware for a trial boot.
-   The platform then performs an automatic reset, booting into the non-active bank in trial mode.
-
-#. **Trial Boot and Confirmation**
-
-   In trial mode, U-Boot evaluates the new firmware and issues either an accept or reject command using the PSA FWU ABI.
-   These commands are sent to the Secure Enclave, instructing the shim to update the firmware metadata accordingly.
-
-#. **Recovery and Fallback Mechanism**
-
-   If the trial boot is successful, the host sends an acknowledgment, transitioning the firmware state from 'trial' to 'regular'.
-
-   If the system fails or becomes unresponsive:
-
-   A watchdog timer triggers a system reset.
-   The BL1 firmware in the Secure Enclave detects repeated failures and reverts to the previously known-good flash bank.
-   This rollback mechanism ensures the device remains operational and recoverable, even after a failed update.
+During boot, the bootloaders in both the Secure Enclave and the Host system read the Metadata Block to
+determine which bank to boot from. If the trial boot succeeds, the Host system sends an acknowledgment
+that transitions the system state from 'trial' to 'regular.' If the system fails during the trial phase
+or hangs, a watchdog timer triggers a reset. The Secure Enclave’s BL1 contains logic to detect multiple
+resets and can revert to the previously known-good bank. This fallback mechanism is essential to ensure
+the device remains available and functional.
 
 
 .. image:: images/SecureFirmwareUpdate.png
@@ -468,7 +389,7 @@ References
 
 --------------
 
-*Copyright (c) 2022-2026, Arm Limited. All rights reserved.*
+*Copyright (c) 2022-2025, Arm Limited. All rights reserved.*
 
 .. _arm-developer-cs1000-website: https://developer.arm.com/Tools%20and%20Software/Corstone-1000%20Software
 .. _arm-developer-cs1000-search: https://developer.arm.com/search#q=corstone-1000
@@ -480,11 +401,6 @@ References
 .. _arm-fmw-framework-a-profile-pdf: https://developer.arm.com/documentation/den0077/latest
 .. _arm-fmw-framework-m-profile-pdf: https://developer.arm.com/architectures/Firmware%20Framework%20for%20M-Profile
 .. _platform-security-fwu-for-a-profile-pdf: https://developer.arm.com/documentation/den0118/a/
-.. _psa-firmware-update-ihi-0093-api-reference-website: https://arm-software.github.io/psa-api/fwu/1.0/api/api.html
-.. _edk2-capsule-generation-tool-repository: https://github.com/tianocore/edk2/blob/master/BaseTools/Source/Python/Capsule/GenerateCapsule.py
-.. _psa-fwu-den0018-specification-website: https://developer.arm.com/documentation/den0118/latest/
-.. _ts-psa-fwu-service-website: https://trusted-services.readthedocs.io/en/stable/services/fwu/psa-fwu-m.html
-.. _tfm-shim-layer-website: https://trustedfirmware-m.readthedocs.io/en/latest/design_docs/services/tfm_fwu_service.html#shim-layer-between-fwu-and-bootloader
 .. _op-tee-os-repository: https://github.com/OP-TEE/optee_os
 .. _psa-certified-website: https://www.psacertified.org/
 .. _psa_l2-ready: https://www.psacertified.org/products/corstone-1000/

meta-arm-bsp/dynamic-layers/meta-arm-systemready/recipes-test/arm-systemready-acs/arm-systemready-ir-acs-fvp-base.inc

@@ -1,2 +1,2 @@
-FILESEXTRAPATHS:prepend := "${THISDIR}/files/${MACHINE}:"
+FILESEXTRAPATHS:append := "${THISDIR}/files/${MACHINE}:"
 SRC_URI:append = " file://report.txt"

meta-arm-bsp/recipes-bsp/external-system/external-system_0.1.0.bb

@@ -3,7 +3,7 @@ DESCRIPTION = "Firmware to be loaded and run in External System Harness in\
                support to the main application CPU."
 HOMEPAGE = "https://git.linaro.org/landing-teams/working/arm/external-system.git"
 DEPENDS = "gcc-arm-none-eabi-native"
-INHIBIT_DEFAULT_DEPS = "1"
+INHIBIT_DEFAULT_DEPS="1"
 LICENSE = "BSD-3-Clause & Apache-2.0"
 LIC_FILES_CHKSUM = "file://license.md;md5=e44b2531cd6ffe9dece394dbe988d9a0 \
                     file://cmsis/LICENSE.txt;md5=e3fc50a88d0a364313df4b21ef20c29e"
@@ -19,6 +19,7 @@ PACKAGE_ARCH = "${MACHINE_ARCH}"
 # PRODUCT is passed to the Makefile to specify the platform to be used.
 PRODUCT = "corstone-1000"
 
+S = "${WORKDIR}/git"
 B = "${WORKDIR}/build"
 
 # remove once arm-none-eabi-gcc updates to 13 or newer like poky

meta-arm-bsp/recipes-bsp/images/corstone1000-firmware-deploy-image.inc

@@ -2,10 +2,7 @@ COMPATIBLE_MACHINE = "corstone1000"
 
 FIRMWARE_BINARIES = "corstone1000-flash-firmware-image-${MACHINE}.wic \
                      bl1.bin \
-                     ${@bb.utils.contains('MACHINE_FEATURES', \
-                                          'corstone1000-extsys', \
-                                          'es_flashfw.bin', \
-                                          '', d)} \
+                     es_flashfw.bin \
                      ${CAPSULE_NAME}.${CAPSULE_EXTENSION} \
                      corstone1000_capsule_cert.crt \
                      corstone1000_capsule_key.key \

meta-arm-bsp/recipes-bsp/images/corstone1000-flash-firmware-image.bb

@@ -14,8 +14,7 @@ inherit tfm_sign_image
 inherit uefi_capsule
 inherit deploy
 
-DEPENDS += "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000-extsys', \
-                                 'external-system', '', d)} \
+DEPENDS += "external-system \
             trusted-firmware-a \
             trusted-firmware-m \
             u-boot \
@@ -26,133 +25,21 @@ IMAGE_LINGUAS = ""
 
 PACKAGE_INSTALL = ""
 
+# The generated ${MACHINE}_image.nopt is used instead of the default wic image
+# for the capsule generation. The uefi.capsule image type doesn't have to
+# depend on the wic because of this.
+#
 # The corstone1000_capsule_cert.crt and corstone1000_capsule_key.key are installed
 # by the U-Boot recipe so this recipe has to depend on that.
-
 CAPSULE_IMGTYPE = ""
-CAPSULE_IMG_LOCATION = "${DEPLOY_DIR_IMAGE}"
-
-# User-configurable common capsule settings
-CAPSULE_EXTENSION ?= "uefi.capsule"
-CAPSULE_VERSION ?= "6"
-CAPSULE_LOWEST_SUPPORTED_VERSION ?= "6"
-CAPSULE_NAME ?= "${MACHINE}-v${CAPSULE_VERSION}"
-CAPSULE_SELECTED_COMPONENTS ?= "BL2 TFM_S FIP INITRAMFS"
-CAPSULE_EXTRA_ARGS ?= "--capflag PersistAcrossReset"
-
-# Non-configurable common payloads settings
-PAYLOAD_CERTIFICATE_PATH = "${DEPLOY_DIR_IMAGE}/corstone1000_capsule_cert.crt"
-PAYLOAD_HARDWARE_INSTANCE = "1"
-PAYLOAD_MONOTONIC_COUNT = "1"
-PAYLOAD_PRIVATE_KEY_PATH = "${DEPLOY_DIR_IMAGE}/corstone1000_capsule_key.key"
-CAPSULE_SELECTED_COMPONENTS += " DUMMY_START DUMMY_END"
-
-# All capsule fields are reset and initialized with DUMMY_START since it is the first payload
-# DUMMY_START
-PAYLOAD_DUMMY_START_INDEX ?= "5"
-PAYLOAD_DUMMY_START_VERSION ?= "${CAPSULE_VERSION}"
-PAYLOAD_DUMMY_START_LOWEST_SUPPORTED_VERSION ?= "${CAPSULE_LOWEST_SUPPORTED_VERSION}"
-PAYLOAD_DUMMY_START_GUID ?=  "6f784cbf-7938-5c23-8d6e-24d2f1410fa9"
-
-CAPSULE_ALL_COMPONENTS = "DUMMY_START "
-CAPSULE_CERTIFICATE_PATHS = "${PAYLOAD_CERTIFICATE_PATH} "
-CAPSULE_GUIDS = "${PAYLOAD_DUMMY_START_GUID} "
-CAPSULE_INDEXES = "${PAYLOAD_DUMMY_START_INDEX} "
-CAPSULE_HARDWARE_INSTANCES = "${PAYLOAD_HARDWARE_INSTANCE} "
-CAPSULE_MONOTONIC_COUNTS = "${PAYLOAD_MONOTONIC_COUNT} "
-CAPSULE_PRIVATE_KEY_PATHS = "${PAYLOAD_PRIVATE_KEY_PATH} "
-UEFI_FIRMWARE_BINARIES = "${B}/dummy.bin "
-CAPSULE_FW_VERSIONS = "${PAYLOAD_DUMMY_START_VERSION} "
-CAPSULE_LOWEST_SUPPORTED_VERSIONS = "${PAYLOAD_DUMMY_START_LOWEST_SUPPORTED_VERSION} "
-
-# BL2
-PAYLOAD_BL2_INDEX ?= "1"
-PAYLOAD_BL2_VERSION ?= "${CAPSULE_VERSION}"
-PAYLOAD_BL2_LOWEST_SUPPORTED_VERSION ?= "${CAPSULE_LOWEST_SUPPORTED_VERSION}"
-PAYLOAD_BL2_GUID:corstone1000-fvp ?= "f1d883f9-dfeb-5363-98d8-686ee3b69f4f"
-PAYLOAD_BL2_GUID:corstone1000-mps3 ?= "fbfbefaa-0a56-50d5-b651-74091d3d62cf"
-
-CAPSULE_ALL_COMPONENTS += "BL2 "
-CAPSULE_CERTIFICATE_PATHS += "${PAYLOAD_CERTIFICATE_PATH} "
-CAPSULE_GUIDS += "${PAYLOAD_BL2_GUID} "
-CAPSULE_INDEXES += "${PAYLOAD_BL2_INDEX} "
-CAPSULE_HARDWARE_INSTANCES += "${PAYLOAD_HARDWARE_INSTANCE} "
-CAPSULE_MONOTONIC_COUNTS += "${PAYLOAD_MONOTONIC_COUNT} "
-CAPSULE_PRIVATE_KEY_PATHS += "${PAYLOAD_PRIVATE_KEY_PATH} "
-UEFI_FIRMWARE_BINARIES += "${DEPLOY_DIR_IMAGE}/bl2_signed.bin "
-CAPSULE_FW_VERSIONS += "${PAYLOAD_BL2_VERSION} "
-CAPSULE_LOWEST_SUPPORTED_VERSIONS += "${PAYLOAD_BL2_LOWEST_SUPPORTED_VERSION} "
-
-# TFM_S
-PAYLOAD_TFM_S_INDEX ?= "2"
-PAYLOAD_TFM_S_VERSION ?= "${CAPSULE_VERSION}"
-PAYLOAD_TFM_S_LOWEST_SUPPORTED_VERSION ?= "${CAPSULE_LOWEST_SUPPORTED_VERSION}"
-PAYLOAD_TFM_S_GUID:corstone1000-fvp ?= "7fad470e-5ec5-5c03-a2c1-4756b495de61"
-PAYLOAD_TFM_S_GUID:corstone1000-mps3 ?= "af4cc7ad-ee2e-5a39-aad5-fac8a1e6173c"
-
-CAPSULE_ALL_COMPONENTS += "TFM_S "
-CAPSULE_CERTIFICATE_PATHS += "${PAYLOAD_CERTIFICATE_PATH} "
-CAPSULE_GUIDS += "${PAYLOAD_TFM_S_GUID} "
-CAPSULE_INDEXES += "${PAYLOAD_TFM_S_INDEX} "
-CAPSULE_HARDWARE_INSTANCES += "${PAYLOAD_HARDWARE_INSTANCE} "
-CAPSULE_MONOTONIC_COUNTS += "${PAYLOAD_MONOTONIC_COUNT} "
-CAPSULE_PRIVATE_KEY_PATHS += "${PAYLOAD_PRIVATE_KEY_PATH} "
-UEFI_FIRMWARE_BINARIES += "${DEPLOY_DIR_IMAGE}/tfm_s_signed.bin "
-CAPSULE_FW_VERSIONS += "${PAYLOAD_TFM_S_VERSION} "
-CAPSULE_LOWEST_SUPPORTED_VERSIONS += "${PAYLOAD_TFM_S_LOWEST_SUPPORTED_VERSION} "
-
-# FIP
-PAYLOAD_FIP_INDEX ?= "3"
-PAYLOAD_FIP_VERSION ?= "${CAPSULE_VERSION}"
-PAYLOAD_FIP_LOWEST_SUPPORTED_VERSION ?= "${CAPSULE_LOWEST_SUPPORTED_VERSION}"
-PAYLOAD_FIP_GUID:corstone1000-fvp ?= "f1933675-5a8c-5b6d-9ef4-846739e89bc8"
-PAYLOAD_FIP_GUID:corstone1000-mps3 ?= "55302f96-c4f0-5cf9-8624-e7cc388f2b68"
-
-CAPSULE_ALL_COMPONENTS += "FIP "
-CAPSULE_CERTIFICATE_PATHS += "${PAYLOAD_CERTIFICATE_PATH} "
-CAPSULE_GUIDS += "${PAYLOAD_FIP_GUID} "
-CAPSULE_INDEXES += "${PAYLOAD_FIP_INDEX} "
-CAPSULE_HARDWARE_INSTANCES += "${PAYLOAD_HARDWARE_INSTANCE} "
-CAPSULE_MONOTONIC_COUNTS += "${PAYLOAD_MONOTONIC_COUNT} "
-CAPSULE_PRIVATE_KEY_PATHS += "${PAYLOAD_PRIVATE_KEY_PATH} "
-UEFI_FIRMWARE_BINARIES += "${DEPLOY_DIR_IMAGE}/signed_fip-corstone1000.bin "
-CAPSULE_FW_VERSIONS += "${PAYLOAD_FIP_VERSION} "
-CAPSULE_LOWEST_SUPPORTED_VERSIONS += "${PAYLOAD_FIP_LOWEST_SUPPORTED_VERSION} "
-
-# INITRAMFS
-PAYLOAD_INITRAMFS_INDEX ?= "4"
-PAYLOAD_INITRAMFS_VERSION ?= "${CAPSULE_VERSION}"
-PAYLOAD_INITRAMFS_LOWEST_SUPPORTED_VERSION ?= "${CAPSULE_LOWEST_SUPPORTED_VERSION}"
-PAYLOAD_INITRAMFS_GUID:corstone1000-fvp ?= "f771aff9-c7e9-5f99-9eda-2369dd694f61"
-PAYLOAD_INITRAMFS_GUID:corstone1000-mps3 ?= "3e8ac972-c33c-5cc9-90a0-cdd3159683ea"
-
-CAPSULE_ALL_COMPONENTS += "INITRAMFS "
-CAPSULE_CERTIFICATE_PATHS += "${PAYLOAD_CERTIFICATE_PATH} "
-CAPSULE_GUIDS += "${PAYLOAD_INITRAMFS_GUID} "
-CAPSULE_INDEXES += "${PAYLOAD_INITRAMFS_INDEX} "
-CAPSULE_HARDWARE_INSTANCES += "${PAYLOAD_HARDWARE_INSTANCE} "
-CAPSULE_MONOTONIC_COUNTS += "${PAYLOAD_MONOTONIC_COUNT} "
-CAPSULE_PRIVATE_KEY_PATHS += "${PAYLOAD_PRIVATE_KEY_PATH} "
-UEFI_FIRMWARE_BINARIES += "${DEPLOY_DIR_IMAGE}/Image.gz-initramfs-${MACHINE}.bin "
-CAPSULE_FW_VERSIONS += "${PAYLOAD_INITRAMFS_VERSION} "
-CAPSULE_LOWEST_SUPPORTED_VERSIONS += "${PAYLOAD_INITRAMFS_LOWEST_SUPPORTED_VERSION} "
-
-# DUMMY_END
-PAYLOAD_DUMMY_END_INDEX ?= "6"
-PAYLOAD_DUMMY_END_VERSION ?= "${CAPSULE_VERSION}"
-PAYLOAD_DUMMY_END_LOWEST_SUPPORTED_VERSION ?= "${CAPSULE_LOWEST_SUPPORTED_VERSION}"
-PAYLOAD_DUMMY_END_GUID ?= "b57e432b-a250-5c73-93e3-90205e64baba"
-
-CAPSULE_ALL_COMPONENTS += "DUMMY_END"
-CAPSULE_CERTIFICATE_PATHS += "${PAYLOAD_CERTIFICATE_PATH}"
-CAPSULE_GUIDS += "${PAYLOAD_DUMMY_END_GUID}"
-CAPSULE_INDEXES += "${PAYLOAD_DUMMY_END_INDEX}"
-CAPSULE_HARDWARE_INSTANCES += "${PAYLOAD_HARDWARE_INSTANCE}"
-CAPSULE_MONOTONIC_COUNTS += "${PAYLOAD_MONOTONIC_COUNT}"
-CAPSULE_PRIVATE_KEY_PATHS += "${PAYLOAD_PRIVATE_KEY_PATH}"
-UEFI_FIRMWARE_BINARIES += "${B}/dummy.bin"
-CAPSULE_FW_VERSIONS += "${PAYLOAD_DUMMY_END_VERSION}"
-CAPSULE_LOWEST_SUPPORTED_VERSIONS += "${PAYLOAD_DUMMY_END_LOWEST_SUPPORTED_VERSION}"
+CAPSULE_CERTIFICATE_PATH = "${DEPLOY_DIR_IMAGE}/corstone1000_capsule_cert.crt"
+CAPSULE_GUID:corstone1000-fvp ?= "989f3a4e-46e0-4cd0-9877-a25c70c01329"
+CAPSULE_GUID:corstone1000-mps3 ?= "df1865d1-90fb-4d59-9c38-c9f2c1bba8cc"
+CAPSULE_IMGLOCATION = "${DEPLOY_DIR_IMAGE}"
+CAPSULE_INDEX = "1"
+CAPSULE_MONOTONIC_COUNT = "1"
+CAPSULE_PRIVATE_KEY_PATH = "${DEPLOY_DIR_IMAGE}/corstone1000_capsule_key.key"
+UEFI_FIRMWARE_BINARY = "${B}/${MACHINE}_image.nopt"
 
 # TF-A settings for signing host images
 TFA_BL2_BINARY = "bl2-corstone1000.bin"
@@ -162,9 +49,16 @@ TFA_BL2_RE_SIGN_BIN_SIZE = "0x2d000"
 TFA_FIP_RE_IMAGE_LOAD_ADDRESS = "0x68130000"
 TFA_FIP_RE_SIGN_BIN_SIZE = "0x00200000"
 RE_LAYOUT_WRAPPER_VERSION = "0.0.7"
-TFM_SIGN_PRIVATE_KEY = "${libdir}/tfm-scripts/root-EC-P256_1.pem"
+TFM_SIGN_PRIVATE_KEY = "${libdir}/tfm-scripts/root-RSA-3072_1.pem"
 RE_IMAGE_OFFSET = "0x1000"
 
+# Offsets for the .nopt image generation
+# These offset values have to be aligned with those in
+# meta-arm/meta-arm-bsp/wic/corstone1000-flash-firmware.wks.in
+TFM_OFFSET = "147456"
+FIP_OFFSET = "475136"
+KERNEL_OFFSET = "2572288"
+
 do_sign_images() {
     # Sign TF-A BL2
     sign_host_image ${RECIPE_SYSROOT}/firmware/${TFA_BL2_BINARY} \
@@ -184,11 +78,21 @@ do_sign_images[depends] = "\
     fiptool-native:do_populate_sysroot \
     "
 
-# Create an empty dummy payload file required for capsule generation
-create_dummy_image() {
-    touch  ${B}/dummy.bin
+# This .nopt image is not the same as the one which is generated by meta-arm/meta-arm/classes/wic_nopt.bbclass.
+# The meta-arm/meta-arm/classes/wic_nopt.bbclass removes the partition table from the wic image, but keeps the
+# second bank. This function creates a no-partition image with only the first bank.
+create_nopt_image() {
+    dd conv=notrunc bs=1 if=${DEPLOY_DIR_IMAGE}/bl2_signed.bin of=${B}/${MACHINE}_image.nopt
+    dd conv=notrunc bs=1 if=${DEPLOY_DIR_IMAGE}/tfm_s_signed.bin of=${B}/${MACHINE}_image.nopt seek=${TFM_OFFSET}
+    dd conv=notrunc bs=1 if=${DEPLOY_DIR_IMAGE}/signed_fip-corstone1000.bin of=${B}/${MACHINE}_image.nopt seek=${FIP_OFFSET}
+    dd conv=notrunc bs=1 if=${DEPLOY_DIR_IMAGE}/Image.gz-initramfs-${MACHINE}.bin of=${B}/${MACHINE}_image.nopt seek=${KERNEL_OFFSET}
+}
+do_image_uefi_capsule[depends] += " linux-yocto:do_deploy"
+do_image_uefi_capsule[mcdepends] += " ${@bb.utils.contains('BBMULTICONFIG', 'firmware', 'mc::firmware:linux-yocto:do_deploy', '', d)}"
+do_image_uefi_capsule[prefuncs] += "create_nopt_image"
+
+do_deploy() {
+    install -m 0755 ${B}/${MACHINE}_image.nopt  ${DEPLOYDIR}
 }
 
-do_image_uefi_capsule[depends] += " linux-yocto:do_deploy corstone1000-flash-firmware-image:do_sign_images"
-do_image_uefi_capsule[mcdepends] += " ${@bb.utils.contains('BBMULTICONFIG', 'firmware', 'mc::firmware:linux-yocto:do_deploy mc::firmware:corstone1000-flash-firmware-image:do_sign_images', '', d)}"
-do_image_uefi_capsule[prefuncs] += "create_dummy_image"
+addtask deploy after do_image_uefi_capsule

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/0001-fix-zynqmp-handle-secure-SGI-at-EL1-for-OP-TEE.patch

@@ -0,0 +1,33 @@
+From f5b2fa90e0c0324f31e72429e7a7382f49a25912 Mon Sep 17 00:00:00 2001
+From: Shen Jiamin <shen_jiamin@comp.nus.edu.sg>
+Date: Wed, 24 Jul 2024 18:58:55 +0800
+Subject: [PATCH] fix(zynqmp): handle secure SGI at EL1 for OP-TEE
+
+OP-TEE requires SGIs to be handled at S-EL1. The
+Makefile was not properly setting the flag
+GICV2_G0_FOR_EL3 to 0 when the SPD is OP-TEE.
+
+Change-Id: I256afa37ddf4ad4a154c43d51807de670c3689bb
+Signed-off-by: Shen Jiamin <shen_jiamin@comp.nus.edu.sg>
+---
+ plat/xilinx/zynqmp/platform.mk | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+Upstream-Status: Backport
+
+diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
+index c340009d0..22eceb621 100644
+--- a/plat/xilinx/zynqmp/platform.mk
++++ b/plat/xilinx/zynqmp/platform.mk
+@@ -21,7 +21,7 @@ ENABLE_LTO := 1
+ EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
+ 
+ # pncd SPD requires secure SGI to be handled at EL1
+-ifeq (${SPD}, $(filter ${SPD},pncd tspd))
++ifeq (${SPD}, $(filter ${SPD},pncd tspd opteed))
+ ifeq (${ZYNQMP_WDT_RESTART},1)
+ $(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible")
+ endif
+-- 
+2.34.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/0001-qemu_measured_boot.c-ignore-TPM-error-and-continue-w.patch

@@ -0,0 +1,33 @@
+From b91c651e6d596cfe27448b19c8fb2f1168493827 Mon Sep 17 00:00:00 2001
+From: Mikko Rapeli <mikko.rapeli@linaro.org>
+Date: Mon, 15 Jan 2024 09:26:56 +0000
+Subject: [PATCH] qemu_measured_boot.c: ignore TPM error and continue with boot
+
+If firmware is configured with TPM support but it's missing
+on HW, e.g. swtpm not started and/or configured with qemu,
+then continue booting. Missing TPM is not a fatal error.
+Enables testing boot without TPM device to see that
+missing TPM is detected further up the SW stack and correct
+fallback actions are taken.
+
+Upstream-Status: Pending
+
+Signed-off-by: Mikko Rapeli <mikko.rapeli@linaro.org>
+---
+ plat/qemu/qemu/qemu_measured_boot.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/plat/qemu/qemu/qemu_measured_boot.c b/plat/qemu/qemu/qemu_measured_boot.c
+index 76a4da17e6a9..ec7f44d3720d 100644
+--- a/plat/qemu/qemu/qemu_measured_boot.c
++++ b/plat/qemu/qemu/qemu_measured_boot.c
+@@ -80,7 +80,8 @@ void bl2_plat_mboot_finish(void)
+ 		 * Note: In QEMU platform, OP-TEE uses nt_fw_config to get the
+ 		 * secure Event Log buffer address.
+ 		 */
+-		panic();
++		ERROR("Ignoring TPM errors, continuing without\n");
++		return;
+ 	}
+ 
+ 	/* Copy Event Log to Non-secure memory */

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-fix-corstone1000-pass-spsr-value-explicitly.patch

@@ -0,0 +1,32 @@
+From d70a07562d3b0a7b4441922fd3ce136565927d04 Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Wed, 21 Feb 2024 07:57:36 +0000
+Subject: [PATCH] fix(corstone1000): pass spsr value explicitly
+
+Passes spsr value for BL32 (OPTEE) explicitly between different boot
+stages.
+
+Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30116/2]
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+---
+ .../corstone1000/common/corstone1000_bl2_mem_params_desc.c     | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
+index fe521a9fa..2cc096f38 100644
+--- a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
++++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
+@@ -72,7 +72,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ 			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+ 		.ep_info.pc = BL33_BASE,
+-
++		.ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
++				       DISABLE_ALL_EXCEPTIONS),
+ 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ 			VERSION_2, image_info_t, 0),
+ 		.image_info.image_base = BL33_BASE,
+-- 
+2.25.1
+
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-plat-corstone1000-add-Cortex-A320-support.patch

@@ -1,241 +0,0 @@
-From 977f06e10e549d01a641a62a1d4850a06d6f0df4 Mon Sep 17 00:00:00 2001
-From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
-Date: Thu, 7 Aug 2025 10:05:02 +0000
-Subject: [PATCH] plat: corstone1000: add Cortex-A320 support
-
-Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on
-Corstone-1000 while keeping Cortex-A35 as the default. When the
-define is enabled, the build switches from `cortex_a35.S` to
-`cortex_a320.S`, maintaining compatibility with existing A35-based
-designs.
-
-Also add Normal-World mappings for the Ethos-U85 NPU and its SRAM
-on Cortex-A320 platforms so U-Boot and other non-secure software
-can safely access these regions:
-
-* **Ethos-U85 registers**: base `0x1A050000`, size `0x00004000` (16 KB),
-  attrs `MT_DEVICE | MT_RW | MT_NS`
-* **Non-secure SRAM**: base `0x02400000`, size `0x00400000` (4 MB),
-  attrs `MT_MEMORY | MT_RW | MT_NS`
-
-Enable GICv3 with GIC-600 when building for Cortex-A320 (retain
-GICv2/GIC-400 for Cortex-A35):
-
-* Update `plat_my_core_pos()` and `plat_arm_calc_core_pos()` to use
-  the Cortex-A320 MPIDR_EL1 affinity layout.
-* Add an A320-specific core-position routine in assembly guarded by
-  `CORSTONE1000_CORTEX_A320`.
-* Switch to the GICv3 driver with GIC-600 extensions: update GIC base
-  addresses, use GICv3 APIs, and set `USE_GIC_DRIVER=3`,
-  `GICV3_SUPPORT_GIC600=1`, `GIC_ENABLE_V4_EXTN=1`.
-
-These changes prepare the platform for Cortex-A320 integration and
-ensure correct GIC configuration and secondary-core bring-up, while
-preserving A35 behavior.
-
-Upstream-Status: Submitted (https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/45729)
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
-Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
-Signed-off-by: Michael Safwat <michael.safwat@arm.com>
----
- .../common/corstone1000_helpers.S             | 35 ++++++++++++++++++-
- .../corstone1000/common/corstone1000_plat.c   |  4 +++
- .../corstone1000/common/corstone1000_pm.c     |  8 +++++
- .../common/include/platform_def.h             | 28 ++++++++++++++-
- plat/arm/board/corstone1000/platform.mk       | 11 ++++++
- 5 files changed, 84 insertions(+), 2 deletions(-)
-
-diff --git a/plat/arm/board/corstone1000/common/corstone1000_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
-index a4ca9fe98..665dbc61a 100644
---- a/plat/arm/board/corstone1000/common/corstone1000_helpers.S
-+++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
-@@ -1,5 +1,5 @@
- /*
-- * Copyright (c) 2021-2024 Arm Limited and Contributors. All rights reserved.
-+ * Copyright (c) 2021-2025 Arm Limited and Contributors. All rights reserved.
-  *
-  * SPDX-License-Identifier: BSD-3-Clause
-  */
-@@ -13,6 +13,39 @@
- 	.globl	plat_is_my_cpu_primary
- 	.globl	plat_arm_calc_core_pos
- 
-+#ifdef CORSTONE1000_CORTEX_A320
-+	.globl	plat_my_core_pos
-+
-+func plat_my_core_pos
-+	mrs	x0, mpidr_el1
-+	b	plat_arm_calc_core_pos
-+endfunc plat_my_core_pos
-+
-+func plat_arm_calc_core_pos
-+	/* Aff0 is always 0 for Cortex-A320
-+	MPIDR format: https://developer.arm.com/documentation/109551/0001/AArch64-registers/AArch64-Identification-registers-summary/MPIDR-EL1--Multiprocessor-Affinity-Register?lang=en
-+	*/
-+	/* Extract Aff1 (core ID) */
-+	ubfx    x1, x0, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
-+
-+	/* Extract Aff2 (cluster lower bits) */
-+	ubfx    x2, x0, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
-+
-+	/* Extract Aff3 (cluster upper bits) */
-+	ubfx    x3, x0, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
-+
-+	/* cluster_id = (Aff3 << 8) | Aff2 */
-+	lsl     x3, x3, #MPIDR_AFFINITY_BITS
-+	orr     x3, x3, x2
-+
-+	/* core_pos = core_id + (cluster_id * FVP_MAX_CPUS_PER_CLUSTER) */
-+	mov	x4, #CORSTONE1000_MAX_CPUS_PER_CLUSTER
-+	madd	x0, x3, x4, x1
-+
-+	ret
-+endfunc plat_arm_calc_core_pos
-+#endif
-+
- 	/* --------------------------------------------------------------------
- 	 * void plat_secondary_cold_boot_setup (void);
- 	 *
-diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
-index e388c82f3..d34e80b29 100644
---- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
-@@ -26,6 +26,10 @@ const mmap_region_t plat_arm_mmap[] = {
- 	ARM_MAP_NS_DRAM1,
- 	CORSTONE1000_MAP_DEVICE,
- 	CORSTONE1000_EXTERNAL_FLASH,
-+#ifdef CORSTONE1000_CORTEX_A320
-+	ARM_MAP_ETHOS_U85,
-+	ARM_MAP_NONSECURE_SRAM,
-+#endif
- 	{0}
- };
- 
-diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
-index ac808873b..a87697e97 100644
---- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
-@@ -8,7 +8,11 @@
- #include <plat/arm/common/plat_arm.h>
- #include <platform_def.h>
- #include <plat/common/platform.h>
-+#ifdef CORSTONE1000_CORTEX_A320
-+#include <drivers/arm/gicv3.h>
-+#else
- #include <drivers/arm/gicv2.h>
-+#endif
- /*******************************************************************************
-  * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
-  * platform layer will take care of registering the handlers with PSCI.
-@@ -24,7 +28,11 @@ static void corstone1000_system_reset(void)
- 	 * Disable GIC CPU interface to prevent pending interrupt
- 	 * from waking up the AP from WFI.
- 	 */
-+#ifdef CORSTONE1000_CORTEX_A320
-+	gicv3_cpuif_disable(plat_my_core_pos());
-+#else
- 	gicv2_cpuif_disable();
-+#endif
- 
- 	/* Flush and invalidate data cache */
- 	dcsw_op_all(DCCISW);
-diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
-index caf3d462f..ee0babbf8 100644
---- a/plat/arm/board/corstone1000/common/include/platform_def.h
-+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
-@@ -1,5 +1,5 @@
- /*
-- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
-+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
-  *
-  * SPDX-License-Identifier: BSD-3-Clause
-  */
-@@ -112,12 +112,19 @@
- #define ARM_SHARED_RAM_SIZE	(SZ_8K)  /* 8 KB */
- #define ARM_SHARED_RAM_BASE	ARM_TRUSTED_SRAM_BASE
- 
-+#ifdef CORSTONE1000_CORTEX_A320
-+#define TOTAL_SECURE_SRAM_SIZE		(SZ_4M)
-+#define TOTAL_NONSECURE_SRAM_SIZE	(SZ_4M)
-+#define PLAT_ARM_TRUSTED_SRAM_SIZE	(TOTAL_SECURE_SRAM_SIZE - \
-+					 ARM_SHARED_RAM_SIZE)
-+#else
- /* The remaining Trusted SRAM is used to load the BL images */
- #define TOTAL_SRAM_SIZE		(SZ_4M)  /* 4 MB */
- 
- 
- #define PLAT_ARM_TRUSTED_SRAM_SIZE	(TOTAL_SRAM_SIZE - \
- 					 ARM_SHARED_RAM_SIZE)
-+#endif
- 
- #define PLAT_ARM_MAX_BL2_SIZE	(180 * SZ_1K)  /* 180 KB */
- 
-@@ -209,8 +216,13 @@
- #define MAX_IO_BLOCK_DEVICES	1
- 
- /* GIC related constants */
-+#ifdef CORSTONE1000_CORTEX_A320
-+#define PLAT_ARM_GICD_BASE	0x1C000000
-+#define PLAT_ARM_GICR_BASE	0x1C040000
-+#else
- #define PLAT_ARM_GICD_BASE	0x1C010000
- #define PLAT_ARM_GICC_BASE	0x1C02F000
-+#endif
- 
- /* MHUv2 Secure Channel receiver and sender */
- #define PLAT_SDK700_MHU0_SEND	0x1B800000
-@@ -335,6 +347,20 @@
- 					CORSTONE1000_DEVICE_BASE, \
- 					CORSTONE1000_DEVICE_SIZE, \
- 					MT_DEVICE | MT_RW | MT_SECURE)
-+#ifdef CORSTONE1000_CORTEX_A320
-+#define ARM_ETHOS_U85_BASE		UL(0x1A050000)
-+#define ARM_ETHOS_U85_SIZE		UL(0x4000)
-+#define ARM_MAP_ETHOS_U85		MAP_REGION_FLAT( \
-+					ARM_ETHOS_U85_BASE, \
-+					ARM_ETHOS_U85_SIZE, \
-+					MT_DEVICE | MT_RW | MT_NS)
-+
-+#define ARM_NONSECURE_SRAM_BASE		(ARM_TRUSTED_SRAM_BASE + TOTAL_SECURE_SRAM_SIZE)
-+#define ARM_MAP_NONSECURE_SRAM		MAP_REGION_FLAT( \
-+					ARM_NONSECURE_SRAM_BASE, \
-+					TOTAL_NONSECURE_SRAM_SIZE, \
-+					MT_MEMORY | MT_RW | MT_NS)
-+#endif
- 
- #define ARM_IRQ_SEC_PHY_TIMER	29
- 
-diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
-index 65be9c1f5..fe3e94865 100644
---- a/plat/arm/board/corstone1000/platform.mk
-+++ b/plat/arm/board/corstone1000/platform.mk
-@@ -9,7 +9,14 @@ ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
-         $(error TARGET_PLATFORM must be fpga or fvp)
- endif
- 
-+ifdef CORSTONE1000_CORTEX_A320
-+CORSTONE1000_CPU_LIBS	+=lib/cpus/aarch64/cortex_a320.S
-+$(eval $(call add_define,CORSTONE1000_CORTEX_A320))
-+GIC_ENABLE_V4_EXTN		:= 1
-+GICV3_SUPPORT_GIC600		:= 1
-+else
- CORSTONE1000_CPU_LIBS	+=lib/cpus/aarch64/cortex_a35.S
-+endif
- 
- PLAT_INCLUDES		:=	-Iplat/arm/board/corstone1000/common/include	\
- 				-Iplat/arm/board/corstone1000/include		\
-@@ -43,7 +50,11 @@ $(eval $(call add_define,CORSTONE1000_FVP_MULTICORE))
- endif
- endif
- 
-+ifdef CORSTONE1000_CORTEX_A320
-+USE_GIC_DRIVER			:=	3
-+else
- USE_GIC_DRIVER			:=	2
-+endif
- 
- BL2_SOURCES		+=	plat/arm/board/corstone1000/common/corstone1000_security.c		\
- 				plat/arm/board/corstone1000/common/corstone1000_err.c		\
--- 
-2.50.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch

@@ -0,0 +1,92 @@
+From 19600e6718e1a5b2ac8ec27d471acdafce0e433e Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Thu, 25 Apr 2024 11:30:58 +0100
+Subject: [PATCH] fix(corstone1000): remove unused NS_SHARED_RAM region
+
+After enabling additional features in Trusted Services, the size of BL32 image
+(OP-TEE + Trusted Services SPs) is larger now. To create more space in secure RAM 
+for BL32 image, this patch removes NS_SHARED_RAM region which is not currently used by
+corstone1000 platform.
+
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30117/2]
+---
+ .../corstone1000/common/corstone1000_plat.c   |  1 -
+ .../common/include/platform_def.h             | 19 +------------------
+ 2 files changed, 1 insertion(+), 19 deletions(-)
+
+diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
+index ed3801caa..a9475859a 100644
+--- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
++++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
+@@ -23,7 +23,6 @@
+ 
+ const mmap_region_t plat_arm_mmap[] = {
+ 	ARM_MAP_SHARED_RAM,
+-	ARM_MAP_NS_SHARED_RAM,
+ 	ARM_MAP_NS_DRAM1,
+ 	CORSTONE1000_MAP_DEVICE,
+ 	CORSTONE1000_EXTERNAL_FLASH,
+diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
+index 442d187f0..18fce4486 100644
+--- a/plat/arm/board/corstone1000/common/include/platform_def.h
++++ b/plat/arm/board/corstone1000/common/include/platform_def.h
+@@ -90,9 +90,6 @@
+  *	partition size: 176 KB
+  *	content: BL2
+  *
+- * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
+- *	partition size: 512 KB
+- *	content: BL33 (u-boot)
+  */
+ 
+ /* DDR memory */
+@@ -117,11 +114,7 @@
+ /* The remaining Trusted SRAM is used to load the BL images */
+ #define TOTAL_SRAM_SIZE		(SZ_4M)  /* 4 MB */
+ 
+-/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */
+-#define ARM_NS_SHARED_RAM_SIZE	(512 * SZ_1K)
+-
+ #define PLAT_ARM_TRUSTED_SRAM_SIZE	(TOTAL_SRAM_SIZE - \
+-					 ARM_NS_SHARED_RAM_SIZE - \
+ 					 ARM_SHARED_RAM_SIZE)
+ 
+ #define PLAT_ARM_MAX_BL2_SIZE	(180 * SZ_1K)  /* 180 KB */
+@@ -160,11 +153,6 @@
+ 
+ /* NS memory */
+ 
+-/* The last 512KB of the SRAM is allocated as shared memory */
+-#define ARM_NS_SHARED_RAM_BASE	(ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \
+-				 (PLAT_ARM_MAX_BL31_SIZE + \
+-				  PLAT_ARM_MAX_BL32_SIZE))
+-
+ #define BL33_BASE		ARM_DRAM1_BASE
+ #define PLAT_ARM_MAX_BL33_SIZE	(12 * SZ_1M)  /* 12 MB*/
+ #define BL33_LIMIT		(ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
+@@ -266,7 +254,7 @@
+ #define PLAT_ARM_TRUSTED_MAILBOX_BASE	ARM_TRUSTED_SRAM_BASE
+ #define PLAT_ARM_NSTIMER_FRAME_ID	U(1)
+ 
+-#define PLAT_ARM_NS_IMAGE_BASE		(ARM_NS_SHARED_RAM_BASE)
++#define PLAT_ARM_NS_IMAGE_BASE		(BL33_BASE)
+
+ #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
+ #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
+@@ -295,11 +283,6 @@
+ 				ARM_SHARED_RAM_SIZE, \
+ 				MT_MEMORY | MT_RW | MT_SECURE)
+ 
+-#define ARM_MAP_NS_SHARED_RAM	MAP_REGION_FLAT( \
+-				ARM_NS_SHARED_RAM_BASE, \
+-				ARM_NS_SHARED_RAM_SIZE, \
+-				MT_MEMORY | MT_RW | MT_NS)
+-
+ #define ARM_MAP_NS_DRAM1	MAP_REGION_FLAT( \
+ 				ARM_NS_DRAM1_BASE, \
+ 				ARM_NS_DRAM1_SIZE, \
+-- 
+2.25.1
+
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch

@@ -0,0 +1,46 @@
+From 37f92eeb4361626072e690adb3b0bb20db7c2fca Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Wed, 15 May 2024 13:54:51 +0100
+Subject: [PATCH] fix(corstone1000): clean the cache and disable interrupt
+ before system reset
+
+Corstone1000 does not properly clean the cache and disable gic interrupts
+before the reset. This causes a race condition especially in FVP after reset.
+This adds proper sequence before resetting the platform.
+
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/30118/2]
+---
+ plat/arm/board/corstone1000/common/corstone1000_pm.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
+index 4b0a791e7..a52e945bf 100644
+--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
++++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
+@@ -7,6 +7,7 @@
+ #include <lib/psci/psci.h>
+ #include <plat/arm/common/plat_arm.h>
+ #include <platform_def.h>
++#include <drivers/arm/gicv2.h>
+ /*******************************************************************************
+  * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
+  * platform layer will take care of registering the handlers with PSCI.
+@@ -18,6 +19,14 @@ static void __dead2 corstone1000_system_reset(void)
+ 	uint32_t volatile * const watchdog_ctrl_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_CTRL_REG;
+ 	uint32_t volatile * const watchdog_val_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_VAL_REG;
+ 
++	/* Flush and invalidate data cache */
++	dcsw_op_all(DCCISW);
++	/*
++	 * Disable GIC CPU interface to prevent pending interrupt
++	 * from waking up the AP from WFI.
++	 */
++	gicv2_cpuif_disable();
++
+ 	*(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL;
+ 	*watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE;
+ 	while (1) {
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch

@@ -0,0 +1,161 @@
+From dcc9cf5111c41edc691f007bd97548d96f5efddb Mon Sep 17 00:00:00 2001
+From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
+Date: Thu, 9 May 2024 16:59:34 +0000
+Subject: [PATCH] feat(corstone1000): add multicore support for fvp
+
+This changeset adds the multicore support for the Corstone-1000 FVP.
+It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
+for the secondary cores.
+
+Upstream-Status: Backport [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/29176]
+Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
+---
+ .../common/corstone1000_helpers.S             | 26 +++++++++++
+ .../corstone1000/common/corstone1000_pm.c     | 43 ++++++++++++++++++-
+ .../common/include/platform_def.h             | 15 ++++++-
+ plat/arm/board/corstone1000/platform.mk       |  7 +++
+ 4 files changed, 89 insertions(+), 2 deletions(-)
+
+diff --git a/plat/arm/board/corstone1000/common/corstone1000_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
+index cbe27c3b5..90dc4fee6 100644
+--- a/plat/arm/board/corstone1000/common/corstone1000_helpers.S
++++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
+@@ -21,8 +21,34 @@
+ 	 * --------------------------------------------------------------------
+ 	 */
+ func plat_secondary_cold_boot_setup
++#if defined(CORSTONE1000_FVP_MULTICORE)
++
++	/* Calculate the address of our hold entry */
++	bl	plat_my_core_pos
++	lsl	x0, x0, #CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT
++	mov_imm	x2, CORSTONE1000_SECONDARY_CORE_HOLD_BASE
++	
++	/* Set the wait state for the secondary core */
++	mov_imm	x3, CORSTONE1000_SECONDARY_CORE_STATE_WAIT
++	str	x3, [x2, x0]
++	dmb	ish
++
++	/* Poll until the primary core signals to go  */
++poll_mailbox:
++	ldr	x1, [x2, x0]
++	cmp	x1, #CORSTONE1000_SECONDARY_CORE_STATE_WAIT
++	beq	1f
++	mov_imm	x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
++	ldr	x1, [x0]
++	br	x1
++1:
++	wfe
++	b	poll_mailbox
++#else
+ cb_panic:
+ 	b	cb_panic
++#endif
++
+ endfunc plat_secondary_cold_boot_setup
+ 
+ 	/* ---------------------------------------------------------------------
+diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
+index a52e945bf..979243317 100644
+--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
++++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
+@@ -33,10 +33,51 @@ static void __dead2 corstone1000_system_reset(void)
+ 		wfi();
+ 	}
+ }
++#if defined(CORSTONE1000_FVP_MULTICORE)
++int corstone1000_validate_ns_entrypoint(uintptr_t entrypoint)
++{
++	/*
++	 * Check if the non secure entrypoint lies within the non
++	 * secure DRAM.
++	 */
++	if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
++		return PSCI_E_SUCCESS;
++	}
++	return PSCI_E_INVALID_ADDRESS;
++}
++
++int corstone1000_pwr_domain_on(u_register_t mpidr)
++{
++	int core_index = plat_core_pos_by_mpidr(mpidr);
++	uint64_t *secondary_core_hold_base = (uint64_t *)CORSTONE1000_SECONDARY_CORE_HOLD_BASE;
+ 
++	/* Validate the core index */
++	if ((core_index < 0) || (core_index > PLATFORM_CORE_COUNT)) {
++		return PSCI_E_INVALID_PARAMS;
++	}
++	secondary_core_hold_base[core_index] = CORSTONE1000_SECONDARY_CORE_STATE_GO;
++	dsbish();
++	sev();
++
++	return PSCI_E_SUCCESS;
++}
++
++void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state)
++{
++	(void)target_state;
++	plat_arm_gic_init();
++}
++#endif
+ plat_psci_ops_t plat_arm_psci_pm_ops = {
++#if defined(CORSTONE1000_FVP_MULTICORE)
++	.pwr_domain_on = corstone1000_pwr_domain_on,
++	.pwr_domain_on_finish = corstone1000_pwr_domain_on_finish,
++	.validate_ns_entrypoint = corstone1000_validate_ns_entrypoint,
++	.system_reset = corstone1000_system_reset,
++#else
++	.validate_ns_entrypoint = NULL,
+ 	.system_reset = corstone1000_system_reset,
+-	.validate_ns_entrypoint = NULL
++#endif
+ };
+ 
+ const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
+diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
+index b9a1d43df..c4839ccf3 100644
+--- a/plat/arm/board/corstone1000/common/include/platform_def.h
++++ b/plat/arm/board/corstone1000/common/include/platform_def.h
+@@ -249,7 +249,20 @@
+  */
+ #define ARM_LOCAL_STATE_OFF	U(2)
+ 
+-#define PLAT_ARM_TRUSTED_MAILBOX_BASE	ARM_TRUSTED_SRAM_BASE
++#define PLAT_ARM_TRUSTED_MAILBOX_BASE   ARM_TRUSTED_SRAM_BASE
++
++#if defined(CORSTONE1000_FVP_MULTICORE)
++/* The secondary core entrypoint address points to bl31_warm_entrypoint
++ * and the address size is 8 bytes */
++#define CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE 	UL(0x8)
++
++#define CORSTONE1000_SECONDARY_CORE_HOLD_BASE         (PLAT_ARM_TRUSTED_MAILBOX_BASE + \
++						CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE)
++#define CORSTONE1000_SECONDARY_CORE_STATE_WAIT ULL(0)
++#define CORSTONE1000_SECONDARY_CORE_STATE_GO   ULL(1)
++#define CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT ULL(3)
++#endif
++
+ #define PLAT_ARM_NSTIMER_FRAME_ID	U(1)
+ 
+ #define PLAT_ARM_NS_IMAGE_BASE		(BL33_BASE)
+diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
+index fd08803e8..45092ace9 100644
+--- a/plat/arm/board/corstone1000/platform.mk
++++ b/plat/arm/board/corstone1000/platform.mk
+@@ -31,6 +31,13 @@ override NEED_BL31	:=	yes
+ NEED_BL32		?=	yes
+ override NEED_BL33	:=	yes
+ 
++ENABLE_MULTICORE	:=	0
++ifneq ($(filter ${TARGET_PLATFORM}, fvp),)
++ifeq (${ENABLE_MULTICORE},1)
++$(eval $(call add_define,CORSTONE1000_FVP_MULTICORE))
++endif
++endif
++
+ # Add CORSTONE1000_WITH_BL32 as a preprocessor define (-D option)
+ ifeq (${NEED_BL32},yes)
+ $(eval $(call add_define,CORSTONE1000_WITH_BL32))
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0006-feat-corstone1000-include-platform-header-file.patch

@@ -0,0 +1,28 @@
+From 8070bf4a89492727b6da3fb7bdec61748eae1d7d Mon Sep 17 00:00:00 2001
+From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
+Date: Tue, 2 Jul 2024 12:49:12 +0000
+Subject: [PATCH] fix(corstone1000): include platform header file
+
+Include platform.h file in order to remove compiler warnings
+
+Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/29727]
+Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
+---
+ plat/arm/board/corstone1000/common/corstone1000_pm.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
+index 979243317..9babe5b11 100644
+--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
++++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
+@@ -8,6 +8,7 @@
+ #include <plat/arm/common/plat_arm.h>
+ #include <platform_def.h>
+ #include <drivers/arm/gicv2.h>
++#include <plat/common/platform.h>
+ /*******************************************************************************
+  * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
+  * platform layer will take care of registering the handlers with PSCI.
+-- 
+2.34.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/tf-a-tests/0001-fix-exclude-Boot-requirement-tests-for-Corstone-1000.patch

@@ -1,33 +0,0 @@
-From 328bfd8cd95bb0973e4966dcb4e3efa05d62f3f9 Mon Sep 17 00:00:00 2001
-From: Christophe Thiblot <christophe.thiblot@arm.com>
-Date: Wed, 2 Jul 2025 15:03:55 +0000
-Subject: [PATCH] fix: exclude Boot requirement tests for Corstone-1000
-
-A test compares the value of the Generic Timer register CNTFRQ visible in
-two frames CNTBaseN and CNTCTLBase that are linked in Armv8-A and reflect
-the same value.
-    
-An issue in Corstone-1000 (errata 2142118) makes the CNTFRQ views
-inconsistents and the then test fails. There is no workaround and
-the test is skipped.
-    
-Errata: https://developer.arm.com/documentation/sden2142076/0002/?lang=en
-
-Signed-off-by: Christophe Thiblot <christophe.thiblot@arm.com>
-Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/40810]
----
- plat/arm/corstone1000/tests_to_skip.txt | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/plat/arm/corstone1000/tests_to_skip.txt b/plat/arm/corstone1000/tests_to_skip.txt
-index d937e42..afa3992 100644
---- a/plat/arm/corstone1000/tests_to_skip.txt
-+++ b/plat/arm/corstone1000/tests_to_skip.txt
-@@ -16,3 +16,4 @@ PSCI CPU Suspend in OSI mode
- PSCI STAT/for valid composite state CPU suspend
- FF-A Setup and Discovery/FF-A RXTX remap unmapped region success
- FF-A Memory Sharing/Normal World VM retrieve request into SPMC
-+Boot requirement tests
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/tf-a-tests/0002-plat-corstone1000-Add-Cortex-A320-support.patch

@@ -1,163 +0,0 @@
-From 82ca3fcf5c323aec4ce8191c349fd7e00a840e02 Mon Sep 17 00:00:00 2001
-From: Michael Safwat <michael.safwat@arm.com>
-Date: Tue, 26 Aug 2025 11:20:01 +0000
-Subject: [PATCH] plat: corstone1000: Add Cortex-A320 support
-
-Switch platform to GICv3 (GIC-600) for Corstone-1000 with Cortex-A320
-depending on CORSTONE1000_CORTEX_A320:
-    - Define GICD and GICR bases.
-    - Update the platform sources to include the GIC-V3 files.
-
-Move the NVM offset to prevent overlap with the TFTF firmware,
-which starts at 0x80000000 (TFTF_BASE).
-
-Introduce a new skip file tests_to_skip_cortex_a320 to be used when building
-TF-A-Tests with CORSTONE1000_CORTEX_A320=1. This ensures that tests which
-are not supported or cause traps on Corstone-1000 with Cortex-A320 are
-consistently skipped during execution.
-
-Skipped entries:
-    CPU extensions/AMUv1 suspend/resume
-    CPU extensions/Use trace buffer control Registers
-
-Signed-off-by: Michael Safwat <michael.safwat@arm.com>
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
-Upstream-Status: Submitted (https://review.trustedfirmware.org/c/TF-A/tf-a-tests/+/42352)
----
- plat/arm/corstone1000/corstone1000_def.h      | 12 +++++++++-
- plat/arm/corstone1000/include/platform_def.h  | 11 +++++----
- plat/arm/corstone1000/platform.mk             | 23 +++++++++++++++++++
- .../tests_to_skip_cortex_a320.txt             | 21 +++++++++++++++++
- 4 files changed, 61 insertions(+), 6 deletions(-)
- create mode 100644 plat/arm/corstone1000/tests_to_skip_cortex_a320.txt
-
-diff --git a/plat/arm/corstone1000/corstone1000_def.h b/plat/arm/corstone1000/corstone1000_def.h
-index 3e6f036a..c4fa9a3b 100644
---- a/plat/arm/corstone1000/corstone1000_def.h
-+++ b/plat/arm/corstone1000/corstone1000_def.h
-@@ -26,13 +26,23 @@
-  * GIC-400 & interrupt handling related constants
-  ******************************************************************************/
- /* GIC memory map */
-+#ifdef CORSTONE1000_CORTEX_A320
-+#define GICD_BASE	0x1C000000
-+#define GICR_BASE	0x1C040000
-+
-+/* GIC re-distributor doesn't exits on gic-600, but we still need to
-+ * provide GICC_BASE as the gic driver needs it
-+ */
-+#define GICC_BASE		0x0
-+#else
-+
- #define GICD_BASE		0x1C010000
- #define GICC_BASE		0x1C02F000
- /* GIC re-distributor doesn't exits on gic-400, but we still need to
-  * provide GICR_BASE as the gic driver needs it
-  */
- #define GICR_BASE		0x0
--
-+#endif
- /*******************************************************************************
-  * PL011 related constants
-  ******************************************************************************/
-diff --git a/plat/arm/corstone1000/include/platform_def.h b/plat/arm/corstone1000/include/platform_def.h
-index a0d6f7b3..1fc505d0 100644
---- a/plat/arm/corstone1000/include/platform_def.h
-+++ b/plat/arm/corstone1000/include/platform_def.h
-@@ -98,12 +98,13 @@
- #endif
- 
- /*
-- * USE 0x200000 DRAM offset to store TFTF data
-- *
-- * Please note that this won't be suitable for all test scenarios and
-- * for this reason some tests will be disabled in this configuration.
-+ * When USE_NVM = 0, TFTF_NVM_OFFSET marks the DRAM region
-+ * used as NVM. This region must not overlap the memory where
-+ * the TFTF image is loaded. The load address is given by
-+ * the TFTF_BASE macro. Set TFTF_NVM_OFFSET to leave enough
-+ * space for the TFTF image.
-  */
--#define TFTF_NVM_OFFSET		0x40000
-+#define TFTF_NVM_OFFSET		0x80000
- #define TFTF_NVM_SIZE		(128 * SZ_1M)	/* 128 MB */
- 
- /*******************************************************************************
-diff --git a/plat/arm/corstone1000/platform.mk b/plat/arm/corstone1000/platform.mk
-index a5a011d5..fd98724a 100644
---- a/plat/arm/corstone1000/platform.mk
-+++ b/plat/arm/corstone1000/platform.mk
-@@ -6,6 +6,19 @@
- 
- PLAT_INCLUDES	:=	-Iplat/arm/corstone1000/include/
- 
-+CORSTONE1000_CORTEX_A320   :=      0
-+ifeq (${CORSTONE1000_CORTEX_A320},1)
-+PLAT_SOURCES   :=   drivers/arm/gic/arm_gic_v2v3.c                  \
-+            drivers/arm/gic/gic_v2.c                        \
-+            drivers/arm/gic/gic_v3.c                        \
-+            drivers/arm/timer/private_timer.c               \
-+            drivers/arm/timer/system_timer.c                \
-+            plat/arm/corstone1000/plat_helpers.S            \
-+            plat/arm/corstone1000/corstone1000_pwr_state.c  \
-+            plat/arm/corstone1000/corstone1000_topology.c   \
-+            plat/arm/corstone1000/corstone1000_mem_prot.c   \
-+            plat/arm/corstone1000/plat_setup.c
-+else
- PLAT_SOURCES	:=	drivers/arm/gic/arm_gic_v2.c			\
- 			drivers/arm/gic/gic_v2.c			\
- 			drivers/arm/timer/private_timer.c		\
-@@ -15,6 +28,7 @@ PLAT_SOURCES	:=	drivers/arm/gic/arm_gic_v2.c			\
- 			plat/arm/corstone1000/corstone1000_topology.c	\
- 			plat/arm/corstone1000/corstone1000_mem_prot.c	\
- 			plat/arm/corstone1000/plat_setup.c
-+endif
- 
- PLAT_SUPPORTS_NS_RESET	:=	1
- 
-@@ -23,6 +37,15 @@ $(eval $(call assert_boolean,PLAT_SUPPORTS_NS_RESET))
- $(eval $(call add_define,TFTF_DEFINES,PLAT_SUPPORTS_NS_RESET))
- 
- FIRMWARE_UPDATE := 0
-+
-+ifeq ($(CORSTONE1000_CORTEX_A320),1)
-+$(eval $(call add_define,TFTF_DEFINES,CORSTONE1000_CORTEX_A320))
-+endif
-+
-+ifeq (${CORSTONE1000_CORTEX_A320},1)
-+PLAT_TESTS_SKIP_LIST    :=      plat/arm/corstone1000/tests_to_skip_cortex_a320.txt
-+else
- PLAT_TESTS_SKIP_LIST    :=      plat/arm/corstone1000/tests_to_skip.txt
-+endif
- 
- include plat/arm/common/arm_common.mk
-diff --git a/plat/arm/corstone1000/tests_to_skip_cortex_a320.txt b/plat/arm/corstone1000/tests_to_skip_cortex_a320.txt
-new file mode 100644
-index 00000000..87b9241d
---- /dev/null
-+++ b/plat/arm/corstone1000/tests_to_skip_cortex_a320.txt
-@@ -0,0 +1,21 @@
-+Realm payload tests
-+Realm payload boot
-+Realm payload multi CPU request
-+Realm payload Delegate and Undelegate
-+Multi CPU Realm payload Delegate and Undelegate
-+Testing delegation fails
-+Realm testing with SPM tests
-+PSCI System Suspend Validation
-+PSCI STAT/Stats test cases after system suspend
-+IRQ support in TSP/Resume preempted STD SMC after PSCI SYSTEM SUSPEND
-+PSCI SYSTEM SUSPEND stress tests
-+Timer framework Validation/Verify the timer interrupt generation
-+CPU Hotplug/CPU hotplug
-+PSCI CPU Suspend
-+PSCI CPU Suspend in OSI mode
-+PSCI STAT/for valid composite state CPU suspend
-+FF-A Setup and Discovery/FF-A RXTX remap unmapped region success
-+FF-A Memory Sharing/Normal World VM retrieve request into SPMC
-+Boot requirement tests
-+CPU extensions/AMUv1 suspend/resume
-+CPU extensions/Use trace buffer control Registers
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend

@@ -3,18 +3,4 @@
 COMPATIBLE_MACHINE:corstone1000 = "corstone1000"
 EXTRA_OEMAKE:append:corstone1000 = " DEBUG=0"
 EXTRA_OEMAKE:append:corstone1000 = " LOG_LEVEL=30"
-
-# Add Cortex-A320 specific configurations
-EXTRA_OEMAKE:append:cortexa320 = " \
-        CORSTONE1000_CORTEX_A320=1 \
-        "
 TFTF_MODE:corstone1000 = "release"
-
-FILESEXTRAPATHS:prepend:corstone1000 := "${THISDIR}/files/corstone1000/tf-a-tests:"
-SRC_URI:append:corstone1000 = " \
-        file://0001-fix-exclude-Boot-requirement-tests-for-Corstone-1000.patch \
-        "
-
-SRC_URI:append:corstone1000 = " \
-        file://0002-plat-corstone1000-Add-Cortex-A320-support.patch \
-        "

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc

@@ -5,8 +5,12 @@ COMPATIBLE_MACHINE = "(corstone1000)"
 FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:"
 SRC_URI:append = " \
 	file://0001-Fix-FF-A-version-in-SPMC-manifest.patch \
-	file://0002-plat-corstone1000-add-Cortex-A320-support.patch \
-"
+	file://0002-fix-corstone1000-pass-spsr-value-explicitly.patch \
+	file://0003-fix-corstone1000-remove-unused-NS_SHARED_RAM-region.patch \
+	file://0004-fix-corstone1000-clean-the-cache-and-disable-interru.patch \
+	file://0005-feat-corstone1000-Add-multicore-support-for-FVP-plat.patch \
+	file://0006-feat-corstone1000-include-platform-header-file.patch \
+       "
 
 TFA_DEBUG = "1"
 TFA_UBOOT ?= "1"
@@ -22,13 +26,6 @@ TFA_SPMD_SPM_AT_SEL2 = "0"
 # BL2 loads BL32 (optee). So, optee needs to be built first:
 DEPENDS += "optee-os"
 
-ENABLE_CORTEX_A35_ERRATA = " \
-    ERRATA_A35_855472=1 \
-"
-ENABLE_CORTEX_A35_ERRATA:cortexta320 = ""
-FVP_GIC_DRIVER ?= "FVP_GICV2"
-FVP_GIC_DRIVER:cortexa320 = "FVP_GICV3"
-
 # Note: Regarding the build option: LOG_LEVEL.
 # There seems to be an issue when setting it
 # to 50 (LOG_LEVEL_VERBOSE), where the kernel
@@ -53,31 +50,9 @@ EXTRA_OEMAKE:append = " \
                         NR_OF_IMAGES_IN_FW_BANK=4 \
                         COT=tbbr \
                         ARM_ROTPK_LOCATION=devel_rsa  \
-                        ${ENABLE_CORTEX_A35_ERRATA} \
+                        ERRATA_A35_855472=1 \
                         ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
                         BL32=${RECIPE_SYSROOT}/${nonarch_base_libdir}/firmware/tee-pager_v2.bin \
-                        FVP_USE_GIC_DRIVER=${FVP_GIC_DRIVER} \
+                        FVP_USE_GIC_DRIVER=FVP_GICV2 \
                         "
 EXTRA_OEMAKE:append:corstone1000-fvp = "${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', ' ENABLE_MULTICORE=1', '', d)}"
-
-# Add Cortex-A320 specific configurations
-EXTRA_OEMAKE:append:cortexa320 = " \
-    CORSTONE1000_CORTEX_A320=1 \
-    HW_ASSISTED_COHERENCY=1 \
-    USE_COHERENT_MEM=0 \
-    CTX_INCLUDE_AARCH32_REGS=0 \
-    ENABLE_FEAT_HCX=1 \
-    ENABLE_FEAT_FGT=1 \
-    ENABLE_FEAT_ECV=1 \
-    ENABLE_FEAT_MTE2=1 \
-    ENABLE_FEAT_AMU=1 \
-    ENABLE_FEAT_CSV2_2=1 \
-    ENABLE_SVE_FOR_NS=1 \
-    ENABLE_SVE_FOR_SWD=1 \
-"
-
-# If GENERATE_COT is set, then TF-A will try to use local poetry install
-# to run the python cot-dt2c command.  Disable the local poetry and use
-# the provided cot-dt2c.
-EXTRA_OEMAKE += "POETRY=''"
-DEPENDS += "cot-dt2c-native"

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-fvp-base.inc

@@ -4,10 +4,10 @@
 # Armv8-A Base Platform FVP
 #
 
-FILESEXTRAPATHS:prepend := "${THISDIR}/files/:${THISDIR}/files/fvp-base:"
+FILESEXTRAPATHS:prepend := "${THISDIR}/files/:${THISDIR}/files/fvp-base"
 
 SRC_URI:append = " \
-    file://optee_spmc_maifest.dts;subdir=${BB_GIT_DEFAULT_DESTSUFFIX}/plat/arm/board/fvp/fdts \
+    file://optee_spmc_maifest.dts;subdir=git/plat/arm/board/fvp/fdts \
 "
 
 # OP-TEE SPMC related configuration
@@ -46,9 +46,6 @@ BL32 = "${@oe.utils.conditional('SPMC_IS_OPTEE', '1',\
 EXTRA_OEMAKE += "${@oe.utils.conditional('SPMC_IS_OPTEE', '1', \
                 ' BL32=${BL32}', '', d)}"
 
-# Enable memory safety in TF-A if machine supports it.
-EXTRA_OEMAKE += "${@bb.utils.contains('MACHINE_FEATURES', 'arm-branch-protection', ' BRANCH_PROTECTION=1', '', d)}"
-
 # Generic configuration
 COMPATIBLE_MACHINE = "fvp-base"
 TFA_PLATFORM = "fvp"
@@ -63,8 +60,8 @@ TFA_BUILD_TARGET = "bl1 bl2 bl31 dtbs fip"
 
 EXTRA_OEMAKE += "FVP_DT_PREFIX=fvp-base-gicv3-psci-1t FVP_USE_GIC_DRIVER=FVP_GICV3"
 
-# Set the ISA to fvp-base conf file and disable AArch32 system registers
-EXTRA_OEMAKE += "ARM_ARCH_MAJOR=${ARM_ISA_MAJOR} ARM_ARCH_MINOR=${ARM_ISA_MINOR} CTX_INCLUDE_AARCH32_REGS=0"
+# Our fvp-base machine explicitly has v8.4 cores
+EXTRA_OEMAKE += "ARM_ARCH_MAJOR=8 ARM_ARCH_MINOR=4"
 
 # If GENERATE_COT is set, then tf-a will try to use local poetry install
 # to run the python cot-dt2c command.  Disable the local poetry and use

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-sgi575.inc

@@ -17,10 +17,3 @@ EXTRA_OEMAKE += "TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rs
 # the provided cot-dt2c.
 EXTRA_OEMAKE += "POETRY=''"
 DEPENDS += "cot-dt2c-native"
-
-# When compiling tf-a with clang, multiple errors are being seen in the
-# ASM files:
-#   error: instruction requires: fp-armv8
-# Given that this is platform is EOLed, forcing it to use GCC and not
-# reporting upstream
-TOOLCHAIN = "gcc"

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.11.0.bb

@@ -0,0 +1,20 @@
+require recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc
+
+# TF-A v2.11.0
+SRCREV_tfa = "f2735ebccf5173f74c0458736ec526276106097e"
+SRCBRANCH = "master"
+
+LIC_FILES_CHKSUM += "file://docs/license.rst;md5=b5fbfdeb6855162dded31fadcd5d4dc5"
+
+# in TF-A src, docs/getting_started/prerequisites.rst lists the expected version mbedtls
+# mbedtls-3.6.0
+SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls;branch=main"
+SRCREV_mbedtls = "2ca6c285a0dd3f33982dd57299012dacab1ff206"
+
+LIC_FILES_CHKSUM_MBEDTLS = "file://mbedtls/LICENSE;md5=379d5819937a6c2f1ef1630d341e026d"
+
+# continue to boot also without TPM
+SRC_URI += "\
+    file://0001-qemu_measured_boot.c-ignore-TPM-error-and-continue-w.patch \
+    file://0001-fix-zynqmp-handle-secure-SGI-at-EL1-for-OP-TEE.patch \
+"

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0001-Platform-Corstone1000-Align-capsule-UEFI-structs.patch

@@ -0,0 +1,97 @@
+From 6ac0d4ce58c1a957c5f086e8c32268fdfc3ea531 Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <emekcan.aras@arm.com>
+Date: Thu, 26 Oct 2023 11:46:04 +0100
+Subject: [PATCH 1/9] Platform: Corstone1000: Align capsule UEFI structs
+
+The UEFI capsules are generated using the U-Boot mkeficapsule tool.
+U-Boot uses packed struct for the UEFI and FMP structures, see [1].
+The structs have to be aligned in the TF-M side parser to avoid
+crashes.
+
+[1] https://github.com/u-boot/u-boot/blob/u-boot-2023.07.y/include/efi_api.h#L245
+
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [6ac0d4ce58c1a957c5f086e8c32268fdfc3ea531]
+---
+ .../fw_update_agent/uefi_capsule_parser.c       | 17 +++++++++--------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c
+index c706c040a..44566e08d 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c
++++ b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c
+@@ -1,10 +1,11 @@
+ /*
+- * Copyright (c) 2021, Arm Limited. All rights reserved.
++ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  *
+  */
+ 
++#include "cmsis_compiler.h"
+ #include "uefi_capsule_parser.h"
+ #include "fwu_agent.h"
+ #include <string.h>
+@@ -29,21 +30,21 @@ Update Capsule Structure (UEFI spec 2.9 1004)
+             Payload n (item_offset[embedded_driver_count + payload_item_count -1])
+ */
+ 
+-typedef struct {
++typedef __PACKED_STRUCT {
+     struct efi_guid         capsule_guid;
+     uint32_t                header_size;
+     uint32_t                flags;
+     uint32_t                capsule_image_size;
+ } efi_capsule_header_t;
+ 
+-typedef struct {
++typedef __PACKED_STRUCT {
+     uint32_t                version;
+     uint16_t                embedded_driver_count;
+     uint16_t                payload_item_count;
+     uint64_t                item_offset_list[];
+ } efi_firmware_management_capsule_header_t;
+ 
+-typedef struct {
++typedef __PACKED_STRUCT {
+     uint32_t                version;
+     struct efi_guid         update_image_type_id;
+     uint8_t                 update_image_index;
+@@ -54,7 +55,7 @@ typedef struct {
+     uint64_t                image_capsule_support; //introduced in v3
+ } efi_firmware_management_capsule_image_header_t;
+ 
+-typedef struct {
++typedef __PACKED_STRUCT {
+     uint32_t                signature;
+     uint32_t                header_size;
+     uint32_t                fw_version;
+@@ -63,20 +64,20 @@ typedef struct {
+ 
+ #define ANYSIZE_ARRAY 0
+ 
+-typedef struct {
++typedef __PACKED_STRUCT {
+     uint32_t                dwLength;
+     uint16_t                wRevision;
+     uint16_t                wCertificateType;
+     uint8_t                 bCertificate[ANYSIZE_ARRAY];
+ } WIN_CERTIFICATE;
+ 
+-typedef struct {
++typedef __PACKED_STRUCT {
+     WIN_CERTIFICATE         hdr;
+     struct efi_guid         cert_type;
+     uint8_t                 cert_data[ANYSIZE_ARRAY];
+ } win_certificate_uefi_guid_t;
+ 
+-typedef struct {
++typedef __PACKED_STRUCT {
+     uint64_t                    monotonic_count;
+     win_certificate_uefi_guid_t   auth_info;
+ } efi_firmware_image_authentication_t;
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0002-Platform-Corstone1000-Fix-BL1-compiler-switch-and-re.patch

@@ -1,46 +0,0 @@
-From 162d46ac77be0ad3e7cf1840fa05578cce084a68 Mon Sep 17 00:00:00 2001
-From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
-Date: Wed, 13 Aug 2025 14:31:53 +0000
-Subject: [PATCH 2/7] Platform: Corstone1000: Fix BL1 compiler switch and
- regression test failure
-
-Introduce a dedicated preprocessor definition (`BL1_BUILD`) added only to the
-platform_bl1_1 target. This ensures that #if BL1 checks are evaluated correctly
-based on the actual build configuration.
-
-Signed-off-by: Michael Safwat <michael.safwat@arm.com>
-Signed-off-by: Bence Balogh <bence.balogh@arm.com>
-Upstream-Status: Backport [f25649cc0de56f360069c6128670f7533ba5e14d]
----
- platform/ext/target/arm/corstone1000/CMakeLists.txt | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
-diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-index 4d165ed9c..3573c8492 100644
---- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-@@ -146,6 +146,7 @@ target_sources(platform_s
-         rse_comms_permissions_hal.c
-         mem_check_v6m_v7m_hal.c
-         ${PLATFORM_DIR}/ext/common/mem_check_v6m_v7m.c
-+        platform.c
- )
- 
- if (PLATFORM_IS_FVP)
-@@ -215,6 +216,13 @@ target_compile_definitions(platform_bl1_1
-         $<$<BOOL:${CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING}>:CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING>
-         MBEDTLS_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default.h"
-         MBEDTLS_PSA_CRYPTO_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/crypto_config_default.h"
-+
-+        # This definition is only added to the bl1_main target. There are
-+        # files that are shared between the BL1 and TFM_S targets. This flag
-+        # can be used if the BL1 target needs different implementation than
-+        # the TFM_S target.
-+        BL1_BUILD
-+
- )
- 
- target_include_directories(platform_bl1_1_interface
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0002-Platform-Corstone1000-Fix-NV-counter-writing.patch

@@ -0,0 +1,69 @@
+From 47c54e8e79df52f40057c3d4be9411447d2787c2 Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Wed, 21 Feb 2024 07:44:25 +0000
+Subject: [PATCH 2/9] Platform: Corstone1000: Fix NV counter writing
+
+The BL1 writes the PLAT_NV_COUNTER_BL1_0 NV counter directly without
+updating the private metadata. Because of this the update_nv_counters()
+function should not update the PLAT_NV_COUNTER_BL1_0 from the metadata.
+
+The tfm_plat_set_nv_counter() had a typo and wrote the
+priv_metadata->nv_counter[FWU_BL2_NV_COUNTER] to every NV counter.
+
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [47c54e8e79df52f40057c3d4be9411447d2787c2]
+---
+ .../corstone1000/fw_update_agent/fwu_agent.c   | 18 +++++++++++-------
+ 1 file changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index 9a9926a3d..b2f31e166 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
++++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -1120,12 +1120,13 @@ static enum fwu_agent_error_t update_nv_counters(
+ 
+     FWU_LOG_MSG("%s: enter\n\r", __func__);
+ 
+-    for (int i = 0; i <= FWU_MAX_NV_COUNTER_INDEX; i++) {
++    /* The FWU_BL2_NV_COUNTER (0) is not mirrored in the private metadata. It is
++     * directly updated in the bl1_2_validate_image_at_addr() function, in
++     * tfm/bl1/bl1_2/main.c.
++     * Because of this, the index starts from FWU_TFM_NV_COUNTER (1). */
++    for (int i = FWU_TFM_NV_COUNTER; i <= FWU_MAX_NV_COUNTER_INDEX; i++) {
+ 
+         switch (i) {
+-            case FWU_BL2_NV_COUNTER:
+-                tfm_nv_counter_i = PLAT_NV_COUNTER_BL1_0;
+-                break;
+             case FWU_TFM_NV_COUNTER:
+                 tfm_nv_counter_i = PLAT_NV_COUNTER_BL2_0;
+                 break;
+@@ -1140,18 +1141,21 @@ static enum fwu_agent_error_t update_nv_counters(
+         err = tfm_plat_read_nv_counter(tfm_nv_counter_i,
+                         sizeof(security_cnt), (uint8_t *)&security_cnt);
+         if (err != TFM_PLAT_ERR_SUCCESS) {
++            FWU_LOG_MSG("%s: couldn't read NV counter\n\r", __func__);
+             return FWU_AGENT_ERROR;
+         }
+ 
+         if (priv_metadata->nv_counter[i] < security_cnt) {
++            FWU_LOG_MSG("%s: staged NV counter is smaller than current value\n\r", __func__);
+             return FWU_AGENT_ERROR;
+         } else if (priv_metadata->nv_counter[i] > security_cnt) {
+-            FWU_LOG_MSG("%s: updaing index = %u nv counter = %u->%u\n\r",
++            FWU_LOG_MSG("%s: updating index = %u nv counter = %u->%u\n\r",
+                         __func__, i, security_cnt,
+-                        priv_metadata->nv_counter[FWU_BL2_NV_COUNTER]);
++                        priv_metadata->nv_counter[i]);
+             err = tfm_plat_set_nv_counter(tfm_nv_counter_i,
+-                                    priv_metadata->nv_counter[FWU_BL2_NV_COUNTER]);
++                                    priv_metadata->nv_counter[i]);
+             if (err != TFM_PLAT_ERR_SUCCESS) {
++                FWU_LOG_MSG("%s: couldn't write NV counter\n\r", __func__);
+                 return FWU_AGENT_ERROR;
+             }
+         }
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0003-Platform-Corstone1000-Enable-firewall-in-FVP.patch

@@ -0,0 +1,177 @@
+From 4b5a9546205e484ac7f53cee369b1db9a7bf2279 Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Wed, 3 Apr 2024 13:37:40 +0100
+Subject: [PATCH 3/9] Platform: Corstone1000: Enable firewall in FVP
+
+Enables host firewall and MPU setup for FVP. It also fixes secure RAM
+configuration and disables access rights to secure RAM from normal world
+for both MPS3 and FVP.
+
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [4b5a9546205e484ac7f53cee369b1db9a7bf2279]
+---
+ .../Device/Include/platform_base_address.h    |  2 +-
+ .../arm/corstone1000/bl1/boot_hal_bl1_1.c     | 42 ++++---------------
+ .../arm/corstone1000/bl2/flash_map_bl2.c      |  2 +-
+ 3 files changed, 11 insertions(+), 35 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
+index 416f0ebcdb..101cad9e7c 100644
+--- a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
++++ b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
+@@ -67,7 +67,7 @@
+  * required by the SE are defined here */
+ #define CORSTONE1000_HOST_ADDRESS_SPACE_BASE       (0x60000000U) /* Host Address Space                */
+ #define CORSTONE1000_HOST_BIR_BASE                 (0x60000000U) /* Boot Instruction Register         */
+-#define CORSTONE1000_HOST_SHARED_RAM_BASE          (0x62000000U) /* Shared RAM                        */
++#define CORSTONE1000_HOST_TRUSTED_RAM_BASE         (0x62000000U) /* Secure RAM                        */
+ #define CORSTONE1000_HOST_XNVM_BASE                (0x68000000U) /* XNVM                              */
+ #define CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE (0x7A010000U) /* Host SCB                          */
+ #define CORSTONE1000_EXT_SYS_RESET_REG             (0x7A010310U) /* external system (cortex-M3)       */
+diff --git a/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c b/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c
+index 45d6768215..2f693d2b1b 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c
++++ b/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c
+@@ -35,7 +35,7 @@ REGION_DECLARE(Image$$, ER_DATA, $$Base)[];
+ REGION_DECLARE(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)[];
+ 
+ #define HOST_ADDRESS_SPACE_BASE         0x00000000
+-#define HOST_SHARED_RAM_BASE            0x02000000
++#define HOST_TRUSTED_RAM_BASE           0x02000000
+ #define HOST_XNVM_BASE                  0x08000000
+ #define HOST_BASE_SYSTEM_CONTROL_BASE   0x1A010000
+ #define HOST_FIREWALL_BASE              0x1A800000
+@@ -347,7 +347,7 @@ static void setup_host_firewall(void)
+ 
+     fc_pe_enable();
+ 
+-    /* CVM - Shared RAM */
++    /* CVM - Secure RAM */
+     fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_CVM);
+     fc_disable_bypass();
+     fc_pe_disable();
+@@ -355,15 +355,12 @@ static void setup_host_firewall(void)
+     fc_select_region(1);
+     fc_disable_regions();
+     fc_disable_mpe(RGN_MPE0);
+-    fc_prog_rgn(RGN_SIZE_4MB, HOST_SHARED_RAM_BASE);
++    fc_prog_rgn(RGN_SIZE_4MB, HOST_TRUSTED_RAM_BASE);
+     fc_init_mpl(RGN_MPE0);
+ 
+     mpl_rights = (RGN_MPL_ANY_MST_MASK | RGN_MPL_SECURE_READ_MASK |
+                                          RGN_MPL_SECURE_WRITE_MASK |
+-                                         RGN_MPL_SECURE_EXECUTE_MASK |
+-                                         RGN_MPL_NONSECURE_READ_MASK |
+-                                         RGN_MPL_NONSECURE_WRITE_MASK |
+-                                         RGN_MPL_NONSECURE_EXECUTE_MASK);
++                                         RGN_MPL_SECURE_EXECUTE_MASK);
+ 
+     fc_enable_mpl(RGN_MPE0, mpl_rights);
+     fc_disable_mpl(RGN_MPE0, ~mpl_rights);
+@@ -398,7 +395,9 @@ static void setup_host_firewall(void)
+ 
+     fc_pe_enable();
+ 
+-    /* Host Expansion Master 0 */
++#if !(PLATFORM_IS_FVP)
++    /* Host Expansion Master 0 (Due to the difference in the models only
++     * programming this for MPS3) */
+     fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_EXPMST0);
+     fc_disable_bypass();
+     fc_pe_disable();
+@@ -433,7 +432,6 @@ static void setup_host_firewall(void)
+     fc_enable_regions();
+     fc_rgn_lock();
+ 
+-#if !(PLATFORM_IS_FVP)
+     fc_select_region(3);
+     fc_disable_regions();
+     fc_disable_mpe(RGN_MPE0);
+@@ -461,16 +459,14 @@ static void setup_host_firewall(void)
+     fc_enable_mpe(RGN_MPE0);
+     fc_enable_regions();
+     fc_rgn_lock();
+-#endif
+ 
+     fc_pe_enable();
+ 
+-    /* Host Expansion Master 0 */
++    /* Host Expansion Master 1*/
+     fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_EXPMST1);
+     fc_disable_bypass();
+     fc_pe_disable();
+ 
+-#if !(PLATFORM_IS_FVP)
+     fc_select_region(1);
+     fc_disable_regions();
+     fc_disable_mpe(RGN_MPE0);
+@@ -484,22 +480,6 @@ static void setup_host_firewall(void)
+     fc_enable_mpe(RGN_MPE0);
+     fc_enable_regions();
+     fc_rgn_lock();
+-#else
+-    fc_select_region(1);
+-    fc_disable_regions();
+-    fc_disable_mpe(RGN_MPE0);
+-    fc_prog_rgn(RGN_SIZE_8MB, HOST_SE_SECURE_FLASH_BASE_FVP);
+-    fc_init_mpl(RGN_MPE0);
+-
+-    mpl_rights = (RGN_MPL_ANY_MST_MASK | RGN_MPL_SECURE_READ_MASK |
+-                                         RGN_MPL_SECURE_WRITE_MASK);
+-
+-    fc_enable_mpl(RGN_MPE0, mpl_rights);
+-    fc_enable_mpe(RGN_MPE0);
+-    fc_enable_regions();
+-    fc_rgn_lock();
+-#endif
+-
+     fc_pe_enable();
+ 
+     /* Always ON Host Peripherals */
+@@ -527,7 +507,6 @@ static void setup_host_firewall(void)
+     }
+ 
+     fc_pe_enable();
+-
+     /* Host System Peripherals */
+     fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_SYSPERIPH);
+     fc_disable_bypass();
+@@ -553,6 +532,7 @@ static void setup_host_firewall(void)
+     }
+ 
+     fc_pe_enable();
++#endif
+ 
+     /* Host System Peripherals */
+     fc_select((void *)CORSTONE1000_HOST_FIREWALL_BASE, COMP_DBGPERIPH);
+@@ -592,13 +572,9 @@ int32_t boot_platform_init(void)
+     if (result != ARM_DRIVER_OK) {
+ 	return 1;
+      }
+-#if !(PLATFORM_IS_FVP)
+         setup_mpu();
+-#endif
+         setup_se_firewall();
+-#if !(PLATFORM_IS_FVP)
+         setup_host_firewall();
+-#endif
+ 
+ #if defined(TFM_BL1_LOGGING) || defined(TEST_BL1_1) || defined(TEST_BL1_2)
+     stdio_init();
+diff --git a/platform/ext/target/arm/corstone1000/bl2/flash_map_bl2.c b/platform/ext/target/arm/corstone1000/bl2/flash_map_bl2.c
+index 2b1cdfa199..06cc3f0f52 100644
+--- a/platform/ext/target/arm/corstone1000/bl2/flash_map_bl2.c
++++ b/platform/ext/target/arm/corstone1000/bl2/flash_map_bl2.c
+@@ -70,7 +70,7 @@ int boot_get_image_exec_ram_info(uint32_t image_id,
+         rc = 0;
+     }
+     else if (image_id == 1 || image_id == 2) {
+-        (*exec_ram_start) = CORSTONE1000_HOST_SHARED_RAM_BASE;
++        (*exec_ram_start) = CORSTONE1000_HOST_TRUSTED_RAM_BASE;
+         (*exec_ram_size) = 0x20000000U;
+         rc = 0;
+     }
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0004-Platform-CS1000-Increase-ITS-max-asset-size.patch

@@ -0,0 +1,41 @@
+From 2a7e418afc96a9c897d3511fd47dbe596f880074 Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <emekcan.aras@arm.com>
+Date: Wed, 17 Apr 2024 11:34:45 +0000
+Subject: [PATCH 4/9] Platform: CS1000: Increase ITS max asset size
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Increases the max asset size for ITS to enable Parsec services and
+tests.
+​
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+Signed-off-by: Vikas Katariya <vikas.katariya@arm.com>
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [2a7e418afc96a9c897d3511fd47dbe596f880074]
+---
+ platform/ext/target/arm/corstone1000/config_tfm_target.h | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/config_tfm_target.h b/platform/ext/target/arm/corstone1000/config_tfm_target.h
+index 2c7341afd..9522379cd 100644
+--- a/platform/ext/target/arm/corstone1000/config_tfm_target.h
++++ b/platform/ext/target/arm/corstone1000/config_tfm_target.h
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2022, Arm Limited. All rights reserved.
++ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  *
+@@ -20,4 +20,7 @@
+ /* The maximum number of assets to be stored in the Protected Storage area. */
+ #define PS_NUM_ASSETS        20
+ 
++/* The maximum size of asset to be stored in the Internal Trusted Storage area. */
++#define ITS_MAX_ASSET_SIZE   2048
++
+ #endif /* __CONFIG_TFM_TARGET_H__ */
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0004-Platform-Corstone1000-Enable-FWU-partition.patch

@@ -1,36 +0,0 @@
-From ab1ecf0cfbbf199c4d868d2c565f7bff3f5245ee Mon Sep 17 00:00:00 2001
-From: Ali Can Ozaslan <ali.oezaslan@arm.com>
-Date: Tue, 15 Oct 2024 12:50:16 +0000
-Subject: [PATCH 4/7] Platform: Corstone1000: Enable FWU partition
-
-Enable firmware update partition for Corstone-1000 platform.
-
-Increase the necessary flags to enable firmware update partition.
-Set TFM_FWU_BOOTLOADER_LIB to use Corstone-1000 specific bootloader
-configuration. Fix linker issues caused by enablement.
-
-Upstream-Status: Backport [0107057d1411ec68e374fbd0ddc0e12abd5754ec]
-Signed-off-by: Ali Can Ozaslan <ali.oezaslan@arm.com>
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
----
- platform/ext/target/arm/corstone1000/config.cmake | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
-index 0e6297dae..e45b56b2f 100644
---- a/platform/ext/target/arm/corstone1000/config.cmake
-+++ b/platform/ext/target/arm/corstone1000/config.cmake
-@@ -55,6 +55,10 @@ set(TFM_PARTITION_CRYPTO                ON          CACHE BOOL      "Enable Cryp
- set(TFM_PARTITION_INITIAL_ATTESTATION   ON          CACHE BOOL      "Enable Initial Attestation partition")
- set(TFM_PARTITION_INTERNAL_TRUSTED_STORAGE ON       CACHE BOOL      "Enable Internal Trusted Storage partition")
- 
-+set(TFM_PARTITION_FIRMWARE_UPDATE         ON        CACHE BOOL      "Enable firmware update partition")
-+set(PLATFORM_HAS_FIRMWARE_UPDATE_SUPPORT ON         CACHE BOOL      "Wheter the platform has firmware update support")
-+set(MCUBOOT_DATA_SHARING                 ON         CACHE BOOL      "Enable Data Sharing")
-+set(TFM_FWU_BOOTLOADER_LIB                "${CMAKE_CURRENT_LIST_DIR}/bootloader/mcuboot"   CACHE STRING    "Bootloader configure file for Firmware Update partition")
- 
- if (${CMAKE_BUILD_TYPE} STREQUAL Debug OR ${CMAKE_BUILD_TYPE} STREQUAL RelWithDebInfo)
-   set(ENABLE_FWU_AGENT_DEBUG_LOGS     TRUE          CACHE BOOL      "Enable Firmware update agent debug logs.")
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0005-Platform-CS1000-Increase-RSE_COMMS-buffer-size.patch

@@ -0,0 +1,38 @@
+From 85e7e9f52177c9617b8554fbacac34c8c591f549 Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Fri, 5 Jul 2024 21:18:08 +0200
+Subject: [PATCH 5/9] Platform: CS1000: Increase RSE_COMMS buffer size
+
+This was needed because the UEFI variable index size was increased in
+the Host side software stack. The RSE_COMMS buffer has to be increased
+to accomodate the bigger messages.
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [85e7e9f52177c9617b8554fbacac34c8c591f549]
+---
+ .../ext/target/arm/corstone1000/rse_comms/rse_comms.h    | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/rse_comms/rse_comms.h b/platform/ext/target/arm/corstone1000/rse_comms/rse_comms.h
+index 41e5c2bc3..720a60b62 100644
+--- a/platform/ext/target/arm/corstone1000/rse_comms/rse_comms.h
++++ b/platform/ext/target/arm/corstone1000/rse_comms/rse_comms.h
+@@ -15,8 +15,13 @@
+ extern "C" {
+ #endif
+ 
+-/* size suits to fit the largest message too (EFI variables) */
+-#define RSE_COMMS_PAYLOAD_MAX_SIZE (0x2100)
++/*
++ * The size suits to fit the largest message too (EFI variables)
++ * This size is defined by the Host's software stack.
++ * The size was chosen by monitoring the messages that are coming
++ * from the Trusted Services SE Proxy partition.
++ */
++#define RSE_COMMS_PAYLOAD_MAX_SIZE (0x43C0)
+ 
+ /*
+  * Allocated for each client request.
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0006-Platform-CS1000-Increase-buffers-for-EFI-vars.patch

@@ -0,0 +1,42 @@
+From 8ca9620a000ba182ebb51c51f49e2b97622f3404 Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Wed, 15 May 2024 22:37:51 +0200
+Subject: [PATCH 6/9] Platform: CS1000: Increase buffers for EFI vars
+
+The UEFI variables are stored in the Protected Storage. The size of
+the variables metadata have been increased in the Host software stack
+so the related buffer sizes have to be increased:
+
+- The PS_MAX_ASSET_SIZE needs to be big enough to store the variables.
+- The CRYPTO_ENGINE_BUF_SIZE needs to be increased because the encryption
+  of the bigger PS assets requires bigger buffer.
+- The CRYPTO_IOVEC_BUFFER_SIZE needs to be increased because the PS
+  assets are passed through the IOVEC buffer between the crypto and
+  PS partition during encryption.
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [8ca9620a000ba182ebb51c51f49e2b97622f3404]
+---
+ platform/ext/target/arm/corstone1000/config_tfm_target.h | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/platform/ext/target/arm/corstone1000/config_tfm_target.h b/platform/ext/target/arm/corstone1000/config_tfm_target.h
+index 9522379cd..0b410dfd4 100644
+--- a/platform/ext/target/arm/corstone1000/config_tfm_target.h
++++ b/platform/ext/target/arm/corstone1000/config_tfm_target.h
+@@ -23,4 +23,12 @@
+ /* The maximum size of asset to be stored in the Internal Trusted Storage area. */
+ #define ITS_MAX_ASSET_SIZE   2048
+ 
++/* The maximum asset size to be stored in the Protected Storage */
++#define PS_MAX_ASSET_SIZE   2592
++
++/* This is needed to be able to process the EFI variables during PS writes. */
++#define CRYPTO_ENGINE_BUF_SIZE 0x5000
++
++/* This is also has to be increased to fit the EFI variables into the iovecs. */
++#define CRYPTO_IOVEC_BUFFER_SIZE    6000
+ #endif /* __CONFIG_TFM_TARGET_H__ */
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0006-Platform-Corstone1000-Increase-buffer-sizes.patch

@@ -1,49 +0,0 @@
-From def9095e7bfd5a82ba6cd4756e990cd9ae7307ab Mon Sep 17 00:00:00 2001
-From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
-Date: Mon, 16 Jun 2025 14:44:39 +0100
-Subject: [PATCH 6/7] Platform: Corstone1000: Increase buffer sizes
-
-Increase PSA_MAX_ASSET_SIZE and CRYPTO_IOVEC_BUFFER_SIZE
-to accommodate large size EFI variables set by new U-Boot version.
-
-This change is required to pass ACS tests related to Set/Get
-EFI variables. These ACS tests started failing after introducing new
-version of U-Boot, Trusted-Services and Trusted-Firmware-M while
-implementing PSA FWU support.
-
-Upstream-Status: Backport [bd80dee733e792eadfd2115f4bfa6bad748e5ce5]
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
----
- platform/ext/target/arm/corstone1000/config_tfm_target.h | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/config_tfm_target.h b/platform/ext/target/arm/corstone1000/config_tfm_target.h
-index 4920f6708..cf13712a1 100644
---- a/platform/ext/target/arm/corstone1000/config_tfm_target.h
-+++ b/platform/ext/target/arm/corstone1000/config_tfm_target.h
-@@ -1,5 +1,5 @@
- /*
-- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
-+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
-  *
-  * SPDX-License-Identifier: BSD-3-Clause
-  *
-@@ -27,13 +27,13 @@
- #define ITS_MAX_ASSET_SIZE   2048
- 
- /* The maximum asset size to be stored in the Protected Storage */
--#define PS_MAX_ASSET_SIZE   2592
-+#define PS_MAX_ASSET_SIZE   3500
- 
- /* This is needed to be able to process the EFI variables during PS writes. */
- #define CRYPTO_ENGINE_BUF_SIZE 0x5000
- 
- /* This is also has to be increased to fit the EFI variables into the iovecs. */
--#define CRYPTO_IOVEC_BUFFER_SIZE    6000
-+#define CRYPTO_IOVEC_BUFFER_SIZE    7200
- 
- /* The Mailbox partition is used as an NS Agent so its stack size is used to
-  * determine the PSP and PSPLIM during the SFN backend initialization. It has to
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0007-Plaform-Corstone1000-Switch-to-metadata-v2.patch

@@ -0,0 +1,202 @@
+From c731d187fbe9fc1e10ad8ecfb3d04bb480bc86b6 Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Mon, 8 Apr 2024 16:04:45 +0100
+Subject: [PATCH 7/9] Plaform: Corstone1000: Switch to metadata v2
+
+This upgrades metadata data structs from v1 to v2 as described in PSA
+FWU Specification:
+https://developer.arm.com/documentation/den0118/latest/
+
+The TrustedFirmware-A v2.11 release supports only the metadata v2. The
+structs in TF-M side had to be aligned to keep the compatibility.
+
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [c731d187fbe9fc1e10ad8ecfb3d04bb480bc86b6]
+---
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 86 +++++++++++++++----
+ 1 file changed, 69 insertions(+), 17 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index b2f31e166..5fddd3238 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
++++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -26,6 +26,15 @@
+ #include "platform.h"
+ #endif
+ 
++#define FWU_METADATA_VERSION		2
++#define FWU_FW_STORE_DESC_OFFSET	0x20
++#define NR_OF_MAX_FW_BANKS		4
++
++/*
++ * Metadata version 2 data structures defined by PSA_FW update specification
++ * at https://developer.arm.com/documentation/den0118/latest/
++ */
++
+ /* Properties of image in a bank */
+ struct fwu_image_properties {
+ 
+@@ -58,6 +67,28 @@ struct fwu_image_entry {
+ 
+ } __packed;
+ 
++struct fwu_fw_store_descriptor {
++
++       /* Number of Banks */
++       uint8_t num_banks;
++
++       /* Reserved */
++       uint8_t reserved;
++
++       /* Number of images per bank */
++       uint16_t num_images;
++
++       /* Size of image_entry(all banks) in bytes */
++       uint16_t img_entry_size;
++
++       /* Size of image bank info structure in bytes */
++       uint16_t bank_info_entry_size;
++
++       /* Array of fwu_image_entry structs */
++       struct fwu_image_entry img_entry[NR_OF_IMAGES_IN_FW_BANK];
++
++} __packed;
++
+ struct fwu_metadata {
+ 
+         /* Metadata CRC value */
+@@ -72,8 +103,23 @@ struct fwu_metadata {
+         /* Previous bank index with which device booted successfully */
+         uint32_t previous_active_index;
+ 
+-        /* Image entry information */
+-        struct fwu_image_entry img_entry[NR_OF_IMAGES_IN_FW_BANK];
++        /* Size of the entire metadata in bytes */
++        uint32_t metadata_size;
++
++        /* Offset of the image descriptor structure */
++        uint16_t desc_offset;
++
++        /* Reserved */
++        uint16_t reserved1;
++
++        /* Bank state: It's not used in corstone1000 at the moment.Currently
++	     * not used by any sw componenets such as u-boot and TF-A */
++        uint8_t bank_state[NR_OF_MAX_FW_BANKS];
++
++        /* Reserved */
++        uint32_t reserved2;
++
++        struct fwu_fw_store_descriptor fw_desc;
+ 
+ } __packed;
+ 
+@@ -607,23 +653,29 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
+ 
+     memset(&_metadata, 0, sizeof(struct fwu_metadata));
+ 
+-    _metadata.version = 1;
++    _metadata.version = FWU_METADATA_VERSION;
+     _metadata.active_index = BANK_0;
+     _metadata.previous_active_index = BANK_1;
++    _metadata.desc_offset= FWU_FW_STORE_DESC_OFFSET;
+ 
++    _metadata.fw_desc.num_banks = NR_OF_FW_BANKS;
++    _metadata.fw_desc.num_images = NR_OF_IMAGES_IN_FW_BANK;
++    _metadata.fw_desc.img_entry_size = sizeof(struct fwu_image_entry) * NR_OF_IMAGES_IN_FW_BANK;
++    _metadata.fw_desc.bank_info_entry_size = sizeof(struct fwu_image_properties) * NR_OF_FW_BANKS;
+     /* bank 0 is the place where images are located at the
+      * start of device lifecycle */
+ 
+     for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+ 
+-        _metadata.img_entry[i].img_props[BANK_0].accepted = IMAGE_ACCEPTED;
+-        _metadata.img_entry[i].img_props[BANK_0].version = image_version;
++        _metadata.fw_desc.img_entry[i].img_props[BANK_0].accepted = IMAGE_ACCEPTED;
++        _metadata.fw_desc.img_entry[i].img_props[BANK_0].version = image_version;
+ 
+-        _metadata.img_entry[i].img_props[BANK_1].accepted = IMAGE_NOT_ACCEPTED;
+-        _metadata.img_entry[i].img_props[BANK_1].version = INVALID_VERSION;
++        _metadata.fw_desc.img_entry[i].img_props[BANK_1].accepted = IMAGE_NOT_ACCEPTED;
++        _metadata.fw_desc.img_entry[i].img_props[BANK_1].version = INVALID_VERSION;
+     }
+ 
+-    /* Calculate CRC32 for fwu metadata */
++    /* Calculate CRC32 for fwu metadata. The first filed in the _metadata has to be the crc_32.
++     * This should be omited from the calculation. */
+     _metadata.crc_32 = crc32((uint8_t *)&_metadata.version,
+                              sizeof(struct fwu_metadata) - sizeof(uint32_t));
+ 
+@@ -685,7 +737,7 @@ static enum fwu_agent_state_t get_fwu_agent_state(
+     }
+ 
+     for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+-        if ((metadata_ptr->img_entry[i].img_props[boot_index].accepted)
++        if ((metadata_ptr->fw_desc.img_entry[i].img_props[boot_index].accepted)
+                 == (IMAGE_NOT_ACCEPTED)) {
+             return FWU_AGENT_STATE_TRIAL;
+         }
+@@ -760,7 +812,7 @@ static enum fwu_agent_error_t flash_full_capsule(
+     }
+ 
+     if (version <=
+-            (metadata->img_entry[IMAGE_0].img_props[active_index].version)) {
++            (metadata->fw_desc.img_entry[IMAGE_0].img_props[active_index].version)) {
+         FWU_LOG_MSG("ERROR: %s: version error\n\r",__func__);
+         return FWU_AGENT_ERROR;
+     }
+@@ -791,9 +843,9 @@ static enum fwu_agent_error_t flash_full_capsule(
+ 
+     /* Change system state to trial bank state */
+     for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+-        metadata->img_entry[i].img_props[previous_active_index].accepted =
++        metadata->fw_desc.img_entry[i].img_props[previous_active_index].accepted =
+                                                         IMAGE_NOT_ACCEPTED;
+-        metadata->img_entry[i].img_props[previous_active_index].version = version;
++        metadata->fw_desc.img_entry[i].img_props[previous_active_index].version = version;
+     }
+     metadata->active_index = previous_active_index;
+     metadata->previous_active_index = active_index;
+@@ -900,7 +952,7 @@ static enum fwu_agent_error_t accept_full_capsule(
+     FWU_LOG_MSG("%s: enter\n\r", __func__);
+ 
+     for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+-        metadata->img_entry[i].img_props[active_index].accepted =
++        metadata->fw_desc.img_entry[i].img_props[active_index].accepted =
+                                                             IMAGE_ACCEPTED;
+     }
+ 
+@@ -990,7 +1042,7 @@ static enum fwu_agent_error_t fwu_select_previous(
+ 
+     index = metadata->previous_active_index;
+     for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+-        if (metadata->img_entry[i].img_props[index].accepted != IMAGE_ACCEPTED)
++        if (metadata->fw_desc.img_entry[i].img_props[index].accepted != IMAGE_ACCEPTED)
+         {
+             FWU_ASSERT(0);
+         }
+@@ -1211,7 +1263,7 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+         /* firmware update failed, revert back to previous bank */
+ 
+         priv_metadata.fmp_last_attempt_version =
+-         _metadata.img_entry[IMAGE_0].img_props[_metadata.active_index].version;
++         _metadata.fw_desc.img_entry[IMAGE_0].img_props[_metadata.active_index].version;
+ 
+         priv_metadata.fmp_last_attempt_status = LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL;
+ 
+@@ -1222,9 +1274,9 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+         /* firmware update successful */
+ 
+         priv_metadata.fmp_version =
+-         _metadata.img_entry[IMAGE_0].img_props[_metadata.active_index].version;
++         _metadata.fw_desc.img_entry[IMAGE_0].img_props[_metadata.active_index].version;
+         priv_metadata.fmp_last_attempt_version =
+-         _metadata.img_entry[IMAGE_0].img_props[_metadata.active_index].version;
++         _metadata.fw_desc.img_entry[IMAGE_0].img_props[_metadata.active_index].version;
+ 
+         priv_metadata.fmp_last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS;
+ 
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0007-Platform-Corstone1000-Remove-duplicate-configuration.patch

@@ -1,34 +0,0 @@
-From 038b35ac96dcdaa640bb5f641b8c028491abb9b7 Mon Sep 17 00:00:00 2001
-From: Yogesh Wani <yogesh.wani@arm.com>
-Date: Wed, 30 Apr 2025 14:39:37 +0100
-Subject: [PATCH 7/7] Platform: Corstone1000: Remove duplicate configuration
- parameters for Corstone-1000
-
-The PS_NUM_ASSET is duplicated in the cmake.config and the
-config_tfm_target.h file under Corstone-1000. The commit removes
-the one from the cmake.config and keeps the one in the header file.
-
-The whole rationale behind this is for the vendor to be able
-to override the configuration using the cmake file.
-
-Upstream-Status: Backport [948cb8e7601dcf1fe822d855c77749287fe6d9bd]
-Signed-off-by: Yogesh Wani <yogesh.wani@arm.com>
----
- platform/ext/target/arm/corstone1000/config.cmake | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
-index f1de066e5..cf4d63f61 100644
---- a/platform/ext/target/arm/corstone1000/config.cmake
-+++ b/platform/ext/target/arm/corstone1000/config.cmake
-@@ -74,7 +74,6 @@ endif()
- # Platform-specific configurations
- set(CONFIG_TFM_USE_TRUSTZONE            OFF)
- set(TFM_MULTI_CORE_TOPOLOGY             ON)
--set(PS_NUM_ASSETS                       "40"        CACHE STRING    "The maximum number of assets to be stored in the Protected Storage area")
- 
- set(MCUBOOT_USE_PSA_CRYPTO            ON               CACHE BOOL      "Enable the cryptographic abstraction layer to use PSA Crypto APIs")
- set(MCUBOOT_SIGNATURE_TYPE            "EC-P256"        CACHE STRING    "Algorithm to use for signature validation [RSA-2048, RSA-3072, EC-P256, EC-P384]")
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0008-Platform-CS1000-Increase-flash-PS-area-size.patch

@@ -0,0 +1,37 @@
+From 3794ba29b66641ebecbd4dd3d9a2a2e8caeb690a Mon Sep 17 00:00:00 2001
+From: Ali Can Ozaslan <ali.oezaslan@arm.com>
+Date: Mon, 15 Jul 2024 13:03:24 +0000
+Subject: [PATCH 8/9] Platform: CS1000: Increase flash PS area size
+
+Previously, approximately only 2MB was used out of the 8MB SE Flash.
+The aim of this commit is to increase the size of PS storage in SE
+Flash.
+Increasing the size minimize the possibilities of it to run out
+of memory as it is not cleared on reset or reprogramming of the device.
+
+The FLASH_PS_AREA_SIZE is increased to 6MB so now 7MB of the SE Flash
+is used. The remaining 1MB is allocated for future uses.
+
+Signed-off-by: Ali Can Ozaslan <ali.oezaslan@arm.com>
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [3794ba29b66641ebecbd4dd3d9a2a2e8caeb690a]
+---
+ platform/ext/target/arm/corstone1000/partition/flash_layout.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/partition/flash_layout.h b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+index a181a7168..07b4cdea7 100644
+--- a/platform/ext/target/arm/corstone1000/partition/flash_layout.h
++++ b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+@@ -192,7 +192,7 @@
+ 
+ #define FLASH_PS_AREA_OFFSET            (FLASH_ITS_AREA_OFFSET + \
+                                          FLASH_ITS_AREA_SIZE)
+-#define FLASH_PS_AREA_SIZE              (16 * SECURE_FLASH_SECTOR_SIZE)
++#define FLASH_PS_AREA_SIZE              (96 * SECURE_FLASH_SECTOR_SIZE)
+ 
+ /* OTP_definitions */
+ #define FLASH_OTP_NV_COUNTERS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + \
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0008-Platform-Corstone1000-Increase-BL1-size-and-align-bi.patch

@@ -1,93 +0,0 @@
-From d708753e317c89dead0759e3ffa6ecabef5a84a3 Mon Sep 17 00:00:00 2001
-From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
-Date: Thu, 21 Aug 2025 09:12:25 +0000
-Subject: [PATCH 1/2] Platform: Corstone1000: Increase BL1 size and align
- binary addresses
-
-The move to Trusted-Firmware-M v2.2.1 makes the BL1 code larger,
-while the provisioning bundle can be trimmed.  At the same time BL2 and
-TF-M binary addresses now need to begin on a 0x100-byte boundary for
-Cortex-M0+ based platforms.
-
-Key changes
---------------------------------
-- Increase `BL1_1_CODE_SIZE` to 58KB to accommodate the v2.2.1 binaries.
-- Reduce `PROVISIONING_DATA_SIZE` to 6KB.
-- `BL2_CODE_START` and `S_CODE_START` are aligned to 0x100 byte boundary
-   so both start addresses are an exact multiple of 0x100.
-
-Upstream-Status: Backport [d56178638a49c8c964aab3bff69ed8396dd6d8fc]
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
----
- .../arm/corstone1000/partition/region_defs.h  | 29 ++++++++++---------
- 1 file changed, 15 insertions(+), 14 deletions(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/partition/region_defs.h b/platform/ext/target/arm/corstone1000/partition/region_defs.h
-index 3e1294484..92e01c0e3 100644
---- a/platform/ext/target/arm/corstone1000/partition/region_defs.h
-+++ b/platform/ext/target/arm/corstone1000/partition/region_defs.h
-@@ -24,6 +24,10 @@
- #include "flash_layout.h"
- #include "bl1_2_config.h"
- 
-+/* Align address to 0x100 bytes boundary */
-+#define ADDR_ALIGN               0x100
-+#define ALIGN_UP_100(addr)       (((addr + (ADDR_ALIGN - 1)) / ADDR_ALIGN) * ADDR_ALIGN)
-+
- /* BL1_1 */
- #define BL1_1_HEAP_SIZE         (0x0001000) /* 4KiB */
- #define BL1_1_MSP_STACK_SIZE    (0x0001800) /* 6KiB */
-@@ -43,14 +47,10 @@
- 
- #define BOOT_TFM_SHARED_DATA_SIZE (0x400)
- 
--#define IMAGE_TFM_CODE_SIZE \
--            (TFM_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
--
--#define IMAGE_BL2_CODE_SIZE \
--            (SE_BL2_PARTITION_SIZE - TFM_BL1_2_HEADER_MAX_SIZE)
--
- /* Secure regions */
--#define S_CODE_START            (SRAM_BASE + BL2_HEADER_SIZE)
-+#define S_CODE_START            ALIGN_UP_100(SRAM_BASE + BL2_HEADER_SIZE)
-+#define S_CODE_ALIGNMENT_DIFF   (S_CODE_START - (SRAM_BASE + BL2_HEADER_SIZE))
-+#define IMAGE_TFM_CODE_SIZE     (TFM_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE - S_CODE_ALIGNMENT_DIFF)
- #define S_CODE_SIZE             (IMAGE_TFM_CODE_SIZE)
- #define S_CODE_LIMIT            (S_CODE_START + S_CODE_SIZE - 1)
- 
-@@ -80,12 +80,13 @@
- #define SECONDARY_PARTITION_START 0
- #define SECONDARY_PARTITION_SIZE (TFM_PARTITION_SIZE)
- 
--
- /* SE BL2 regions */
--#define BL2_IMAGE_START   (SRAM_BASE + SRAM_SIZE - SE_BL2_PARTITION_SIZE)
--#define BL2_CODE_START    (BL2_IMAGE_START + TFM_BL1_2_HEADER_MAX_SIZE)
--#define BL2_CODE_SIZE     (IMAGE_BL2_CODE_SIZE)
--#define BL2_CODE_LIMIT    (BL2_CODE_START + BL2_CODE_SIZE - 1)
-+#define BL2_IMAGE_START            (SRAM_BASE + SRAM_SIZE - SE_BL2_PARTITION_SIZE)
-+#define BL2_CODE_START             ALIGN_UP_100(BL2_IMAGE_START + TFM_BL1_2_HEADER_MAX_SIZE)
-+#define BL2_CODE_ALIGNMENT_DIFF    (BL2_CODE_START - (BL2_IMAGE_START + TFM_BL1_2_HEADER_MAX_SIZE))
-+#define IMAGE_BL2_CODE_SIZE        (SE_BL2_PARTITION_SIZE - TFM_BL1_2_HEADER_MAX_SIZE - BL2_CODE_ALIGNMENT_DIFF)
-+#define BL2_CODE_SIZE              (IMAGE_BL2_CODE_SIZE)
-+#define BL2_CODE_LIMIT             (BL2_CODE_START + BL2_CODE_SIZE - 1)
- 
- #define BL2_DATA_START    (S_DATA_START)
- #define BL2_DATA_SIZE     (BL2_IMAGE_START - BL2_DATA_START)
-@@ -93,11 +94,11 @@
- 
- /* SE BL1 regions */
- #define BL1_1_CODE_START    (0)
--#define BL1_1_CODE_SIZE     (0x0000C800)     /* 50 KiB */
-+#define BL1_1_CODE_SIZE     (0x0000E800)     /* 58 KiB */
- #define BL1_1_CODE_LIMIT    (BL1_1_CODE_START + BL1_1_CODE_SIZE - 1)
- 
- #define PROVISIONING_DATA_START (BL1_1_CODE_START + BL1_1_CODE_SIZE)
--#define PROVISIONING_DATA_SIZE  (0x00002000)     /* 8 KiB */
-+#define PROVISIONING_DATA_SIZE  (0x00001800)     /* 6 KiB */
- #define PROVISIONING_DATA_LIMIT (PROVISIONING_DATA_START + PROVISIONING_DATA_SIZE - 1)
- 
- #define BL1_1_DATA_START    (SRAM_BASE)
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0009-Platform-CS1K-Adapt-ADAC-enabled-build-to-the-new-BL.patch

@@ -1,45 +0,0 @@
-From 31d3a21a2012d64c7acff55183477c7593ef4b31 Mon Sep 17 00:00:00 2001
-From: Antonio de Angelis <Antonio.deAngelis@arm.com>
-Date: Fri, 18 Apr 2025 21:00:55 +0100
-Subject: [PATCH] Platform: CS1K: Adapt ADAC enabled build to the new BL2 build
- restructure
-
-The BL2 build was restructured in order to always migrate to use
-MCUBOOT_USE_PSA_CRYPTO and then support hardware crypto drivers
-through the PSA driver interface instead of the _ALT interface
-which will be deprecated in newer versions of Mbed TLS. The ADAC
-enabled library will then use PSA Crypto APIs through the thin
-PSA Crypto core which is available in the BL2 build, without the
-need to link the old driver through psa_adac_cc312.
-
-Upstream-Status: Backport [36cc3a7cda2356d3a256e1271b75a93f35531b2f]
-Signed-off-by: Antonio de Angelis <antonio.deangelis@arm.com>
-Change-Id: I413116406ee18506ed3bcfe83ce7709542ea6f47
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
----
- platform/ext/target/arm/corstone1000/CMakeLists.txt | 9 ---------
- 1 file changed, 9 deletions(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-index 6105c951b..ca5a034e3 100644
---- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-@@ -436,15 +436,6 @@ if (${PLATFORM_PSA_ADAC_SECURE_DEBUG})
-             trusted-firmware-m-psa-adac
-     )
- 
--    target_link_libraries(trusted-firmware-m-psa-adac
--        PRIVATE
--            psa_adac_cc312
--    )
--
--    target_link_libraries(psa_adac_psa_crypto
--        PRIVATE
--            bl2_mbedcrypto_config
--    )
- endif()
- 
- 
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0009-corstone1000-Remove-reset-after-capsule-update.patch

@@ -0,0 +1,28 @@
+From 898d3c148521b331302c587e658d7e0a4f645c77 Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Mon, 27 May 2024 17:11:31 +0200
+Subject: [PATCH 09/10] corstone1000: Remove reset after capsule update
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/29065]
+---
+ .../target/arm/corstone1000/services/src/tfm_platform_system.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+index 41305ed966..1e837ce3b5 100644
+--- a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
++++ b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+@@ -28,9 +28,6 @@ enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
+ 
+         case IOCTL_CORSTONE1000_FWU_FLASH_IMAGES:
+             result = corstone1000_fwu_flash_image();
+-            if (!result) {
+-                NVIC_SystemReset();
+-            }
+             break;
+ 
+         case IOCTL_CORSTONE1000_FWU_HOST_ACK:
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0010-plat-corstone1000-Add-support-for-Cortex-A320-varian.patch

@@ -1,490 +0,0 @@
-From 2f09a03bc8396164c8075ac802751b6150b8a6c0 Mon Sep 17 00:00:00 2001
-From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
-Date: Tue, 29 Jul 2025 15:09:45 +0000
-Subject: [PATCH] plat: corstone1000: Add support for Cortex-A320 variant
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add support for powering on the Cortex-A320 host in the DSU-120T
-cluster and reserve Host SRAM for the normal world on the
-Corstone-1000 platform. These changes enable secure-enclave firmware
-control of the Cortex-A320 power domain and memory access
-configuration.
-
-**DSU-120T Power-Policy Unit (PPU) driver**
-
-* Introduce a minimal driver to program the DSU-120T Power-Policy
-  Units, allowing the secure-enclave firmware to bring the
-  Cortex-A320 host cluster out of reset.
-* The DSU utility-bus registers are located at:
-  * `0x6091_0000` in the Host memory map.
-  * `0xC091_0000` in the Secure-Enclave memory map.
-* The FC1 firewall is configured so that only the Secure Enclave may
-  write to this window.
-* Add new CMake option `CORSTONE1000_DSU_120T` and platform define to
-  enable Cortex-A320 DSU-120T–specific code.
-
-**Host SRAM allocation**
-
-* Reserve a 4 MiB block of Host SRAM at `0x0240_0000` for the
-  Cortex-A320 normal world.
-* Open the same region in the Host-side firewall (CVM, region 2)
-  to allow non-secure access.
-* This configuration is compiled in when `CORSTONE1000_CORTEX_A320`
-  is defined.
-
-These updates prepare the Corstone-1000 platform for Cortex-A320
-integration with proper cluster power management and normal-world
-memory accessibility.
-
-Upstream-Status: Submitted (https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/45749)
-Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
----
- .../target/arm/corstone1000/CMakeLists.txt    |  31 +++
- .../Device/Include/platform_base_address.h    |   8 +-
- .../arm/corstone1000/bl1/boot_hal_bl1_1.c     |  50 ++++-
- .../target/arm/corstone1000/dsu-120t/ppu.c    |  40 ++++
- .../target/arm/corstone1000/dsu-120t/ppu.h    | 185 ++++++++++++++++++
- .../arm/corstone1000/tfm_hal_multi_core.c     |  28 ++-
- 6 files changed, 339 insertions(+), 3 deletions(-)
- create mode 100644 platform/ext/target/arm/corstone1000/dsu-120t/ppu.c
- create mode 100644 platform/ext/target/arm/corstone1000/dsu-120t/ppu.h
-
-diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-index 91bf197d8..993c51591 100644
---- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-@@ -423,6 +423,37 @@ target_sources(tfm_spm
-         $<$<BOOL:${TFM_S_REG_TEST}>:${CMAKE_CURRENT_SOURCE_DIR}/target_cfg.c>
- )
- 
-+#========================= DSU-120T ============================================#
-+if (CORSTONE1000_DSU_120T)
-+    target_sources(tfm_psa_rot_partition_ns_agent_mailbox
-+        PUBLIC
-+            dsu-120t/ppu.c
-+    )
-+
-+    target_compile_definitions(tfm_psa_rot_partition_ns_agent_mailbox
-+        PUBLIC
-+            CORSTONE1000_DSU_120T
-+    )
-+
-+    target_compile_definitions(platform_bl1_1
-+        PUBLIC
-+            CORSTONE1000_DSU_120T
-+    )
-+
-+    target_include_directories(tfm_psa_rot_partition_ns_agent_mailbox
-+        PUBLIC
-+            dsu-120t
-+    )
-+endif()
-+
-+#========================= Ethos-U NPU =========================================#
-+if (CORSTONE1000_CORTEX_A320)
-+    target_compile_definitions(platform_bl1_1
-+        PUBLIC
-+            CORSTONE1000_CORTEX_A320
-+    )
-+endif()
-+
- #========================= tfm_adac ============================================#
- 
- if (${PLATFORM_PSA_ADAC_SECURE_DEBUG})
-diff --git a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
-index 5f9f03ddc..3908d69bc 100644
---- a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
-+++ b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
-@@ -1,5 +1,7 @@
- /*
-- * Copyright (c) 2017-2024 Arm Limited. All rights reserved.
-+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-  *
-  * Licensed under the Apache License, Version 2.0 (the "License");
-  * you may not use this file except in compliance with the License.
-@@ -79,6 +81,10 @@
- #define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE_SE_SECURE_FLASH (0x90010000U) /* AXI QSPI Controller for SE FLash  */
- #define CORSTONE1000_HOST_DRAM_UEFI_CAPSULE        (0xA0000000U) /* 1.5 GB DDR                        */
- 
-+#ifdef CORSTONE1000_DSU_120T
-+#define CORSTONE1000_HOST_DSU_120T_BASE            (0xC0910000U) /* DSU-120T PPU                      */
-+#endif
-+
- /* Map Component definitions to Corstone definitions */
- #define CC3XX_BASE_S        CORSTONE1000_CRYPTO_ACCELERATOR_BASE
- 
-diff --git a/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c b/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c
-index b51a233e9..1a5e98ad3 100644
---- a/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c
-+++ b/platform/ext/target/arm/corstone1000/bl1/boot_hal_bl1_1.c
-@@ -1,5 +1,5 @@
- /*
-- * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
-+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
-  *
-  * SPDX-License-Identifier: BSD-3-Clause
-  *
-@@ -48,6 +48,15 @@ REGION_DECLARE(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)[];
- #define HOST_SE_SECURE_FLASH_BASE_FVP       0x60010000
- #define HOST_AXI_QSPI_CTRL_REG_BASE_SE_SECURE_FLASH    0x60010000
- 
-+#ifdef CORSTONE1000_DSU_120T
-+#define HOST_DSU_120T_BASE              0x60910000
-+#endif
-+
-+#ifdef CORSTONE1000_CORTEX_A320
-+#define HOST_SECURE_SRAM_SIZE           0x400000
-+#define HOST_NONSECURE_SRAM_BASE        (HOST_TRUSTED_RAM_BASE + HOST_SECURE_SRAM_SIZE)
-+#endif
-+
- #define HOST_DRAM_BASE                  0x80000000
- #define HOST_DRAM_UEFI_CAPSULE          0x80000000
- 
-@@ -286,6 +295,25 @@ static void setup_se_firewall(void)
-     fc_enable_regions();
- #endif
- 
-+#ifdef CORSTONE1000_DSU_120T
-+#if (PLATFORM_IS_FVP)
-+    fc_select_region(7);
-+    fc_disable_regions();
-+    fc_disable_mpe(RGN_MPE0);
-+    fc_prog_rgn(RGN_SIZE_16MB, CORSTONE1000_HOST_DSU_120T_BASE);
-+    fc_prog_rgn_upper_addr(HOST_DSU_120T_BASE);
-+    fc_enable_addr_trans();
-+    fc_init_mpl(RGN_MPE0);
-+
-+    mpl_rights = (RGN_MPL_SECURE_READ_MASK |
-+                  RGN_MPL_SECURE_WRITE_MASK);
-+
-+    fc_enable_mpl(RGN_MPE0, mpl_rights);
-+    fc_prog_mid(RGN_MPE0, SE_MID);
-+    fc_enable_mpe(RGN_MPE0);
-+    fc_enable_regions();
-+#endif
-+#endif
-     fc_pe_enable();
- }
- 
-@@ -369,6 +397,26 @@ static void setup_host_firewall(void)
-     fc_enable_regions();
-     fc_rgn_lock();
- 
-+#ifdef CORSTONE1000_CORTEX_A320
-+    /* CVM - Non Secure RAM */
-+    fc_select_region(2);
-+    fc_disable_regions();
-+    fc_disable_mpe(RGN_MPE0);
-+    fc_prog_rgn(RGN_SIZE_4MB, HOST_NONSECURE_SRAM_BASE);
-+    fc_init_mpl(RGN_MPE0);
-+
-+    mpl_rights = (RGN_MPL_ANY_MST_MASK | RGN_MPL_NONSECURE_READ_MASK |
-+                                         RGN_MPL_NONSECURE_WRITE_MASK |
-+                                         RGN_MPL_NONSECURE_EXECUTE_MASK);
-+
-+    fc_enable_mpl(RGN_MPE0, mpl_rights);
-+    fc_disable_mpl(RGN_MPE0, ~mpl_rights);
-+
-+    fc_enable_mpe(RGN_MPE0);
-+    fc_enable_regions();
-+    fc_rgn_lock();
-+#endif
-+    
-     fc_pe_enable();
- 
-     /* DDR */
-diff --git a/platform/ext/target/arm/corstone1000/dsu-120t/ppu.c b/platform/ext/target/arm/corstone1000/dsu-120t/ppu.c
-new file mode 100644
-index 000000000..d6be5982a
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/dsu-120t/ppu.c
-@@ -0,0 +1,40 @@
-+/*
-+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+
-+#include <stdint.h>
-+#include "ppu.h"
-+
-+void PPU_SetPowerPolicy(PPU_TypeDef *ppu, PPU_PowerPolicy_Type policy, bool isDynamic)
-+{
-+    uint32_t regval = ppu->PWPR;
-+
-+    regval &= ~(PPU_PWPR_PWR_POLICY_Msk | PPU_PWPR_PWR_DYN_EN_Msk);
-+
-+    regval |= ((policy << PPU_PWPR_PWR_POLICY_Pos) & PPU_PWPR_PWR_POLICY_Msk);
-+
-+    if (isDynamic) {
-+        regval |= PPU_PWPR_PWR_DYN_EN_Msk;
-+    }
-+
-+    ppu->PWPR = regval;
-+}
-+
-+void PPU_SetOperatingPolicy(PPU_TypeDef *ppu, PPU_OperatingPolicy_Type policy, bool isDynamic)
-+{
-+    uint32_t regval = ppu->PWPR;
-+
-+    regval &= ~(PPU_PWPR_OP_POLICY_Msk | PPU_PWPR_OP_DYN_EN_Msk);
-+
-+    regval |= ((policy << PPU_PWPR_OP_POLICY_Pos) & PPU_PWPR_OP_POLICY_Msk);
-+
-+    if (isDynamic) {
-+        regval |= PPU_PWPR_OP_DYN_EN_Msk;
-+    }
-+
-+    ppu->PWPR = regval;
-+}
-+
-diff --git a/platform/ext/target/arm/corstone1000/dsu-120t/ppu.h b/platform/ext/target/arm/corstone1000/dsu-120t/ppu.h
-new file mode 100644
-index 000000000..05470df9a
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/dsu-120t/ppu.h
-@@ -0,0 +1,185 @@
-+/*
-+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+#ifndef PPU_H
-+#define PPU_H
-+
-+#include <stdbool.h>
-+#include <stdint.h>
-+#include "platform_base_address.h"
-+
-+// Bit definition for PPU_PWPR register
-+#define PPU_PWPR_PWR_POLICY_Pos            (0U)                                // Power mode policy
-+#define PPU_PWPR_PWR_POLICY_Msk            (0xFUL << PPU_PWPR_PWR_POLICY_Pos)  // 4 bits
-+#define PPU_PWPR_PWR_POLICY_OFF            (0UL << PPU_PWPR_PWR_POLICY_Pos)    // Logic off and RAM off.
-+#define PPU_PWPR_PWR_POLICY_OFF_EMU        (1UL << PPU_PWPR_PWR_POLICY_Pos)    // Emulated Off. Logic on with RAM on. This mode is used to emulate the functional condition of OFF without removing
-+#define PPU_PWPR_PWR_POLICY_MEM_RET        (2UL << PPU_PWPR_PWR_POLICY_Pos)    // Memory Retention. Logic off with RAM retained.
-+#define PPU_PWPR_PWR_POLICY_MEM_RET_EMU    (3UL << PPU_PWPR_PWR_POLICY_Pos)    // Emulated Memory Retention. Logic on with RAM on. This mode is used to emulate the functional condition of
-+#define PPU_PWPR_PWR_POLICY_FULL_RET       (5UL << PPU_PWPR_PWR_POLICY_Pos)    // Full Retention. Slice logic off with RAM contents retained.
-+#define PPU_PWPR_PWR_POLICY_FUNC_RET       (7UL << PPU_PWPR_PWR_POLICY_Pos)    // Functional Retention. Logic on with L3 Cache and Snoop Filter retained.
-+#define PPU_PWPR_PWR_POLICY_ON             (8UL << PPU_PWPR_PWR_POLICY_Pos)    // Logic on with RAM on, cluster is functional.
-+#define PPU_PWPR_PWR_POLICY_WARM_RST       (9UL << PPU_PWPR_PWR_POLICY_Pos)    // Warm Reset. Warm reset application with logic and RAM on.
-+#define PPU_PWPR_PWR_POLICY_DBG_RECOV      (10UL << PPU_PWPR_PWR_POLICY_Pos)   // Debug Recovery Reset. Warm reset application with logic and RAM on.
-+#define PPU_PWPR_PWR_DYN_EN_Pos            (8U)                                // Power mode dynamic transition enable.
-+#define PPU_PWPR_PWR_DYN_EN_Msk            (0x1UL << PPU_PWPR_PWR_DYN_EN_Pos)  // 1 bit
-+#define PPU_PWPR_LOCK_EN_Pos               (12U)                               // Lock enable bit for OFF, OFF_EMU, MEM_RET and MEM_RET_EMU power modes.
-+#define PPU_PWPR_LOCK_EN_Msk               (0x1UL << PPU_PWPR_LOCK_EN_Pos)     // 1 bit
-+#define PPU_PWPR_OP_POLICY_Pos             (16U)                               // Operating mode policy
-+#define PPU_PWPR_OP_POLICY_Msk             (0xFUL << PPU_PWPR_OP_POLICY_Pos)   // 4 bits
-+#define PPU_PWPR_OP_POLICY_OPMODE_00       (0UL << PPU_PWPR_OP_POLICY_Pos)     // ONE_SLICE_SF_ONLY_ON: One L3 Cache slice is operational, the Cache RAM is powered down.
-+#define PPU_PWPR_OP_POLICY_OPMODE_01       (1UL << PPU_PWPR_OP_POLICY_Pos)     // ONE_SLICE_HALF_RAM_ON: One L3 Cache slice is operational, half of the Cache RAMs are powered on.
-+#define PPU_PWPR_OP_POLICY_OPMODE_03       (3UL << PPU_PWPR_OP_POLICY_Pos)     // ONE_SLICE_FULL_RAM_ON: One L3 Cache slice is operational, all of the Cache RAMs are powered on.
-+#define PPU_PWPR_OP_POLICY_OPMODE_04       (4UL << PPU_PWPR_OP_POLICY_Pos)     // ALL_SLICE_SF_ONLY_ON: All L3 Cache slices are operational, the Cache RAMs in each slice are powered down.
-+#define PPU_PWPR_OP_POLICY_OPMODE_05       (5UL << PPU_PWPR_OP_POLICY_Pos)     // ALL_SLICE_HALF_RAM_ON: All L3 Cache slices are operational, half of the Cache RAMs are powered on.
-+#define PPU_PWPR_OP_POLICY_OPMODE_07       (7UL << PPU_PWPR_OP_POLICY_Pos)     // ALL_SLICE_FULL_RAM_ON: All L3 Cache slices are operational, all of the Cache RAMs are powered on.
-+#define PPU_PWPR_OP_POLICY_OPMODE_08       (8UL << PPU_PWPR_OP_POLICY_Pos)     // HALF_SLICE_SF_ONLY_ON: Half L3 Cache slices are operational, the Cache RAMs in each slice are powered down.
-+#define PPU_PWPR_OP_POLICY_OPMODE_09       (9UL << PPU_PWPR_OP_POLICY_Pos)     // HALF_SLICE_HALF_RAM_ON: Half L3 Cache slices are operational, half of the Cache RAMs are powered on.
-+#define PPU_PWPR_OP_POLICY_OPMODE_0B       (11UL << PPU_PWPR_PWR_POLICY_Pos)   // HALF_SLICE_FULL_RAM_ON: Half L3 Cache slices are operational, all of the Cache RAMs are powered on.
-+#define PPU_PWPR_OP_DYN_EN_Pos             (24U)                               // Operating mode dynamic transition enable.
-+#define PPU_PWPR_OP_DYN_EN_Msk             (0x1UL << PPU_PWPR_OP_DYN_EN_Pos)   // 1 bit
-+
-+// Bit definition for PPU_PWSR register
-+#define PPU_PWSR_PWR_STATUS_Pos            (0U)
-+#define PPU_PWSR_PWR_STATUS_Msk            (0xFUL << PPU_PWSR_PWR_STATUS_Pos)      // 4 bits
-+#define PPU_PWSR_PWR_STATUS_OFF            (0UL << PPU_PWSR_PWR_STATUS_Pos)        // Logic off and RAM off.
-+#define PPU_PWSR_PWR_STATUS_OFF_EMU        (1UL << PPU_PWSR_PWR_STATUS_Pos)        // Emulated Off. Logic on with RAM on. This mode is used to emulate the functional condition of OFF without removing
-+#define PPU_PWSR_PWR_STATUS_MEM_RET        (2UL << PPU_PWSR_PWR_STATUS_Pos)        // Memory Retention. Logic off with RAM retained.
-+#define PPU_PWSR_PWR_STATUS_MEM_RET_EMU    (3UL << PPU_PWSR_PWR_STATUS_Pos)        // Emulated Memory Retention. Logic on with RAM on. This mode is used to emulate the functional condition of
-+#define PPU_PWSR_PWR_STATUS_FULL_RET       (5UL << PPU_PWSR_PWR_STATUS_Pos)        // Full Retention. Slice logic off with RAM contents retained.
-+#define PPU_PWSR_PWR_STATUS_FUNC_RET       (7UL << PPU_PWSR_PWR_STATUS_Pos)        // Functional Retention. Logic on with L3 Cache and Snoop Filter retained.
-+#define PPU_PWSR_PWR_STATUS_ON             (8UL << PPU_PWSR_PWR_STATUS_Pos)        // Logic on with RAM on, cluster is functional.
-+#define PPU_PWSR_PWR_STATUS_WARM_RST       (9UL << PPU_PWSR_PWR_STATUS_Pos)        // Warm Reset. Warm reset application with logic and RAM on.
-+#define PPU_PWSR_PWR_STATUS_DBG_RECOV      (10UL << PPU_PWSR_PWR_STATUS_Pos)       // Debug Recovery Reset. Warm reset application with logic and RAM on.
-+#define PPU_PWSR_PWR_DYN_STATUS_Pos        (8U)                                    // Power mode dynamic transition enable.
-+#define PPU_PWSR_PWR_DYN_STATUS_Msk        (0x1UL << PPU_PWSR_PWR_DYN_STATUS_Pos)  // 1 bit
-+#define PPU_PWSR_LOCK_STATUS_Pos           (12U)                                   // Lock enable bit for OFF, OFF_EMU, MEM_RET and MEM_RET_EMU power modes.
-+#define PPU_PWSR_LOCK_STATUS_Msk           (0x1UL << PPU_PWSR_LOCK_STATUS_Pos)     // 1 bit
-+#define PPU_PWSR_OP_STATUS_Pos             (16U)                                   // Operating mode policy
-+#define PPU_PWSR_OP_STATUS_Msk             (0xFUL << PPU_PWSR_OP_STATUS_Pos)       // 4 bits
-+#define PPU_PWSR_OP_STATUS_OPMODE_00       (0UL << PPU_PWSR_OP_STATUS_Pos)         // ONE_SLICE_SF_ONLY_ON: One L3 Cache slice is operational, only the snoop filter RAM instances are active in the slice
-+#define PPU_PWSR_OP_STATUS_OPMODE_01       (1UL << PPU_PWSR_OP_STATUS_Pos)         // ONE_SLICE_HALF_RAM_ON: One L3 Cache slice is operational, half of the Cache RAMs are powered on.
-+#define PPU_PWSR_OP_STATUS_OPMODE_03       (3UL << PPU_PWSR_OP_STATUS_Pos)         // ONE_SLICE_FULL_RAM_ON: One L3 Cache slice is operational, all of the Cache RAMs are powered on.
-+#define PPU_PWSR_OP_STATUS_OPMODE_04       (4UL << PPU_PWSR_OP_STATUS_Pos)         // ALL_SLICE_SF_ONLY_ON: All L3 Cache slices are operational, the Cache RAMs in each slice are powered down.
-+#define PPU_PWSR_OP_STATUS_OPMODE_05       (5UL << PPU_PWSR_OP_STATUS_Pos)         // ALL_SLICE_HALF_RAM_ON: All L3 Cache slices are operational, half of the Cache RAMs are powered on.
-+#define PPU_PWSR_OP_STATUS_OPMODE_07       (7UL << PPU_PWSR_OP_STATUS_Pos)         // ALL_SLICE_FULL_RAM_ON: All L3 Cache slices are operational, all of the Cache RAMs are powered on.
-+#define PPU_PWSR_OP_STATUS_OPMODE_08       (8UL << PPU_PWSR_OP_STATUS_Pos)         // HALF_SLICE_SF_ONLY_ON: Half L3 Cache slices are operational, the Cache RAMs in each slice are powered down.
-+#define PPU_PWSR_OP_STATUS_OPMODE_09       (9UL << PPU_PWSR_OP_STATUS_Pos)         // HALF_SLICE_HALF_RAM_ON: Half L3 Cache slices are operational, half of the Cache RAMs are powered on.
-+#define PPU_PWSR_OP_STATUS_OPMODE_0B       (11UL << PPU_PWSR_OP_STATUS_Pos)        // HALF_SLICE_FULL_RAM_ON: Half L3 Cache slices are operational, all of the Cache RAMs are powered on.
-+#define PPU_PWSR_OP_DYN_STATUS_Pos         (24U)                                   // Operating mode dynamic transition enable.
-+#define PPU_PWSR_OP_DYN_STATUS_Msk         (0x1UL << PPU_PWSR_OP_DYN_STATUS_Pos)   // 1 bit
-+
-+/*!< PPU memory offsets */
-+#define DSU_120T_CLUSTER_PPU_OFFSET  0x030000
-+#define DSU_120T_CORE0_PPU_OFFSET    0x080000
-+#define DSU_120T_CORE1_PPU_OFFSET    0x180000
-+#define DSU_120T_CORE2_PPU_OFFSET    0x280000
-+#define DSU_120T_CORE3_PPU_OFFSET    0x380000
-+
-+/*!< PPU memory map */
-+#define CLUSTER_PPU_BASE (CORSTONE1000_HOST_DSU_120T_BASE + DSU_120T_CLUSTER_PPU_OFFSET)
-+#define CORE0_PPU_BASE (CORSTONE1000_HOST_DSU_120T_BASE + DSU_120T_CORE0_PPU_OFFSET)
-+#define CORE1_PPU_BASE (CORSTONE1000_HOST_DSU_120T_BASE + DSU_120T_CORE1_PPU_OFFSET)
-+#define CORE2_PPU_BASE (CORSTONE1000_HOST_DSU_120T_BASE + DSU_120T_CORE2_PPU_OFFSET)
-+#define CORE3_PPU_BASE (CORSTONE1000_HOST_DSU_120T_BASE + DSU_120T_CORE3_PPU_OFFSET)
-+
-+/*!< PPU declarations */
-+#define CLUSTER_PPU ((PPU_TypeDef *) CLUSTER_PPU_BASE)
-+#define CORE0_PPU   ((PPU_TypeDef *) CORE0_PPU_BASE)
-+#define CORE1_PPU   ((PPU_TypeDef *) CORE1_PPU_BASE)
-+#define CORE2_PPU   ((PPU_TypeDef *) CORE2_PPU_BASE)
-+#define CORE3_PPU   ((PPU_TypeDef *) CORE3_PPU_BASE)
-+
-+typedef struct
-+{
-+    volatile uint32_t PWPR;                      /*!< PPU Power Policy Register, Address offset: 0x00 */
-+    volatile uint32_t PMER;                      /*!< PPU Power Mode Emulation Enable Register, Address offset: 0x04 */
-+    volatile uint32_t PWSR;                      /*!< PPU Power Status Register, Address offset: 0x08 */
-+    volatile uint32_t RESERVED0;                 /*!< Reserved, Address offset: 0x0C */
-+    volatile uint32_t DISR;                      /*!< PPU Device Interface Input Current Status Register, Address offset: 0x10 */
-+    volatile uint32_t MISR;                      /*!< PPU Miscellaneous Input Current Status Register, Address offset: 0x14 */
-+    volatile uint32_t STSR;                      /*!< PPU Stored Status Register, Address offset: 0x18 */
-+    volatile uint32_t UNLK;                      /*!< PPU Unlock Register, Address offset: 0x1C */
-+    volatile uint32_t PWCR;                      /*!< PPU Power Configuration Register, Address offset: 0x20 */
-+    volatile uint32_t PTCR;                      /*!< PPU Power Mode Transition Register, Address offsets: 0x24 */
-+    volatile uint32_t RESERVED1[2];              /*!< Reserved: Address offsets 0x28 - 0x2C */
-+    volatile uint32_t IMR;                       /*!< PPU Interrupt Mask Register, Address offsets: 0x30 */
-+    volatile uint32_t AIMR;                      /*!< PPU Additional Interrupt Mask Register, Address offsets: 0x34 */
-+    volatile uint32_t ISR;                       /*!< PPU Interrupt Status Register, Address offsets: 0x38 */
-+    volatile uint32_t AISR;                      /*!< PPU Additional Interrupt Status Register, Address offsets: 0x3C */
-+    volatile uint32_t IESR;                      /*!< PPU Input Edge Sensitivity Register	Address offsets: 0x040 */
-+    volatile uint32_t OPSR;                      /*!< PPU Operating Mode Active Edge Sensitivity Register	Address offsets: 0x044 */
-+    volatile uint32_t RESERVED2[2];              /*!< Reserved: Address offsets 0x48 - 0x4C */
-+    volatile uint32_t FUNRR;                     /*!< Functional Retention RAM Configuration Register	Address offsets: 0x050 */
-+    volatile uint32_t FULRR;                     /*!< Full Retention RAM Configuration Register	Address offsets: 0x054 */
-+    volatile uint32_t MEMRR;                     /*!< Memory Retention RAM Configuration Register	Address offsets: 0x058 */
-+    volatile uint32_t RESERVED3[69];             /*!< Reserved: Address offsets 0x5C - 0x16C */
-+    volatile uint32_t DCDR0;                     /*!< Device Control Delay Configuration Register 0	Address offsets: 0x170 */
-+    volatile uint32_t DCDR1;                     /*!< Device Control Delay Configuration Register 1	Address offsets: 0x174 */
-+    volatile uint32_t RESERVED4[910];            /*!< Reserved, offsets 0x178 - 0xFAC */
-+    volatile uint32_t IDR0;                      /*!< PPU Identification Register 0, Address offsets: 0xFB0 */
-+    volatile uint32_t IDR1;                      /*!< PPU Identification Register 1, Address offsets: 0xFB4 */
-+    volatile uint32_t RESERVED5[4];             /*!< Reserved, offsets 0xFB8 - 0xFC4 */
-+    volatile uint32_t IIDR;                      /*!< PPU Implementation Identification Register, Address offsets: 0xFC8 */
-+    volatile uint32_t AIDR;                      /*!< PPU Architecture Identification Register, Address offsets: 0xFCC */
-+    volatile uint32_t PIDR4;                     /*!< PPU Peripheral Identification Register 4, Address offsets: 0xFD0 */
-+    volatile uint32_t PIDR5;                     /*!< PPU Peripheral Identification Register 5, Address offsets: 0xFD4 */
-+    volatile uint32_t PIDR6;                     /*!< PPU Peripheral Identification Register 6, Address offsets: 0xFD8 */
-+    volatile uint32_t PIDR7;                     /*!< PPU Peripheral Identification Register 7, Address offsets: 0xFDC */
-+    volatile uint32_t PIDR0;                     /*!< PPU Peripheral Identification Register 0, Address offsets: 0xFE0 */
-+    volatile uint32_t PIDR1;                     /*!< PPU Peripheral Identification Register 1, Address offsets: 0xFE4 */
-+    volatile uint32_t PIDR2;                     /*!< PPU Peripheral Identification Register 2, Address offsets: 0xFE8 */
-+    volatile uint32_t PIDR3;                     /*!< PPU Peripheral Identification Register 3, Address offsets: 0xFEC */
-+    volatile uint32_t CIDR0;                     /*!< PPU Component Identification Register 0,	Address offsets: 0xFF0 */
-+    volatile uint32_t CIDR1;                     /*!< PPU Component Identification Register 1,	Address offsets: 0xFF4 */
-+    volatile uint32_t CIDR2;                     /*!< PPU Component Identification Register 2,	Address offsets: 0xFF8 */
-+    volatile uint32_t CIDR3;                     /*!< PPU Component Identification Register 3,	Address offsets: 0xFFC */
-+} PPU_TypeDef;
-+
-+typedef enum {
-+    PPU_PWR_MODE_OFF         = 0, // Logic off and RAM off.
-+    PPU_PWR_MODE_OFF_EMU     = 1, // Emulated Off. Logic on with RAM on. This mode is used to emulate the functional condition of OFF without removing
-+    PPU_PWR_MODE_MEM_RET     = 2, // Memory Retention. Logic off with RAM retained.
-+    PPU_PWR_MODE_MEM_RET_EMU = 3, // Emulated Memory Retention. Logic on with RAM on. This mode is used to emulate the functional condition of
-+    PPU_PWR_MODE_FULL_RET    = 5, // Full Retention. Slice logic off with RAM contents retained.
-+    PPU_PWR_MODE_FUNC_RET    = 7, // Functional Retention. Logic on with L3 Cache and Snoop Filter retained.
-+    PPU_PWR_MODE_ON          = 8, // Logic on with RAM on, cluster is functional.
-+    PPU_PWR_MODE_WARM_RST    = 9, // Warm Reset. Warm reset application with logic and RAM on.
-+    PPU_PWR_MODE_DBG_RECOV   = 10 // Debug Recovery Reset. Warm reset application with logic and RAM on.
-+} PPU_PowerPolicy_Type;
-+
-+typedef enum {
-+    PPU_OP_MODE_ONE_SLICE_SF_ONLY_ON   = 0, // One L3 Cache slice is operational, only the snoop filter RAM instances are active in the slice
-+    PPU_OP_MODE_ONE_SLICE_HALF_RAM_ON  = 1, // One L3 Cache slice is operational, half of the Cache RAMs are powered on.
-+    PPU_OP_MODE_ONE_SLICE_FULL_RAM_ON  = 3, // One L3 Cache slice is operational, all of the Cache RAMs are powered on.
-+    PPU_OP_MODE_ALL_SLICE_SF_ONLY_ON   = 4, // All L3 Cache slices are operational, the Cache RAMs in each slice are powered down.
-+    PPU_OP_MODE_ALL_SLICE_HALF_RAM_ON  = 5, // All L3 Cache slices are operational, half of the Cache RAMs are powered on.
-+    PPU_OP_MODE_ALL_SLICE_FULL_RAM_ON  = 7, // All L3 Cache slices are operational, all of the Cache RAMs are powered on.
-+    PPU_OP_MODE_HALF_SLICE_SF_ONLY_ON  = 8, // Half L3 Cache slices are operational, the Cache RAMs in each slice are powered down.
-+    PPU_OP_MODE_HALF_SLICE_HALF_RAM_ON = 9, // Half L3 Cache slices are operational, half of the Cache RAMs are powered on.
-+    PPU_OP_MODE_HALF_SLICE_FULL_RAM_ON = 11 // Half L3 Cache slices are operational, all of the Cache RAMs are powered on.
-+} PPU_OperatingPolicy_Type;
-+
-+/**
-+ * @brief  Set the power policy for a given PPU instance.
-+ *         Only modifies PWR_POLICY and PWR_DYN_EN bits.
-+ * @param  ppu: Pointer to the PPU instance (e.g., CLUSTER_PPU, CORE0_PPU1)
-+ * @param  policy: Power mode policy (e.g., PPU_PWR_MODE_ON)
-+ * @param  dynamic: Enable dynamic transitions enabled for power modes, allowing transitions to be initiated by changes on power mode DEVACTIVE inputs if non-zero
-+ * @retval None
-+ */
-+void PPU_SetPowerPolicy(PPU_TypeDef *ppu, PPU_PowerPolicy_Type policy, bool isDynamic);
-+
-+/**
-+ * @brief  Set the operating mode policy for a given PPU instance.
-+*          Only modifies OP_POLICY and OP_DYN_EN bits.
-+ * @param  ppu: Pointer to the PPU instance (e.g., CLUSTER_PPU, CORE0_PPU)
-+ * @param  policy: Operating mode policy (e.g., PPU_OP_MODE_ONE_SLICE_SF_ONLY_ON)
-+ * @param  dynamic: Enable dynamic transitions enabled for operating modes, allowing transitions to be initiated by changes on operating mode DEVACTIVE inputs if non-zero
-+ * @retval None
-+ */
-+void PPU_SetOperatingPolicy(PPU_TypeDef *ppu, PPU_OperatingPolicy_Type policy, bool isDynamic);
-+
-+#endif /* PPU_H */
-diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
-index d0c6b8d59..10c66ac41 100644
---- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
-+++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
-@@ -1,5 +1,5 @@
- /*
-- * Copyright (c) 2018-2024 Arm Limited. All rights reserved.
-+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
-  *
-  * SPDX-License-Identifier: BSD-3-Clause
-  *
-@@ -11,6 +11,10 @@
- #include "tfm_hal_multi_core.h"
- #include "fwu_agent.h"
- 
-+#ifdef CORSTONE1000_DSU_120T
-+#include "ppu.h"
-+#endif
-+
- #define HOST_SYS_RST_CTRL_OFFSET     0x000
- #define HOST_CPU_PE0_CONFIG_OFFSET   0x010
- #define HOST_CPU_PE1_CONFIG_OFFSET   0x020
-@@ -98,6 +102,28 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
- 
-     (void) start_addr;
- 
-+#ifdef CORSTONE1000_DSU_120T
-+    /* Power on DSU-120T cluster */
-+    PPU_SetOperatingPolicy(CLUSTER_PPU, PPU_OP_MODE_ONE_SLICE_SF_ONLY_ON, false);
-+    PPU_SetPowerPolicy(CLUSTER_PPU, PPU_PWR_MODE_ON, false);
-+    
-+    /* Power on Cortex-A320 core0 in DSU-120T Cluster */
-+    PPU_SetOperatingPolicy(CORE0_PPU, PPU_OP_MODE_ONE_SLICE_SF_ONLY_ON, false);
-+    PPU_SetPowerPolicy(CORE0_PPU, PPU_PWR_MODE_ON, false);
-+    
-+#if CORSTONE1000_FVP_MULTICORE
-+    /* Power on all Cortex-A320 cores in DSU-120T Cluster */
-+    PPU_SetOperatingPolicy(CORE1_PPU, PPU_OP_MODE_ONE_SLICE_SF_ONLY_ON, false);
-+    PPU_SetPowerPolicy(CORE1_PPU, PPU_PWR_MODE_ON, false);
-+    
-+    PPU_SetOperatingPolicy(CORE2_PPU, PPU_OP_MODE_ONE_SLICE_SF_ONLY_ON, false);
-+    PPU_SetPowerPolicy(CORE2_PPU, PPU_PWR_MODE_ON, false);
-+
-+    PPU_SetOperatingPolicy(CORE3_PPU, PPU_OP_MODE_ONE_SLICE_SF_ONLY_ON, false);
-+    PPU_SetPowerPolicy(CORE3_PPU, PPU_PWR_MODE_ON, false);
-+#endif
-+#endif
-+
- #ifdef EXTERNAL_SYSTEM_SUPPORT
-     /*release EXT SYS out of reset*/
-     tfm_external_system_boot();
--- 
-2.50.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0010-platform-CS1000-Add-multicore-support-for-FVP.patch

@@ -0,0 +1,119 @@
+From 1eb9bc330bf387ff26a6df93d3b8c843174dc40b Mon Sep 17 00:00:00 2001
+From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
+Date: Thu, 9 May 2024 13:20:57 +0000
+Subject: [PATCH 10/10] platform: CS1000: Add multicore support for FVP
+
+This changeset adds the support to enable the secondary cores for
+the Corstone-1000 FVP
+
+Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/29242]
+Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
+---
+ .../target/arm/corstone1000/CMakeLists.txt    |  6 +++
+ .../corstone1000/Device/Config/device_cfg.h   |  6 +++
+ .../arm/corstone1000/tfm_hal_multi_core.c     | 38 ++++++++++++++++++-
+ 3 files changed, 48 insertions(+), 2 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index 95e3f57b4f..e46123cc6f 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
++++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -381,6 +381,12 @@ target_sources(tfm_psa_rot_partition_ns_agent_mailbox
+         tfm_hal_multi_core.c
+ )
+ 
++if (PLATFORM_IS_FVP)
++target_compile_definitions(tfm_psa_rot_partition_ns_agent_mailbox
++    PUBLIC
++    	$<$<BOOL:${ENABLE_MULTICORE}>:CORSTONE1000_FVP_MULTICORE>
++)
++endif()
+ #========================= tfm_spm ============================================#
+ 
+ target_sources(tfm_spm
+diff --git a/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h b/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h
+index 222905d3dd..9d48f119ed 100644
+--- a/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h
++++ b/platform/ext/target/arm/corstone1000/Device/Config/device_cfg.h
+@@ -45,5 +45,11 @@
+ /* CFI Controller */
+ #define CFI_S
+ 
++/* Total number of host cores */
++#if CORSTONE1000_FVP_MULTICORE
++#define PLATFORM_HOST_MAX_CORE_COUNT 4
++#else
++#define PLATFORM_HOST_MAX_CORE_COUNT 1
++#endif
+ 
+ #endif  /* __DEVICE_CFG_H__ */
+diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+index f0e2bc333a..ce72e50c9b 100644
+--- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
++++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+@@ -11,9 +11,14 @@
+ #include "tfm_hal_multi_core.h"
+ #include "fwu_agent.h"
+ 
+-#define HOST_SYS_RST_CTRL_OFFSET 0x0
++#define HOST_SYS_RST_CTRL_OFFSET     0x000
++#define HOST_CPU_PE0_CONFIG_OFFSET   0x010
++#define HOST_CPU_PE1_CONFIG_OFFSET   0x020
++#define HOST_CPU_PE2_CONFIG_OFFSET   0x030
++#define HOST_CPU_PE3_CONFIG_OFFSET   0x040
++#define HOST_CPU_BOOT_MASK_OFFSET    0x300
+ #define HOST_CPU_CORE0_WAKEUP_OFFSET 0x308
+-#define HOST_CPU_PE0_CONFIG_OFFSET 0x010
++
+ #define AA64nAA32_MASK (1 << 3)
+ 
+ #ifdef EXTERNAL_SYSTEM_SUPPORT
+@@ -53,9 +58,29 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
+     volatile uint32_t *PE0_CONFIG =
+                         (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
+                                      + HOST_CPU_PE0_CONFIG_OFFSET);
++#if CORSTONE1000_FVP_MULTICORE
++    volatile uint32_t *PE1_CONFIG =
++                        (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
++                                     + HOST_CPU_PE1_CONFIG_OFFSET);
++    volatile uint32_t *PE2_CONFIG =
++                        (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
++                                     + HOST_CPU_PE2_CONFIG_OFFSET);
++    volatile uint32_t *PE3_CONFIG =
++                        (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
++                                     + HOST_CPU_PE3_CONFIG_OFFSET);
++    volatile uint32_t *CPU_BOOT_MASK =
++                        (uint32_t *)(CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE
++		                     + HOST_CPU_BOOT_MASK_OFFSET);
+ 
++    *CPU_BOOT_MASK = 0xf;
++#endif
+     /* Select host CPU architecture as AArch64 */
+     *PE0_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */
++#if CORSTONE1000_FVP_MULTICORE
++    *PE1_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */
++    *PE2_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */
++    *PE3_CONFIG |= AA64nAA32_MASK; /* 0b1 – AArch64 */
++#endif
+ 
+     /* wakeup CORE0 before bringing it out of reset */
+     *reset_ctl_wakeup_reg = 0x1;
+@@ -63,6 +88,15 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
+     /* Clear HOST_SYS_RST_CTRL register to bring host out of RESET */
+     *reset_ctl_reg = 0;
+ 
++#if CORSTONE1000_FVP_MULTICORE
++    /* Wake up secondary cores.
++     * This should be done after bringing the primary core out of reset. */
++    for(int core_index=1; core_index < PLATFORM_HOST_MAX_CORE_COUNT; core_index++)
++    {
++	    *reset_ctl_wakeup_reg = (0x1 << core_index);
++    }
++#endif
++
+     (void) start_addr;
+ 
+ #ifdef EXTERNAL_SYSTEM_SUPPORT
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0011-BL2-Remove-the-weak-function-definition.patch

@@ -1,116 +0,0 @@
-From bea93292fdd5eecd4d106a4288004493cabd13b2 Mon Sep 17 00:00:00 2001
-From: Maulik Patel <maulik.patel@arm.com>
-Date: Mon, 14 Jul 2025 14:55:09 +0100
-Subject: [PATCH] BL2: Remove the weak function definition
-
-When psa_adac_generate_challenge is called from the psa adac crypto
-library (psa_adac_psa_crypto), linker uses the weak function defined in
-the thin_psa_crypto_core.c since it part of same static library
-(bl2_cc3xx_psa_driver_api).
-
-This weak function is intended to be overridden by the strong function
-defined in the linked library (cc3xx_psa_random).
-
-This commit creates separate static library for the weak function
-mbedtls_psa_external_get_random and links it only when the
-crypto hardware accelerator is not enabled.
-
-Upstream-Status: Backport [aef30c4e6507db792648b01f81bc82d3c54f7d43]
-Signed-off-by: Maulik Patel <maulik.patel@arm.com>
-Change-Id: Ic51944a2f4c9bf0bcc0560a38e40c85444bd8aac
----
- bl2/CMakeLists.txt             | 14 ++++++++++++++
- bl2/src/psa_stub_rng.c         | 24 ++++++++++++++++++++++++
- bl2/src/thin_psa_crypto_core.c | 16 ----------------
- 3 files changed, 38 insertions(+), 16 deletions(-)
- create mode 100644 bl2/src/psa_stub_rng.c
-
-diff --git a/bl2/CMakeLists.txt b/bl2/CMakeLists.txt
-index f6c2f894d0..d852102427 100644
---- a/bl2/CMakeLists.txt
-+++ b/bl2/CMakeLists.txt
-@@ -57,6 +57,19 @@ endif()
- 
- ############################### BL2_CRYPTO #####################################
- 
-+# Adds a static library target named 'bl2_fallback_rng' which includes the source file
-+# 'src/psa_stub_rng.c'. This source file contains only the __weak stub implementation,
-+# serving as a fallback for random number generation in case no other RNG is provided.
-+if(NOT CRYPTO_HW_ACCELERATOR)
-+    add_library(bl2_fallback_rng STATIC
-+        src/psa_stub_rng.c
-+    )
-+    target_link_libraries(bl2_fallback_rng
-+        PUBLIC
-+            bl2_crypto_config
-+    )
-+endif()
-+
- set(is_384_bit_curve "$<STREQUAL:${SIG_LEN},384>")
- set(is_256_bit_curve "$<STREQUAL:${SIG_LEN},256>")
- set(build_sha_384    "$<AND:${is_ec_signature},${is_384_bit_curve}>")
-@@ -150,6 +163,7 @@ target_link_libraries(bl2
-         $<$<BOOL:${TEST_BL2}>:mcuboot_tests>
-     PUBLIC
-         bl2_crypto
-+        $<$<NOT:$<BOOL:${CRYPTO_HW_ACCELERATOR}>>:bl2_fallback_rng>
- )
- 
- target_compile_options(bl2
-diff --git a/bl2/src/psa_stub_rng.c b/bl2/src/psa_stub_rng.c
-new file mode 100644
-index 0000000000..6ede1ddc59
---- /dev/null
-+++ b/bl2/src/psa_stub_rng.c
-@@ -0,0 +1,24 @@
-+/*
-+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+/**
-+ * \note This source file is derivative work of psa_crypto.c from the Mbed TLS project
-+ */
-+#include <stdint.h>
-+#include "psa/crypto.h"
-+
-+/* This function is stubbed as no source of randomness is required
-+ * by APIs used in the BLx stages. Nevertheless, an hardwware driver
-+ * for a TRNG might override this implementation with a valid one
-+ * hence mark it as a weak
-+ */
-+__attribute__((weak))
-+psa_status_t mbedtls_psa_external_get_random(
-+    mbedtls_psa_external_random_context_t *context,
-+    uint8_t *output, size_t output_size, size_t *output_length)
-+{
-+    return PSA_ERROR_NOT_SUPPORTED;
-+}
-diff --git a/bl2/src/thin_psa_crypto_core.c b/bl2/src/thin_psa_crypto_core.c
-index 4c0c1897a2..07e3e1e07b 100644
---- a/bl2/src/thin_psa_crypto_core.c
-+++ b/bl2/src/thin_psa_crypto_core.c
-@@ -677,19 +677,3 @@ psa_status_t psa_driver_wrapper_export_public_key(
- 
-     return PSA_SUCCESS;
- }
--
--#if defined(MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG)
--/* This function is stubbed as no source of randomness is required
-- * by APIs used in the BLx stages. Nevertheless, an hardwware driver
-- * for a TRNG might override this implementation with a valid one
-- * hence mark it as a weak
-- */
--__attribute__((weak))
--psa_status_t mbedtls_psa_external_get_random(
--    mbedtls_psa_external_random_context_t *context,
--    uint8_t *output, size_t output_size, size_t *output_length)
--{
--    return PSA_ERROR_NOT_SUPPORTED;
--}
--#endif /* MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG */
--/*!@}*/
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0011-Platform-CS1000-Fix-Bank-offsets.patch

@@ -0,0 +1,36 @@
+From 939a39a0705ed2571fe5b842a9d5f80036f71a12 Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Fri, 2 Aug 2024 22:02:55 +0200
+Subject: [PATCH 9/9] Platform: CS1000: Fix Bank offsets
+
+The BANK_0_PARTITION_OFFSET and BANK_1_PARTITION_OFFSET are used for
+erasing the banks during capsule update. The fwu_agent erases the flash
+using them as starting addresses. The BL2 (MCUBoot) should also
+be erased during capsule update.
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [939a39a0705ed2571fe5b842a9d5f80036f71a12]
+---
+ .../ext/target/arm/corstone1000/partition/flash_layout.h    | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/partition/flash_layout.h b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+index 07b4cdea7..f42dda809 100644
+--- a/platform/ext/target/arm/corstone1000/partition/flash_layout.h
++++ b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+@@ -109,10 +109,8 @@
+ #define FWU_PRIVATE_METADATA_REPLICA_2_OFFSET   (FWU_PRIVATE_METADATA_REPLICA_1_OFFSET + \
+                                                  FWU_METADATA_FLASH_SECTOR_SIZE)
+ 
+-#define BANK_0_PARTITION_OFFSET         (SE_BL2_BANK_0_OFFSET + \
+-                                         SE_BL2_PARTITION_SIZE)
+-#define BANK_1_PARTITION_OFFSET         (SE_BL2_BANK_1_OFFSET + \
+-                                         SE_BL2_PARTITION_SIZE)
++#define BANK_0_PARTITION_OFFSET         (SE_BL2_BANK_0_OFFSET)
++#define BANK_1_PARTITION_OFFSET         (SE_BL2_BANK_1_OFFSET)
+ 
+ /* BL1: mcuboot flashmap configurations */
+ #define FLASH_AREA_8_ID                 (1)
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0012-Corstone-1000-Enable-different-DRBG-configurations.patch

@@ -1,40 +0,0 @@
-From d60a6b4edda3465d86ec264b2cbfd7d14109ed5f Mon Sep 17 00:00:00 2001
-From: Devaraj Ranganna <devaraj.ranganna@arm.com>
-Date: Thu, 18 Sep 2025 22:07:38 +0100
-Subject: [PATCH 2/2] Corstone-1000: Enable different DRBG configurations
-
-The following DRBG configurations are enabled:
-
-* `CC3XX_CONFIG_DRBG_CTR_ENABLE`
-* `CC3XX_CONFIG_DRBG_HMAC_ENABLE`
-* `CC3XX_CONFIG_DRBG_HASH_ENABLE`
-
-The choice of DRBG is defined by `CC3XX_CONFIG_ENABLE_RANDOM_CTR_DRBG`.
-
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
----
- platform/ext/target/arm/corstone1000/cc3xx_config.h | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/platform/ext/target/arm/corstone1000/cc3xx_config.h b/platform/ext/target/arm/corstone1000/cc3xx_config.h
-index c5654a6bdb..199a99e1ca 100644
---- a/platform/ext/target/arm/corstone1000/cc3xx_config.h
-+++ b/platform/ext/target/arm/corstone1000/cc3xx_config.h
-@@ -87,6 +87,13 @@
- #error "cc3xx_config: RNG config must select a single DRBG"
- #endif /* CC3XX_CONFIG_RNG_DRBG_HMAC + CC3XX_CONFIG_RNG_DRBG_CTR + CC3XX_CONFIG_RNG_DRBG_HASH */
- 
-+/* Whether the CTR_DRBG is enabled through the generic interface */
-+#define CC3XX_CONFIG_DRBG_CTR_ENABLE
-+/* Whether the HMAC_DRBG is enabled through the generic interface */
-+#define CC3XX_CONFIG_DRBG_HMAC_ENABLE
-+/* Whether the HASH_DRBG is enabled through the generic interface */
-+#define CC3XX_CONFIG_DRBG_HASH_ENABLE
-+
- /* Whether an external TRNG should be used in place of the standard CC3XX TRNG */
- /* #define CC3XX_CONFIG_RNG_EXTERNAL_TRNG */
- 
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0012-Platform-CS1000-Increase-BL2-partition-size.patch

@@ -0,0 +1,111 @@
+From ddd4abdb3893e284a35303e4a5ac7b6ad2ed8320 Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Tue, 16 Jul 2024 21:04:49 +0200
+Subject: [PATCH] Platform: CS1000: Increase BL2 partition size
+
+Enabling secure debug increases the BL2 code size considerably. This
+patch increases the BL2 partition size to enable secure debug feature
+on Corstone-1000. The TF-M partition size has to be decreased for this.
+The RAM_MPU_REGION_BLOCK_1_SIZE had to be aligned with the changes to
+fully cover the S_DATA.
+
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/30406]
+---
+ .../ext/target/arm/corstone1000/CMakeLists.txt     |  9 ++++++---
+ .../target/arm/corstone1000/create-flash-image.sh  | 14 ++++++++------
+ .../arm/corstone1000/partition/flash_layout.h      |  4 ++--
+ 3 files changed, 16 insertions(+), 11 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index b13dc26c0e..3ba26e0de7 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
++++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -44,10 +44,13 @@ target_compile_definitions(platform_region_defs
+         # The RAM MPU Region block sizes are calculated manually. The RAM has to be covered
+         # with the MPU regions. These regions also have to be the power of 2 and
+         # the start addresses have to be aligned to these sizes. The sizes can be calculated
+-        # from the S_DATA_START and S_DATA_SIZE defines.
+-        RAM_MPU_REGION_BLOCK_1_SIZE=0x4000
++        # from the S_DATA_START and S_DATA_SIZE defines the following way:
++        # S_DATA_SIZE = RAM_MPU_REGION_BLOCK_1_SIZE + RAM_MPU_REGION_BLOCK_2_SIZE
++        # And the following constraints have to be taken:
++        # S_DATA_START % RAM_MPU_REGION_BLOCK_1_SIZE = 0
++        # (S_DATA_START + RAM_MPU_REGION_BLOCK_1_SIZE) % RAM_MPU_REGION_BLOCK_2_SIZE = 0
++        RAM_MPU_REGION_BLOCK_1_SIZE=0x10000
+         RAM_MPU_REGION_BLOCK_2_SIZE=0x20000
+-
+ )
+ #========================= Platform common defs ===============================#
+ 
+diff --git a/platform/ext/target/arm/corstone1000/create-flash-image.sh b/platform/ext/target/arm/corstone1000/create-flash-image.sh
+index a6be61384f..06f0d1ec9a 100755
+--- a/platform/ext/target/arm/corstone1000/create-flash-image.sh
++++ b/platform/ext/target/arm/corstone1000/create-flash-image.sh
+@@ -1,6 +1,6 @@
+ #!/bin/bash
+ #-------------------------------------------------------------------------------
+-# Copyright (c) 2023, Arm Limited. All rights reserved.
++# Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+@@ -65,6 +65,8 @@ FWU_METADATA_TYPE_UUID="8A7A84A0-8387-40F6-AB41-A8B9A5A60D23"
+ PRIVATE_METADATA_TYPE_UUID="ECB55DC3-8AB7-4A84-AB56-EB0A9974DB42"
+ SE_BL2_TYPE_UUID="64BD8ADB-02C0-4819-8688-03AB4CAB0ED9"
+ TFM_TYPE_UUID="D763C27F-07F6-4FF0-B2F3-060CB465CD4E"
++SE_BL2_PARTITION_SIZE="+144k"
++TFM_S_PARTITION_SIZE="+320K"
+ 
+ # Create the image
+ rm -f $IMAGE
+@@ -81,10 +83,10 @@ sgdisk  --mbrtogpt \
+         --new=3:48:+4K --typecode=3:$FWU_METADATA_TYPE_UUID --partition-guid=3:$(uuidgen) --change-name=3:'Bkup-FWU-Metadata' \
+         --new=4:56:+4K --typecode=4:$PRIVATE_METADATA_TYPE_UUID --partition-guid=4:$(uuidgen) --change-name=4:'private_metadata_replica_1' \
+         --new=5:64:+4k --typecode=5:$PRIVATE_METADATA_TYPE_UUID --partition-guid=5:$(uuidgen) --change-name=5:'private_metadata_replica_2' \
+-        --new=6:72:+100k --typecode=6:$SE_BL2_TYPE_UUID --partition-guid=6:$(uuidgen) --change-name=6:'bl2_primary' \
+-        --new=7:272:+368K --typecode=7:$TFM_TYPE_UUID --partition-guid=7:$(uuidgen) --change-name=7:'tfm_primary' \
+-        --new=8:32784:+100k --typecode=8:$SE_BL2_TYPE_UUID --partition-guid=8:$(uuidgen) --change-name=8:'bl2_secondary' \
+-        --new=9:32984:+368K --typecode=9:$TFM_TYPE_UUID --partition-guid=9:$(uuidgen) --change-name=9:'tfm_secondary' \
++        --new=6:72:$SE_BL2_PARTITION_SIZE --typecode=6:$SE_BL2_TYPE_UUID --partition-guid=6:$(uuidgen) --change-name=6:'bl2_primary' \
++        --new=7:360:$TFM_S_PARTITION_SIZE --typecode=7:$TFM_TYPE_UUID --partition-guid=7:$(uuidgen) --change-name=7:'tfm_primary' \
++        --new=8:32784:$SE_BL2_PARTITION_SIZE --typecode=8:$SE_BL2_TYPE_UUID --partition-guid=8:$(uuidgen) --change-name=8:'bl2_secondary' \
++        --new=9:33072:$TFM_S_PARTITION_SIZE --typecode=9:$TFM_TYPE_UUID --partition-guid=9:$(uuidgen) --change-name=9:'tfm_secondary' \
+         --new=10:65496:65501  --partition-guid=10:$(uuidgen) --change-name=10:'reserved_2' \
+         $IMAGE
+ 
+@@ -93,7 +95,7 @@ sgdisk  --mbrtogpt \
+ # Write partitions
+ # conv=notrunc avoids truncation to keep the geometry of the image.
+ dd if=$BIN_DIR/bl2_signed.bin of=${IMAGE}  seek=72 conv=notrunc
+-dd if=$BIN_DIR/tfm_s_signed.bin of=${IMAGE} seek=272 conv=notrunc
++dd if=$BIN_DIR/tfm_s_signed.bin of=${IMAGE} seek=360 conv=notrunc
+ 
+ # Print the gpt table
+ sgdisk -p $IMAGE
+diff --git a/platform/ext/target/arm/corstone1000/partition/flash_layout.h b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+index 9fc1d9fa63..73c430ce57 100644
+--- a/platform/ext/target/arm/corstone1000/partition/flash_layout.h
++++ b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+@@ -92,7 +92,7 @@
+ #define FLASH_DEV_NAME_BL1              FLASH_DEV_NAME
+ 
+ /* Static Configurations of the Flash */
+-#define SE_BL2_PARTITION_SIZE           (0x18000)    /* 96 KB */
++#define SE_BL2_PARTITION_SIZE           (0x24000)    /* 144 KB */
+ #define SE_BL2_BANK_0_OFFSET            (0x9000)  /* 72nd LBA */
+ #define SE_BL2_BANK_1_OFFSET            (0x1002000)  /* 32784th LBA */
+ 
+@@ -137,7 +137,7 @@
+ 
+ /* Bank configurations */
+ #define BANK_PARTITION_SIZE             (0xFE0000)   /* 15.875 MB */
+-#define TFM_PARTITION_SIZE              (0x5C000)    /* 368 KB */
++#define TFM_PARTITION_SIZE              (0x50000)    /* 320 KB */
+ 
+ /************************************************************/
+ /* Bank : Images flash offsets are with respect to the bank */
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0013-CC312-ADAC-Add-PSA_WANT_ALG_SHA_256-definition.patch

@@ -0,0 +1,42 @@
+From 756cfad0cc05e7f4c02faa74aea14962aa54420c Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Wed, 31 Jul 2024 13:38:09 +0200
+Subject: [PATCH 2/3] CC312: ADAC: Add PSA_WANT_ALG_SHA_256 definition
+
+The bl2_mbedcrypto_config is linked to the psa_adac_cc312 target so
+the MCUBOOT_PSA_CRYPTO_CONFIG_FILEPATH and
+MCUBOOT_MBEDCRYPTO_CONFIG_FILEPATH configs are used for the ADAC driver
+too. The MCUBOOT_USE_PSA_CRYPTO is OFF by default, that means the
+MCUBOOT_PSA_CRYPTO_CONFIG_FILEPATH is not included during the build so
+the PSA_WANT_ALG_SHA_256 is not defined for the ADAC driver. Because
+of this, the PSA_HASH_MAX_SIZE is not set correctly for the sources
+of the psa_adac_cc312 target. This caused runtime issues.
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/31131]
+---
+ platform/ext/accelerator/cc312/psa-adac/CMakeLists.txt | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/platform/ext/accelerator/cc312/psa-adac/CMakeLists.txt b/platform/ext/accelerator/cc312/psa-adac/CMakeLists.txt
+index cb0553b40a..d7f5a54f3c 100644
+--- a/platform/ext/accelerator/cc312/psa-adac/CMakeLists.txt
++++ b/platform/ext/accelerator/cc312/psa-adac/CMakeLists.txt
+@@ -1,5 +1,5 @@
+ #-------------------------------------------------------------------------------
+-# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
++# Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+@@ -32,6 +32,7 @@ target_compile_options(psa_adac_cc312
+         -DCC_IOT
+         -DUSE_MBEDTLS_CRYPTOCELL
+         -D_INTERNAL_CC_NO_RSA_SCHEME_15_SUPPORT
++        -DPSA_WANT_ALG_SHA_256
+ )
+ 
+ target_link_libraries(psa_adac_cc312
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0013-bl2-corstone-1000-Remove-psa_adac_to_tfm_apply_permi.patch

@@ -1,51 +0,0 @@
-From 2165f9db2257905d20722a2b87ceb53f320fc198 Mon Sep 17 00:00:00 2001
-From: Devaraj Ranganna <devaraj.ranganna@arm.com>
-Date: Mon, 22 Sep 2025 12:48:57 +0100
-Subject: [PATCH 1/2] bl2: corstone-1000: Remove
- `psa_adac_to_tfm_apply_permissions`
-
-The API `psa_adac_to_tfm_apply_permissions` is added to `psa-adac`
-library. Therefore, remove it from
-`platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c`.
-
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
----
- .../arm/corstone1000/bl2/boot_hal_bl2.c       | 21 -------------------
- 1 file changed, 21 deletions(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c b/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c
-index 2abcfb5fd3..8c4eb80d03 100644
---- a/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c
-+++ b/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c
-@@ -111,27 +111,6 @@ static bool fill_flash_map_with_fip_data(uint8_t boot_index) {
- #endif /* !TFM_S_REG_TEST */
- 
- #ifdef PLATFORM_PSA_ADAC_SECURE_DEBUG
--int psa_adac_to_tfm_apply_permissions(uint8_t permissions_mask[16])
--{
--    (void)permissions_mask;
--
--    int ret;
--    uint32_t dcu_reg_values[4];
--
--    /* Below values provide same access as when platform is in development
--       life cycle state */
--    dcu_reg_values[0] = 0xffffe7fc;
--    dcu_reg_values[1] = 0x800703ff;
--    dcu_reg_values[2] = 0xffffffff;
--    dcu_reg_values[3] = 0xffffffff;
--
--    ret = crypto_hw_apply_debug_permissions((uint8_t*)dcu_reg_values, 16);
--    BOOT_LOG_INF("%s: debug permission apply %s\n\r", __func__,
--            (ret == 0) ? "success" : "fail");
--
--    return ret;
--}
--
- uint8_t secure_debug_rotpk[32];
- #endif /* PLATFORM_PSA_ADAC_SECURE_DEBUG */
- 
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0014-Platform-CS1000-Add-crypto-configs-for-ADAC.patch

@@ -0,0 +1,41 @@
+From 8d6ed0ac3b1eee4b1e279993ec351e9bd80b68dc Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Wed, 31 Jul 2024 13:38:27 +0200
+Subject: [PATCH] Platform: CS1000: Add crypto configs for ADAC
+
+The psa_adac_psa_crypto target needs the MBEDTLS_CONFIG_FILE and
+MBEDTLS_PSA_CRYPTO_CONFIG_FILE defines in order to build correctly.
+The default crypto config files are used here.
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Submitted [https://review.trustedfirmware.org/c/TF-M/trusted-firmware-m/+/31132]
+---
+ platform/ext/target/arm/corstone1000/CMakeLists.txt | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index 530c4059d..3709bf3ec 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
++++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -412,6 +412,18 @@ if (${PLATFORM_PSA_ADAC_SECURE_DEBUG})
+         PRIVATE
+             platform_bl2
+     )
++
++    target_compile_definitions(psa_adac_psa_crypto
++        PRIVATE
++            MBEDTLS_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default.h"
++            MBEDTLS_PSA_CRYPTO_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/crypto_config_default.h"
++    )
++
++    target_link_libraries(psa_adac_psa_crypto
++        PRIVATE
++            psa_crypto_library_config
++    )
++
+ endif()
+ 
+ find_package(Python3)
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0014-bl2-corstone-1000-secure-debug-waiting-in-CM-LCS.patch

@@ -1,56 +0,0 @@
-From fddaf5d297f56305b50b672477cabb840d6f426b Mon Sep 17 00:00:00 2001
-From: Devaraj Ranganna <devaraj.ranganna@arm.com>
-Date: Mon, 22 Sep 2025 12:59:43 +0100
-Subject: [PATCH 2/2] bl2: corstone-1000: secure debug waiting in CM LCS
-
-Currently, when the device is in Secure Enable (SE) LCS state, setting
-`dcu_en` register causes CC-312 reset, which effectively resets the
-device as they are both on same power domain. Therefore, temporarily
-disable moving SE enable before waiting for secure debug notification.
-The device will be in CM provisioned state.
-
-Long-term solution is to implement a solution similar to RSE, secure
-debug handshake is completed and then a reset is triggered and `dcu_en`
-is applied during bl2.
-
-Upstream-Status: Inappropriate [Need to be redesigned]
-Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
----
- .../ext/target/arm/corstone1000/bl2/boot_hal_bl2.c  | 13 ++++++++++++-
- 1 file changed, 12 insertions(+), 1 deletion(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c b/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c
-index 8c4eb80d03..bf7b62881a 100644
---- a/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c
-+++ b/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c
-@@ -165,7 +165,18 @@ int32_t boot_platform_post_init(void)
-     }
- 
- #ifdef PLATFORM_PSA_ADAC_SECURE_DEBUG
-+    /*  TODO: Currently, when the device is in Secure Enable (SE) LCS state,
-+        setting `dcu_en` register causes CC-312 reset, which effectively resets
-+        the device as they are both on same power domain. Therefore, temporarily
-+        disable moving SE enable before waiting for secure debug notification.
-+        The device will be in CM provisioned state.
-+
-+        Long-term solution is to implement a solution similar to RSE, secure
-+        debug handshake is completed and then a reset is triggered and `dcu_en`
-+        is applied during bl2.
-+
-     if (!tfm_plat_provisioning_is_required()) {
-+    */
- 
-         plat_err = tfm_plat_otp_read(PLAT_OTP_ID_SECURE_DEBUG_PK, 32, secure_debug_rotpk);
-         if (plat_err != TFM_PLAT_ERR_SUCCESS) {
-@@ -176,7 +187,7 @@ int32_t boot_platform_post_init(void)
-         BOOT_LOG_INF("%s: Corstone-1000 Secure Debug is a %s.\r\n", __func__,
-                 (result == 0) ? "success" : "failure");
- 
--    }
-+  /*}*/
- #endif
- 
-     return 0;
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0015-CC3XX-Add-logging-on-cc3xx_dcu.c.patch

@@ -1,88 +0,0 @@
-From 6c2aae4f5dae05d12b834ea8ca5c7da505ffd965 Mon Sep 17 00:00:00 2001
-From: Antonio de Angelis <Antonio.deAngelis@arm.com>
-Date: Thu, 18 Sep 2025 11:17:46 +0100
-Subject: [PATCH 1/4] CC3XX: Add logging on cc3xx_dcu.c
-
-Helps understanding which values are being applied and the
-current status of the system (current DCU opens, DCU locks and
-the restriction mask).
-
-Upstream-Status: Backport [7d3931b4f02ea253f065d593743a7c2e0cbca0d7]
-Signed-off-by: Antonio de Angelis <antonio.deangelis@arm.com>
-Change-Id: I426ee064a0008d8031aabdea91fa771b8c892fe4
-
----
- .../cc3xx/low_level_driver/src/cc3xx_dcu.c    | 29 +++++++++++++++++++
- 1 file changed, 29 insertions(+)
-
-diff --git a/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c b/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c
-index bc23ed6aba..ce9b1afc4a 100644
---- a/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c
-+++ b/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c
-@@ -10,6 +10,9 @@
- #include <assert.h>
- #include <string.h>
- 
-+/* FixMe: Remove this when CC3XX_INFO logging gets sorted */
-+#define CC3XX_INFO(...)
-+
- /**
-  * @brief Check that the requested permissions are in accordance with the
-  *        hardware restriction mask
-@@ -21,6 +24,12 @@ static cc3xx_err_t check_dcu_restriction_mask(const uint32_t *val)
- {
-     size_t idx;
- 
-+    CC3XX_INFO("icv_dcu_restriction_mask: 0x%08x_%08x_%08x_%08x\r\n",
-+               P_CC3XX->ao.ao_icv_dcu_restriction_mask[0],
-+               P_CC3XX->ao.ao_icv_dcu_restriction_mask[1],
-+               P_CC3XX->ao.ao_icv_dcu_restriction_mask[2],
-+               P_CC3XX->ao.ao_icv_dcu_restriction_mask[3]);
-+
-     for (idx = 0; idx < sizeof(P_CC3XX->ao.ao_icv_dcu_restriction_mask) / sizeof(uint32_t); idx++) {
-         if (val[idx] & ~P_CC3XX->ao.ao_icv_dcu_restriction_mask[idx]) {
-             return CC3XX_ERR_DCU_MASK_MISMATCH;
-@@ -42,6 +51,18 @@ static cc3xx_err_t check_dcu_locks(const uint32_t *val)
-     size_t idx;
-     uint32_t dcu_has_to_change;
- 
-+    CC3XX_INFO("Current host_dcu_en: 0x%08x_%08x_%08x_%08x\r\n",
-+               P_CC3XX->ao.host_dcu_en[0],
-+               P_CC3XX->ao.host_dcu_en[1],
-+               P_CC3XX->ao.host_dcu_en[2],
-+               P_CC3XX->ao.host_dcu_en[3]);
-+
-+    CC3XX_INFO("host_dcu_lock: 0x%08x_%08x_%08x_%08x\r\n",
-+               P_CC3XX->ao.host_dcu_lock[0],
-+               P_CC3XX->ao.host_dcu_lock[1],
-+               P_CC3XX->ao.host_dcu_lock[2],
-+               P_CC3XX->ao.host_dcu_lock[3]);
-+
-     for (idx = 0; idx < sizeof(P_CC3XX->ao.host_dcu_en) / sizeof(uint32_t); idx++) {
-         /* Check if the host_dcu_en has to change */
-         dcu_has_to_change = P_CC3XX->ao.host_dcu_en[idx] ^ val[idx];
-@@ -123,6 +144,12 @@ cc3xx_err_t cc3xx_dcu_set_enabled(const uint8_t *permissions_mask, size_t len)
-         dcu_en_requested[idx] = *((uint32_t *)(permissions_mask + (idx*sizeof(uint32_t))));
-     }
- 
-+    CC3XX_INFO("Requested host_dcu_en: 0x%08x_%08x_%08x_%08x\r\n",
-+               dcu_en_requested[0],
-+               dcu_en_requested[1],
-+               dcu_en_requested[2],
-+               dcu_en_requested[3]);
-+
-     /* Check the restriction mask for the dcu_en*/
-     err = check_dcu_restriction_mask(dcu_en_requested);
-     if (err != CC3XX_ERR_SUCCESS) {
-@@ -139,6 +166,8 @@ cc3xx_err_t cc3xx_dcu_set_enabled(const uint8_t *permissions_mask, size_t len)
-         P_CC3XX->ao.host_dcu_en[idx] = dcu_en_requested[idx];
-     }
- 
-+    CC3XX_INFO("Requested host_dcu_en applied successfully\r\n");
-+
-     return CC3XX_ERR_SUCCESS;
- }
- /** @} */ // end of cc3xx_dcu
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0015-Platform-CS1000-Fix-platform-name-in-logs.patch

@@ -0,0 +1,27 @@
+From 8f0cd9710be508adab91d8b5ab5aa2d39e89c287 Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Wed, 31 Jul 2024 19:57:33 +0200
+Subject: [PATCH] Platform: CS1000: Fix platform name in logs
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Backport [c3fa68995b247c802589890c6ea3e721127b0c78]
+---
+ platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c b/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c
+index 8aacd877e4..f5baf08cb4 100644
+--- a/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c
++++ b/platform/ext/target/arm/corstone1000/bl2/boot_hal_bl2.c
+@@ -192,7 +192,7 @@ int32_t boot_platform_post_init(void)
+         }
+ 
+         result = tfm_to_psa_adac_corstone1000_secure_debug(secure_debug_rotpk, 32);
+-        BOOT_LOG_INF("%s: dipda_secure_debug is a %s.\r\n", __func__,
++        BOOT_LOG_INF("%s: Corstone-1000 Secure Debug is a %s.\r\n", __func__,
+                 (result == 0) ? "success" : "failure");
+ 
+     }
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0016-CC3XX-DCU-Check-dcu_en-against-the-permanent_disable.patch

@@ -1,72 +0,0 @@
-From b51461b88a0fb4ab60e21fcf7f85503e0a7aade0 Mon Sep 17 00:00:00 2001
-From: Antonio de Angelis <Antonio.deAngelis@arm.com>
-Date: Thu, 18 Sep 2025 13:02:36 +0100
-Subject: [PATCH 2/4] CC3XX: DCU: Check dcu_en against the
- permanent_disable_mask
-
-Regardless of the lifecycle state, there is a permanent disable
-mask register against which the required DCU_EN need to be checked.
-
-Upstream-Status: Backport [ab8edf16290fc13aa2eb5f5149235613c4f7c9a0]
-Signed-off-by: Antonio de Angelis <antonio.deangelis@arm.com>
-Change-Id: I2b4435d6ae7ebb8238987be06ac0c3b40b6dc991
-
----
- .../cc3xx/low_level_driver/src/cc3xx_dcu.c    | 34 ++++++++++++++++++-
- 1 file changed, 33 insertions(+), 1 deletion(-)
-
-diff --git a/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c b/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c
-index ce9b1afc4a..089589f278 100644
---- a/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c
-+++ b/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c
-@@ -39,6 +39,32 @@ static cc3xx_err_t check_dcu_restriction_mask(const uint32_t *val)
-     return CC3XX_ERR_SUCCESS;
- }
- 
-+/**
-+ * @brief Check that the requested permissions are in accordance with the
-+ *        permanent disable mask. A 1 in the mask means disabled
-+ *
-+ * @param[in] val Sets of permissions, i.e. host_dcu_en to check as an array of 4 words
-+ * @return cc3xx_err_t CC3XX_ERR_SUCCESS or CC3XX_ERR_DCU_MASK_MISMATCH
-+ */
-+static cc3xx_err_t check_dcu_permanent_disable_mask(const uint32_t *val)
-+{
-+    size_t idx;
-+
-+    CC3XX_INFO("permanent_disable_mask: 0x%08x_%08x_%08x_%08x\r\n",
-+               P_CC3XX->ao.ao_permanent_disable_mask[0],
-+               P_CC3XX->ao.ao_permanent_disable_mask[1],
-+               P_CC3XX->ao.ao_permanent_disable_mask[2],
-+               P_CC3XX->ao.ao_permanent_disable_mask[3]);
-+
-+    for (idx = 0; idx < sizeof(P_CC3XX->ao.ao_permanent_disable_mask) / sizeof(uint32_t); idx++) {
-+        if (val[idx] & P_CC3XX->ao.ao_permanent_disable_mask[idx]) {
-+            return CC3XX_ERR_DCU_MASK_MISMATCH;
-+        }
-+    }
-+
-+    return CC3XX_ERR_SUCCESS;
-+}
-+
- /**
-  * @brief Check that the requested permissions are in accordance with the
-  *        current status of the DCU locks
-@@ -150,7 +176,13 @@ cc3xx_err_t cc3xx_dcu_set_enabled(const uint8_t *permissions_mask, size_t len)
-                dcu_en_requested[2],
-                dcu_en_requested[3]);
- 
--    /* Check the restriction mask for the dcu_en*/
-+    /* Check the permanent disable mask for the dcu_en */
-+    err = check_dcu_permanent_disable_mask(dcu_en_requested);
-+    if (err != CC3XX_ERR_SUCCESS) {
-+        return err;
-+    }
-+
-+    /* Check the ICV restriction mask for the dcu_en */
-     err = check_dcu_restriction_mask(dcu_en_requested);
-     if (err != CC3XX_ERR_SUCCESS) {
-         return err;
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0017-CC3XX-DCU-Enable-checking-ICV-restriction-mask-confi.patch

@@ -1,118 +0,0 @@
-From 7607a80c43e6cdc9aab6aea61dcc6b4a567136b2 Mon Sep 17 00:00:00 2001
-From: Antonio de Angelis <Antonio.deAngelis@arm.com>
-Date: Fri, 19 Sep 2025 10:21:59 +0100
-Subject: [PATCH 3/4] CC3XX: DCU: Enable checking ICV restriction mask
- configurable
-
-To allow for platforms which might not convey the CM/DM cert
-enable information to the driver to work correctly. The ICV
-restriction mask is a software only feature hence restrictions
-won't be taken into account when the feature is not enabled in FW.
-
-Upstream-Status: Backport [ffb14450be486b5cb9cc8d0cce8903fc3bb5de34]
-Signed-off-by: Antonio de Angelis <antonio.deangelis@arm.com>
-Change-Id: Ie5b7efadf9ef1f722546585669383e660acf97a9
-
----
- .../target/arm/corstone1000/cc3xx_config.h    |  3 +++
- .../cc3xx/low_level_driver/src/cc3xx_dcu.c    | 21 ++++++++++++++-----
- .../target/arm/musca_b1/cc312/cc3xx_config.h  |  3 +++
- 3 files changed, 22 insertions(+), 5 deletions(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/cc3xx_config.h b/platform/ext/target/arm/corstone1000/cc3xx_config.h
-index 199a99e1ca..a63a2df07a 100644
---- a/platform/ext/target/arm/corstone1000/cc3xx_config.h
-+++ b/platform/ext/target/arm/corstone1000/cc3xx_config.h
-@@ -13,6 +13,9 @@
- #define CC3XX_CONFIG_BASE_ADDRESS (CC3XX_BASE_S)
- #endif /* CC3XX_CONFIG_BASE_ADDRESS */
- 
-+/* Whether the DCU apply permission function enforces ICV restriction mask */
-+#define CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK
-+
- /* Whether uint32_t accesses must be strictly 4-byte aligned */
- /* CC3XX_CONFIG_STRICT_UINT32_T_ALIGNMENT */
- 
-diff --git a/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c b/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c
-index 089589f278..f2b70819c0 100644
---- a/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c
-+++ b/platform/ext/target/arm/drivers/cc3xx/low_level_driver/src/cc3xx_dcu.c
-@@ -1,18 +1,26 @@
- /*
-- * Copyright (c) 2024, The TrustedFirmware-M Contributors. All rights reserved.
-+ * SPDX-FileCopyrightText: Copyright The TrustedFirmware-M Contributors
-  *
-  * SPDX-License-Identifier: BSD-3-Clause
-  *
-  */
- 
--#include "cc3xx_dcu.h"
--#include "cc3xx_dev.h"
-+#ifndef CC3XX_CONFIG_FILE
-+#include "cc3xx_config.h"
-+#else
-+#include CC3XX_CONFIG_FILE
-+#endif
-+
- #include <assert.h>
- #include <string.h>
- 
-+#include "cc3xx_dcu.h"
-+#include "cc3xx_dev.h"
-+
- /* FixMe: Remove this when CC3XX_INFO logging gets sorted */
- #define CC3XX_INFO(...)
- 
-+#ifdef CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK
- /**
-  * @brief Check that the requested permissions are in accordance with the
-  *        hardware restriction mask
-@@ -20,7 +28,7 @@
-  * @param[in] val Sets of permissions, i.e. host_dcu_en to check as an array of 4 words
-  * @return cc3xx_err_t CC3XX_ERR_SUCCESS or CC3XX_ERR_DCU_MASK_MISMATCH
-  */
--static cc3xx_err_t check_dcu_restriction_mask(const uint32_t *val)
-+static cc3xx_err_t check_dcu_icv_restriction_mask(const uint32_t *val)
- {
-     size_t idx;
- 
-@@ -38,6 +46,7 @@ static cc3xx_err_t check_dcu_restriction_mask(const uint32_t *val)
- 
-     return CC3XX_ERR_SUCCESS;
- }
-+#endif /* CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK */
- 
- /**
-  * @brief Check that the requested permissions are in accordance with the
-@@ -182,11 +191,13 @@ cc3xx_err_t cc3xx_dcu_set_enabled(const uint8_t *permissions_mask, size_t len)
-         return err;
-     }
- 
-+#ifdef CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK
-     /* Check the ICV restriction mask for the dcu_en */
--    err = check_dcu_restriction_mask(dcu_en_requested);
-+    err = check_dcu_icv_restriction_mask(dcu_en_requested);
-     if (err != CC3XX_ERR_SUCCESS) {
-         return err;
-     }
-+#endif /* CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK */
- 
-     /* Check if any dcu_lock has been locked for the corresponding dcu_en */
-     err = check_dcu_locks(dcu_en_requested);
-diff --git a/platform/ext/target/arm/musca_b1/cc312/cc3xx_config.h b/platform/ext/target/arm/musca_b1/cc312/cc3xx_config.h
-index cd38d3e837..6fc7ae0fa0 100644
---- a/platform/ext/target/arm/musca_b1/cc312/cc3xx_config.h
-+++ b/platform/ext/target/arm/musca_b1/cc312/cc3xx_config.h
-@@ -13,6 +13,9 @@
- #define CC3XX_CONFIG_BASE_ADDRESS (CC3XX_BASE_S)
- #endif /* CC3XX_CONFIG_BASE_ADDRESS */
- 
-+/* Whether the DCU apply permission function enforces ICV restriction mask */
-+#define CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK
-+
- /* Whether uint32_t accesses must be strictly 4-byte aligned */
- /* CC3XX_CONFIG_STRICT_UINT32_T_ALIGNMENT */
- 
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0017-Platform-CS1000-Remove-unused-BL1-files.patch

@@ -1,13 +1,12 @@
-From 778d62d8ebe91212363cdab2fa1eef6a977ae6e2 Mon Sep 17 00:00:00 2001
-From: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
-Date: Wed, 13 Aug 2025 14:02:57 +0000
-Subject: [PATCH 1/7] Platform: CS1000: Remove unused BL1 files
+From 67e5aa83efce5f75df1c5d027e2d52f0da2eaba0 Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Thu, 5 Sep 2024 17:21:50 +0200
+Subject: [PATCH 1/5] Platform: CS1000: Remove unused BL1 files
 
 These files are not referenced anywhere so removed them to prevent
 confusion.
-
 Signed-off-by: Bence Balogh <bence.balogh@arm.com>
-Upstream-Status: Backport [9a7bdf9ef595196e1e518a27d3c79079aedb5bda]
+Upstream-Status: Pending [Not submitted to upstream yet]
 ---
  .../arm/corstone1000/bl1/CMakeLists.txt       | 345 ------------------
  .../arm/corstone1000/bl1/bl1_security_cnt.c   |  75 ----
@@ -17,7 +16,7 @@ Upstream-Status: Backport [9a7bdf9ef595196e1e518a27d3c79079aedb5bda]
 
 diff --git a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
 deleted file mode 100644
-index d85b0611d..000000000
+index 5e140eecf6..0000000000
 --- a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
 +++ /dev/null
 @@ -1,345 +0,0 @@
@@ -54,14 +53,14 @@ index d85b0611d..000000000
 -
 -add_convert_to_bin_target(bl1)
 -
--# bl2_crypto reused as it is, but it pulls the MCUBOOT_IMAGE_NUMBER=${MCUBOOT_IMAGE_NUMBER}
+-# bl2_mbedcrypto reused as it is, but it pulls the MCUBOOT_IMAGE_NUMBER=${MCUBOOT_IMAGE_NUMBER}
 -# configuration, where image number is 3. (Coming from BL2 build). To not to collide with BL1's
 -# build where image number is 1 mbedcrypto library is separated from the build of other source
 -# files.
 -target_link_libraries(bl1
 -    PRIVATE
 -        bl1_main
--        bl2_crypto
+-        bl2_mbedcrypto
 -        cmsis_stack_override
 -        cmsis
 -)
@@ -160,7 +159,7 @@ index d85b0611d..000000000
 -target_link_libraries(bl1_main
 -    PRIVATE
 -        mcuboot_config
--        bl2_crypto_config
+-        bl2_mbedcrypto_config
 -)
 -
 -target_include_directories(bl1_main
@@ -368,7 +367,7 @@ index d85b0611d..000000000
 -)
 diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c b/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c
 deleted file mode 100644
-index 32c1481cc..000000000
+index 32c1481cca..0000000000
 --- a/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c
 +++ /dev/null
 @@ -1,75 +0,0 @@
@@ -448,5 +447,5 @@ index 32c1481cc..000000000
 -    return 0;
 -}
 -- 
-2.43.0
+2.25.1
 

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0018-Platform-ADAC-Musca-B1-and-Corstone-1000-do-not-chec.patch

@@ -1,49 +0,0 @@
-From d50f841de57c0848595834ab8cde4c89e4ffc1ca Mon Sep 17 00:00:00 2001
-From: Antonio de Angelis <Antonio.deAngelis@arm.com>
-Date: Fri, 19 Sep 2025 10:31:21 +0100
-Subject: [PATCH 4/4] Platform: ADAC: Musca-B1 and Corstone-1000 do not check
- ICV restrictions mask
-
-As the permissions being requested in our reference certificates are not
-taking into consideration this aspect yet. As restriction checking is purely
-a FW feature, this means that ICV restrictions are not taken into any
-considerations (i.e. which DCU_EN are exclusively reserved for CM or DM)
-
-Upstream-Status: Backport [392f6752bd70052371278c93693b8c3d95cce0c9]
-Signed-off-by: Antonio de Angelis <antonio.deangelis@arm.com>
-Change-Id: I8ef4e432a395e1938d749082fbd25fa58916211c
-
----
- platform/ext/target/arm/corstone1000/cc3xx_config.h   | 2 +-
- platform/ext/target/arm/musca_b1/cc312/cc3xx_config.h | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/cc3xx_config.h b/platform/ext/target/arm/corstone1000/cc3xx_config.h
-index a63a2df07a..e3f7843986 100644
---- a/platform/ext/target/arm/corstone1000/cc3xx_config.h
-+++ b/platform/ext/target/arm/corstone1000/cc3xx_config.h
-@@ -14,7 +14,7 @@
- #endif /* CC3XX_CONFIG_BASE_ADDRESS */
- 
- /* Whether the DCU apply permission function enforces ICV restriction mask */
--#define CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK
-+/* #define CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK */
- 
- /* Whether uint32_t accesses must be strictly 4-byte aligned */
- /* CC3XX_CONFIG_STRICT_UINT32_T_ALIGNMENT */
-diff --git a/platform/ext/target/arm/musca_b1/cc312/cc3xx_config.h b/platform/ext/target/arm/musca_b1/cc312/cc3xx_config.h
-index 6fc7ae0fa0..1faf4a06e5 100644
---- a/platform/ext/target/arm/musca_b1/cc312/cc3xx_config.h
-+++ b/platform/ext/target/arm/musca_b1/cc312/cc3xx_config.h
-@@ -14,7 +14,7 @@
- #endif /* CC3XX_CONFIG_BASE_ADDRESS */
- 
- /* Whether the DCU apply permission function enforces ICV restriction mask */
--#define CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK
-+/* #define CC3XX_CONFIG_DCU_ICV_RESTRICTION_MASK_CHECK */
- 
- /* Whether uint32_t accesses must be strictly 4-byte aligned */
- /* CC3XX_CONFIG_STRICT_UINT32_T_ALIGNMENT */
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0018-Platform-CS1000-Remove-duplicated-metadata-write.patch

@@ -0,0 +1,61 @@
+From 60793058794f0ac8ea35a69b2dddf97ccba1acdb Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Thu, 5 Sep 2024 21:29:07 +0200
+Subject: [PATCH 2/5] Platform: CS1000: Remove duplicated metadata write
+
+The metadata replica_2 was written twice which is not needed.
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 28 -------------------
+ 1 file changed, 28 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index d0028a56d8..2b69447dc5 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
++++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -499,20 +499,6 @@ static enum fwu_agent_error_t metadata_write(
+         return FWU_AGENT_ERROR;
+     }
+ 
+-    FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
+-                  FWU_METADATA_REPLICA_2_OFFSET, sizeof(struct fwu_metadata));
+-
+-    ret = FWU_METADATA_FLASH_DEV.EraseSector(FWU_METADATA_REPLICA_2_OFFSET);
+-    if (ret != ARM_DRIVER_OK) {
+-        return FWU_AGENT_ERROR;
+-    }
+-
+-    ret = FWU_METADATA_FLASH_DEV.ProgramData(FWU_METADATA_REPLICA_2_OFFSET,
+-                                p_metadata, sizeof(struct fwu_metadata));
+-    if (ret < 0 || ret != sizeof(struct fwu_metadata)) {
+-        return FWU_AGENT_ERROR;
+-    }
+-
+     FWU_LOG_MSG("%s: success: active = %u, previous = %d\n\r", __func__,
+                   p_metadata->active_index, p_metadata->previous_active_index);
+     return FWU_AGENT_SUCCESS;
+@@ -569,20 +555,6 @@ static enum fwu_agent_error_t metadata_write(
+         return FWU_AGENT_ERROR;
+     }
+ 
+-    FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
+-                  FWU_METADATA_REPLICA_2_OFFSET, sizeof(struct fwu_metadata));
+-
+-    ret = FWU_METADATA_FLASH_DEV.EraseSector(FWU_METADATA_REPLICA_2_OFFSET);
+-    if (ret != ARM_DRIVER_OK) {
+-        return FWU_AGENT_ERROR;
+-    }
+-
+-    ret = FWU_METADATA_FLASH_DEV.ProgramData(FWU_METADATA_REPLICA_2_OFFSET,
+-                                p_metadata, sizeof(struct fwu_metadata));
+-    if (ret < 0 || ret != sizeof(struct fwu_metadata)) {
+-        return FWU_AGENT_ERROR;
+-    }
+-
+     FWU_LOG_MSG("%s: success: active = %u, previous = %d\n\r", __func__,
+                   p_metadata->active_index, p_metadata->previous_active_index);
+     return FWU_AGENT_SUCCESS;
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0019-Platform-CS1000-Fix-compiler-switch-in-BL1.patch

@@ -0,0 +1,193 @@
+From 09827a44518b05a2cc58602dda18474973abfb83 Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Thu, 5 Sep 2024 17:28:56 +0200
+Subject: [PATCH 3/5] Platform: CS1000: Fix compiler switch in BL1
+
+The fwu_agent.c used the "BL1" definition to check if the source file
+is building for the BL1 or for the TFM_S target.
+But the "BL1" definition is added to the build flags for every file
+that links against platform_region_defs, see
+tfm/cmake/spe-CMakeLists.cmake:
+
+target_compile_definitions(platform_region_defs
+    INTERFACE
+        $<$<BOOL:${BL1}>:BL1>
+       ....
+)
+
+This means the "#if BL1" condition was true for both cases.
+
+This commit:
+- Adds a new definition that is only added to the
+  platform_bl1_1 target.
+- Fixes the #elif with no expression error that came up.
+- Moves the partition table loading because previously it was not
+  loaded during the runtime TFM_S execution, only in BL2.
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ .../target/arm/corstone1000/CMakeLists.txt    |  7 ++++
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 33 +++++++++----------
+ 2 files changed, 23 insertions(+), 17 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index 89db1732a9..f6880cba3c 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
++++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -144,6 +144,7 @@ target_sources(platform_s
+         partition/gpt.c
+         $<$<NOT:$<BOOL:${PLATFORM_DEFAULT_OTP}>>:${PLATFORM_DIR}/ext/accelerator/cc312/otp_cc312.c>
+         rse_comms_permissions_hal.c
++        platform.c
+ )
+ 
+ if (PLATFORM_IS_FVP)
+@@ -213,6 +214,12 @@ target_compile_definitions(platform_bl1_1
+         $<$<BOOL:${CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING}>:CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING>
+         MBEDTLS_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/tfm_mbedcrypto_config_default.h"
+         MBEDTLS_PSA_CRYPTO_CONFIG_FILE="${CMAKE_SOURCE_DIR}/lib/ext/mbedcrypto/mbedcrypto_config/crypto_config_default.h"
++
++        # This definition is only added to the bl1_main target. There are
++        # files that are shared between the BL1 and TFM_S targets. This flag
++        # can be used if the BL1 target needs different implementation than
++        # the TFM_S target.
++        BL1_BUILD
+ )
+ 
+ target_include_directories(platform_bl1_1_interface
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index 2b69447dc5..9890eeaf90 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
++++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -21,7 +21,7 @@
+ #include "uefi_fmp.h"
+ #include "uart_stdout.h"
+ #include "soft_crc.h"
+-#if !BL1
++#ifndef BL1_BUILD
+ #include "partition.h"
+ #include "platform.h"
+ #endif
+@@ -197,7 +197,7 @@ extern ARM_DRIVER_FLASH FWU_METADATA_FLASH_DEV;
+ 
+ #define HOST_ACK_TIMEOUT_SEC    (6 * 60) /* ~seconds, not exact */
+ 
+-#if BL1
++#ifdef BL1_BUILD
+ static enum fwu_agent_error_t private_metadata_read(
+         struct fwu_private_metadata* p_metadata)
+ {
+@@ -220,7 +220,7 @@ static enum fwu_agent_error_t private_metadata_read(
+ 
+     return FWU_AGENT_SUCCESS;
+ }
+-#elif
++#else
+ static enum fwu_agent_error_t private_metadata_read(
+         struct fwu_private_metadata* p_metadata)
+ {
+@@ -253,7 +253,7 @@ static enum fwu_agent_error_t private_metadata_read(
+ }
+ #endif
+ 
+-#if BL1
++#ifdef BL1_BUILD
+ static enum fwu_agent_error_t private_metadata_write(
+         struct fwu_private_metadata* p_metadata)
+ {
+@@ -280,7 +280,7 @@ static enum fwu_agent_error_t private_metadata_write(
+     FWU_LOG_MSG("%s: success\n\r", __func__);
+     return FWU_AGENT_SUCCESS;
+ }
+-#elif
++#else
+ static enum fwu_agent_error_t private_metadata_write(
+         struct fwu_private_metadata* p_metadata)
+ {
+@@ -339,7 +339,7 @@ static enum fwu_agent_error_t metadata_validate(struct fwu_metadata *p_metadata)
+     return FWU_AGENT_SUCCESS;
+ }
+ 
+-#if BL1
++#ifdef BL1_BUILD
+ static enum fwu_agent_error_t metadata_read_without_validation(struct fwu_metadata *p_metadata)
+ {
+     int ret;
+@@ -362,7 +362,7 @@ static enum fwu_agent_error_t metadata_read_without_validation(struct fwu_metada
+ 
+     return FWU_AGENT_SUCCESS;
+ }
+-#elif
++#else
+ static enum fwu_agent_error_t metadata_read_without_validation(struct fwu_metadata *p_metadata)
+ {
+     uuid_t metadata_uuid = FWU_METADATA_TYPE_UUID;
+@@ -396,7 +396,7 @@ static enum fwu_agent_error_t metadata_read_without_validation(struct fwu_metada
+ }
+ #endif
+ 
+-#if BL1
++#ifdef BL1_BUILD
+ static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
+ {
+     int ret;
+@@ -423,7 +423,7 @@ static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
+ 
+     return FWU_AGENT_SUCCESS;
+ }
+-#elif
++#else
+ static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
+ {
+     uuid_t metadata_uuid = FWU_METADATA_TYPE_UUID;
+@@ -461,7 +461,7 @@ static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
+ #endif
+ 
+ 
+-#if BL1
++#ifdef BL1_BUILD
+ static enum fwu_agent_error_t metadata_write(
+                         struct fwu_metadata *p_metadata)
+ {
+@@ -503,7 +503,7 @@ static enum fwu_agent_error_t metadata_write(
+                   p_metadata->active_index, p_metadata->previous_active_index);
+     return FWU_AGENT_SUCCESS;
+ }
+-#elif
++#else
+ static enum fwu_agent_error_t metadata_write(
+                         struct fwu_metadata *p_metadata)
+ {
+@@ -567,11 +567,15 @@ enum fwu_agent_error_t fwu_metadata_init(void)
+     enum fwu_agent_error_t ret;
+     ARM_FLASH_INFO* flash_info;
+ 
+-
+     if (is_initialized) {
+         return FWU_AGENT_SUCCESS;
+     }
+ 
++    #ifndef BL1_BUILD
++    plat_io_storage_init();
++    partition_init(PLATFORM_GPT_IMAGE);
++    #endif
++
+     /* Code assumes everything fits into a sector */
+     if (sizeof(struct fwu_metadata) > FWU_METADATA_FLASH_SECTOR_SIZE) {
+         return FWU_AGENT_ERROR;
+@@ -605,11 +609,6 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
+ 
+     FWU_LOG_MSG("%s: enter\n\r", __func__);
+ 
+-#if !BL1
+-    plat_io_storage_init();
+-    partition_init(PLATFORM_GPT_IMAGE);
+-#endif
+-
+     ret = fwu_metadata_init();
+     if (ret) {
+         return ret;
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0020-Platform-CS1000-Validate-both-metadata-replicas.patch

@@ -0,0 +1,370 @@
+From 5fd2662e1f20b5c645ff0755e84424bae303fa45 Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Mon, 9 Sep 2024 09:42:58 +0200
+Subject: [PATCH] Platform: CS1000: Validate both metadata replicas
+
+According to the [1] both metadata replica integrity should be checked
+during the update agent initialization, and if one of the replica is
+corrupted then it should be fixed by copying the other replica.
+
+This commit:
+- Adds the integrity check and correction to the
+  corstone1000_fwu_host_ack() function. This function is called when
+  the Host core has booted.
+- Updates the metadata_read() function so both replica can be read.
+- Adds metadata_write_replica() function to write metadata replicas
+  separately.
+
+[1] https://developer.arm.com/documentation/den0118/a/?lang=en
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 167 ++++++++++++------
+ .../corstone1000/fw_update_agent/fwu_agent.h  |   7 +
+ 2 files changed, 119 insertions(+), 55 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index 92b918c67..aad6208e0 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
++++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -395,20 +395,33 @@ static enum fwu_agent_error_t metadata_read_without_validation(struct fwu_metada
+ #endif
+ 
+ #ifdef BL1_BUILD
+-static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
++static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata, uint8_t replica_num)
+ {
+     int ret;
++    uint32_t replica_offset = 0;
+ 
+-    FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
+-                  FWU_METADATA_REPLICA_1_OFFSET, sizeof(struct fwu_metadata));
++    FWU_LOG_MSG("%s: enter\n\r", __func__);
+ 
+     if (!p_metadata) {
+         return FWU_AGENT_ERROR;
+     }
+ 
+-    ret = FWU_METADATA_FLASH_DEV.ReadData(FWU_METADATA_REPLICA_1_OFFSET,
+-                                p_metadata, sizeof(struct fwu_metadata));
+-    if (ret < 0 || ret != sizeof(struct fwu_metadata)) {
++    if (replica_num == 1) {
++        replica_offset = FWU_METADATA_REPLICA_1_OFFSET;
++    } else if (replica_num == 2) {
++        replica_offset = FWU_METADATA_REPLICA_2_OFFSET;
++    } else {
++        FWU_LOG_MSG("%s: replica_num must be 1 or 2\n\r", __func__);
++        return FWU_AGENT_ERROR;
++    }
++
++    FWU_LOG_MSG("%s: flash addr = %u, size = %d\n\r", __func__,
++                  replica_offset, sizeof(*p_metadata));
++
++
++    ret = FWU_METADATA_FLASH_DEV.ReadData(replica_offset,
++                                p_metadata, sizeof(*p_metadata));
++    if (ret < 0 || ret != sizeof(*p_metadata)) {
+         return FWU_AGENT_ERROR;
+     }
+ 
+@@ -422,17 +435,27 @@ static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
+     return FWU_AGENT_SUCCESS;
+ }
+ #else
+-static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
++static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata, uint8_t replica_num)
+ {
+     uuid_t metadata_uuid = FWU_METADATA_TYPE_UUID;
+     partition_entry_t *part;
+     int ret;
+ 
++    FWU_LOG_MSG("%s: enter\n\r", __func__);
++
+     if (!p_metadata) {
+         return FWU_AGENT_ERROR;
+     }
+ 
+-    part = get_partition_entry_by_type(&metadata_uuid);
++    if (replica_num == 1) {
++        part = get_partition_entry_by_type(&metadata_uuid);
++    } else if (replica_num == 2) {
++        part = get_partition_replica_by_type(&metadata_uuid);
++    } else {
++        FWU_LOG_MSG("%s: replica_num must be 1 or 2\n\r", __func__);
++        return FWU_AGENT_ERROR;
++    }
++
+     if (!part) {
+         FWU_LOG_MSG("%s: FWU metadata partition not found\n\r", __func__);
+         return FWU_AGENT_ERROR;
+@@ -461,39 +484,38 @@ static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
+ 
+ #ifdef BL1_BUILD
+ static enum fwu_agent_error_t metadata_write(
+-                        struct fwu_metadata *p_metadata)
++                        struct fwu_metadata *p_metadata, uint8_t replica_num)
+ {
+     int ret;
++    uint32_t replica_offset = 0;
+ 
+-    FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
+-                  FWU_METADATA_REPLICA_1_OFFSET, sizeof(struct fwu_metadata));
++    FWU_LOG_MSG("%s: enter\n\r", __func__);
+ 
+     if (!p_metadata) {
+         return FWU_AGENT_ERROR;
+     }
+ 
+-    ret = FWU_METADATA_FLASH_DEV.EraseSector(FWU_METADATA_REPLICA_1_OFFSET);
+-    if (ret != ARM_DRIVER_OK) {
+-        return FWU_AGENT_ERROR;
+-    }
+-
+-    ret = FWU_METADATA_FLASH_DEV.ProgramData(FWU_METADATA_REPLICA_1_OFFSET,
+-                                p_metadata, sizeof(struct fwu_metadata));
+-    if (ret < 0 || ret != sizeof(struct fwu_metadata)) {
++    if (replica_num == 1) {
++        replica_offset = FWU_METADATA_REPLICA_1_OFFSET;
++    } else if (replica_num == 2) {
++        replica_offset = FWU_METADATA_REPLICA_2_OFFSET;
++    } else {
++        FWU_LOG_MSG("%s: replica_num must be 1 or 2\n\r", __func__);
+         return FWU_AGENT_ERROR;
+     }
+ 
+     FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
+-                  FWU_METADATA_REPLICA_2_OFFSET, sizeof(struct fwu_metadata));
++                  replica_offset, sizeof(*p_metadata));
+ 
+-    ret = FWU_METADATA_FLASH_DEV.EraseSector(FWU_METADATA_REPLICA_2_OFFSET);
++
++    ret = FWU_METADATA_FLASH_DEV.EraseSector(replica_offset);
+     if (ret != ARM_DRIVER_OK) {
+         return FWU_AGENT_ERROR;
+     }
+ 
+-    ret = FWU_METADATA_FLASH_DEV.ProgramData(FWU_METADATA_REPLICA_2_OFFSET,
+-                                p_metadata, sizeof(struct fwu_metadata));
+-    if (ret < 0 || ret != sizeof(struct fwu_metadata)) {
++    ret = FWU_METADATA_FLASH_DEV.ProgramData(replica_offset,
++                                p_metadata, sizeof(*p_metadata));
++    if (ret < 0 || ret != sizeof(*p_metadata)) {
+         return FWU_AGENT_ERROR;
+     }
+ 
+@@ -503,7 +525,7 @@ static enum fwu_agent_error_t metadata_write(
+ }
+ #else
+ static enum fwu_agent_error_t metadata_write(
+-                        struct fwu_metadata *p_metadata)
++                        struct fwu_metadata *p_metadata, uint8_t replica_num)
+ {
+     uuid_t metadata_uuid = FWU_METADATA_TYPE_UUID;
+     partition_entry_t *part;
+@@ -513,7 +535,15 @@ static enum fwu_agent_error_t metadata_write(
+         return FWU_AGENT_ERROR;
+     }
+ 
+-    part = get_partition_entry_by_type(&metadata_uuid);
++    if (replica_num == 1) {
++        part = get_partition_entry_by_type(&metadata_uuid);
++    } else if (replica_num == 2) {
++        part = get_partition_replica_by_type(&metadata_uuid);
++    } else {
++        FWU_LOG_MSG("%s: replica_num must be 1 or 2\n\r", __func__);
++        return FWU_AGENT_ERROR;
++    }
++
+     if (!part) {
+         FWU_LOG_MSG("%s: FWU metadata partition not found\n\r", __func__);
+         return FWU_AGENT_ERROR;
+@@ -533,32 +563,51 @@ static enum fwu_agent_error_t metadata_write(
+         return FWU_AGENT_ERROR;
+     }
+ 
+-    part = get_partition_replica_by_type(&metadata_uuid);
+-    if (!part) {
+-        FWU_LOG_MSG("%s: FWU metadata replica partition not found\n\r", __func__);
+-        return FWU_AGENT_ERROR;
+-    }
++    FWU_LOG_MSG("%s: success: active = %u, previous = %d\n\r", __func__,
++                  p_metadata->active_index, p_metadata->previous_active_index);
++    return FWU_AGENT_SUCCESS;
++}
++#endif
+ 
+-    FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
+-                  part->start, sizeof(struct fwu_metadata));
++static enum fwu_agent_error_t metadata_write_both_replica(
++                        struct fwu_metadata *p_metadata)
++{
++    enum fwu_agent_error_t ret = FWU_AGENT_ERROR;
+ 
+-    ret = FWU_METADATA_FLASH_DEV.EraseSector(part->start);
+-    if (ret != ARM_DRIVER_OK) {
+-        return FWU_AGENT_ERROR;
++    ret = metadata_write(&_metadata, 1);
++    if (ret) {
++        return ret;
+     }
+ 
+-    ret = FWU_METADATA_FLASH_DEV.ProgramData(part->start,
+-                                p_metadata, sizeof(struct fwu_metadata));
+-    if (ret < 0 || ret != sizeof(struct fwu_metadata)) {
+-        return FWU_AGENT_ERROR;
++    ret = metadata_write(&_metadata, 2);
++    if (ret) {
++        return ret;
+     }
+ 
+-    FWU_LOG_MSG("%s: success: active = %u, previous = %d\n\r", __func__,
+-                  p_metadata->active_index, p_metadata->previous_active_index);
+     return FWU_AGENT_SUCCESS;
+ }
+-#endif
+ 
++enum fwu_agent_error_t fwu_metadata_check_and_correct_integrity(void)
++{
++    enum fwu_agent_error_t ret_replica_1 = FWU_AGENT_ERROR;
++    enum fwu_agent_error_t ret_replica_2 = FWU_AGENT_ERROR;
++
++    /* Check integrity of both metadata replica */
++    ret_replica_1 = metadata_read(&_metadata, 1);
++    ret_replica_2 = metadata_read(&_metadata, 2);
++
++    if (ret_replica_1 != FWU_AGENT_SUCCESS && ret_replica_2 != FWU_AGENT_SUCCESS) {
++        return FWU_AGENT_ERROR;
++    } else if (ret_replica_1 == FWU_AGENT_SUCCESS && ret_replica_2 != FWU_AGENT_SUCCESS) {
++        metadata_read(&_metadata, 1);
++        metadata_write(&_metadata, 2);
++    } else if (ret_replica_1 != FWU_AGENT_SUCCESS && ret_replica_2 == FWU_AGENT_SUCCESS) {
++        metadata_read(&_metadata, 2);
++        metadata_write(&_metadata, 1);
++    }
++
++    return FWU_AGENT_SUCCESS;
++}
+ 
+ enum fwu_agent_error_t fwu_metadata_init(void)
+ {
+@@ -617,8 +666,8 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
+      * had a firmware data?. If yes, then don't initialize
+      * metadata
+      */
+-    metadata_read(&_metadata);
+-    if(_metadata.active_index < 2 || _metadata.previous_active_index <2){
++    metadata_read(&_metadata, 1);
++    if(_metadata.active_index < 2 || _metadata.previous_active_index < 2){
+     	if(_metadata.active_index ^ _metadata.previous_active_index)
+     		return FWU_AGENT_SUCCESS;
+     }
+@@ -652,13 +701,13 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
+     _metadata.crc_32 = crc32((uint8_t *)&_metadata.version,
+                              sizeof(struct fwu_metadata) - sizeof(uint32_t));
+ 
+-    ret = metadata_write(&_metadata);
++    ret = metadata_write_both_replica(&_metadata);
+     if (ret) {
+         return ret;
+     }
+ 
+-    memset(&_metadata, 0, sizeof(struct fwu_metadata));
+-    ret = metadata_read(&_metadata);
++    memset(&_metadata, 0, sizeof(_metadata));
++    ret = metadata_read(&_metadata, 1);
+     if (ret) {
+         return ret;
+     }
+@@ -825,7 +874,7 @@ static enum fwu_agent_error_t flash_full_capsule(
+     metadata->crc_32 = crc32((uint8_t *)&metadata->version,
+                               sizeof(struct fwu_metadata) - sizeof(uint32_t));
+ 
+-    ret = metadata_write(metadata);
++    ret = metadata_write_both_replica(metadata);
+     if (ret) {
+         return ret;
+     }
+@@ -852,7 +901,7 @@ enum fwu_agent_error_t corstone1000_fwu_flash_image(void)
+ 
+     Select_Write_Mode_For_Shared_Flash();
+ 
+-    if (metadata_read(&_metadata)) {
++    if (metadata_read(&_metadata, 1)) {
+         ret =  FWU_AGENT_ERROR;
+         goto out;
+     }
+@@ -938,7 +987,7 @@ static enum fwu_agent_error_t accept_full_capsule(
+     metadata->crc_32 = crc32((uint8_t *)&metadata->version,
+                               sizeof(struct fwu_metadata) - sizeof(uint32_t));
+ 
+-    ret = metadata_write(metadata);
++    ret = metadata_write_both_replica(metadata);
+     if (ret) {
+         return ret;
+     }
+@@ -1034,7 +1083,7 @@ static enum fwu_agent_error_t fwu_select_previous(
+     metadata->crc_32 = crc32((uint8_t *)&metadata->version,
+                               sizeof(struct fwu_metadata) - sizeof(uint32_t));
+ 
+-    ret = metadata_write(metadata);
++    ret = metadata_write_both_replica(metadata);
+     if (ret) {
+         return ret;
+     }
+@@ -1064,7 +1113,7 @@ void bl1_get_active_bl2_image(uint32_t *offset)
+         FWU_ASSERT(0);
+     }
+ 
+-    if (metadata_read(&_metadata)) {
++    if (metadata_read(&_metadata, 1)) {
+         FWU_ASSERT(0);
+     }
+ 
+@@ -1203,9 +1252,17 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+         return FWU_AGENT_ERROR;
+     }
+ 
++    /* This cannot be added to the fwu_metadata_init() because that function is
++     * called before the logging is enabled by TF-M. */
++    ret = fwu_metadata_check_and_correct_integrity();
++    if (ret = FWU_AGENT_SUCCESS) {
++        FWU_LOG_MSG("fwu_metadata_check_and_correct_integrity failed\r\n");
++        return ret;
++    }
++
+     Select_Write_Mode_For_Shared_Flash();
+ 
+-    if (metadata_read(&_metadata)) {
++    if (metadata_read(&_metadata, 1)) {
+         ret = FWU_AGENT_ERROR;
+         goto out;
+     }
+@@ -1315,7 +1372,7 @@ void host_acknowledgement_timer_to_reset(void)
+         FWU_ASSERT(0);
+     }
+ 
+-    if (metadata_read(&_metadata)) {
++    if (metadata_read(&_metadata, 1)) {
+         FWU_ASSERT(0);
+     }
+ 
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+index 701f20558..78e104277 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
++++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+@@ -70,4 +70,11 @@ enum fwu_nv_counter_index_t {
+ enum fwu_agent_error_t fwu_stage_nv_counter(enum fwu_nv_counter_index_t index,
+         uint32_t img_security_cnt);
+ 
++/*
++ * Check if both metadata replica is valid by calculating and comparing crc32.
++ * If one of the replica is corrupted then update it with the valid replica.
++ * If both of the replicas are corrupted then the correction is not possible.
++ */
++enum fwu_agent_error_t fwu_metadata_check_and_correct_integrity(void);
++
+ #endif /* FWU_AGENT_H */
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0021-platform-corstone1000-add-unique-guid-for-mps3.patch

@@ -0,0 +1,41 @@
+From a32e7195a4fc1c9d890f9e22a795443d01dc1e8f Mon Sep 17 00:00:00 2001
+From: Anusmita Dutta Mazumder <anusmita.duttamazumder@arm.com>
+Date: Tue, 2 Apr 2024 13:04:56 +0000
+Subject: [PATCH 03/10] platform: corstone1000: add unique guid for mps3
+
+This patch sets unique GUID for Corstone1000 FVP and MPS3
+
+Upstream-Status: Inappropriate [Redesign of Capsule update interface is required]
+Signed-off-by: Anusmita Dutta Mazumder <anusmita.duttamazumder@arm.com>
+---
+ .../target/arm/corstone1000/fw_update_agent/fwu_agent.c   | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index 003ab9faf8..5768df19b8 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
++++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -113,13 +113,19 @@ enum fwu_agent_state_t {
+ };
+ 
+ struct efi_guid full_capsule_image_guid = {
++#if PLATFORM_IS_FVP
+     .time_low = 0x989f3a4e,
+     .time_mid = 0x46e0,
+     .time_hi_and_version = 0x4cd0,
+     .clock_seq_and_node = {0x98, 0x77, 0xa2, 0x5c, 0x70, 0xc0, 0x13, 0x29}
++#else
++    .time_low = 0xdf1865d1,
++    .time_mid = 0x90fb,
++    .time_hi_and_version = 0x4d59,
++    .clock_seq_and_node = {0x9c, 0x38, 0xc9, 0xf2, 0xc1, 0xbb, 0xa8, 0xcc}
++#endif
+ };
+ 
+-
+ #define IMAGE_ACCEPTED          (1)
+ #define IMAGE_NOT_ACCEPTED      (0)
+ #define BANK_0                  (0)
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0022-CC312-alignment-of-cc312-differences.patch

@@ -1,7 +1,7 @@
-From bfc977a43ea6b328136599a7558c3706739579b6 Mon Sep 17 00:00:00 2001
+From 60ab8bbf85e9e84afd23948a71cf84c69f4aad7a Mon Sep 17 00:00:00 2001
 From: Ali Can Ozaslan <ali.oezaslan@arm.com>
 Date: Wed, 15 May 2024 12:12:15 +0000
-Subject: [PATCH 3/7] CC312: alignment of cc312 differences between fvp and
+Subject: [PATCH 07/10] CC312: alignment of cc312 differences between fvp and
  mps3 corstone1000 platforms
 
 Configures CC312 mps3 model same as predefined cc312 FVP
@@ -15,7 +15,7 @@ Upstream-Status: Inappropriate [Requires an aligment cc3xx with mps3 hw and fvp
  1 file changed, 3 insertions(+)
 
 diff --git a/lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/cc_lib.c b/lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/cc_lib.c
-index 31e4332be..4b08c0252 100644
+index 31e4332bed..4b08c02526 100644
 --- a/lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/cc_lib.c
 +++ b/lib/ext/cryptocell-312-runtime/host/src/cc3x_lib/cc_lib.c
 @@ -207,6 +207,9 @@ CClibRetCode_t CC_LibInit(CCRndContext_t *rndContext_ptr, CCRndWorkBuff_t  *rndW
@@ -29,5 +29,5 @@ index 31e4332be..4b08c0252 100644
      reg = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_AO_LOCK_BITS));
      CC_REG_FLD_SET(0, HOST_AO_LOCK_BITS, HOST_FORCE_DFA_ENABLE, reg, 0x0);
 -- 
-2.43.0
+2.25.1
 

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/psa-adac/0002-ADAC-Link-psa_interface-instead-of-tfm_sprt.patch

@@ -0,0 +1,35 @@
+From af71103845498eef4f859deba4b904a195f2817f Mon Sep 17 00:00:00 2001
+From: Bence Balogh <bence.balogh@arm.com>
+Date: Mon, 22 Jul 2024 17:33:23 +0200
+Subject: [PATCH] ADAC: Link psa_interface instead of tfm_sprt
+
+The tfm_sprt brings in other functionalities that are not needed for
+the Secure Debug.
+
+The printf() override in tfm_sp_log_raw.c can cause problems because
+it calls tfm_hal_output_sp_log() which triggers an SVC. The SVC calls
+tfm_hal_output_spm_log which relies on an SPM, which might not be
+initialized at that point.
+
+Signed-off-by: Bence Balogh <bence.balogh@arm.com>
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ psa_crypto/CMakeLists.txt | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/psa_crypto/CMakeLists.txt b/psa_crypto/CMakeLists.txt
+index 3e70624..58d95f7 100644
+--- a/psa_crypto/CMakeLists.txt
++++ b/psa_crypto/CMakeLists.txt
+@@ -18,7 +18,7 @@ target_sources(psa_adac_psa_crypto
+ target_link_libraries(psa_adac_psa_crypto
+     PRIVATE
+         psa_adac_config
+-        tfm_sprt
++        psa_interface
+ )
+ 
+ target_link_libraries(trusted-firmware-m-psa-adac
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/psa-adac/0003-Fix-psa_key_handle_t-initialization.patch

@@ -9,7 +9,7 @@ struct. In this case, it is defined in the used configuration header
 so the struct cannot be initialized with -1.
 
 Signed-off-by: Bence Balogh <bence.balogh@arm.com>
-Upstream-Status: Inappropriate [mbedcrypto configs have to be fixed to build secure-debug mps3 without this patch]
+Upstream-Status: Pending [Not submitted to upstream yet]
 ---
  psa_crypto/adac_crypto_psa_mac.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/psa-adac/0003-cmake-Update-psa_adac_psa_crypto-dependencies.patch

@@ -1,30 +0,0 @@
-From 3c552d0b46559160581e89bf310db0b176e33074 Mon Sep 17 00:00:00 2001
-From: Devaraj Ranganna <devaraj.ranganna@arm.com>
-Date: Thu, 18 Sep 2025 17:45:20 +0100
-Subject: [PATCH] cmake: Update `psa_adac_psa_crypto` dependencies
-
-The auto-generated header files are part of `psa_adac_core` library.
-Therefore, link `psa_adac_psa_crypto` library with `psa_adac_core`
-library.
-
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
----
- psa_crypto/CMakeLists.txt | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/psa_crypto/CMakeLists.txt b/psa_crypto/CMakeLists.txt
-index b1c3f5d..efc284d 100644
---- a/psa_crypto/CMakeLists.txt
-+++ b/psa_crypto/CMakeLists.txt
-@@ -20,6 +20,7 @@ target_link_libraries(psa_adac_psa_crypto
-         psa_adac_config
-         $<$<BOOL:${PSA_ADAC_AS_TFM_RUNTIME_SERVICE}>:tfm_sprt>
-         psa_interface
-+        psa_adac_core
- )
- 
- target_link_libraries(trusted-firmware-m-psa-adac
--- 
-2.43.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc

@@ -6,58 +6,48 @@ TFM_PLATFORM = "arm/corstone1000"
 
 TFM_DEBUG = "1"
 
-# These dependencies are needed for TF-M v2.2.0 and above
-# https://github.com/TrustedFirmware-M/trusted-firmware-m/blob/TF-Mv2.2.0/tools/requirements.txt
-DEPENDS:append = " clang-native python3-rich-native python3-pyelftools-native"
-
 ## Default is the MPS3 board
 TFM_PLATFORM_IS_FVP ?= "FALSE"
-
-## Default is Cortex-A35
-## Cortex-A320 is implemented inside a DynamIQ Shared Unit-120T (DSU-120T) cluster
-EXTRA_OECMAKE:append:cortexa320 = " \
-    -DCORSTONE1000_CORTEX_A320=TRUE \
-    -DCORSTONE1000_DSU_120T=TRUE \
-"
-
 EXTRA_OECMAKE += "-DPLATFORM_IS_FVP=${TFM_PLATFORM_IS_FVP}"
 EXTRA_OECMAKE += "-DCC312_LEGACY_DRIVER_API_ENABLED=OFF"
 EXTRA_OECMAKE:append:corstone1000-fvp = " -DENABLE_MULTICORE=${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000_fvp_smp', 'TRUE', 'FALSE', d)}"
 EXTRA_OECMAKE:append:corstone1000-mps3 = " -DPLATFORM_PSA_ADAC_SECURE_DEBUG=${@bb.utils.contains('MACHINE_FEATURES', 'secure-debug', 'ON', 'OFF', d)}"
-EXTRA_OECMAKE:append:corstone1000-mps3 = " -DPLATFORM_PSA_ADAC_SOURCE_PATH=${UNPACKDIR}/tfm-psa-adac -DPLATFORM_PSA_ADAC_BUILD_PATH=${B}/tfm-psa-adac-build"
+EXTRA_OECMAKE:append:corstone1000-mps3 = " -DPLATFORM_PSA_ADAC_SOURCE_PATH=${S}/../tfm-psa-adac -DPLATFORM_PSA_ADAC_BUILD_PATH=${B}/tfm-psa-adac-build"
 
 SRC_URI += " \
             file://0001-arm-trusted-firmware-m-disable-address-warnings-into.patch \
            "
 
 FILESEXTRAPATHS:prepend := "${THISDIR}/files:"
-SRCREV_tfm-psa-adac:corstone1000 = "f2809ae231be33a1afcd7714f40756c67d846c88"
 SRC_URI:append:corstone1000 = " \
-    file://0001-Platform-CS1000-Remove-unused-BL1-files.patch \
-    file://0002-Platform-Corstone1000-Fix-BL1-compiler-switch-and-re.patch \
-    file://0003-CC312-alignment-of-cc312-differences-between-fvp-and.patch \
-    file://0004-Platform-Corstone1000-Enable-FWU-partition.patch \
-    file://0005-Platform-Corstone1000-Implement-Bootloader-Abstracti.patch \
-    file://0006-Platform-Corstone1000-Increase-buffer-sizes.patch \
-    file://0007-Platform-Corstone1000-Remove-duplicate-configuration.patch \
-    file://0008-Platform-Corstone1000-Increase-BL1-size-and-align-bi.patch \
-    file://0009-Platform-CS1K-Adapt-ADAC-enabled-build-to-the-new-BL.patch \
-    file://0010-plat-corstone1000-Add-support-for-Cortex-A320-varian.patch \
-    file://0011-BL2-Remove-the-weak-function-definition.patch \
-    file://0012-Corstone-1000-Enable-different-DRBG-configurations.patch \
-    file://0013-bl2-corstone-1000-Remove-psa_adac_to_tfm_apply_permi.patch \
-    file://0014-bl2-corstone-1000-secure-debug-waiting-in-CM-LCS.patch \
-    file://0015-CC3XX-Add-logging-on-cc3xx_dcu.c.patch \
-    file://0016-CC3XX-DCU-Check-dcu_en-against-the-permanent_disable.patch \
-    file://0017-CC3XX-DCU-Enable-checking-ICV-restriction-mask-confi.patch \
-    file://0018-Platform-ADAC-Musca-B1-and-Corstone-1000-do-not-chec.patch \
+    file://0001-Platform-Corstone1000-Align-capsule-UEFI-structs.patch \
+    file://0002-Platform-Corstone1000-Fix-NV-counter-writing.patch \
+    file://0003-Platform-Corstone1000-Enable-firewall-in-FVP.patch \
+    file://0004-Platform-CS1000-Increase-ITS-max-asset-size.patch \
+    file://0005-Platform-CS1000-Increase-RSE_COMMS-buffer-size.patch \
+    file://0006-Platform-CS1000-Increase-buffers-for-EFI-vars.patch \
+    file://0007-Plaform-Corstone1000-Switch-to-metadata-v2.patch \
+    file://0008-Platform-CS1000-Increase-flash-PS-area-size.patch \
+    file://0009-corstone1000-Remove-reset-after-capsule-update.patch \
+    file://0010-platform-CS1000-Add-multicore-support-for-FVP.patch \
+    file://0011-Platform-CS1000-Fix-Bank-offsets.patch \
+    file://0012-Platform-CS1000-Increase-BL2-partition-size.patch \
+    file://0013-CC312-ADAC-Add-PSA_WANT_ALG_SHA_256-definition.patch \
+    file://0014-Platform-CS1000-Add-crypto-configs-for-ADAC.patch \
+    file://0015-Platform-CS1000-Fix-platform-name-in-logs.patch \
+    file://0017-Platform-CS1000-Remove-unused-BL1-files.patch \
+    file://0018-Platform-CS1000-Remove-duplicated-metadata-write.patch \
+    file://0019-Platform-CS1000-Fix-compiler-switch-in-BL1.patch \
+    file://0020-Platform-CS1000-Validate-both-metadata-replicas.patch \
+    file://0021-platform-corstone1000-add-unique-guid-for-mps3.patch \
+    file://0022-CC312-alignment-of-cc312-differences.patch \
     "
 
 FILESEXTRAPATHS:prepend:corstone1000-mps3 := "${THISDIR}/files/corstone1000/psa-adac:"
 SRC_URI:append:corstone1000-mps3 = " \
     file://0001-PSA-revert-header-versions.patch;patchdir=../tfm-psa-adac \
-    file://0002-Fix-psa_key_handle_t-initialization.patch;patchdir=../tfm-psa-adac \
-    file://0003-cmake-Update-psa_adac_psa_crypto-dependencies.patch;patchdir=../tfm-psa-adac \
+    file://0002-ADAC-Link-psa_interface-instead-of-tfm_sprt.patch;patchdir=../tfm-psa-adac \
+    file://0003-Fix-psa_key_handle_t-initialization.patch;patchdir=../tfm-psa-adac \
     "
 
 do_install() {
@@ -69,7 +59,6 @@ do_install() {
 
 create_bl1_image(){
     dd conv=notrunc bs=1 if=${D}/firmware/bl1_1.bin of=${D}/firmware/bl1.bin seek=0
-    # Size of bl1_1.bin is 58KB (59392 bytes)  
-    dd conv=notrunc bs=1 if=${D}/firmware/bl1_provisioning_bundle.bin of=${D}/firmware/bl1.bin seek=59392
+    dd conv=notrunc bs=1 if=${D}/firmware/bl1_provisioning_bundle.bin of=${D}/firmware/bl1.bin seek=40960
 }
 do_install[postfuncs] += "create_bl1_image"

meta-arm-bsp/recipes-bsp/u-boot/u-boot-corstone1000.inc

@@ -1,8 +1,8 @@
 # Corstone1000 specific U-boot support
 
 DEPENDS:append = " openssl-native efitools-native"
-CORSTONE1000_DEVICE_TREE:corstone1000-mps3 = "arm/corstone1000-mps3"
-CORSTONE1000_DEVICE_TREE:corstone1000-fvp = "arm/corstone1000-fvp"
+CORSTONE1000_DEVICE_TREE:corstone1000-mps3 = "corstone1000-mps3"
+CORSTONE1000_DEVICE_TREE:corstone1000-fvp = "corstone1000-fvp"
 EXTRA_OEMAKE:append = ' DEVICE_TREE=${CORSTONE1000_DEVICE_TREE}'
 
 UBOOT_CONFIG ??= "EFI"
@@ -15,82 +15,70 @@ UBOOT_EXTLINUX = "0"
 
 SYSROOT_DIRS:append = " /boot"
 
-# FWU patches
 SRC_URI:append = " \
-    file://0001-arm_ffa-Add-NULL-pointer-check-to-the-uclass-driver-.patch \
-    file://0002-arm_ffa-Add-FFA_MEM_SHARE-support.patch                    \
-    file://0003-arm_ffa-Add-FFA_MEM_RECLAIM-support.patch                  \
-    file://0004-arm_ffa-sandbox-Replace-the-emulator-error-log-with-.patch \
-    file://0005-arm_ffa-sandbox-Improve-the-readability-of-clearing-.patch \
-    file://0006-arm_ffa-sandbox-Add-FFA_MEM_SHARE-emulation.patch          \
-    file://0007-arm_ffa-sandbox-Add-FFA_MEM_SHARE-tests.patch              \
-    file://0008-arm_ffa-sandbox-Add-FFA_MEM_RECLAIM-emulation.patch        \
-    file://0009-arm_ffa-sandbox-Add-FFA_MEM_RECLAIM-tests.patch            \
-    file://0010-fwu_arm_psa-Initialize-the-update-agent.patch              \
-    file://0011-fwu_arm_psa-Read-the-FWU-directory-through-get_image.patch \
-    file://0012-fwu_arm_psa-Add-staging-ABIs.patch                         \
-    file://0013-efi_loader-fwu_arm_psa-Add-set_image-and-get_image_i.patch \
-    file://0014-efi_loader-fwu_arm_psa-Keep-the-FMP-payload-header.patch   \
-    file://0015-efi_loader-fwu_arm_psa-Skip-accepting-the-payload-af.patch \
-    file://0016-efi_loader-fwu-fwu_arm_psa-Disable-trial-state-handl.patch \
-    file://0017-fwu_arm_psa-Add-FWU-acceptance-mechanism.patch             \
-    file://0018-fwu_arm_psa-Add-ESRT-support.patch                         \
-    file://0019-fwu_arm_psa-Add-ExitBootService-notification-handler.patch \
-    file://0020-efi_loader-capsule-Add-runtime-capsule-flags-checks.patch  \
-    file://0021-fwu_arm_psa-corstone1000-Enable-FWU-support.patch          \
-    file://0022-fwu_arm_psa-corstone1000-Perform-bank-logic-when-rea.patch \
-    file://0023-fwu_arm_psa-corstone1000-Notify-SE-Proxy-SP-on-ExitB.patch \
-    file://0024-fwu_arm_psa-corstone1000-Set-Boot0001-for-on-disk-FW.patch \
-    "
-# Other features
-SRC_URI:append = " \
-    file://0025-corstone1000-set-CONFIG_FFA_SHARED_MM_BUF_ADDR.patch \
-    file://0026-corstone1000-Enable-MMC-for-FVP.patch \
-    file://0027-corstone1000-Enable-secure-boot-configs.patch \
-    file://0028-corstone1000-Enable-EFI-set_time-config.patch \
-    file://0029-corstone1000-Enable-set-print-EFI-variables.patch \
-    file://0030-corstone1000-Enable-virtio-net-support.patch \
-    file://0031-arm-corstone1000-Fix-unrecognized-filesystem-type.patch \
-    file://0032-corstone1000-dts-Add-external-system-node.patch \
-    file://0033-arm-bsp-u-boot-dts-Reserve-memory-for-RSS-comm-point.patch \
-    "
-
-# Purging device tree nodes
-SRC_URI:append = " \
-    file://0034-dt-Provide-a-way-to-remove-non-compliant-nodes-and-p.patch \
-    file://0035-bootefi-Call-the-EVT_FT_FIXUP-event-handler.patch          \
-    file://0036-corstone1000-Purge-U-Boot-specific-DT-nodes.patch          \
+    file://0001-FF-A-v15-arm64-smccc-add-support-for-SMCCCv1.2-x0-x1.patch \
+    file://0002-FF-A-v15-lib-uuid-introduce-uuid_str_to_le_bin-funct.patch \
+    file://0003-FF-A-v15-lib-uuid-introduce-testcase-for-uuid_str_to.patch \
+    file://0004-FF-A-v15-arm_ffa-introduce-Arm-FF-A-support.patch \
+    file://0005-FF-A-v15-arm_ffa-introduce-armffa-command.patch \
+    file://0006-FF-A-v15-arm_ffa-introduce-sandbox-FF-A-support.patch \
+    file://0007-FF-A-v15-arm_ffa-introduce-sandbox-test-cases-for-UC.patch \
+    file://0008-FF-A-v15-arm_ffa-introduce-armffa-command-Sandbox-te.patch \
+    file://0009-FF-A-v15-arm_ffa-efi-introduce-FF-A-MM-communication.patch \
+    file://0010-FF-A-v15-arm_ffa-efi-corstone1000-enable-MM-communic.patch \
+    file://0011-efi-corstone1000-fwu-introduce-EFI-capsule-update.patch \
+    file://0012-arm-corstone1000-fix-unrecognized-filesystem-type.patch \
+    file://0013-efi_loader-corstone1000-remove-guid-check-from-corst.patch \
+    file://0014-efi_loader-populate-ESRT-table-if-EFI_ESRT-config-op.patch \
+    file://0015-efi_firmware-add-get_image_info-for-corstone1000.patch \
+    file://0016-efi_loader-fix-null-pointer-exception-with-get_image.patch \
+    file://0017-arm-corstone1000-add-mmc-for-fvp.patch \
+    file://0018-corstone1000-add-compressed-kernel-support.patch \
+    file://0019-arm-corstone1000-esrt-support.patch \
+    file://0020-corstone1000-enable-distro-booting-command.patch \
+    file://0021-corstone1000-add-fwu-metadata-store-info.patch \
+    file://0022-fwu_metadata-make-sure-structures-are-packed.patch \
+    file://0023-corstone1000-add-boot-index.patch \
+    file://0024-corstone1000-adjust-boot-bank-and-kernel-location.patch \
+    file://0025-corstone1000-add-nvmxip-fwu-mdata-and-gpt-options.patch \
+    file://0026-nvmxip-move-header-to-include.patch \
+    file://0027-corstone1000-set-kernel_addr-based-on-boot_idx.patch \
+    file://0028-corstone1000-boot-index-from-active.patch \
+    file://0029-corstone1000-enable-PSCI-reset.patch \
+    file://0030-Enable-EFI-set-get-time-services.patch \
+    file://0031-corstone1000-detect-inflated-kernel-size.patch \
+    file://0032-corstone1000-ESRT-add-unique-firmware-GUID.patch \
+    file://0033-dt-Provide-a-way-to-remove-non-compliant-nodes-and-p.patch \
+    file://0034-bootefi-Call-the-EVT_FT_FIXUP-event-handler.patch \
+    file://0035-corstone1000-purge-U-Boot-specific-DT-nodes.patch \
+    file://0036-corstone1000-add-signature-device-tree-overlay.patch \
+    file://0037-corstone1000-enable-authenticated-capsule-config.patch \
+    file://0038-corstone1000-introduce-EFI-authenticated-capsule-upd.patch \
+    file://0039-enables-ondisk-capsule-update-feature.patch		  \
+    file://0040-fix-runtime-capsule-update-flags-checks.patch		  \
+    file://0041-scatter-gather-flag-workaround.patch			  \
+    file://0042-corstone1000-enable-virtio-net-support.patch		  \
+    file://0043-firmware-psci-Fix-bind_smccc_features-psci-check.patch		  \
+    file://0044-corstone1000-set-unique-GUID-for-fvp-and-mps3.patch		  \
+    file://0045-efi-corstone1000-fwu-update-RPC-ABI.patch			  \
+    file://0046-Corstone1000-Change-MMCOMM-buffer-location.patch		  \
+    file://0047-corstone1000-dts-add-external-system-node.patch \
+    file://0048-corstone1000-Enable-UEFI-Secure-boot.patch 			  \
+    file://0049-corstone1000-Add-secondary-cores-cpu-nodes-for-FVP.patch	  \
+    file://0050-fwu-Use-metadata-v2.patch	  \
     ${@bb.utils.contains('MACHINE_FEATURES', 'corstone1000-extsys', \
-                         '', 'file://0037-corstone1000-purge-remoteproc-DTS-node.patch' , d)} \
+                         '', 'file://0051-corstone1000-purge-remoteproc-dts-node.patch' , d)} \
+    file://0052-reserve-memory-for-se-comm.patch \
     "
 
-# Add OF_UPSTREAM support
-SRC_URI:append = " \
-    file://0038-corstone1000-enable-OF_UPSTREAM-device-tree-support.patch \
-"
-
-# Use 32 bit cells for reserved-memory node in dts
-SRC_URI:append = " \
-    file://0040-corstone1000-dts-use-32-bit-cells-for-reserved-memor.patch \
-"
-
-# Add Cortex-a320 support
-SRC_URI:append = " \
-    file://0039-corstone1000-Add-Cortex-A320-support-on-FVP.patch \
-"
-
-# Add Cortex-a320 specific configurations
-SRC_URI:append:cortexa320 = " \
-    file://corstone1000-a320.cfg \
-"
-
-uboot_configure_config:append() {
-   openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ -keyout ${B}/CRT.key -out $builddir/CRT.crt -nodes -days 365
+do_configure:append() {
+    openssl req -x509 -sha256 -newkey rsa:2048 -subj /CN=CRT/ -keyout ${B}/CRT.key -out ${B}/CRT.crt -nodes -days 365
+    cert-to-efi-sig-list ${B}/CRT.crt ${B}/corstone1000_defconfig/CRT.esl
 }
 
 FILES:${PN} += "/corstone1000_capsule_*"
-uboot_install_config:append() {
-   install -D -p -m 0644 $builddir/CRT.crt ${D}/corstone1000_capsule_cert.crt
+do_install:append() {
+   install -D -p -m 0644 ${B}/CRT.crt ${D}/corstone1000_capsule_cert.crt
    install -D -p -m 0644 ${B}/CRT.key ${D}/corstone1000_capsule_key.key
 }
 

meta-arm-bsp/recipes-bsp/u-boot/u-boot-fvp-base.inc

@@ -1,7 +1,6 @@
 # FVP base specific U-boot support
 
 SRC_URI:append = " \
-    file://virtio-boot.cfg \
     file://0001-vexpress64-Set-the-DM_RNG-property.patch \
     file://0002-vexpress64-Select-PSCI-RESET-by-default.patch \
     file://0003-vexpress64-Imply-CONFIG_ARM64_CRC32-by-default.patch \

meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0001-FF-A-v15-arm64-smccc-add-support-for-SMCCCv1.2-x0-x1.patch

@@ -0,0 +1,198 @@
+From cc651db9a1370e697fd2525ce58b81ff7e112474 Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Fri, 29 Jul 2022 13:06:19 +0100
+Subject: [PATCH] FF-A v15: arm64: smccc: add support for SMCCCv1.2 x0-x17
+ registers
+
+add support for x0-x17 registers used by the SMC calls
+
+In SMCCC v1.2 [1] arguments are passed in registers x1-x17.
+Results are returned in x0-x17.
+
+This work is inspired from the following kernel commit:
+
+arm64: smccc: Add support for SMCCCv1.2 extended input/output registers
+
+[1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token=
+
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
+Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
+Reviewed-by: Simon Glass <sjg@chromium.org>
+Cc: Tom Rini <trini@konsulko.com>
+Upstream-Status: Submitted [cover letter: https://lore.kernel.org/all/20230713132847.176000-1-abdellatif.elkhlifi@arm.com/]
+---
+ arch/arm/cpu/armv8/smccc-call.S | 57 ++++++++++++++++++++++++++++++++-
+ arch/arm/lib/asm-offsets.c      | 16 +++++++++
+ include/linux/arm-smccc.h       | 45 ++++++++++++++++++++++++++
+ 3 files changed, 117 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/cpu/armv8/smccc-call.S b/arch/arm/cpu/armv8/smccc-call.S
+index dc92b28777..93f66d3366 100644
+--- a/arch/arm/cpu/armv8/smccc-call.S
++++ b/arch/arm/cpu/armv8/smccc-call.S
+@@ -1,7 +1,11 @@
+ /* SPDX-License-Identifier: GPL-2.0 */
+ /*
+  * Copyright (c) 2015, Linaro Limited
+- */
++ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
++ *
++ * Authors:
++ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
++*/
+ #include <linux/linkage.h>
+ #include <linux/arm-smccc.h>
+ #include <generated/asm-offsets.h>
+@@ -45,3 +49,54 @@ ENDPROC(__arm_smccc_smc)
+ ENTRY(__arm_smccc_hvc)
+ 	SMCCC	hvc
+ ENDPROC(__arm_smccc_hvc)
++
++#ifdef CONFIG_ARM64
++
++	.macro SMCCC_1_2 instr
++	/* Save `res` and free a GPR that won't be clobbered */
++	stp     x1, x19, [sp, #-16]!
++
++	/* Ensure `args` won't be clobbered while loading regs in next step */
++	mov	x19, x0
++
++	/* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
++	ldp	x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
++	ldp	x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
++	ldp	x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
++	ldp	x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
++	ldp	x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
++	ldp	x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
++	ldp	x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
++	ldp	x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
++	ldp	x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
++
++	\instr #0
++
++	/* Load the `res` from the stack */
++	ldr	x19, [sp]
++
++	/* Store the registers x0 - x17 into the result structure */
++	stp	x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
++	stp	x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
++	stp	x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
++	stp	x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
++	stp	x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
++	stp	x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
++	stp	x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
++	stp	x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
++	stp	x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
++
++	/* Restore original x19 */
++	ldp     xzr, x19, [sp], #16
++	ret
++	.endm
++
++/*
++ * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
++ *			  struct arm_smccc_1_2_regs *res);
++ */
++ENTRY(arm_smccc_1_2_smc)
++	SMCCC_1_2 smc
++ENDPROC(arm_smccc_1_2_smc)
++
++#endif
+diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
+index 6de0ce9152..181a8ac4c2 100644
+--- a/arch/arm/lib/asm-offsets.c
++++ b/arch/arm/lib/asm-offsets.c
+@@ -9,6 +9,11 @@
+  * generate asm statements containing #defines,
+  * compile this file to assembler, and then extract the
+  * #defines from the assembly-language output.
++ *
++ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
++ *
++ * Authors:
++ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+  */
+ 
+ #include <common.h>
+@@ -90,6 +95,17 @@ int main(void)
+ 	DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
+ 	DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
+ 	DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
++#ifdef CONFIG_ARM64
++	DEFINE(ARM_SMCCC_1_2_REGS_X0_OFFS,	offsetof(struct arm_smccc_1_2_regs, a0));
++	DEFINE(ARM_SMCCC_1_2_REGS_X2_OFFS,	offsetof(struct arm_smccc_1_2_regs, a2));
++	DEFINE(ARM_SMCCC_1_2_REGS_X4_OFFS,	offsetof(struct arm_smccc_1_2_regs, a4));
++	DEFINE(ARM_SMCCC_1_2_REGS_X6_OFFS,	offsetof(struct arm_smccc_1_2_regs, a6));
++	DEFINE(ARM_SMCCC_1_2_REGS_X8_OFFS,	offsetof(struct arm_smccc_1_2_regs, a8));
++	DEFINE(ARM_SMCCC_1_2_REGS_X10_OFFS,	offsetof(struct arm_smccc_1_2_regs, a10));
++	DEFINE(ARM_SMCCC_1_2_REGS_X12_OFFS,	offsetof(struct arm_smccc_1_2_regs, a12));
++	DEFINE(ARM_SMCCC_1_2_REGS_X14_OFFS,	offsetof(struct arm_smccc_1_2_regs, a14));
++	DEFINE(ARM_SMCCC_1_2_REGS_X16_OFFS,	offsetof(struct arm_smccc_1_2_regs, a16));
++#endif
+ #endif
+ 
+ 	return 0;
+diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
+index e1d09884a1..f44e9e8f93 100644
+--- a/include/linux/arm-smccc.h
++++ b/include/linux/arm-smccc.h
+@@ -1,6 +1,10 @@
+ /* SPDX-License-Identifier: GPL-2.0 */
+ /*
+  * Copyright (c) 2015, Linaro Limited
++ * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
++ *
++ * Authors:
++ *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+  */
+ #ifndef __LINUX_ARM_SMCCC_H
+ #define __LINUX_ARM_SMCCC_H
+@@ -70,6 +74,47 @@ struct arm_smccc_res {
+ 	unsigned long a3;
+ };
+ 
++#ifdef CONFIG_ARM64
++/**
++ * struct arm_smccc_1_2_regs - Arguments for or Results from SMC call
++ * @a0-a17 argument values from registers 0 to 17
++ */
++struct arm_smccc_1_2_regs {
++	unsigned long a0;
++	unsigned long a1;
++	unsigned long a2;
++	unsigned long a3;
++	unsigned long a4;
++	unsigned long a5;
++	unsigned long a6;
++	unsigned long a7;
++	unsigned long a8;
++	unsigned long a9;
++	unsigned long a10;
++	unsigned long a11;
++	unsigned long a12;
++	unsigned long a13;
++	unsigned long a14;
++	unsigned long a15;
++	unsigned long a16;
++	unsigned long a17;
++};
++
++/**
++ * arm_smccc_1_2_smc() - make SMC calls
++ * @args: arguments passed via struct arm_smccc_1_2_regs
++ * @res: result values via struct arm_smccc_1_2_regs
++ *
++ * This function is used to make SMC calls following SMC Calling Convention
++ * v1.2 or above. The content of the supplied param are copied from the
++ * structure to registers prior to the SMC instruction. The return values
++ * are updated with the content from registers on return from the SMC
++ * instruction.
++ */
++asmlinkage void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
++				  struct arm_smccc_1_2_regs *res);
++#endif
++
+ /**
+  * struct arm_smccc_quirk - Contains quirk information
+  * @id: quirk identification

meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0001-arm_ffa-Add-NULL-pointer-check-to-the-uclass-driver-.patch

@@ -1,64 +0,0 @@
-From 9b001c37347aa8fa5ecbd68f12714a12c74b6ea5 Mon Sep 17 00:00:00 2001
-From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
-Date: Wed, 30 Oct 2024 14:10:43 +0000
-Subject: [PATCH 01/36] arm_ffa: Add NULL pointer check to the uclass driver
- operations
-
-Add NULL pointer check for ops
-
-The device driver can miss defining an operations structure.
-So, ffa_get_ops() can return NULL.
-This commit adds checks for ops in the uclass driver operations
-and an error is returned when ops is NULL.
-
-Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
-Upstream-Status: Submitted [cover letter: https://lore.kernel.org/all/20250702152528.1180414-1-abdellatif.elkhlifi@arm.com/]
----
- drivers/firmware/arm-ffa/arm-ffa-uclass.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
-index 96c64964bb7..f8d231204db 100644
---- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c
-+++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c
-@@ -1,6 +1,6 @@
- // SPDX-License-Identifier: GPL-2.0+
- /*
-- * Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
-+ * Copyright 2022-2023, 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
-  *
-  * Authors:
-  *   Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
-@@ -954,6 +954,9 @@ int ffa_partition_info_get(struct udevice *dev, const char *uuid_str,
- {
- 	struct ffa_bus_ops *ops = ffa_get_ops(dev);
- 
-+	if (!ops)
-+		return -EINVAL;
-+
- 	if (!ops->partition_info_get)
- 		return -ENOSYS;
- 
-@@ -979,6 +982,9 @@ int ffa_sync_send_receive(struct udevice *dev, u16 dst_part_id,
- {
- 	struct ffa_bus_ops *ops = ffa_get_ops(dev);
- 
-+	if (!ops)
-+		return -EINVAL;
-+
- 	if (!ops->sync_send_receive)
- 		return -ENOSYS;
- 
-@@ -1000,6 +1006,9 @@ int ffa_rxtx_unmap(struct udevice *dev)
- {
- 	struct ffa_bus_ops *ops = ffa_get_ops(dev);
- 
-+	if (!ops)
-+		return -EINVAL;
-+
- 	if (!ops->rxtx_unmap)
- 		return -ENOSYS;
- 
--- 
-2.25.1
-