trusted-firmware-a: fix build error when using ccache

When ccache is enabled trusted-firmware-a recipe fails with this
error message:

    make: *** No rule to make target 'aarch64-poky-linux-gcc'. Stop.

ccache prefix CC variable with 'ccache' word before compiler. Because
there are no quotes assigned to CC, only 'ccache' is assigned. The
compiler becomes a make target, producing the build error.

Add single quotes to LD is a good measure to prevent this kind of error.

Signed-off-by: Javier Tia <javier.tia@linaro.org>
Signed-off-by: Jon Mason <jon.mason@arm.com>

.gitlab-ci.yml

@@ -1,4 +1,12 @@
-image: ghcr.io/siemens/kas/kas:latest-release
+image: ghcr.io/siemens/kas/kas:3.2
+
+variables:
+  CPU_REQUEST: ""
+  DEFAULT_TAG: ""
+  # These are needed as the k8s executor doesn't respect the container entrypoint
+  # by default
+  FF_USE_LEGACY_KUBERNETES_EXECUTION_STRATEGY: 0
+  FF_KUBERNETES_HONOR_ENTRYPOINT: 1
 
 stages:
   - prep
@@ -6,6 +14,8 @@ stages:
 
 # Common job fragment to get a worker ready
 .setup:
+  tags:
+    - $DEFAULT_TAG
   stage: build
   interruptible: true
   variables:
@@ -25,11 +35,14 @@ stages:
     - mkdir --verbose --parents $KAS_WORK_DIR $KAS_REPO_REF_DIR $SSTATE_DIR $DL_DIR $TOOLCHAIN_DIR $TOOLCHAIN_LINK_DIR
     # Must do this here, as it's the only way to make sure the toolchain is installed on the same builder
     - ./ci/get-binary-toolchains $DL_DIR $TOOLCHAIN_DIR $TOOLCHAIN_LINK_DIR
-    - sudo apt update && sudo apt install --yes telnet python3-subunit
+    # This can be removed with Kas 3.2
+    - sudo apt-get update && sudo apt-get install --yes python3-subunit
 
 # Generalised fragment to do a Kas build
 .build:
   extends: .setup
+  variables:
+    KUBERNETES_CPU_REQUEST: $CPU_REQUEST
   script:
     - KASFILES=$(./ci/jobs-to-kas "$CI_JOB_NAME")
     - kas shell --update --force-checkout $KASFILES -c 'cat conf/*.conf'
@@ -82,7 +95,7 @@ corstone1000-fvp:
   extends: .build
   parallel:
     matrix:
-      - TESTING: testimage
+      - TESTING: [testimage,tftf]
   tags:
     - x86_64
 
@@ -249,8 +262,7 @@ pending-updates:
 
 # What percentage of machines in the layer do we build
 machine-coverage:
-  stage: build
-  interruptible: true
+  extends: .setup
   script:
     - ./ci/check-machine-coverage
   coverage: '/Coverage: \d+/'

ci/base.yml

@@ -30,7 +30,7 @@ local_conf_header:
     CONF_VERSION = "2"
     BB_NUMBER_THREADS = "16"
     PARALLEL_MAKE = "-j16"
-    LICENSE_FLAGS_ACCEPTED += "armcompiler Arm-FVP-EULA"
+    LICENSE_FLAGS_ACCEPTED += "Arm-FVP-EULA"
   setup: |
     PACKAGE_CLASSES = "package_ipk"
     PACKAGECONFIG:remove:pn-qemu-system-native = "gtk+ sdl"

ci/clang.yml

@@ -4,7 +4,6 @@ header:
 repos:
   meta-clang:
     url: https://github.com/kraj/meta-clang
-    refspec: master
 
 local_conf_header:
   clang: |

ci/get-binary-toolchains

@@ -1,8 +1,9 @@
 #!/bin/bash
-set -u
+set -u -e
 
-HOST_ARCH=$(uname -m)
-VER="11.2-2022.02"
+BASENAME=gcc-arm
+VER=${VER:-10.3-2021.07}
+HOST_ARCH=${HOST_ARCH:-$(uname -m)}
 
 DOWNLOAD_DIR=$1
 TOOLCHAIN_DIR=$2
@@ -11,36 +12,39 @@ TOOLCHAIN_LINK_DIR=$3
 # These should be already created by .gitlab-ci.yml, but do here if run outside of that env
 mkdir -p $DOWNLOAD_DIR $TOOLCHAIN_DIR $TOOLCHAIN_LINK_DIR
 
+download() {
+	TRIPLE=$1
+	URL=https://developer.arm.com/-/media/Files/downloads/gnu-a/$VER/binrel/$BASENAME-$VER-$HOST_ARCH-$TRIPLE.tar.xz
+	wget -P $DOWNLOAD_DIR -nc $URL
+}
+
 if [ $HOST_ARCH = "aarch64" ]; then
-	#AArch64 Linux hosted cross compilers
+	# AArch64 Linux hosted cross compilers
 
-	#AArch32 target with hard float (arm-none-linux-gnueabihf)
-	wget -P $DOWNLOAD_DIR -nc https://developer.arm.com/-/media/Files/downloads/gnu/$VER/binrel/gcc-arm-$VER-$HOST_ARCH-arm-none-linux-gnueabihf.tar.xz
+	# AArch32 target with hard float
+	download arm-none-linux-gnueabihf
 elif [ $HOST_ARCH = "x86_64" ]; then
-	#x86_64 Linux hosted cross compilers
+	# x86_64 Linux hosted cross compilers
 
-	#AArch32 target with hard float (arm-linux-none-gnueabihf)
-	wget -P $DOWNLOAD_DIR -nc https://developer.arm.com/-/media/Files/downloads/gnu/$VER/binrel/gcc-arm-$VER-$HOST_ARCH-arm-none-linux-gnueabihf.tar.xz
+	# AArch32 target with hard float
+	download arm-none-linux-gnueabihf
 
-	#AArch64 GNU/Linux target (aarch64-none-linux-gnu)
-	wget -P $DOWNLOAD_DIR -nc https://developer.arm.com/-/media/Files/downloads/gnu/$VER/binrel/gcc-arm-$VER-$HOST_ARCH-aarch64-none-linux-gnu.tar.xz
-
-	#AArch64 GNU/Linux target (aarch64_be-none-linux-gnu)
-	wget -P $DOWNLOAD_DIR -nc https://developer.arm.com/-/media/Files/downloads/gnu/$VER/binrel/gcc-arm-$VER-$HOST_ARCH-aarch64_be-none-linux-gnu.tar.xz
+	# AArch64 GNU/Linux target
+	download aarch64-none-linux-gnu
 else
 	echo "ERROR - Unknown build arch of $HOST_ARCH"
 	exit 1
 fi
 
-for i in arm aarch64 aarch64_be; do
-	if [ ! -d $TOOLCHAIN_DIR/gcc-arm-$VER-$HOST_ARCH-$i-none-linux-gnu*/ ]; then
-		if [ ! -f $DOWNLOAD_DIR/gcc-arm-$VER-$HOST_ARCH-$i-none-linux-gnu*.tar.xz ]; then
+for i in arm aarch64; do
+	if [ ! -d $TOOLCHAIN_DIR/$BASENAME-$VER-$HOST_ARCH-$i-none-linux-gnu*/ ]; then
+		if [ ! -f $DOWNLOAD_DIR/$BASENAME-$VER-$HOST_ARCH-$i-none-linux-gnu*.tar.xz ]; then
 			continue
 		fi
 
-		tar -C $TOOLCHAIN_DIR -axvf $DOWNLOAD_DIR/gcc-arm-$VER-$HOST_ARCH-$i-none-linux-gnu*.tar.xz
+		tar -C $TOOLCHAIN_DIR -axvf $DOWNLOAD_DIR/$BASENAME-$VER-$HOST_ARCH-$i-none-linux-gnu*.tar.xz
 	fi
 
 	# Setup a link for the toolchain to use local to the building machine (e.g., not in a shared location)
-	ln -s $TOOLCHAIN_DIR/gcc-arm-$VER-$HOST_ARCH-$i-none-linux-gnu* $TOOLCHAIN_LINK_DIR/$i
+	ln -s $TOOLCHAIN_DIR/$BASENAME-$VER-$HOST_ARCH-$i-none-linux-gnu* $TOOLCHAIN_LINK_DIR/$i
 done

ci/meta-virtualization.yml

@@ -6,4 +6,3 @@ header:
 repos:
   meta-virtualization:
     url: git://git.yoctoproject.org/meta-virtualization
-    refspec: master

ci/microbit-v1.yml

@@ -4,8 +4,4 @@ header:
     - ci/base.yml
     - ci/meta-zephyr.yml
 
-local_conf_header:
-  failing_tests: |
-    ZEPHYRTESTS:remove = "common"
-
 machine: microbit-v1

ci/qemu-cortex-m3.yml

@@ -13,6 +13,8 @@ local_conf_header:
   tclibc: |
     TCLIBC = "newlib"
   nonbuilding_tests: |
-    ZEPHYRTESTS:remove = "context pending sleep"
+    ZEPHYRTESTS:remove = "context pending poll sleep"
+  qemu_opts: |
+    QB_OPT_APPEND = "-icount shift=3,align=off,sleep=on -rtc clock=vm"
 
 machine: qemu-cortex-m3

ci/tftf.yml

@@ -0,0 +1,7 @@
+header:
+  version: 9
+
+local_conf_header:
+  tftf: |
+    TFA_UBOOT = "0"
+    TFTF_TESTS = "1"

ci/toolchains.yml

@@ -11,9 +11,7 @@ local_conf_header:
   toolchains: |
     SDKMACHINE = "x86_64"
 
-# No target armcompiler as currently there is no arm64 build
 target:
-  - nativesdk-armcompiler
   - gcc-aarch64-none-elf
   - nativesdk-gcc-aarch64-none-elf
   - gcc-arm-none-eabi

documentation/oeqa-fvp.md

@@ -0,0 +1,55 @@
+# OEQA on Arm FVPs
+
+OE-Core's [oeqa][OEQA] framework provides a method of performing runtime tests on machines using the `testimage` Yocto task. meta-arm has good support for writing test cases against [Arm FVPs][FVP], meaning the [runfvp][RUNFVP] boot configuration can be re-used.
+
+Tests can be configured to run automatically post-build by setting the variable `TESTIMAGE_AUTO="1"`, e.g. in your Kas file or local.conf.
+
+There are two main methods of testing, using different test "targets".
+
+## OEFVPTarget
+
+This runs test cases on a machine using SSH. It therefore requires that an SSH server is installed in the image.
+
+In test cases, the primary interface with the target is, e.g:
+```
+(status, output) = self.target.run('uname -a')
+```
+which runs a single command on the target (using `ssh -c`) and returns the status code and the output. It is therefore useful for running tests in a Linux environment.
+
+For examples of test cases, see meta/lib/oeqa/runtime/cases in OE-Core. The majority of test cases depend on `ssh.SSHTest.test_ssh`, which first validates that the SSH connection is functioning.
+
+Example machine configuration:
+```
+TEST_TARGET = "OEFVPTarget"
+TEST_SERVER_IP = "127.0.0.1"
+TEST_TARGET_IP = "127.0.0.1:8022"
+IMAGE_FEATURES:append = " ssh-server-dropbear"
+FVP_CONFIG[bp.virtio_net.hostbridge.userNetPorts] ?= "8022=22"
+```
+
+## OEFVPSerialTarget
+
+This runs tests against one or more serial consoles on the FVP. It is more flexible than OEFVPTarget, but test cases written for this test target do not support the test cases in OE-core. As it does not require an SSH server, it is suitable for machines with performance or memory limitations.
+
+Internally, this test target launches a [Pexpect][PEXPECT] instance for each entry in FVP_CONSOLES which can be used with the provided alias. The whole Pexpect API is exposed on the target, where the alias is always passed as the first argument, e.g.:
+```
+self.target.expect('default', r'root@.*\:~#', timeout=30)
+self.assertNotIn(b'ERROR:', self.target.before('tf-a'))
+```
+
+For an example of a full test case, see meta-arm/lib/oeqa/runtime/cases/linuxboot.py This test case can be used to minimally verify that a machine boots to a Linux shell. The default timeout is 10 minutes, but this can be configured with the variable TEST_FVP_LINUX_BOOT_TIMEOUT, which expects a value in seconds.
+
+The SSH interface described above is also available on OEFVPSerialTarget to support writing a set of hybrid test suites that use a combination of serial and SSH access. Note however that this test target does not guarantee that Linux has booted to shell prior to running any tests, so the test cases in OE-core are not supported.
+
+Example machine configuration:
+```
+TEST_TARGET="OEFVPSerialTarget"
+TEST_SUITES="linuxboot"
+FVP_CONSOLES[default] = "terminal_0"
+FVP_CONSOLES[tf-a] = "s_terminal_0"
+```
+
+[OEQA]: https://docs.yoctoproject.org/test-manual/intro.html
+[FVP]: https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms
+[RUNFVP]: runfvp.md
+[PEXPECT]: https://pexpect.readthedocs.io/en/stable/overview.html

documentation/runfvp.md

@@ -98,13 +98,16 @@ FVP_TERMINALS[bp.terminal_2] = ""
 FVP_TERMINALS[bp.terminal_3] = ""
 ```
 
-### `FVP_CONSOLE`
+### `FVP_CONSOLES`
 
-This specifies what serial port is used when `--console` is passed to runfvp. Note that this has to be the FVP identifier but without the board prefix, for example:
+This specifies what serial ports can be used in oeqa tests, along with an alias to be used in the test cases. Note that the values have to be the FVP identifier but without the board prefix, for example:
 ```
-FVP_CONSOLE = "terminal_0"
+FVP_CONSOLES[default] = "terminal_0"
+FVP_CONSOLES[tf-a] = "s_terminal_0"
 ```
 
+The 'default' console is also used when `--console` is passed to runfvp.
+
 ### `FVP_EXTRA_ARGS`
 
 Arbitrary extra arguments that are passed directly to the FVP.  For example:
@@ -113,6 +116,14 @@ Arbitrary extra arguments that are passed directly to the FVP.  For example:
 FVP_EXTRA_ARGS = "--simlimit 60"
 ```
 
+### `FVP_ENV_PASSTHROUGH`
+
+The FVP is launched with an isolated set of environment variables. Add the name of a Bitbake variable to this list to pass it through to the FVP environment. For example:
+
+```
+FVP_ENV_PASSTHROUGH = "ARMLMD_LICENSE_FILE FM_TRACE_PLUGINS"
+```
+
 
 [AEM]: https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/arm-ecosystem-models
 [FVP]: https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms

kas/corstone1000-base.yml

@@ -5,7 +5,7 @@ distro: poky-tiny
 
 defaults:
   repos:
-    refspec: master
+    refspec: kirkstone
 
 repos:
   meta-arm:
@@ -16,7 +16,6 @@ repos:
 
   poky:
     url: https://git.yoctoproject.org/git/poky
-    refspec: master
     layers:
       meta:
       meta-poky:
@@ -24,15 +23,10 @@ repos:
 
   meta-openembedded:
     url: https://git.openembedded.org/meta-openembedded
-    refspec: master
     layers:
       meta-oe:
       meta-python:
 
-  meta-arm-image:
-     url: https://git.gitlab.arm.com/arm-reference-solutions/meta-arm-image.git
-     refspec: 9f611833ef58394b707836d69356c4e27d0265fc 
-
 local_conf_header:
   base: |
     CONF_VERSION = "2"

kas/corstone1000-fvp.yml

@@ -3,13 +3,6 @@ header:
   includes:
     - kas/corstone1000-base.yml
 
-repos:
-  run-scripts:
-     url: https://git.gitlab.arm.com/arm-reference-solutions/model-scripts.git
-     refspec: b40b4227fe6b6fc8e4b688db8928f4be76e94eb7
-     layers:
-      .: 'excluded'
-
 machine: corstone1000-fvp
 
 local_conf_header:

kas/tftf.yml

@@ -0,0 +1,7 @@
+header:
+  version: 9
+
+local_conf_header:
+  tftf: |
+    TFA_UBOOT = "0"
+    TFTF_TESTS = "1"

meta-arm-bsp/conf/machine/corstone1000-fvp.conf

@@ -8,8 +8,8 @@ TFA_TARGET_PLATFORM = "fvp"
 TFM_PLATFORM_IS_FVP = "TRUE"
 
 # testimage config
-TEST_TARGET = "OEFVPTarget"
-TEST_SUITES = "noop"
+TEST_TARGET = "OEFVPSerialTarget"
+TEST_SUITES = "linuxboot"
 
 # FVP Config
 FVP_PROVIDER ?= "fvp-corstone1000-native"

meta-arm-bsp/conf/machine/corstone500.conf

@@ -33,8 +33,8 @@ WKS_FILE_DEPENDS:append = " ${EXTRA_IMAGEDEPENDS}"
 
 WKS_FILE ?= "core-image-minimal.corstone500.wks"
 
-TEST_TARGET = "OEFVPTarget"
-TEST_SUITES = "noop"
+TEST_TARGET = "OEFVPSerialTarget"
+TEST_SUITES = "linuxboot"
 
 FVP_PROVIDER ?= "fvp-corstone500-native"
 FVP_EXE ?= "FVP_Corstone-500"

meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf

@@ -32,8 +32,8 @@ PACKAGECONFIG:remove:pn-openssh = "rng-tools"
 MACHINE_EXTRA_RRECOMMENDS += "ssh-pregen-hostkeys"
 
 # testimage configuration
-TEST_TARGET = "OEFVPTarget"
-TEST_SUITES = "ping ssh"
+TEST_TARGET = "OEFVPSerialTarget"
+TEST_SUITES = "linuxboot"
 TEST_TARGET_IP ?= "127.0.0.1:8022"
 TEST_SERVER_IP ?= "127.0.1.1"
 
@@ -43,32 +43,24 @@ FVP_EXE ?= "FVP_BaseR_AEMv8R"
 FVP_CONSOLE ?= "terminal_0"
 
 # FVP parameters
-FVP_CONFIG[bp.virtioblockdevice.image_path] ?= "${DEPLOY_DIR_IMAGE}/${IMAGE_NAME}.rootfs.wic"
-FVP_CONFIG[bp.dram_metadata.init_value] ?= "0"
-FVP_CONFIG[bp.dram_metadata.is_enabled] ?= "true"
-FVP_CONFIG[bp.exclusive_monitor.monitor_access_level] ?= "1"
-FVP_CONFIG[bp.pl011_uart0.unbuffered_output] ?= "1"
-FVP_CONFIG[bp.pl011_uart0.untimed_fifos] ?= "true"
+FVP_CONFIG[bp.exclusive_monitor.monitor_access_level] ?= "2"
 FVP_CONFIG[bp.refcounter.non_arch_start_at_default] ?= "1"
-FVP_CONFIG[bp.smsc_91c111.enabled] ?= "0"
-FVP_CONFIG[bp.ve_sysregs.mmbSiteDefault] ?= "0"
-FVP_CONFIG[cache_state_modelled] ?= "0"
-FVP_CONFIG[cluster0.gicv3.cpuintf-mmap-access-level] ?= "2"
-FVP_CONFIG[cluster0.gicv3.SRE-enable-action-on-mmap] ?= "2"
-FVP_CONFIG[cluster0.gicv3.SRE-EL2-enable-RAO] ?= "1"
-FVP_CONFIG[cluster0.gicv3.extended-interrupt-range-support] ?= "1"
-FVP_CONFIG[cluster0.has_aarch64] ?= "1"
-FVP_CONFIG[cluster0.NUM_CORES] ?= "4"
-FVP_CONFIG[cluster0.stage12_tlb_size] ?= "512"
-FVP_CONFIG[gic_distributor.GICD_CTLR-DS-1-means-secure-only] ?= "1"
-FVP_CONFIG[gic_distributor.GITS_BASER0-type] ?= "1"
-FVP_CONFIG[gic_distributor.ITS-count] ?= "1"
-FVP_CONFIG[gic_distributor.ITS-hardware-collection-count] ?= "1"
-FVP_CONFIG[gic_distributor.has-two-security-states] ?= "0"
-FVP_CONFIG[pctl.startup] ?= "0.0.0.*"
-FVP_CONFIG[bp.virtio_net.enabled] ?= "1"
-FVP_CONFIG[bp.virtio_net.hostbridge.userNetworking] ?= "1"
-FVP_CONFIG[bp.virtio_net.hostbridge.userNetPorts] ?= "8022=22"
-FVP_CONFIG[bp.virtio_rng.enabled] ?= "1"
-FVP_CONFIG[bp.vis.rate_limit-enable] ?= "0"
 FVP_CONFIG[bp.refcounter.use_real_time] ?= "1"
+FVP_CONFIG[bp.ve_sysregs.exit_on_shutdown] ?= "1"
+FVP_CONFIG[bp.virtio_net.enabled] ?= "1"
+FVP_CONFIG[bp.virtio_net.hostbridge.userNetPorts] ?= "8022=22"
+FVP_CONFIG[bp.virtio_net.hostbridge.userNetworking] ?= "1"
+FVP_CONFIG[bp.virtio_net.secure_accesses] = "1"
+FVP_CONFIG[bp.virtio_rng.enabled] ?= "1"
+FVP_CONFIG[bp.virtio_rng.secure_accesses] = "1"
+FVP_CONFIG[bp.virtioblockdevice.image_path] ?= "${DEPLOY_DIR_IMAGE}/${IMAGE_NAME}.rootfs.wic"
+FVP_CONFIG[bp.virtioblockdevice.secure_accesses] = "1"
+FVP_CONFIG[cache_state_modelled] ?= "0"
+FVP_CONFIG[cci400.force_on_from_start] = "1"
+FVP_CONFIG[cluster0.gicv3.cpuintf-mmap-access-level] ?= "2"
+FVP_CONFIG[cluster0.gicv3.extended-interrupt-range-support] ?= "1"
+FVP_CONFIG[cluster0.gicv3.SRE-EL2-enable-RAO] ?= "1"
+FVP_CONFIG[cluster0.gicv3.SRE-enable-action-on-mmap] ?= "2"
+FVP_CONFIG[cluster0.has_aarch64] ?= "1"
+FVP_CONFIG[gic_distributor.GICD_CTLR-DS-1-means-secure-only] ?= "1"
+FVP_CONFIG[gic_distributor.has-two-security-states] ?= "0"

meta-arm-bsp/conf/machine/include/corstone1000.inc

@@ -48,13 +48,16 @@ EXTRA_IMAGEDEPENDS += "secure-partitions"
 # Linux kernel
 PREFERRED_PROVIDER_virtual/kernel:forcevariable = "linux-yocto"
 PREFERRED_VERSION_linux-yocto = "5.15%"
-KERNEL_IMAGETYPE = "Image"
+KERNEL_IMAGETYPE = "Image.gz"
 
 INITRAMFS_IMAGE_BUNDLE ?= "1"
 
 #telling the build system which image is responsible of the generation of the initramfs rootfs
 INITRAMFS_IMAGE = "corstone1000-initramfs-image"
 
+# prevent the kernel image from being included in the intramfs rootfs
+PACKAGE_EXCLUDE = "kernel-image-*"
+
 # enable this feature for kernel debugging
 # MACHINE_FEATURES += "corstone1000_kernel_debug"
 
@@ -65,4 +68,3 @@ SERIAL_CONSOLES ?= "115200;ttyAMA0"
 WKS_FILE_DEPENDS:append = " ${EXTRA_IMAGEDEPENDS}"
 
 WKS_FILE ?= "corstone1000-image.corstone1000.wks"
-

meta-arm-bsp/conf/machine/juno.conf

@@ -10,10 +10,10 @@ require conf/machine/include/arm/arch-armv8a.inc
 
 MACHINE_FEATURES = "usbhost usbgadget alsa screen wifi bluetooth optee pci"
 
-KERNEL_IMAGETYPE = "Image"
+KERNEL_IMAGETYPE = "Image.gz"
 KERNEL_DEVICETREE = "arm/juno.dtb arm/juno-r1.dtb arm/juno-r2.dtb"
 
-IMAGE_FSTYPES += "tar.bz2 ext4"
+IMAGE_FSTYPES += "tar.bz2 ext4 cpio.gz"
 
 SERIAL_CONSOLES = "115200;ttyAMA0"
 
@@ -25,3 +25,6 @@ EXTRA_IMAGEDEPENDS += "trusted-firmware-a virtual/bootloader firmware-image-juno
 
 # Juno u-boot configuration
 UBOOT_MACHINE = "vexpress_aemv8a_juno_defconfig"
+
+INITRAMFS_IMAGE_BUNDLE ?= "1"
+INITRAMFS_IMAGE = "core-image-minimal"

meta-arm-bsp/conf/machine/n1sdp.conf

@@ -25,6 +25,8 @@ PREFERRED_VERSION_linux-yocto ?= "5.15%"
 MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "linux-firmware-rtl8168"
 
 EXTRA_IMAGEDEPENDS += "trusted-firmware-a"
+PREFERRED_VERSION_trusted-firmware-a ?= "2.7%"
+
 EXTRA_IMAGEDEPENDS += "virtual/control-processor-firmware"
 
 #UEFI EDK2 firmware

meta-arm-bsp/documentation/fvp-baser-aemv8r64.md

@@ -27,7 +27,7 @@ The fvp-baser-aemv8r64 Yocto MACHINE supports the following BSP components,
 where either a standard or Real-Time Linux kernel (PREEMPT\_RT) can be built
 and run:
 
- - FVP_Base_AEMv8R: v11.17.21
+ - FVP_Base_AEMv8R: v11.19.14
  - boot-wrapper-aarch64: provides PSCI support
  - U-Boot: v2022.01 - provides UEFI services
  - Linux kernel: linux-yocto-5.15
@@ -107,7 +107,7 @@ For more details on kas, see https://kas.readthedocs.io/.
 
 To build the images for the fvp-baser-aemv8r64 machine, you also need to accept
 the EULA at
-https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms/end-user-license-agreement-for-fixed-virtual-platforms
+https://developer.arm.com/downloads/-/arm-ecosystem-fvps/eula
 by setting the following environment variable:
 
     FVP_BASE_R_ARM_EULA_ACCEPT="True"

meta-arm-bsp/recipes-bsp/images/firmware-image-juno.bb

@@ -63,10 +63,10 @@ do_deploy() {
     done
 
     if [ "${INITRAMFS_IMAGE_BUNDLE}" -eq 1 ]; then
-        cp -L -f ${DEPLOY_DIR_IMAGE}/Image-initramfs-juno.bin \
+        cp -L -f ${DEPLOY_DIR_IMAGE}/Image.gz-initramfs-juno.bin \
             ${D}/${UNPACK_DIR}/SOFTWARE/Image
     else
-        cp -L -f ${DEPLOY_DIR_IMAGE}/Image ${D}/${UNPACK_DIR}/SOFTWARE/
+        cp -L -f ${DEPLOY_DIR_IMAGE}/${KERNEL_IMAGETYPE} ${D}/${UNPACK_DIR}/SOFTWARE/
     fi
 
     # Compress the files

meta-arm-bsp/recipes-bsp/images/n1sdp-board-firmware_2020.07.27.bb

@@ -11,10 +11,11 @@ INHIBIT_DEFAULT_DEPS = "1"
 PACKAGE_ARCH = "${MACHINE_ARCH}"
 COMPATIBLE_MACHINE = "n1sdp"
 
-SRC_URI = "https://git.linaro.org/landing-teams/working/arm/n1sdp-board-firmware.git/snapshot/${BPN}-N1SDP-${PV}.tar.gz"
-SRC_URI[sha256sum] = "57feba404026f2d6d49c167d63e0e84653ad8b808b13e2244b81fea9e0d58d66"
+SRC_URI = "git://git.linaro.org/landing-teams/working/arm/n1sdp-board-firmware.git;protocol=https;branch=master"
 
-S = "${WORKDIR}/${BPN}-N1SDP-${PV}"
+SRCREV  = "9a095cbdf8ef59a7433e2769e4e2e92782b68c50"
+
+S = "${WORKDIR}/git"
 
 INSTALL_DIR = "/n1sdp-board-firmware_source"
 

meta-arm-bsp/recipes-bsp/images/sdcard-image-n1sdp_0.1.bb

@@ -2,7 +2,7 @@ SUMMARY = "Firmware image recipe for generating SD-Card artifacts."
 
 inherit deploy nopackages
 
-DEPENDS = "edk2-firmware \
+DEPENDS = "trusted-firmware-a \
            virtual/control-processor-firmware \
            n1sdp-board-firmware"
 
@@ -27,8 +27,8 @@ prepare_package() {
     cp -av ${RECIPE_SYSROOT}/${FIRMWARE_DIR}/* ${PRIMARY_DIR}
     mkdir -p ${PRIMARY_DIR}/SOFTWARE/
 
-    # Copy uefi binary
-    cp -v ${RECIPE_SYSROOT}/firmware/uefi.bin ${PRIMARY_DIR}/SOFTWARE/
+    # Copy FIP binary
+    cp -v ${RECIPE_SYSROOT}/firmware/fip.bin ${PRIMARY_DIR}/SOFTWARE/
 
     # Copy SOC binaries
     for f in ${SOC_BINARIES}; do
@@ -42,6 +42,11 @@ prepare_package() {
     sed -i -e 's|.*SOCCON: 0x1170.*PLATFORM_CTRL.*|SOCCON: 0x1170 0x00000100   ;SoC SCC PLATFORM_CTRL|' \
         ${PRIMARY_DIR}/MB/HBI0316A/io_v123f.txt
 
+    # Update load address for trusted boot
+    sed -i -e '/^IMAGE4ADDRESS:/ s|0x60200000|0x64200000|' ${PRIMARY_DIR}/MB/HBI0316A/images.txt
+    sed -i -e '/^IMAGE4UPDATE:/ s|FORCE   |SCP_AUTO|' ${PRIMARY_DIR}/MB/HBI0316A/images.txt
+    sed -i -e '/^IMAGE4FILE: \\SOFTWARE\\/s|uefi.bin|fip.bin |' ${PRIMARY_DIR}/MB/HBI0316A/images.txt
+
     # Slave/Secondary
     cp -av ${RECIPE_SYSROOT}/${FIRMWARE_DIR}/* ${SECONDARY_DIR}
     mkdir -p ${SECONDARY_DIR}/SOFTWARE/

meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware-n1sdp.inc

@@ -3,6 +3,10 @@
 SCP_PLATFORM  = "n1sdp"
 SCP_LOG_LEVEL = "INFO"
 
+# master branch at n1sdp: Introduce trusted board boot
+SRCREV  = "3e4c34ceccc1c960eb3a4adaa922f2a0c6b36be3"
+PV .= "+git${SRCPV}"
+
 COMPATIBLE_MACHINE:n1sdp = "n1sdp"
 
 DEPENDS += "fiptool-native"
@@ -12,7 +16,7 @@ do_install:append() {
    fiptool \
        create \
        --scp-fw "${D}/firmware/scp_ramfw.bin" \
-       --soc-fw "${RECIPE_SYSROOT}/firmware/bl31.bin" \
+       --blob uuid=cfacc2c4-15e8-4668-82be-430a38fad705,file="${RECIPE_SYSROOT}/firmware/bl1.bin" \
        "scp_fw.bin"
 
    # This UUID is FIP_UUID_MCP_BL2 in SCP-Firmware.

meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware_2.10.%.bbappend

@@ -0,0 +1,7 @@
+# Include machine specific SCP configurations
+
+MACHINE_SCP_REQUIRE ?= ""
+
+MACHINE_SCP_REQUIRE:n1sdp = "scp-firmware-n1sdp.inc"
+
+require ${MACHINE_SCP_REQUIRE}

meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware_2.9.%.bbappend

@@ -3,7 +3,6 @@
 MACHINE_SCP_REQUIRE ?= ""
 
 MACHINE_SCP_REQUIRE:juno = "scp-firmware-juno.inc"
-MACHINE_SCP_REQUIRE:n1sdp = "scp-firmware-n1sdp.inc"
 MACHINE_SCP_REQUIRE:sgi575 = "scp-firmware-sgi575.inc"
 MACHINE_SCP_REQUIRE:tc = "scp-firmware-tc.inc"
 

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0001-Rename-Diphda-to-corstone1000.patch

@@ -1,587 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
-
-From b4d59c85d1045998275cd219efe5849803c2c616 Mon Sep 17 00:00:00 2001
-From: "Arpita S.K" <Arpita.S.K@arm.com>
-Date: Wed, 13 Oct 2021 18:05:11 +0530
-Subject: [PATCH] Rename Diphda to corstone1000
-
-Replace all the instances of Diphda as functions,
-macros etc. with corstone1000
-
-Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
----
- docs/about/maintainers.rst                    |  2 +-
- .../arm/{diphda => corstone1000}/index.rst    |  6 +-
- docs/plat/arm/index.rst                       |  2 +-
- plat/arm/board/common/rotpk/arm_dev_rotpk.S   |  2 +-
- .../corstone1000_bl2_mem_params_desc.c}       |  8 +-
- .../common/corstone1000_err.c}                |  2 +-
- .../common/corstone1000_helpers.S}            |  4 +-
- .../common/corstone1000_plat.c}               |  6 +-
- .../common/corstone1000_pm.c}                 |  0
- .../common/corstone1000_security.c}           |  0
- .../common/corstone1000_stack_protector.c}    |  0
- .../common/corstone1000_topology.c}           | 12 +--
- .../common/corstone1000_trusted_boot.c}       |  2 +-
- .../fdts/corstone1000_spmc_manifest.dts}      |  0
- .../common/include/platform_def.h             | 52 ++++++------
- .../include/plat_macros.S                     |  0
- plat/arm/board/corstone1000/platform.mk       | 83 +++++++++++++++++++
- plat/arm/board/diphda/platform.mk             | 83 -------------------
- 18 files changed, 132 insertions(+), 132 deletions(-)
- rename docs/plat/arm/{diphda => corstone1000}/index.rst (93%)
- rename plat/arm/board/{diphda/common/diphda_bl2_mem_params_desc.c => corstone1000/common/corstone1000_bl2_mem_params_desc.c} (92%)
- rename plat/arm/board/{diphda/common/diphda_err.c => corstone1000/common/corstone1000_err.c} (89%)
- rename plat/arm/board/{diphda/common/diphda_helpers.S => corstone1000/common/corstone1000_helpers.S} (94%)
- rename plat/arm/board/{diphda/common/diphda_plat.c => corstone1000/common/corstone1000_plat.c} (92%)
- rename plat/arm/board/{diphda/common/diphda_pm.c => corstone1000/common/corstone1000_pm.c} (100%)
- rename plat/arm/board/{diphda/common/diphda_security.c => corstone1000/common/corstone1000_security.c} (100%)
- rename plat/arm/board/{diphda/common/diphda_stack_protector.c => corstone1000/common/corstone1000_stack_protector.c} (100%)
- rename plat/arm/board/{diphda/common/diphda_topology.c => corstone1000/common/corstone1000_topology.c} (77%)
- rename plat/arm/board/{diphda/common/diphda_trusted_boot.c => corstone1000/common/corstone1000_trusted_boot.c} (97%)
- rename plat/arm/board/{diphda/common/fdts/diphda_spmc_manifest.dts => corstone1000/common/fdts/corstone1000_spmc_manifest.dts} (100%)
- rename plat/arm/board/{diphda => corstone1000}/common/include/platform_def.h (89%)
- rename plat/arm/board/{diphda => corstone1000}/include/plat_macros.S (100%)
- create mode 100644 plat/arm/board/corstone1000/platform.mk
- delete mode 100644 plat/arm/board/diphda/platform.mk
-
-diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
-index 07f258c774..2d9eb1440d 100644
---- a/docs/about/maintainers.rst
-+++ b/docs/about/maintainers.rst
-@@ -399,7 +399,7 @@ Arm Rich IoT Platform ports
- :|G|: `vishnu-banavath`_
- :|F|: plat/arm/board/corstone700
- :|F|: plat/arm/board/a5ds
--:|F|: plat/arm/board/diphda
-+:|F|: plat/arm/board/corstone1000
- 
- Arm Reference Design platform ports
- ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-diff --git a/docs/plat/arm/diphda/index.rst b/docs/plat/arm/corstone1000/index.rst
-similarity index 93%
-rename from docs/plat/arm/diphda/index.rst
-rename to docs/plat/arm/corstone1000/index.rst
-index 27afda43f5..b889b7f2e9 100644
---- a/docs/plat/arm/diphda/index.rst
-+++ b/docs/plat/arm/corstone1000/index.rst
-@@ -1,7 +1,7 @@
--Diphda Platform
-+Corstone1000 Platform
- ==========================
- 
--Some of the features of the Diphda platform referenced in TF-A include:
-+Some of the features of the Corstone1000 platform referenced in TF-A include:
- 
- - Cortex-A35 application processor (64-bit mode)
- - Secure Enclave
-@@ -37,7 +37,7 @@ Build Procedure (TF-A only)
-       CC=aarch64-none-elf-gcc \
-       V=1 \
-       BUILD_BASE=<path to the build folder> \
--      PLAT=diphda \
-+      PLAT=corstone1000 \
-       SPD=spmd \
-       SPMD_SPM_AT_SEL2=0 \
-       DEBUG=1 \
-diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst
-index c834f6ae70..23c561ff57 100644
---- a/docs/plat/arm/index.rst
-+++ b/docs/plat/arm/index.rst
-@@ -12,7 +12,7 @@ Arm Development Platforms
-    arm_fpga/index
-    arm-build-options
-    morello/index
--   diphda/index
-+   corstone1000/index
- 
- This chapter holds documentation related to Arm's development platforms,
- including both software models (FVPs) and hardware development boards
-diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
-index 38f91fe5f8..125ddf67c7 100644
---- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S
-+++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
-@@ -4,7 +4,7 @@
-  * SPDX-License-Identifier: BSD-3-Clause
-  */
- 
--/* diphda platform provides custom values for the macros defined in
-+/* corstone1000 platform provides custom values for the macros defined in
-  * arm_def.h , so only platform_def.h needs to be included
-  */
- #if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)
-diff --git a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
-similarity index 92%
-rename from plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
-rename to plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
-index 916c868d21..7baa82d31b 100644
---- a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
-@@ -44,7 +44,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
- 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- 			VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
- 		.ep_info.pc = BL32_BASE,
--			.ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE,
-+			.ep_info.args.arg0 = CORSTONE1000_TOS_FW_CONFIG_BASE,
- 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- 			VERSION_2, image_info_t, 0),
- 		.image_info.image_base = BL32_BASE,
-@@ -56,9 +56,9 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
- 	/* Fill TOS_FW_CONFIG related information */
- 	{
- 		.image_id = TOS_FW_CONFIG_ID,
--		.image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE,
--		.image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \
--			DIPHDA_TOS_FW_CONFIG_BASE,
-+		.image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE,
-+		.image_info.image_max_size = CORSTONE1000_TOS_FW_CONFIG_LIMIT - \
-+			CORSTONE1000_TOS_FW_CONFIG_BASE,
- 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
- 			VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
- 		SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
-diff --git a/plat/arm/board/diphda/common/diphda_err.c b/plat/arm/board/corstone1000/common/corstone1000_err.c
-similarity index 89%
-rename from plat/arm/board/diphda/common/diphda_err.c
-rename to plat/arm/board/corstone1000/common/corstone1000_err.c
-index 89a3b8249c..5f8e7da437 100644
---- a/plat/arm/board/diphda/common/diphda_err.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_err.c
-@@ -7,7 +7,7 @@
- #include <plat/arm/common/plat_arm.h>
- 
- /*
-- * diphda error handler
-+ * corstone1000 error handler
-  */
- void __dead2 plat_arm_error_handler(int err)
- {
-diff --git a/plat/arm/board/diphda/common/diphda_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
-similarity index 94%
-rename from plat/arm/board/diphda/common/diphda_helpers.S
-rename to plat/arm/board/corstone1000/common/corstone1000_helpers.S
-index c9d2a88de9..87122270b0 100644
---- a/plat/arm/board/diphda/common/diphda_helpers.S
-+++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
-@@ -29,7 +29,7 @@ endfunc plat_secondary_cold_boot_setup
- 	 * unsigned long plat_get_my_entrypoint (void);
- 	 *
- 	 * Main job of this routine is to distinguish between a cold and warm
--	 * boot. On diphda, this information can be queried from the power
-+	 * boot. On corstone1000, this information can be queried from the power
- 	 * controller. The Power Control SYS Status Register (PSYSR) indicates
- 	 * the wake-up reason for the CPU.
- 	 *
-@@ -61,7 +61,7 @@ func plat_is_my_cpu_primary
- 	mrs	x0, mpidr_el1
- 	mov_imm	x1, MPIDR_AFFINITY_MASK
- 	and	x0, x0, x1
--	cmp	x0, #DIPHDA_PRIMARY_CPU
-+	cmp	x0, #CORSTONE1000_PRIMARY_CPU
- 	cset	w0, eq
- 	ret
- endfunc plat_is_my_cpu_primary
-diff --git a/plat/arm/board/diphda/common/diphda_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
-similarity index 92%
-rename from plat/arm/board/diphda/common/diphda_plat.c
-rename to plat/arm/board/corstone1000/common/corstone1000_plat.c
-index 28d15a59e6..7a38b0b2ee 100644
---- a/plat/arm/board/diphda/common/diphda_plat.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
-@@ -21,12 +21,12 @@ const mmap_region_t plat_arm_mmap[] = {
- 	ARM_MAP_SHARED_RAM,
- 	ARM_MAP_NS_SHARED_RAM,
- 	ARM_MAP_NS_DRAM1,
--	DIPHDA_MAP_DEVICE,
--	DIPHDA_EXTERNAL_FLASH,
-+	CORSTONE1000_MAP_DEVICE,
-+	CORSTONE1000_EXTERNAL_FLASH,
- 	{0}
- };
- 
--/* diphda only has one always-on power domain and there
-+/* corstone1000 only has one always-on power domain and there
-  * is no power control present
-  */
- void __init plat_arm_pwrc_setup(void)
-diff --git a/plat/arm/board/diphda/common/diphda_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
-similarity index 100%
-rename from plat/arm/board/diphda/common/diphda_pm.c
-rename to plat/arm/board/corstone1000/common/corstone1000_pm.c
-diff --git a/plat/arm/board/diphda/common/diphda_security.c b/plat/arm/board/corstone1000/common/corstone1000_security.c
-similarity index 100%
-rename from plat/arm/board/diphda/common/diphda_security.c
-rename to plat/arm/board/corstone1000/common/corstone1000_security.c
-diff --git a/plat/arm/board/diphda/common/diphda_stack_protector.c b/plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
-similarity index 100%
-rename from plat/arm/board/diphda/common/diphda_stack_protector.c
-rename to plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
-diff --git a/plat/arm/board/diphda/common/diphda_topology.c b/plat/arm/board/corstone1000/common/corstone1000_topology.c
-similarity index 77%
-rename from plat/arm/board/diphda/common/diphda_topology.c
-rename to plat/arm/board/corstone1000/common/corstone1000_topology.c
-index 9dfd05d091..2a3b6913a1 100644
---- a/plat/arm/board/diphda/common/diphda_topology.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_topology.c
-@@ -7,8 +7,8 @@
- #include <plat/arm/common/plat_arm.h>
- #include <plat/common/platform.h>
- 
--/* The diphda power domain tree descriptor */
--static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
-+/* The corstone1000 power domain tree descriptor */
-+static unsigned char corstone1000_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
- 							+ 2];
- /*******************************************************************************
-  * This function dynamically constructs the topology according to
-@@ -22,13 +22,13 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
- 	 * The highest level is the system level. The next level is constituted
- 	 * by clusters and then cores in clusters.
- 	 */
--	diphda_power_domain_tree_desc[0] = 1;
--	diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
-+	corstone1000_power_domain_tree_desc[0] = 1;
-+	corstone1000_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
- 
- 	for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
--		diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
-+		corstone1000_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
- 
--	return diphda_power_domain_tree_desc;
-+	return corstone1000_power_domain_tree_desc;
- }
- 
- /******************************************************************************
-diff --git a/plat/arm/board/diphda/common/diphda_trusted_boot.c b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
-similarity index 97%
-rename from plat/arm/board/diphda/common/diphda_trusted_boot.c
-rename to plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
-index ddb41faa6b..2e2e9475a5 100644
---- a/plat/arm/board/diphda/common/diphda_trusted_boot.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
-@@ -38,7 +38,7 @@ int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
-  */
- int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
- {
--    *nv_ctr = DIPHDA_FW_NVCTR_VAL;
-+    *nv_ctr = CORSTONE1000_FW_NVCTR_VAL;
-     return 0;
- }
- 
-diff --git a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
-similarity index 100%
-rename from plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
-rename to plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
-diff --git a/plat/arm/board/diphda/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
-similarity index 89%
-rename from plat/arm/board/diphda/common/include/platform_def.h
-rename to plat/arm/board/corstone1000/common/include/platform_def.h
-index 37fd71b6aa..e36bb626ee 100644
---- a/plat/arm/board/diphda/common/include/platform_def.h
-+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
-@@ -34,17 +34,17 @@
- #define V2M_IOFPGA_UART0_CLK_IN_HZ		50000000
- #define V2M_IOFPGA_UART1_CLK_IN_HZ		50000000
- 
--/* Core/Cluster/Thread counts for diphda */
--#define DIPHDA_CLUSTER_COUNT			U(1)
--#define DIPHDA_MAX_CPUS_PER_CLUSTER		U(4)
--#define DIPHDA_MAX_PE_PER_CPU			U(1)
--#define DIPHDA_PRIMARY_CPU			U(0)
-+/* Core/Cluster/Thread counts for corstone1000 */
-+#define CORSTONE1000_CLUSTER_COUNT			U(1)
-+#define CORSTONE1000_MAX_CPUS_PER_CLUSTER		U(4)
-+#define CORSTONE1000_MAX_PE_PER_CPU			U(1)
-+#define CORSTONE1000_PRIMARY_CPU			U(0)
- 
--#define PLAT_ARM_CLUSTER_COUNT		DIPHDA_CLUSTER_COUNT
-+#define PLAT_ARM_CLUSTER_COUNT		CORSTONE1000_CLUSTER_COUNT
- 
- #define PLATFORM_CORE_COUNT			(PLAT_ARM_CLUSTER_COUNT *      \
--						DIPHDA_MAX_CPUS_PER_CLUSTER *  \
--						DIPHDA_MAX_PE_PER_CPU)
-+						CORSTONE1000_MAX_CPUS_PER_CLUSTER *  \
-+						CORSTONE1000_MAX_PE_PER_CPU)
- 
- /* UART related constants */
- #define PLAT_ARM_BOOT_UART_BASE		0x1a510000
-@@ -85,7 +85,7 @@
-  *
-  *             BL32 (optee-os)
-  *
-- * <DIPHDA_TOS_FW_CONFIG_BASE> = 0x20ae000
-+ * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
-  *
-  *         partition size: 8 KB
-  *
-@@ -132,7 +132,7 @@
- #define ARM_DRAM1_END				(ARM_DRAM1_BASE +	\
- 						ARM_DRAM1_SIZE - 1)
- 
--/* DRAM1 and DRAM2 are the same for diphda */
-+/* DRAM1 and DRAM2 are the same for corstone1000 */
- #define ARM_DRAM2_BASE			ARM_DRAM1_BASE
- #define ARM_DRAM2_SIZE			ARM_DRAM1_SIZE
- #define ARM_DRAM2_END				ARM_DRAM1_END
-@@ -173,13 +173,13 @@
- 						PLAT_ARM_MAX_BL31_SIZE)
- #define BL31_LIMIT				BL2_SIGNATURE_BASE
- 
--#define DIPHDA_TOS_FW_CONFIG_BASE		(BL31_BASE - \
--						DIPHDA_TOS_FW_CONFIG_SIZE)
--#define DIPHDA_TOS_FW_CONFIG_SIZE		UL(0x00002000)  /* 8 KB */
--#define DIPHDA_TOS_FW_CONFIG_LIMIT		BL31_BASE
-+#define CORSTONE1000_TOS_FW_CONFIG_BASE		(BL31_BASE - \
-+						CORSTONE1000_TOS_FW_CONFIG_SIZE)
-+#define CORSTONE1000_TOS_FW_CONFIG_SIZE		UL(0x00002000)  /* 8 KB */
-+#define CORSTONE1000_TOS_FW_CONFIG_LIMIT		BL31_BASE
- 
- #define BL32_BASE				ARM_BL_RAM_BASE
--#define PLAT_ARM_MAX_BL32_SIZE		(DIPHDA_TOS_FW_CONFIG_BASE - \
-+#define PLAT_ARM_MAX_BL32_SIZE		(CORSTONE1000_TOS_FW_CONFIG_BASE - \
- 						BL32_BASE)     /* 688 KB */
- #define BL32_LIMIT				(BL32_BASE + \
- 						PLAT_ARM_MAX_BL32_SIZE)
-@@ -220,7 +220,7 @@
- /*
-  * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
-  * FW_CONFIG is intended to host the device tree. Currently, This area is not
-- * used because diphda platform doesn't use a device tree at TF-A level.
-+ * used because corstone1000 platform doesn't use a device tree at TF-A level.
-  */
- #define ARM_FW_CONFIG_BASE			(ARM_SHARED_RAM_BASE \
- 						+ sizeof(meminfo_t))
-@@ -261,8 +261,8 @@
- 
- #define SYS_COUNTER_FREQ_IN_TICKS	UL(50000000) /* 50MHz */
- 
--#define DIPHDA_IRQ_TZ_WDOG			32
--#define DIPHDA_IRQ_SEC_SYS_TIMER		34
-+#define CORSTONE1000_IRQ_TZ_WDOG			32
-+#define CORSTONE1000_IRQ_SEC_SYS_TIMER		34
- 
- #define PLAT_MAX_PWR_LVL			2
- /*
-@@ -308,7 +308,7 @@
- 
- #define PLATFORM_STACK_SIZE			UL(0x440)
- 
--#define DIPHDA_EXTERNAL_FLASH			MAP_REGION_FLAT(	\
-+#define CORSTONE1000_EXTERNAL_FLASH			MAP_REGION_FLAT(	\
- 						PLAT_ARM_NVM_BASE,	\
- 						PLAT_ARM_NVM_SIZE,	\
- 						MT_DEVICE | MT_RO | MT_SECURE)
-@@ -356,11 +356,11 @@
- 						ARM_FW_CONFIG_BASE),   \
- 						MT_MEMORY | MT_RW | MT_SECURE)
- 
--#define DIPHDA_DEVICE_BASE			(0x1A000000)
--#define DIPHDA_DEVICE_SIZE			(0x26000000)
--#define DIPHDA_MAP_DEVICE			MAP_REGION_FLAT(	\
--						DIPHDA_DEVICE_BASE,	\
--						DIPHDA_DEVICE_SIZE,	\
-+#define CORSTONE1000_DEVICE_BASE			(0x1A000000)
-+#define CORSTONE1000_DEVICE_SIZE			(0x26000000)
-+#define CORSTONE1000_MAP_DEVICE			MAP_REGION_FLAT(	\
-+						CORSTONE1000_DEVICE_BASE,	\
-+						CORSTONE1000_DEVICE_SIZE,	\
- 						MT_DEVICE | MT_RW | MT_SECURE)
- 
- #define ARM_IRQ_SEC_PHY_TIMER			29
-@@ -406,9 +406,9 @@
-  */
- #define PLAT_ARM_G1S_IRQ_PROPS(grp)	\
- 	ARM_G1S_IRQ_PROPS(grp), \
--	INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
-+	INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
- 		(grp), GIC_INTR_CFG_LEVEL), \
--	INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \
-+	INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \
- 		GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
- 
- #define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
-diff --git a/plat/arm/board/diphda/include/plat_macros.S b/plat/arm/board/corstone1000/include/plat_macros.S
-similarity index 100%
-rename from plat/arm/board/diphda/include/plat_macros.S
-rename to plat/arm/board/corstone1000/include/plat_macros.S
-diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
-new file mode 100644
-index 0000000000..93e2ea0826
---- /dev/null
-+++ b/plat/arm/board/corstone1000/platform.mk
-@@ -0,0 +1,83 @@
-+#
-+# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
-+#
-+# SPDX-License-Identifier: BSD-3-Clause
-+#
-+
-+# Making sure the corstone1000 platform type is specified
-+ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
-+	$(error TARGET_PLATFORM must be fpga or fvp)
-+endif
-+
-+CORSTONE1000_CPU_LIBS	+=lib/cpus/aarch64/cortex_a35.S
-+
-+PLAT_INCLUDES		:=	-Iplat/arm/board/corstone1000/common/include	\
-+				-Iplat/arm/board/corstone1000/include		\
-+				-Iinclude/plat/arm/common			\
-+				-Iinclude/plat/arm/css/common/aarch64
-+
-+
-+CORSTONE1000_FW_NVCTR_VAL	:=	255
-+TFW_NVCTR_VAL		:=	${CORSTONE1000_FW_NVCTR_VAL}
-+NTFW_NVCTR_VAL		:=	${CORSTONE1000_FW_NVCTR_VAL}
-+
-+override NEED_BL1	:=	no
-+
-+override NEED_BL2	:=	yes
-+FIP_BL2_ARGS := tb-fw
-+
-+override NEED_BL2U	:=	no
-+override NEED_BL31	:=	yes
-+NEED_BL32		:=	yes
-+override NEED_BL33	:=	yes
-+
-+# Include GICv2 driver files
-+include drivers/arm/gic/v2/gicv2.mk
-+
-+CORSTONE1000_GIC_SOURCES	:=	${GICV2_SOURCES}			\
-+				plat/common/plat_gicv2.c		\
-+				plat/arm/common/arm_gicv2.c
-+
-+
-+BL2_SOURCES		+=	plat/arm/board/corstone1000/common/corstone1000_security.c		\
-+				plat/arm/board/corstone1000/common/corstone1000_err.c		\
-+				plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c	\
-+				lib/utils/mem_region.c					\
-+				plat/arm/board/corstone1000/common/corstone1000_helpers.S		\
-+				plat/arm/board/corstone1000/common/corstone1000_plat.c		\
-+				plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \
-+				${CORSTONE1000_CPU_LIBS}					\
-+
-+
-+BL31_SOURCES	+=	drivers/cfi/v2m/v2m_flash.c				\
-+			lib/utils/mem_region.c					\
-+			plat/arm/board/corstone1000/common/corstone1000_helpers.S		\
-+			plat/arm/board/corstone1000/common/corstone1000_topology.c		\
-+			plat/arm/board/corstone1000/common/corstone1000_security.c		\
-+			plat/arm/board/corstone1000/common/corstone1000_plat.c		\
-+			plat/arm/board/corstone1000/common/corstone1000_pm.c		\
-+			${CORSTONE1000_CPU_LIBS}					\
-+			${CORSTONE1000_GIC_SOURCES}
-+
-+ifneq (${ENABLE_STACK_PROTECTOR},0)
-+	ifneq (${ENABLE_STACK_PROTECTOR},none)
-+		CORSTONE1000_SECURITY_SOURCES := plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
-+		BL2_SOURCES += ${CORSTONE1000_SECURITY_SOURCES}
-+		BL31_SOURCES += ${CORSTONE1000_SECURITY_SOURCES}
-+	endif
-+endif
-+
-+FDT_SOURCES		+=	plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
-+CORSTONE1000_TOS_FW_CONFIG	:=	${BUILD_PLAT}/fdts/corstone1000_spmc_manifest.dtb
-+
-+# Add the SPMC manifest to FIP and specify the same to certtool
-+$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE1000_TOS_FW_CONFIG},--tos-fw-config,${CORSTONE1000_TOS_FW_CONFIG}))
-+
-+# Adding TARGET_PLATFORM as a GCC define (-D option)
-+$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
-+
-+# Adding CORSTONE1000_FW_NVCTR_VAL as a GCC define (-D option)
-+$(eval $(call add_define,CORSTONE1000_FW_NVCTR_VAL))
-+
-+include plat/arm/common/arm_common.mk
-+include plat/arm/board/common/board_common.mk
-diff --git a/plat/arm/board/diphda/platform.mk b/plat/arm/board/diphda/platform.mk
-deleted file mode 100644
-index 8b89cee7ed..0000000000
---- a/plat/arm/board/diphda/platform.mk
-+++ /dev/null
-@@ -1,83 +0,0 @@
--#
--# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
--#
--# SPDX-License-Identifier: BSD-3-Clause
--#
--
--# Making sure the diphda platform type is specified
--ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
--	$(error TARGET_PLATFORM must be fpga or fvp)
--endif
--
--DIPHDA_CPU_LIBS	+=lib/cpus/aarch64/cortex_a35.S
--
--PLAT_INCLUDES		:=	-Iplat/arm/board/diphda/common/include	\
--				-Iplat/arm/board/diphda/include		\
--				-Iinclude/plat/arm/common			\
--				-Iinclude/plat/arm/css/common/aarch64
--
--
--DIPHDA_FW_NVCTR_VAL	:=	255
--TFW_NVCTR_VAL		:=	${DIPHDA_FW_NVCTR_VAL}
--NTFW_NVCTR_VAL		:=	${DIPHDA_FW_NVCTR_VAL}
--
--override NEED_BL1	:=	no
--
--override NEED_BL2	:=	yes
--FIP_BL2_ARGS := tb-fw
--
--override NEED_BL2U	:=	no
--override NEED_BL31	:=	yes
--NEED_BL32		:=	yes
--override NEED_BL33	:=	yes
--
--# Include GICv2 driver files
--include drivers/arm/gic/v2/gicv2.mk
--
--DIPHDA_GIC_SOURCES	:=	${GICV2_SOURCES}			\
--				plat/common/plat_gicv2.c		\
--				plat/arm/common/arm_gicv2.c
--
--
--BL2_SOURCES		+=	plat/arm/board/diphda/common/diphda_security.c		\
--				plat/arm/board/diphda/common/diphda_err.c		\
--				plat/arm/board/diphda/common/diphda_trusted_boot.c	\
--				lib/utils/mem_region.c					\
--				plat/arm/board/diphda/common/diphda_helpers.S		\
--				plat/arm/board/diphda/common/diphda_plat.c		\
--				plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \
--				${DIPHDA_CPU_LIBS}					\
--
--
--BL31_SOURCES	+=	drivers/cfi/v2m/v2m_flash.c				\
--			lib/utils/mem_region.c					\
--			plat/arm/board/diphda/common/diphda_helpers.S		\
--			plat/arm/board/diphda/common/diphda_topology.c		\
--			plat/arm/board/diphda/common/diphda_security.c		\
--			plat/arm/board/diphda/common/diphda_plat.c		\
--			plat/arm/board/diphda/common/diphda_pm.c		\
--			${DIPHDA_CPU_LIBS}					\
--			${DIPHDA_GIC_SOURCES}
--
--ifneq (${ENABLE_STACK_PROTECTOR},0)
--	ifneq (${ENABLE_STACK_PROTECTOR},none)
--		DIPHDA_SECURITY_SOURCES := plat/arm/board/diphda/common/diphda_stack_protector.c
--		BL2_SOURCES += ${DIPHDA_SECURITY_SOURCES}
--		BL31_SOURCES += ${DIPHDA_SECURITY_SOURCES}
--	endif
--endif
--
--FDT_SOURCES		+=	plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
--DIPHDA_TOS_FW_CONFIG	:=	${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb
--
--# Add the SPMC manifest to FIP and specify the same to certtool
--$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG}))
--
--# Adding TARGET_PLATFORM as a GCC define (-D option)
--$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
--
--# Adding DIPHDA_FW_NVCTR_VAL as a GCC define (-D option)
--$(eval $(call add_define,DIPHDA_FW_NVCTR_VAL))
--
--include plat/arm/common/arm_common.mk
--include plat/arm/board/common/board_common.mk
--- 
-2.33.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-plat-arm-corstone1000-made-changes-to-accommodate-3M.patch

@@ -1,201 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
-
-From bf95f27e300e962140a5dec45c2b1727c0829511 Mon Sep 17 00:00:00 2001
-From: "Arpita S.K" <Arpita.S.K@arm.com>
-Date: Wed, 13 Oct 2021 14:49:26 +0530
-Subject: [PATCH] plat/arm: corstone1000: made changes to accommodate 3MB for
- optee
-
-* These changes are required to accommodate 3MB for OP-TEE and this
-is required for SP's part of optee
-* Added size macro's for better readability of the code
-* Moved uboot execution memory from CVM to DDR
-
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
----
- include/plat/common/common_def.h              | 25 ++++++++
- .../common/corstone1000_bl2_mem_params_desc.c |  7 +--
- .../common/include/platform_def.h             | 59 +++++++++++--------
- 3 files changed, 64 insertions(+), 27 deletions(-)
-
-diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
-index 14ae603b9b..5bb58692ef 100644
---- a/include/plat/common/common_def.h
-+++ b/include/plat/common/common_def.h
-@@ -12,6 +12,31 @@
- #include <lib/utils_def.h>
- #include <lib/xlat_tables/xlat_tables_defs.h>
- 
-+#define SZ_1K                          0x00000400
-+#define SZ_2K                          0x00000800
-+#define SZ_4K                          0x00001000
-+#define SZ_8K                          0x00002000
-+#define SZ_16K                         0x00004000
-+#define SZ_32K                         0x00008000
-+#define SZ_64K                         0x00010000
-+#define SZ_128K                                0x00020000
-+#define SZ_256K                                0x00040000
-+#define SZ_512K                                0x00080000
-+
-+#define SZ_1M                          0x00100000
-+#define SZ_2M                          0x00200000
-+#define SZ_4M                          0x00400000
-+#define SZ_8M                          0x00800000
-+#define SZ_16M                         0x01000000
-+#define SZ_32M                         0x02000000
-+#define SZ_64M                         0x04000000
-+#define SZ_128M                                0x08000000
-+#define SZ_256M                                0x10000000
-+#define SZ_512M                                0x20000000
-+
-+#define SZ_1G                          0x40000000
-+#define SZ_2G                          0x80000000
-+
- /******************************************************************************
-  * Required platform porting definitions that are expected to be common to
-  * all platforms
-diff --git a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
-index 7baa82d31b..6e90936a14 100644
---- a/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
-@@ -71,13 +71,12 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
- 		.image_id = BL33_IMAGE_ID,
- 		SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
- 			VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
--		.ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
-+		.ep_info.pc = BL33_BASE,
- 
- 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
- 			VERSION_2, image_info_t, 0),
--		.image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
--		.image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
--			- PLAT_ARM_NS_IMAGE_BASE,
-+		.image_info.image_base = BL33_BASE,
-+		.image_info.image_max_size = BL33_LIMIT - BL33_BASE,
- 
- 		.next_handoff_image_id = INVALID_IMAGE_ID,
- 	},
-diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
-index e36bb626ee..a0ac0fe758 100644
---- a/plat/arm/board/corstone1000/common/include/platform_def.h
-+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
-@@ -119,7 +119,7 @@
-  *
-  * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
-  *
-- *         partition size: 3 MB
-+ *         partition size: 512 KB
-  *
-  *         content:
-  *
-@@ -128,13 +128,13 @@
- 
- /* DDR memory */
- #define ARM_DRAM1_BASE			UL(0x80000000)
--#define ARM_DRAM1_SIZE			UL(0x80000000)
-+#define ARM_DRAM1_SIZE                 (SZ_2G) /* 2GB*/
- #define ARM_DRAM1_END				(ARM_DRAM1_BASE +	\
- 						ARM_DRAM1_SIZE - 1)
- 
- /* DRAM1 and DRAM2 are the same for corstone1000 */
--#define ARM_DRAM2_BASE			ARM_DRAM1_BASE
--#define ARM_DRAM2_SIZE			ARM_DRAM1_SIZE
-+#define ARM_DRAM2_BASE                         ARM_DRAM1_BASE
-+#define ARM_DRAM2_SIZE                         ARM_DRAM1_SIZE
- #define ARM_DRAM2_END				ARM_DRAM1_END
- 
- #define ARM_NS_DRAM1_BASE			ARM_DRAM1_BASE
-@@ -144,23 +144,31 @@
- 
- /* The first 8 KB of Trusted SRAM are used as shared memory */
- #define ARM_TRUSTED_SRAM_BASE			UL(0x02000000)
--#define ARM_SHARED_RAM_SIZE			UL(0x00002000)  /* 8 KB */
-+#define ARM_SHARED_RAM_SIZE                    (SZ_8K)  /* 8 KB */
- #define ARM_SHARED_RAM_BASE			ARM_TRUSTED_SRAM_BASE
- 
- /* The remaining Trusted SRAM is used to load the BL images */
-+#define TOTAL_SRAM_SIZE                                (SZ_4M) /* 4 MB */
- 
--#define PLAT_ARM_TRUSTED_SRAM_SIZE		UL(0x00100000)  /* 1 MB */
-+/* Last 512KB of CVM is allocated for shared RAM
-+ * as an example openAMP */
-+#define ARM_NS_SHARED_RAM_SIZE                 (512 * SZ_1K)
- 
--#define PLAT_ARM_MAX_BL2_SIZE			UL(0x0002d000)  /* 180 KB */
-+#define PLAT_ARM_TRUSTED_SRAM_SIZE             (TOTAL_SRAM_SIZE - \
-+                                                ARM_NS_SHARED_RAM_SIZE - \
-+                                                ARM_SHARED_RAM_SIZE)
- 
--#define PLAT_ARM_MAX_BL31_SIZE		UL(0x00023000)  /* 140 KB */
-+#define PLAT_ARM_MAX_BL2_SIZE                  (180 * SZ_1K)  /* 180 KB */
- 
--#define ARM_BL_RAM_BASE			(ARM_SHARED_RAM_BASE +	\
--						ARM_SHARED_RAM_SIZE)
--#define ARM_BL_RAM_SIZE			(PLAT_ARM_TRUSTED_SRAM_SIZE -	\
--						ARM_SHARED_RAM_SIZE)
-+#define PLAT_ARM_MAX_BL31_SIZE                  (140 * SZ_1K)  /* 140 KB */
-+
-+#define ARM_BL_RAM_BASE                                (ARM_SHARED_RAM_BASE +  \
-+                                                        ARM_SHARED_RAM_SIZE)
-+#define ARM_BL_RAM_SIZE                                (PLAT_ARM_TRUSTED_SRAM_SIZE - \
-+                                                        ARM_SHARED_RAM_SIZE)
-+
-+#define BL2_SIGNATURE_SIZE                     (SZ_4K)  /* 4 KB */
- 
--#define BL2_SIGNATURE_SIZE			UL(0x00001000)  /* 4 KB */
- #define BL2_SIGNATURE_BASE			(BL2_LIMIT - \
- 						PLAT_ARM_MAX_BL2_SIZE)
- #define BL2_BASE				(BL2_LIMIT - \
-@@ -175,14 +183,15 @@
- 
- #define CORSTONE1000_TOS_FW_CONFIG_BASE		(BL31_BASE - \
- 						CORSTONE1000_TOS_FW_CONFIG_SIZE)
--#define CORSTONE1000_TOS_FW_CONFIG_SIZE		UL(0x00002000)  /* 8 KB */
-+#define CORSTONE1000_TOS_FW_CONFIG_SIZE              (SZ_8K)  /* 8 KB */
- #define CORSTONE1000_TOS_FW_CONFIG_LIMIT		BL31_BASE
- 
- #define BL32_BASE				ARM_BL_RAM_BASE
--#define PLAT_ARM_MAX_BL32_SIZE		(CORSTONE1000_TOS_FW_CONFIG_BASE - \
--						BL32_BASE)     /* 688 KB */
--#define BL32_LIMIT				(BL32_BASE + \
--						PLAT_ARM_MAX_BL32_SIZE)
-+#define PLAT_ARM_MAX_BL32_SIZE                 (CORSTONE1000_TOS_FW_CONFIG_BASE - \
-+                                                BL32_BASE)
-+
-+#define BL32_LIMIT                             (BL32_BASE + \
-+                                                PLAT_ARM_MAX_BL32_SIZE)
- 
- /* SPD_spmd settings */
- 
-@@ -191,10 +200,14 @@
- 
- /* NS memory */
- 
--/* The last 3 MB of the SRAM is allocated to the non secure area */
--#define ARM_NS_SHARED_RAM_BASE		(ARM_TRUSTED_SRAM_BASE + \
--						PLAT_ARM_TRUSTED_SRAM_SIZE)
--#define ARM_NS_SHARED_RAM_SIZE		UL(0x00300000)  /* 3 MB */
-+/* The last 512KB of the SRAM is allocated as shared memory */
-+#define ARM_NS_SHARED_RAM_BASE         (ARM_TRUSTED_SRAM_BASE + TOTAL_SRAM_SIZE - \
-+                                        (PLAT_ARM_MAX_BL31_SIZE + \
-+                                         PLAT_ARM_MAX_BL32_SIZE))
-+
-+#define BL33_BASE                      ARM_DRAM1_BASE
-+#define PLAT_ARM_MAX_BL33_SIZE         (12 * SZ_1M) /* 12 MB*/
-+#define BL33_LIMIT                     (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE)
- 
- /* end of the definition of SRAM memory layout */
- 
-@@ -204,7 +217,7 @@
- #define PLAT_ARM_FIP_MAX_SIZE			UL(0x1ff000)  /* 1.996 MB */
- 
- #define PLAT_ARM_NVM_BASE			V2M_FLASH0_BASE
--#define PLAT_ARM_NVM_SIZE			UL(0x02000000)  /* 32 MB */
-+#define PLAT_ARM_NVM_SIZE			(SZ_32M)  /* 32 MB */
- 
- #define PLAT_ARM_FLASH_IMAGE_BASE		PLAT_ARM_FIP_BASE
- #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE		PLAT_ARM_FIP_MAX_SIZE
--- 
-2.33.0
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0003-corstone1000-implement-platform-specific-psci-reset.patch

@@ -1,60 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
-
-From 1b99c6dd614002a79e4dda96d630089775a1d233 Mon Sep 17 00:00:00 2001
-From: Emekcan Aras <Emekcan.Aras@arm.com>
-Date: Wed, 17 Nov 2021 18:45:32 +0000
-Subject: [PATCH] corstone1000: implement platform specific psci reset
-
-This implements platform specific psci reset for the corstone1000.
-Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
----
- .../corstone1000/common/corstone1000_pm.c     | 23 +++++++++++++++++--
- 1 file changed, 21 insertions(+), 2 deletions(-)
-
-diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
-index 12b322e27..e95ab30b7 100644
---- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
-@@ -6,17 +6,36 @@
- 
- #include <lib/psci/psci.h>
- #include <plat/arm/common/plat_arm.h>
--
- /*******************************************************************************
-  * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
-  * platform layer will take care of registering the handlers with PSCI.
-  ******************************************************************************/
-+
-+#define SECURE_WATCHDOG_ADDR_CTRL_REG     0x1A320000
-+#define SECURE_WATCHDOG_ADDR_VAL_REG      0x1A320008
-+#define SECURE_WATCHDOG_MASK_ENABLE       0x01
-+#define SECURE_WATCHDOG_COUNTDOWN_VAL     0x1000
-+
-+static void __dead2 corstone1000_system_reset(void)
-+{
-+
-+    uint32_t volatile * const watchdog_ctrl_reg = (int *) SECURE_WATCHDOG_ADDR_CTRL_REG;
-+    uint32_t volatile * const watchdog_val_reg = (int *) SECURE_WATCHDOG_ADDR_VAL_REG;
-+
-+   *(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL;
-+   *watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE;
-+     while (1){
-+        wfi();
-+    }
-+}
-+
- plat_psci_ops_t plat_arm_psci_pm_ops = {
--	/* dummy struct */
-+    .system_reset = corstone1000_system_reset,
- 	.validate_ns_entrypoint = NULL
- };
- 
- const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
- {
-+    ops = &plat_arm_psci_pm_ops;
- 	return ops;
- }
--- 
-2.25.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-plat-arm-corstone1000-change-base-address-of-FIP-in-the-fl.patch

@@ -1,33 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 5541d466ebf46f0a14fae3effbcc46bcc2dd8efc Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Mon, 20 Sep 2021 06:01:54 +0100
-Subject: [PATCH 1/1] plat/arm: corstone1000: change base address of FIP in the flash
-
-More space in the flash is reserved up front for metadata
-parser and UEFI variables. That requires change in the flash
-base address of where images are present.
-
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- plat/arm/board/corstone1000/common/include/platform_def.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
-index 97d7b2974..079b1c9d4 100644
---- a/plat/arm/board/corstone1000/common/include/platform_def.h
-+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
-@@ -208,7 +208,7 @@
- 
- /* NOR Flash */
- 
--#define PLAT_ARM_FIP_BASE			UL(0x08131000)
-+#define PLAT_ARM_FIP_BASE			UL(0x081EF000)
- #define PLAT_ARM_FIP_MAX_SIZE			UL(0x1ff000)  /* 1.996 MB */
- 
- #define PLAT_ARM_NVM_BASE			V2M_FLASH0_BASE
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0005-plat-arm-corstone1000-identify-which-bank-to-load-fip-from.patch

@@ -1,102 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 03218b5bb3ef32298624a54d1b3b3cf3c8c5d800 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Wed, 27 Oct 2021 16:31:04 +0100
-Subject: [PATCH 1/1] plat/arm: corstone1000: identify which bank to load fip
- from
-
-Secure enclave decide the boot bank based on the firmware update
-state of the system and updated the boot bank information at a given
-location in the flash. In this commit, bl2 reads the givev flash location
-to indentify the bank from which it should load fip from.
-
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../corstone1000/common/corstone1000_plat.c   | 39 +++++++++++++++++++
- .../common/include/platform_def.h             |  6 ++-
- 2 files changed, 43 insertions(+), 2 deletions(-)
-
-diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c
-index 7a38b0b2e..4351d5e9d 100644
---- a/plat/arm/board/corstone1000/common/corstone1000_plat.c
-+++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c
-@@ -11,6 +11,10 @@
- #include <plat/arm/common/plat_arm.h>
- #include <plat/common/platform.h>
- #include <platform_def.h>
-+#include <drivers/generic_delay_timer.h>
-+#include <plat/arm/common/arm_fconf_getter.h>
-+#include <plat/arm/common/arm_fconf_io_storage.h>
-+#include <drivers/io/io_storage.h>
- 
- /*
-  * Table of regions to map using the MMU.
-@@ -26,6 +30,41 @@ const mmap_region_t plat_arm_mmap[] = {
- 	{0}
- };
- 
-+void identify_fip_start_address(void)
-+{
-+	const struct plat_io_policy *policy;
-+	volatile uint32_t *boot_bank_flag = (uint32_t*)(PLAT_ARM_BOOT_BANK_FLAG);
-+
-+	VERBOSE("Boot bank flag = %u.\n\r", *boot_bank_flag);
-+
-+	policy = FCONF_GET_PROPERTY(arm, io_policies, FIP_IMAGE_ID);
-+
-+	assert(policy != NULL);
-+	assert(policy->image_spec != 0UL);
-+
-+	io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec;
-+
-+	if ((*boot_bank_flag) == 0) {
-+		VERBOSE("Booting from bank 0: fip offset = 0x%lx\n\r",
-+						PLAT_ARM_FIP_BASE_BANK0);
-+		spec->offset = PLAT_ARM_FIP_BASE_BANK0;
-+	} else {
-+		VERBOSE("Booting from bank 1: fip offset = 0x%lx\n\r",
-+						PLAT_ARM_FIP_BASE_BANK1);
-+		spec->offset = PLAT_ARM_FIP_BASE_BANK1;
-+	}
-+}
-+
-+void bl2_platform_setup(void)
-+{
-+	arm_bl2_platform_setup();
-+	/*
-+	 * Identify the start address of the FIP by reading the boot
-+	 * index flag from the flash.
-+	 */
-+	identify_fip_start_address();
-+}
-+
- /* corstone1000 only has one always-on power domain and there
-  * is no power control present
-  */
-diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
-index edc90fa72..868e41388 100644
---- a/plat/arm/board/corstone1000/common/include/platform_def.h
-+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
-@@ -213,13 +213,15 @@
- 
- /* NOR Flash */
- 
--#define PLAT_ARM_FIP_BASE			UL(0x081EF000)
-+#define PLAT_ARM_BOOT_BANK_FLAG			UL(0x08002000)
-+#define PLAT_ARM_FIP_BASE_BANK0			UL(0x081EF000)
-+#define PLAT_ARM_FIP_BASE_BANK1			UL(0x0916F000)
- #define PLAT_ARM_FIP_MAX_SIZE			UL(0x1ff000)  /* 1.996 MB */
- 
- #define PLAT_ARM_NVM_BASE			V2M_FLASH0_BASE
- #define PLAT_ARM_NVM_SIZE			(SZ_32M)  /* 32 MB */
- 
--#define PLAT_ARM_FLASH_IMAGE_BASE		PLAT_ARM_FIP_BASE
-+#define PLAT_ARM_FLASH_IMAGE_BASE		PLAT_ARM_FIP_BASE_BANK0
- #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE		PLAT_ARM_FIP_MAX_SIZE
- 
- /*
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/n1sdp/bl_size.patch

@@ -0,0 +1,40 @@
+From 80b1efa92486a87f9e82dbf665ef612291148de8 Mon Sep 17 00:00:00 2001
+From: Adam Johnston <adam.johnston@arm.com>
+Date: Tue, 14 Jun 2022 11:19:30 +0000
+Subject: [PATCH] arm-bsp/trusted-firmware-a: N1SDP trusted boot
+
+Increase max size of BL2 on N1SDP by 4KB to enable trusted boot
+Decrease max size of BL1 on N1SDP by 8KB so BL1/BL2 fits above BL31 progbits
+
+Signed-off-by: Adam Johnston <adam.johnston@arm.com>
+Upstream-Status: Pending [Flagged to upstream]
+
+---
+ plat/arm/board/n1sdp/include/platform_def.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
+index c9b81bafa..7468a31ed 100644
+--- a/plat/arm/board/n1sdp/include/platform_def.h
++++ b/plat/arm/board/n1sdp/include/platform_def.h
+@@ -91,7 +91,7 @@
+  * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+  * plus a little space for growth.
+  */
+-#define PLAT_ARM_MAX_BL1_RW_SIZE	0xE000
++#define PLAT_ARM_MAX_BL1_RW_SIZE	0xC000
+ 
+ /*
+  * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
+@@ -110,7 +110,7 @@
+  * little space for growth.
+  */
+ #if TRUSTED_BOARD_BOOT
+-# define PLAT_ARM_MAX_BL2_SIZE		0x20000
++# define PLAT_ARM_MAX_BL2_SIZE		0x21000
+ #else
+ # define PLAT_ARM_MAX_BL2_SIZE		0x14000
+ #endif
+-- 
+2.35.1
+

meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.6.bbappend

@@ -0,0 +1,3 @@
+# Machine specific TFAs
+
+COMPATIBLE_MACHINE:corstone1000 = "corstone1000"

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc

@@ -11,7 +11,7 @@ SRC_URI:remove = " \
      "  
 
 TFA_DEBUG = "1"
-TFA_UBOOT = "1"
+TFA_UBOOT ?= "1"
 TFA_MBEDTLS = "1"
 TFA_BUILD_TARGET = "bl2 bl31 fip"
 

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-n1sdp.inc

@@ -2,8 +2,29 @@
 
 COMPATIBLE_MACHINE = "n1sdp"
 TFA_PLATFORM       = "n1sdp"
-TFA_BUILD_TARGET   = "bl31 dtbs"
-TFA_INSTALL_TARGET = "bl31 n1sdp-multi-chip n1sdp-single-chip"
+TFA_BUILD_TARGET   = "all fip"
+TFA_INSTALL_TARGET = "bl1 bl2 bl31 n1sdp-multi-chip n1sdp-single-chip n1sdp_fw_config n1sdp_tb_fw_config fip"
 TFA_DEBUG          = "1"
-TFA_MBEDTLS        = "0"
+TFA_MBEDTLS        = "1"
 TFA_UBOOT          = "0"
+TFA_UEFI           = "1"
+
+SRC_URI:remove = " \
+    file://ssl.patch \
+    " 
+
+SRC_URI:append = " \
+    file://bl_size.patch \
+    "
+
+TFA_ROT_KEY= "plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem"
+
+EXTRA_OEMAKE:append = "\
+                    TRUSTED_BOARD_BOOT=1 \
+                    GENERATE_COT=1 \
+                    CREATE_KEYS=1 \
+                    ENABLE_PIE=0 \
+                    ARM_ROTPK_LOCATION="devel_rsa" \
+                    ROT_KEY="${TFA_ROT_KEY}" \
+                    BL33=${RECIPE_SYSROOT}/firmware/uefi.bin \
+                    "

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.6.bbappend

@@ -6,7 +6,6 @@ MACHINE_TFA_REQUIRE:corstone1000 = "trusted-firmware-a-corstone1000.inc"
 MACHINE_TFA_REQUIRE:fvp-base = "trusted-firmware-a-fvp.inc"
 MACHINE_TFA_REQUIRE:fvp-base-arm32 = "trusted-firmware-a-fvp-arm32.inc"
 MACHINE_TFA_REQUIRE:juno = "trusted-firmware-a-juno.inc"
-MACHINE_TFA_REQUIRE:n1sdp = "trusted-firmware-a-n1sdp.inc"
 MACHINE_TFA_REQUIRE:sgi575 = "trusted-firmware-a-sgi575.inc"
 MACHINE_TFA_REQUIRE:tc = "trusted-firmware-a-tc.inc"
 

meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.7.bbappend

@@ -0,0 +1,6 @@
+# Machine specific TFAs
+
+MACHINE_TFA_REQUIRE ?= ""
+MACHINE_TFA_REQUIRE:n1sdp = "trusted-firmware-a-n1sdp.inc"
+
+require ${MACHINE_TFA_REQUIRE}

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0001-corstone1000-disable-secure-debug-temporarily.patch

@@ -1,33 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From beb8a8d92537b9574717f0a9a914642c15b439b1 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Wed, 29 Sep 2021 04:58:59 +0100
-Subject: [PATCH 01/15] corstone1000: disable secure debug temporarily
-
-Until ARM-DS is ready to use psa-adac secure debug protocol,
-disable the secure debug in the platform. At present, the
-secure debug integration is tested with the PyOCD based
-scripts.
-
-Change-Id: I3dd0f20e5714a2db69425607d9404172ce52129e
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- platform/ext/target/arm/corstone1000/config.cmake | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
-index dc12d27f9c..203e6b79a6 100644
---- a/platform/ext/target/arm/corstone1000/config.cmake
-+++ b/platform/ext/target/arm/corstone1000/config.cmake
-@@ -37,5 +37,5 @@ set(OPENAMP_VERSION                     "33037b04e0732e58fc0fa36afc244999ef632e1
- if (${PLATFORM_IS_FVP})
-     set(PLATFORM_PSA_ADAC_SECURE_DEBUG      FALSE        CACHE BOOL      "Whether to use psa-adac secure debug.")
- else()
--    set(PLATFORM_PSA_ADAC_SECURE_DEBUG      TRUE        CACHE BOOL      "Whether to use psa-adac secure debug.")
-+    set(PLATFORM_PSA_ADAC_SECURE_DEBUG      FALSE        CACHE BOOL      "Whether to use psa-adac secure debug.")
- endif()
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0002-corstone1000-provision-firmware-update-metadata-fwu.patch

@@ -1,470 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 8e2b5cee153763dd35bba1bff3568e2e3c6f58d3 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Fri, 1 Oct 2021 14:20:55 +0100
-Subject: [PATCH 02/15] corstone1000: provision firmware update metadata (fwu)
-
-Firmware update metadata region in the flash is provisioned.
-The metadata is provisioned assuming images are present in
-bank-0.
-
-Change-Id: I2a2274505d80528a3a0cc9211c1c6263415015d8
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../arm/corstone1000/bl1/CMakeLists.txt       |   2 +
- .../arm/corstone1000/bl1/bl1_boot_hal.c       |  18 +
- .../corstone1000/fw_update_agent/fwu_agent.c  | 309 ++++++++++++++++++
- .../corstone1000/fw_update_agent/fwu_agent.h  |  31 ++
- .../arm/corstone1000/partition/flash_layout.h |  11 +-
- 5 files changed, 369 insertions(+), 2 deletions(-)
- create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
- create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-
-diff --git a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
-index 0634fed4b8..92a78c1168 100644
---- a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
-@@ -238,6 +238,7 @@ target_sources(bl1_main
-         ../Device/Source/system_core_init.c
-         ../Native_Driver/firewall.c
-         ../Native_Driver/uart_pl011_drv.c
-+        ../fw_update_agent/fwu_agent.c
-         bl1_boot_hal.c
-         bl1_flash_map.c
-         bl1_security_cnt.c
-@@ -267,6 +268,7 @@ target_include_directories(bl1_main
-         ../CMSIS_Driver/Config
-         ../Device/Config
-         ../Native_Driver
-+        ../fw_update_agent
- )
- 
- ############################### SIGNING BL2 image ##################################
-diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-index 3d1e3e72fc..5e5e5c9e68 100644
---- a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-@@ -12,8 +12,12 @@
- #include "Driver_Flash.h"
- #include "flash_layout.h"
- #include "bootutil/fault_injection_hardening.h"
-+#include "bootutil/bootutil_log.h"
- #include "firewall.h"
- #include "mpu_config.h"
-+#include "tfm_plat_otp.h"
-+#include "tfm_plat_provisioning.h"
-+#include "fwu_agent.h"
- 
- #if defined(CRYPTO_HW_ACCELERATOR) || \
-     defined(CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING)
-@@ -595,6 +599,20 @@ int32_t boot_platform_init(void)
-     }
- #endif /* CRYPTO_HW_ACCELERATOR */
- 
-+    result = tfm_plat_otp_init();
-+    if (result != TFM_PLAT_ERR_SUCCESS) {
-+        BOOT_LOG_ERR("OTP system initialization failed");
-+        FIH_PANIC;
-+    }
-+
-+    if (tfm_plat_provisioning_is_required()) {
-+        result = fwu_metadata_provision();
-+        if (result != FWU_AGENT_SUCCESS) {
-+            BOOT_LOG_ERR("Provisioning FWU Metadata failed");
-+            FIH_PANIC;
-+        }
-+    }
-+
-     return 0;
- }
- 
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-new file mode 100644
-index 0000000000..b9c507e4ef
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-@@ -0,0 +1,309 @@
-+/*
-+ * Copyright (c) 2021, Arm Limited. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+
-+#include <stdint.h>
-+#include <string.h>
-+#include "fwu_agent.h"
-+#include "Driver_Flash.h"
-+#include "flash_layout.h"
-+#include "fip_parser/external/uuid.h"
-+
-+/* Properties of image in a bank */
-+struct fwu_image_properties {
-+
-+        /* UUID of the image in this bank */
-+        uuid_t img_uuid;
-+
-+        /* [0]: bit describing the image acceptance status –
-+         *      1 means the image is accepted
-+         * [31:1]: MBZ
-+         */
-+        uint32_t accepted;
-+
-+        /* NOTE: using the reserved field */
-+        /* image version */
-+        uint32_t version;
-+
-+} __packed;
-+
-+/* Image entry information */
-+struct fwu_image_entry {
-+
-+        /* UUID identifying the image type */
-+        uuid_t img_type_uuid;
-+
-+        /* UUID of the storage volume where the image is located */
-+        uuid_t location_uuid;
-+
-+        /* Properties of images with img_type_uuid in the different FW banks */
-+        struct fwu_image_properties img_props[NR_OF_FW_BANKS];
-+
-+} __packed;
-+
-+struct fwu_metadata {
-+
-+        /* Metadata CRC value */
-+        uint32_t crc_32;
-+
-+        /* Metadata version */
-+        uint32_t version;
-+
-+        /* Bank index with which device boots */
-+        uint32_t active_index;
-+
-+        /* Previous bank index with which device booted successfully */
-+        uint32_t previous_active_index;
-+
-+        /* Image entry information */
-+        struct fwu_image_entry img_entry[NR_OF_IMAGES_IN_FW_BANK];
-+
-+} __packed;
-+
-+/* This is Corstone1000 speific metadata for OTA.
-+ * Private metadata is written at next sector following
-+ * FWU METADATA location */
-+struct fwu_private_metadata {
-+
-+       /* boot_index: the bank from which system is booted from */
-+       uint32_t boot_index;
-+
-+} __packed;
-+
-+struct fwu_metadata _metadata;
-+int is_initialized = 0;
-+
-+#define IMAGE_ACCEPTED          (1)
-+#define IMAGE_NOT_ACCEPTED      (0)
-+#define BANK_0                  (0)
-+#define BANK_1                  (1)
-+#define IMAGE_0                 (0)
-+#define IMAGE_1                 (1)
-+#define IMAGE_2                 (2)
-+#define IMAGE_3                 (3)
-+#define INVALID_VERSION         (0xffffffff)
-+
-+#ifndef FWU_METADATA_FLASH_DEV
-+    #ifndef FLASH_DEV_NAME
-+    #error "FWU_METADATA_FLASH_DEV or FLASH_DEV_NAME must be defined in flash_layout.h"
-+    #else
-+    #define FWU_METADATA_FLASH_DEV FLASH_DEV_NAME
-+    #endif
-+#endif
-+
-+/* Import the CMSIS flash device driver */
-+extern ARM_DRIVER_FLASH FWU_METADATA_FLASH_DEV;
-+
-+static enum fwu_agent_error_t private_metadata_read(
-+        struct fwu_private_metadata* p_metadata)
-+{
-+    int ret;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    if (!p_metadata) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    ret = FWU_METADATA_FLASH_DEV.ReadData(FWU_PRIVATE_AREA_OFFSET, p_metadata,
-+                                          sizeof(struct fwu_private_metadata));
-+    if (ret != ARM_DRIVER_OK) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    FWU_LOG_MSG("%s: success: boot_index = %u\n\r", __func__,
-+                        p_metadata->boot_index);
-+
-+    return FWU_AGENT_SUCCESS;
-+}
-+
-+static enum fwu_agent_error_t private_metadata_write(
-+        struct fwu_private_metadata* p_metadata)
-+{
-+    int ret;
-+
-+    FWU_LOG_MSG("%s: enter: boot_index = %u\n\r", __func__,
-+                        p_metadata->boot_index);
-+
-+    if (!p_metadata) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    ret = FWU_METADATA_FLASH_DEV.EraseSector(FWU_PRIVATE_AREA_OFFSET);
-+    if (ret != ARM_DRIVER_OK) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    ret = FWU_METADATA_FLASH_DEV.ProgramData(FWU_PRIVATE_AREA_OFFSET,
-+                                p_metadata, sizeof(struct fwu_private_metadata));
-+    if (ret != ARM_DRIVER_OK) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    FWU_LOG_MSG("%s: success\n\r", __func__);
-+    return FWU_AGENT_SUCCESS;
-+}
-+
-+static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
-+{
-+    int ret;
-+
-+    FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
-+                  FWU_METADATA_REPLICA_1_OFFSET, sizeof(struct fwu_metadata));
-+
-+    if (!p_metadata) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    ret = FWU_METADATA_FLASH_DEV.ReadData(FWU_METADATA_REPLICA_1_OFFSET,
-+                                p_metadata, sizeof(struct fwu_metadata));
-+    if (ret != ARM_DRIVER_OK) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    FWU_LOG_MSG("%s: success: active = %u, previous = %d\n\r", __func__,
-+                  p_metadata->active_index, p_metadata->previous_active_index);
-+
-+    return FWU_AGENT_SUCCESS;
-+}
-+
-+static enum fwu_agent_error_t metadata_write(
-+                        struct fwu_metadata *p_metadata)
-+{
-+    int ret;
-+
-+    FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
-+                  FWU_METADATA_REPLICA_1_OFFSET, sizeof(struct fwu_metadata));
-+
-+    if (!p_metadata) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    ret = FWU_METADATA_FLASH_DEV.EraseSector(FWU_METADATA_REPLICA_1_OFFSET);
-+    if (ret != ARM_DRIVER_OK) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    ret = FWU_METADATA_FLASH_DEV.ProgramData(FWU_METADATA_REPLICA_1_OFFSET,
-+                                p_metadata, sizeof(struct fwu_metadata));
-+    if (ret != ARM_DRIVER_OK) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    FWU_LOG_MSG("%s: success: active = %u, previous = %d\n\r", __func__,
-+                  p_metadata->active_index, p_metadata->previous_active_index);
-+    return FWU_AGENT_SUCCESS;
-+}
-+
-+enum fwu_agent_error_t fwu_metadata_init(void)
-+{
-+    enum fwu_agent_error_t ret;
-+    ARM_FLASH_INFO* flash_info;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    if (is_initialized) {
-+        return FWU_AGENT_SUCCESS;
-+    }
-+
-+    /* Code assumes everything fits into a sector */
-+    if (sizeof(struct fwu_metadata) > FWU_METADATA_FLASH_SECTOR_SIZE) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    if (sizeof(struct fwu_private_metadata) > FWU_METADATA_FLASH_SECTOR_SIZE) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    ret = FWU_METADATA_FLASH_DEV.Initialize(NULL);
-+    if (ret != ARM_DRIVER_OK) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    flash_info = FWU_METADATA_FLASH_DEV.GetInfo();
-+    if (flash_info->program_unit != 1) {
-+        FWU_METADATA_FLASH_DEV.Uninitialize();
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    is_initialized = 1;
-+
-+    FWU_LOG_MSG("%s: is_initialized = %d\n\r", __func__, is_initialized);
-+
-+    return FWU_AGENT_SUCCESS;
-+}
-+
-+enum fwu_agent_error_t fwu_metadata_provision(void)
-+{
-+    enum fwu_agent_error_t ret;
-+    struct fwu_private_metadata priv_metadata;
-+    uint32_t image_version = 0;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    ret = fwu_metadata_init();
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    /* Provision FWU Agent Metadata */
-+
-+    memset(&_metadata, 0, sizeof(struct fwu_metadata));
-+
-+    _metadata.version = 1;
-+    _metadata.active_index = 0;
-+    _metadata.previous_active_index = 1;
-+
-+    /* bank 0 is the place where images are located at the
-+     * start of device lifecycle */
-+
-+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
-+
-+        _metadata.img_entry[i].img_props[BANK_0].accepted = IMAGE_ACCEPTED;
-+        _metadata.img_entry[i].img_props[BANK_0].version = image_version;
-+
-+        _metadata.img_entry[i].img_props[BANK_1].accepted = IMAGE_NOT_ACCEPTED;
-+        _metadata.img_entry[i].img_props[BANK_1].version = INVALID_VERSION;
-+    }
-+
-+    ret = metadata_write(&_metadata);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    memset(&_metadata, 0, sizeof(struct fwu_metadata));
-+    ret = metadata_read(&_metadata);
-+    if (ret) {
-+        return ret;
-+    }
-+    FWU_LOG_MSG("%s: provisioned values: active = %u, previous = %d\n\r",
-+             __func__, _metadata.active_index, _metadata.previous_active_index);
-+
-+
-+    /* Provision Private metadata for update agent which is shared
-+       beween BL1 and tf-m of secure enclave */
-+
-+    memset(&priv_metadata, 0, sizeof(struct fwu_private_metadata));
-+
-+    priv_metadata.boot_index = BANK_0;
-+
-+    ret = private_metadata_write(&priv_metadata);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    memset(&priv_metadata, 0, sizeof(struct fwu_private_metadata));
-+    ret = private_metadata_read(&priv_metadata);
-+    if (ret) {
-+        return ret;
-+    }
-+    FWU_LOG_MSG("%s: provisioned values: boot_index = %u\n\r", __func__,
-+                        priv_metadata.boot_index);
-+
-+    FWU_LOG_MSG("%s: FWU METADATA PROVISIONED.\n\r", __func__);
-+    return FWU_AGENT_SUCCESS;
-+}
-+
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-new file mode 100644
-index 0000000000..449d354100
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-@@ -0,0 +1,31 @@
-+/*
-+ * Copyright (c) 2021, Arm Limited. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+
-+#ifndef FWU_AGENT_H
-+#define FWU_AGENT_H
-+
-+/* Set 1 to enable debug messages */
-+#define ENABLE_DEBUG_LOGS         1
-+
-+#if (ENABLE_DEBUG_LOGS == 1)
-+    #include <stdio.h>
-+    #define FWU_LOG_MSG(f_, ...) printf((f_), ##__VA_ARGS__)
-+#else
-+    #define FWU_LOG_MSG(f_, ...)
-+#endif
-+
-+enum fwu_agent_error_t {
-+        FWU_AGENT_SUCCESS = 0,
-+        FWU_AGENT_ERROR = (-1)
-+};
-+
-+enum fwu_agent_error_t fwu_metadata_provision(void);
-+enum fwu_agent_error_t fwu_metadata_init(void);
-+
-+
-+#endif /* FWU_AGENT_H */
-+
-diff --git a/platform/ext/target/arm/corstone1000/partition/flash_layout.h b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
-index f120a7b8ee..47445d9d29 100644
---- a/platform/ext/target/arm/corstone1000/partition/flash_layout.h
-+++ b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
-@@ -117,11 +117,18 @@
- 
- 
- /* 1MB: space in flash to store metadata and uefi variables */
-+#define FWU_METADATA_FLASH_DEV          (FLASH_DEV_NAME)
-+#define FWU_METADATA_FLASH_SECTOR_SIZE  (FLASH_SECTOR_SIZE)
-+
- #define FWU_METADATA_PARTITION_OFFSET   (FLASH_BASE_OFFSET)
--#define FWU_METADATA_AREA_SIZE          (FLASH_SECTOR_SIZE)     /* 4KB */
-+#define FWU_METADATA_AREA_SIZE          (FWU_METADATA_FLASH_SECTOR_SIZE)
- #define FWU_METADATA_REPLICA_1_OFFSET   (FLASH_BASE_OFFSET)
- #define FWU_METADATA_REPLICA_2_OFFSET   (FWU_METADATA_REPLICA_1_OFFSET + \
-                                          FWU_METADATA_AREA_SIZE)
-+#define FWU_PRIVATE_AREA_SIZE           (FLASH_SECTOR_SIZE)
-+#define FWU_PRIVATE_AREA_OFFSET         (FWU_METADATA_REPLICA_2_OFFSET + \
-+                                         FWU_METADATA_AREA_SIZE)
-+
- #define NR_OF_FW_BANKS                  (2)
- #define NR_OF_IMAGES_IN_FW_BANK         (4) /* Secure Enclave: BL2 and TF-M \
-                                              * Host: FIP and Kernel image
-@@ -217,7 +224,7 @@
- /*** ITS, PS and NV Counters ***/
- /*******************************/
- 
--#define FLASH_ITS_AREA_OFFSET           (0)
-+#define FLASH_ITS_AREA_OFFSET           (0x10000)  /* 64 KB */
- #define FLASH_ITS_AREA_SIZE             (4 * FLASH_SECTOR_SIZE)  /* 4 KiB */
- 
- #define FLASH_PS_AREA_OFFSET            (FLASH_ITS_AREA_OFFSET + \
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0003-corstone1000-parse-the-uefi-firmware-update-capsule.patch

@@ -1,243 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 22aeb7708773c2cc9df2cc501d411b94c09fd0bd Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Sat, 2 Oct 2021 12:31:07 +0100
-Subject: [PATCH 03/15] corstone1000: parse the uefi firmware update capsule
-
-The Host (OTA Client) sends a capsule containing fwu images
-to secure enclave. The commit parses the capsule to retrieve
-images.
-
-Change-Id: Icf097cf88911a568bdc9eba8c98e2da93994f0bc
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../target/arm/corstone1000/CMakeLists.txt    |   2 +
- .../fw_update_agent/uefi_capsule_parser.c     | 155 ++++++++++++++++++
- .../fw_update_agent/uefi_capsule_parser.h     |  31 ++++
- 3 files changed, 188 insertions(+)
- create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c
- create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.h
-
-diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-index 16d256bc34..f34035d361 100644
---- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-@@ -51,6 +51,7 @@ target_include_directories(platform_s
-         services/include
-     INTERFACE
-         cc312
-+        fw_update_agent
- )
- 
- target_sources(platform_s
-@@ -67,6 +68,7 @@ target_sources(platform_s
-         tfm_hal_platform.c
-         ${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_nvic.c
-         $<$<BOOL:TFM_PARTITION_PLATFORM>:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c>
-+        fw_update_agent/uefi_capsule_parser.c
- )
- 
- if (PLATFORM_IS_FVP)
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c
-new file mode 100644
-index 0000000000..32133b2eb2
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c
-@@ -0,0 +1,155 @@
-+/*
-+ * Copyright (c) 2021, Arm Limited. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+
-+#include "uefi_capsule_parser.h"
-+#include "fwu_agent.h"
-+#include <string.h>
-+
-+/*
-+Update Capsule Structure (UEFI spec 2.9 1004)
-+    EFI_CAPSULE_HEADER
-+    ...
-+    ...
-+    ...
-+    CAPSULE_BODY
-+        efi_firmware_management_capsule_header
-+        Optional Driver 1 (item_offset[0])
-+        Optional Driver 2 (item_offset[1])
-+            Payload 1 (item_offset[2])
-+                efi_firmware_management_capsule_iamge_header
-+                Binary Update image (Image_length == update_image_size)
-+                Vendor Code bytes  (Data lenght == update_vendorcode_size)
-+            Payload 2 (item_offset[3])
-+            ...
-+            ...
-+            Payload n (item_offset[embedded_driver_count + payload_item_count -1])
-+*/
-+
-+typedef struct {
-+    struct efi_guid         capsule_guid;
-+    uint32_t                header_size;
-+    uint32_t                flags;
-+    uint32_t                capsule_image_size;
-+} efi_capsule_header_t;
-+
-+typedef struct {
-+    uint32_t                version;
-+    uint16_t                embedded_driver_count;
-+    uint16_t                payload_item_count;
-+    uint64_t                item_offset_list[];
-+} efi_firmware_management_capsule_header_t;
-+
-+typedef struct {
-+    uint32_t                version;
-+    struct efi_guid         update_image_type_id;
-+    uint8_t                 update_image_index;
-+    uint8_t                 reserved_bytes[3];
-+    uint32_t                update_image_size;
-+    uint32_t                update_vendorcode_size;
-+    uint64_t                update_hardware_instance; //introduced in v2
-+    uint64_t                image_capsule_support; //introduced in v3
-+} efi_firmware_management_capsule_image_header_t;
-+
-+#define ANYSIZE_ARRAY 0
-+
-+typedef struct {
-+    uint32_t                dwLength;
-+    uint16_t                wRevision;
-+    uint16_t                wCertificateType;
-+    uint8_t                 bCertificate[ANYSIZE_ARRAY];
-+} WIN_CERTIFICATE;
-+
-+typedef struct {
-+    WIN_CERTIFICATE         hdr;
-+    struct efi_guid         cert_type;
-+    uint8_t                 cert_data[ANYSIZE_ARRAY];
-+} win_certificate_uefi_guid_t;
-+
-+typedef struct {
-+    uint64_t                    monotonic_count;
-+    win_certificate_uefi_guid_t   auth_info;
-+} efi_firmware_image_authentication_t;
-+
-+
-+enum uefi_capsule_error_t uefi_capsule_retrieve_images(void* capsule_ptr,
-+        capsule_image_info_t* images_info)
-+{
-+    char *ptr = (char*)capsule_ptr;
-+    efi_capsule_header_t* capsule_header;
-+    efi_firmware_management_capsule_header_t* payload_header;
-+    efi_firmware_management_capsule_image_header_t* image_header;
-+    efi_firmware_image_authentication_t* image_auth;
-+    uint32_t total_size;
-+    uint32_t image_count;
-+    uint32_t auth_size;
-+
-+    FWU_LOG_MSG("%s: enter, capsule ptr = 0x%p\n\r", __func__, capsule_ptr);
-+
-+    if (!capsule_ptr) {
-+        return UEFI_CAPSULE_PARSER_ERROR;
-+    }
-+
-+    capsule_header = (efi_capsule_header_t*)ptr;
-+    ptr += sizeof(efi_capsule_header_t) + sizeof(uint32_t);
-+    payload_header = (efi_firmware_management_capsule_header_t*)ptr;
-+
-+    total_size = capsule_header->capsule_image_size;
-+    image_count = payload_header->payload_item_count;
-+    images_info->nr_image = image_count;
-+
-+    FWU_LOG_MSG("%s: capsule size = %u, image count = %u\n\r", __func__,
-+                        total_size, image_count);
-+
-+    if ((image_count == 0) || (image_count > NR_OF_IMAGES_IN_FW_BANK)) {
-+        return UEFI_CAPSULE_PARSER_ERROR;
-+    }
-+
-+    for (int i = 0; i < image_count; i++) {
-+
-+        image_header = (efi_firmware_management_capsule_image_header_t*)(ptr +
-+                                payload_header->item_offset_list[i]);
-+
-+        images_info->size[i] = image_header->update_image_size;
-+        images_info->version[i] = image_header->version;
-+        FWU_LOG_MSG("%s: image %i version = %u\n\r", __func__, i,
-+                                images_info->version[i]);
-+
-+        image_auth = (efi_firmware_image_authentication_t*)(
-+                        (char*)image_header +
-+                        sizeof (efi_firmware_management_capsule_image_header_t)
-+                     );
-+        auth_size = sizeof(uint64_t) /* monotonic_count */  +
-+                    image_auth->auth_info.hdr.dwLength /* WIN_CERTIFICATE + cert_data */ +
-+                    sizeof(struct efi_guid) /* cert_type */;
-+
-+        FWU_LOG_MSG("%s: auth size = %u\n\r", __func__, auth_size);
-+
-+        images_info->size[i] -= auth_size;
-+
-+        images_info->image[i] = (
-+                (char*)image_header +
-+                sizeof(efi_firmware_management_capsule_image_header_t) +
-+                auth_size);
-+
-+        memcpy(&images_info->guid[i], &(image_header->update_image_type_id),
-+                                                        sizeof(struct efi_guid));
-+
-+        FWU_LOG_MSG("%s: image %d at %p, size=%u\n\r", __func__, i,
-+                        images_info->image[i], images_info->size[i]);
-+
-+        if ((payload_header->item_offset_list[i] +
-+             sizeof(efi_firmware_management_capsule_image_header_t) +
-+             image_header->update_image_size) > total_size)
-+        {
-+            return UEFI_CAPSULE_PARSER_ERROR;
-+        }
-+
-+    }
-+
-+    FWU_LOG_MSG("%s: exit\n\r", __func__);
-+    return UEFI_CAPSULE_PARSER_SUCCESS;
-+}
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.h b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.h
-new file mode 100644
-index 0000000000..a890a709e9
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.h
-@@ -0,0 +1,31 @@
-+/*
-+ * Copyright (c) 2021, Arm Limited. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+
-+#ifndef UEFI_CAPSULE_PARSER_H
-+#define UEFI_CAPSULE_PARSER_H
-+
-+#include <stdint.h>
-+#include "fip_parser/external/uuid.h"
-+#include "flash_layout.h"
-+
-+enum uefi_capsule_error_t {
-+    UEFI_CAPSULE_PARSER_SUCCESS = 0,
-+    UEFI_CAPSULE_PARSER_ERROR = (-1)
-+};
-+
-+typedef struct capsule_image_info {
-+    uint32_t nr_image;
-+    void *image[NR_OF_IMAGES_IN_FW_BANK];
-+    struct efi_guid guid[NR_OF_IMAGES_IN_FW_BANK];
-+    uint32_t size[NR_OF_IMAGES_IN_FW_BANK];
-+    uint32_t version[NR_OF_IMAGES_IN_FW_BANK];
-+} capsule_image_info_t;
-+
-+enum uefi_capsule_error_t uefi_capsule_retrieve_images(void* capsule_ptr,
-+        capsule_image_info_t* images_info);
-+
-+#endif /* UEFI_CAPSULE_PARSER_H */
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0004-corstone1000-add-firmware-update-fwu-agent-into-TF-M.patch

@@ -1,106 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From c1ae09844562f33ddf07b8f5ca6b7d98ccbaf24c Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Sat, 2 Oct 2021 18:48:31 +0100
-Subject: [PATCH 04/15] corstone1000: add firmware update (fwu) agent into TF-M
-
-The commit links the firmware-update (fwu) agent into the
-TF-M.
-
-The commit also configures the secure enclave firewall to
-access DRAM, where uefi capsule will be written by ota client
-for fwu agent to parse.
-
-Change-Id: I89617a9b515d6aa5cc4f383b5a75a4beef73cc33
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../ext/target/arm/corstone1000/CMakeLists.txt  |  1 +
- .../Device/Include/platform_base_address.h      |  1 +
- .../target/arm/corstone1000/bl1/bl1_boot_hal.c  | 17 +++++++++++++++++
- .../target/arm/corstone1000/tfm_hal_platform.c  |  5 +++++
- 4 files changed, 24 insertions(+)
-
-diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-index f34035d361..81623f16ff 100644
---- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-@@ -69,6 +69,7 @@ target_sources(platform_s
-         ${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_nvic.c
-         $<$<BOOL:TFM_PARTITION_PLATFORM>:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c>
-         fw_update_agent/uefi_capsule_parser.c
-+        fw_update_agent/fwu_agent.c
- )
- 
- if (PLATFORM_IS_FVP)
-diff --git a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
-index 5f37caa09c..e86ddcfbc9 100644
---- a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
-+++ b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
-@@ -75,5 +75,6 @@
- #define CORSTONE1000_HOST_FPGA_SCC_REGISTERS       (0x80000000U) /* FPGA SCC Registers                */
- #define CORSTONE1000_HOST_SE_SECURE_FLASH_BASE_FVP (0x80010000U) /* SE Flash                          */
- #define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE   (0x80050000U) /* AXI QSPI Controller               */
-+#define CORSTONE1000_HOST_DRAM_UEFI_CAPSULE        (0xA0000000U) /* 1.5 GB DDR                        */
- 
- #endif  /* __PLATFORM_BASE_ADDRESS_H__ */
-diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-index 5e5e5c9e68..54042495d7 100644
---- a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-@@ -47,6 +47,7 @@ REGION_DECLARE(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)[];
- #define HOST_AXI_QSPI_CTRL_REG_BASE_SE_SECURE_FLASH    0x60010000
- 
- #define HOST_DRAM_BASE                  0x80000000
-+#define HOST_DRAM_UEFI_CAPSULE          0x80000000
- 
- #define SE_MID                          0
- 
-@@ -249,6 +250,22 @@ static void setup_se_firewall(void)
-     fc_enable_mpe(RGN_MPE0);
-     fc_enable_regions();
- 
-+    /* DDR/DRAM/UEFI_CAPSULE: 32MB */
-+    fc_select_region(6);
-+    fc_disable_regions();
-+    fc_disable_mpe(RGN_MPE0);
-+    fc_prog_rgn(RGN_SIZE_32MB, CORSTONE1000_HOST_DRAM_UEFI_CAPSULE);
-+    fc_prog_rgn_upper_addr(HOST_DRAM_UEFI_CAPSULE);
-+    fc_enable_addr_trans();
-+    fc_init_mpl(RGN_MPE0);
-+    mpl_rights = (RGN_MPL_SECURE_READ_MASK |
-+                  RGN_MPL_SECURE_WRITE_MASK);
-+
-+    fc_enable_mpl(RGN_MPE0, mpl_rights);
-+    fc_prog_mid(RGN_MPE0, SE_MID);
-+    fc_enable_mpe(RGN_MPE0);
-+    fc_enable_regions();
-+
- 
-     fc_pe_enable();
- }
-diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
-index 71472ea08c..0072b5b928 100644
---- a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
-+++ b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
-@@ -8,11 +8,16 @@
- #include "cmsis.h"
- #include "tfm_hal_platform.h"
- #include "uart_stdout.h"
-+#include "fwu_agent.h"
- 
- enum tfm_hal_status_t tfm_hal_platform_init(void)
- {
-     __enable_irq();
-     stdio_init();
- 
-+    if (fwu_metadata_init()) {
-+        return TFM_HAL_ERROR_GENERIC;
-+    }
-+
-     return TFM_HAL_SUCCESS;
- }
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0005-corstone1000-implement-corstone1000_fwu_flash_images.patch

@@ -1,437 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 593087034655eca09ff8e80e67c3252399fa0ce7 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Sat, 2 Oct 2021 18:51:21 +0100
-Subject: [PATCH 05/15] corstone1000: implement corstone1000_fwu_flash_images
-
-The API, corstone1000_fwu_flash_images, is an non-secure host
-inteface (firmware update client) to send new updatable images,
-and to start the update process. The implementation of the API does
-version verfification before coping the images to the update bank.
-After copy, the platform is reset.
-
-On successful call to the API, the firmware update state of the
-system changes from regular state to trial state. On reset,
-the system is expected but not guaranteed to boot from the
-update/trial bank.
-
-Change-Id: I6c278145ec95ec522f7e59d00e1640a039c9778e
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../corstone1000/CMSIS_Driver/Driver_Flash.c  |  11 +
- .../corstone1000/Native_Driver/flash_common.h |   1 +
- .../corstone1000/fw_update_agent/fwu_agent.c  | 225 ++++++++++++++++++
- .../corstone1000/fw_update_agent/fwu_agent.h  |  11 +
- .../include/corstone1000_ioctl_requests.h     |  32 +++
- .../services/src/tfm_platform_system.c        |  24 +-
- 6 files changed, 300 insertions(+), 4 deletions(-)
- create mode 100644 platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h
-
-diff --git a/platform/ext/target/arm/corstone1000/CMSIS_Driver/Driver_Flash.c b/platform/ext/target/arm/corstone1000/CMSIS_Driver/Driver_Flash.c
-index 10952d4cbe..01c535e094 100644
---- a/platform/ext/target/arm/corstone1000/CMSIS_Driver/Driver_Flash.c
-+++ b/platform/ext/target/arm/corstone1000/CMSIS_Driver/Driver_Flash.c
-@@ -175,6 +175,11 @@ int32_t Select_XIP_Mode_For_Shared_Flash(void)
-     return ARM_DRIVER_OK;
- }
- 
-+int32_t Select_Write_Mode_For_Shared_Flash(void)
-+{
-+    return ARM_DRIVER_OK;
-+}
-+
- static int32_t STRATAFLASHJ3_Initialize(ARM_Flash_SignalEvent_t cb_event)
- {
-     ARG_UNUSED(cb_event);
-@@ -392,6 +397,12 @@ int32_t Select_XIP_Mode_For_Shared_Flash(void)
-     return ARM_DRIVER_OK;
- }
- 
-+int32_t Select_Write_Mode_For_Shared_Flash(void)
-+{
-+    select_qspi_mode(&AXI_QSPI_DEV_S);
-+    return ARM_DRIVER_OK;
-+}
-+
- static ARM_FLASH_CAPABILITIES N25Q256A_Driver_GetCapabilities(void)
- {
-     return N25Q256ADriverCapabilities;
-diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/flash_common.h b/platform/ext/target/arm/corstone1000/Native_Driver/flash_common.h
-index 76d5303f83..2e91fb2db4 100644
---- a/platform/ext/target/arm/corstone1000/Native_Driver/flash_common.h
-+++ b/platform/ext/target/arm/corstone1000/Native_Driver/flash_common.h
-@@ -18,6 +18,7 @@ extern "C"
- #include "Driver_Common.h"
- 
- int32_t Select_XIP_Mode_For_Shared_Flash(void);
-+int32_t Select_Write_Mode_For_Shared_Flash(void);
- 
- #ifdef  __cplusplus
- }
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-index b9c507e4ef..7fa64db0f7 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-@@ -11,6 +11,10 @@
- #include "Driver_Flash.h"
- #include "flash_layout.h"
- #include "fip_parser/external/uuid.h"
-+#include "region_defs.h"
-+#include "uefi_capsule_parser.h"
-+#include "flash_common.h"
-+#include "platform_base_address.h"
- 
- /* Properties of image in a bank */
- struct fwu_image_properties {
-@@ -73,9 +77,27 @@ struct fwu_private_metadata {
- 
- } __packed;
- 
-+
- struct fwu_metadata _metadata;
-+
- int is_initialized = 0;
- 
-+capsule_image_info_t capsule_info;
-+
-+enum fwu_agent_state_t {
-+    FWU_AGENT_STATE_UNKNOWN = -1,
-+    FWU_AGENT_STATE_REGULAR = 0,
-+    FWU_AGENT_STATE_TRIAL,
-+};
-+
-+struct efi_guid full_capsule_image_guid = {
-+    .time_low = 0x3a770ddc,
-+    .time_mid = 0x409b,
-+    .time_hi_and_version = 0x48b2,
-+    .clock_seq_and_node = {0x81, 0x41, 0x93, 0xb7, 0xc6, 0x0b, 0x20, 0x9e}
-+};
-+
-+
- #define IMAGE_ACCEPTED          (1)
- #define IMAGE_NOT_ACCEPTED      (0)
- #define BANK_0                  (0)
-@@ -84,8 +106,12 @@ int is_initialized = 0;
- #define IMAGE_1                 (1)
- #define IMAGE_2                 (2)
- #define IMAGE_3                 (3)
-+#define IMAGE_END               (IMAGE_3)
-+#define IMAGE_ALL               (IMAGE_END + 1)
-+#define IMAGE_NOT_RECOGNIZED    (-1)
- #define INVALID_VERSION         (0xffffffff)
- 
-+
- #ifndef FWU_METADATA_FLASH_DEV
-     #ifndef FLASH_DEV_NAME
-     #error "FWU_METADATA_FLASH_DEV or FLASH_DEV_NAME must be defined in flash_layout.h"
-@@ -307,3 +333,202 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
-     return FWU_AGENT_SUCCESS;
- }
- 
-+static enum fwu_agent_state_t get_fwu_agent_state(
-+        struct fwu_metadata *metadata_ptr,
-+        struct fwu_private_metadata *priv_metadata_ptr)
-+{
-+    uint32_t boot_index;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    boot_index = priv_metadata_ptr->boot_index;
-+
-+    if (boot_index != metadata_ptr->active_index) {
-+        return FWU_AGENT_STATE_TRIAL;
-+    }
-+
-+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
-+        if ((metadata_ptr->img_entry[i].img_props[boot_index].accepted)
-+                == (IMAGE_NOT_ACCEPTED)) {
-+            return FWU_AGENT_STATE_TRIAL;
-+        }
-+    }
-+
-+    FWU_LOG_MSG("%s: exit: FWU_AGENT_STATE_REGULAR\n\r", __func__);
-+    return FWU_AGENT_STATE_REGULAR;
-+}
-+
-+static int get_image_info_in_bank(struct efi_guid* guid, uint32_t* image_bank_offset)
-+{
-+    if ((memcmp(guid, &full_capsule_image_guid, sizeof(struct efi_guid))) == 0) {
-+        *image_bank_offset = 0;
-+        return IMAGE_ALL;
-+    }
-+
-+    return IMAGE_NOT_RECOGNIZED;
-+}
-+
-+static enum fwu_agent_error_t erase_bank(uint32_t bank_offset)
-+{
-+    int ret;
-+    uint32_t sectors;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    if ((bank_offset % FWU_METADATA_FLASH_SECTOR_SIZE) != 0) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    if ((BANK_PARTITION_SIZE % FWU_METADATA_FLASH_SECTOR_SIZE) != 0) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    sectors = BANK_PARTITION_SIZE / FWU_METADATA_FLASH_SECTOR_SIZE;
-+
-+    FWU_LOG_MSG("%s: erasing sectors = %u, from offset = %u\n\r", __func__,
-+                     sectors, bank_offset);
-+
-+    for (int i = 0; i < sectors; i++) {
-+        ret = FWU_METADATA_FLASH_DEV.EraseSector(
-+                bank_offset + (i * FWU_METADATA_FLASH_SECTOR_SIZE));
-+        if (ret != ARM_DRIVER_OK) {
-+            return FWU_AGENT_ERROR;
-+        }
-+    }
-+
-+    FWU_LOG_MSG("%s: exit\n\r", __func__);
-+    return FWU_AGENT_SUCCESS;
-+}
-+
-+
-+static enum fwu_agent_error_t flash_full_capsule(
-+        struct fwu_metadata* metadata, void* images, uint32_t size,
-+        uint32_t version)
-+{
-+    int ret;
-+    uint32_t active_index = metadata->active_index;
-+    uint32_t bank_offset;
-+    uint32_t previous_active_index;
-+
-+    FWU_LOG_MSG("%s: enter: image = 0x%p, size = %u, version = %u\n\r"
-+                , __func__, images, size, version);
-+
-+    if (!metadata || !images) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    if (size > BANK_PARTITION_SIZE) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    if (version <=
-+            (metadata->img_entry[IMAGE_0].img_props[active_index].version)) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    if (active_index == BANK_0) {
-+        previous_active_index = BANK_1;
-+        bank_offset = BANK_1_PARTITION_OFFSET;
-+    } else if (active_index == BANK_1) {
-+        previous_active_index = BANK_0;
-+        bank_offset = BANK_0_PARTITION_OFFSET;
-+    } else {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    if (erase_bank(bank_offset)) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    FWU_LOG_MSG("%s: writing capsule to the flash at offset = %u...\n\r",
-+                      __func__, bank_offset);
-+    ret = FWU_METADATA_FLASH_DEV.ProgramData(bank_offset, images, size);
-+    if (ret != ARM_DRIVER_OK) {
-+        return FWU_AGENT_ERROR;
-+    }
-+    FWU_LOG_MSG("%s: images are written to bank offset = %u\n\r", __func__,
-+                     bank_offset);
-+
-+    /* Change system state to trial bank state */
-+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
-+        metadata->img_entry[i].img_props[previous_active_index].accepted =
-+                                                        IMAGE_NOT_ACCEPTED;
-+        metadata->img_entry[i].img_props[previous_active_index].version = version;
-+    }
-+    metadata->active_index = previous_active_index;
-+    metadata->previous_active_index = active_index;
-+
-+    ret = metadata_write(metadata);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    FWU_LOG_MSG("%s: exit\n\r", __func__);
-+    return FWU_AGENT_SUCCESS;
-+}
-+
-+enum fwu_agent_error_t corstone1000_fwu_flash_image(void)
-+{
-+    enum fwu_agent_error_t ret;
-+    struct fwu_private_metadata priv_metadata;
-+    enum fwu_agent_state_t current_state;
-+    void *capsule_ptr = (char*)CORSTONE1000_HOST_DRAM_UEFI_CAPSULE;
-+    int image_index;
-+    uint32_t image_bank_offset;
-+    uint32_t nr_images;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    if (!is_initialized) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    Select_Write_Mode_For_Shared_Flash();
-+
-+    if (metadata_read(&_metadata)) {
-+        ret =  FWU_AGENT_ERROR;
-+        goto out;
-+    }
-+
-+    if (private_metadata_read(&priv_metadata)) {
-+        ret =  FWU_AGENT_ERROR;
-+        goto out;
-+    }
-+
-+    /* Firmware update process can only start in regular state. */
-+    current_state = get_fwu_agent_state(&_metadata, &priv_metadata);
-+    if (current_state != FWU_AGENT_STATE_REGULAR) {
-+        ret =  FWU_AGENT_ERROR;
-+        goto out;
-+    }
-+
-+    memset(&capsule_info, 0, sizeof(capsule_image_info_t));
-+    if (uefi_capsule_retrieve_images(capsule_ptr, &capsule_info)) {
-+        ret =  FWU_AGENT_ERROR;
-+        goto out;
-+    }
-+    nr_images = capsule_info.nr_image;
-+
-+    for (int i = 0; i < nr_images; i++) {
-+        image_index = get_image_info_in_bank(&capsule_info.guid[i],
-+                                &image_bank_offset);
-+        switch(image_index) {
-+            case IMAGE_ALL:
-+                ret = flash_full_capsule(&_metadata, capsule_info.image[i],
-+                                         capsule_info.size[i],
-+                                         capsule_info.version[i]);
-+                break;
-+            default:
-+                FWU_LOG_MSG("%s: sent image not recognized\n\r", __func__);
-+                ret = FWU_AGENT_ERROR;
-+                break;
-+        }
-+    }
-+
-+out:
-+    Select_XIP_Mode_For_Shared_Flash();
-+
-+    FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
-+    return ret;
-+}
-+
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-index 449d354100..f5ab877ef1 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-@@ -23,9 +23,20 @@ enum fwu_agent_error_t {
-         FWU_AGENT_ERROR = (-1)
- };
- 
-+#define FWU_ASSERT(_c_)                                                        \
-+                if (!(_c_)) {                                                  \
-+                    FWU_LOG_MSG("%s:%d assert hit\n\r", __func__, __LINE__);   \
-+                    while(1) {};                                               \
-+                }                                                              \
-+
-+
- enum fwu_agent_error_t fwu_metadata_provision(void);
- enum fwu_agent_error_t fwu_metadata_init(void);
- 
-+/* host to secure enclave:
-+ * firwmare update image is sent accross
-+ */
-+enum fwu_agent_error_t corstone1000_fwu_flash_image(void);
- 
- #endif /* FWU_AGENT_H */
- 
-diff --git a/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h b/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h
-new file mode 100644
-index 0000000000..8ac67346b6
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright (c) 2021, Arm Limited. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+
-+#ifndef CORSTONE1000_IOCTL_REQUESTS_H
-+#define CORSTONE1000_IOCTL_REQUESTS_H
-+
-+#include<stdint.h>
-+
-+
-+enum corstone1000_ioctl_id_t {
-+   IOCTL_CORSTONE1000_FWU_FLASH_IMAGES = 0,
-+   IOCTL_CORSTONE1000_FWU_HOST_ACK,
-+};
-+
-+
-+typedef struct corstone1000_ioctl_in_params {
-+
-+    uint32_t ioctl_id;
-+
-+} corstone1000_ioctl_in_params_t;
-+
-+typedef struct corstone1000_ioctl_out_params {
-+
-+    int32_t result;
-+
-+} corstone1000_ioctl_out_params_t;
-+
-+#endif /* CORSTONE1000_IOCTL_REQUESTS_H */
-diff --git a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
-index ed31c8895a..f9629a1688 100644
---- a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
-+++ b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
-@@ -7,6 +7,8 @@
- 
- #include "tfm_platform_system.h"
- #include "platform_description.h"
-+#include "corstone1000_ioctl_requests.h"
-+#include "fwu_agent.h"
- 
- void tfm_platform_hal_system_reset(void)
- {
-@@ -18,8 +20,22 @@ enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
-                                                psa_invec  *in_vec,
-                                                psa_outvec *out_vec)
- {
--    (void)in_vec;
--    (void)out_vec;
--    /* No IOCTL is ipmlemented */
--    return TFM_PLATFORM_ERR_NOT_SUPPORTED;
-+    int32_t ret = TFM_PLATFORM_ERR_SUCCESS;
-+    const corstone1000_ioctl_in_params_t *in_params =
-+                                    (corstone1000_ioctl_in_params_t *)in_vec->base;
-+    corstone1000_ioctl_out_params_t *out_params = (corstone1000_ioctl_out_params_t *)out_vec->base;
-+
-+    switch(in_params->ioctl_id) {
-+        case IOCTL_CORSTONE1000_FWU_FLASH_IMAGES:
-+            out_params->result = corstone1000_fwu_flash_image();
-+            if (!out_params->result) {
-+                NVIC_SystemReset();
-+            }
-+            break;
-+        default:
-+            ret = TFM_PLATFORM_ERR_NOT_SUPPORTED;
-+            break;
-+    }
-+
-+    return ret;
- }
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0006-corstone1000-add-logic-to-select-boot-bank.patch

@@ -1,266 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 7ec8812451a4e25ca0790f84c7a0ee1f260f864c Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Mon, 11 Oct 2021 20:12:46 +0100
-Subject: [PATCH 06/15] corstone1000: add logic to select boot bank
-
-Bl1 selects the boot bank depending upon the firmware update state
-of the system. When in the trial state, new images are being tried,
-BL1 select trial/update image bank for a pre-determined number of
-times. If in all attempts, the trial bank fails to boot, BL1 falls
-back to the previous active bank. For any reason, if previous active
-bank also fails to boot for that pre-determined number of times,
-the BL1 simply goes into an assert halt state. Idealy a recovery
-mechanism should boot but this is currently out-of-scope for the
-project.
-
-BL2 logic simply tries to boot from the bank selected by the BL1.
-
-It is expected that the fail boots are detected by secure enclave,
-and in those cases, reset of the system is triggered.
-
-Change-Id: I773752f789bf8b402436c61134ac79bb405553b5
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../target/arm/corstone1000/CMakeLists.txt    |   2 +
- .../arm/corstone1000/bl1/bl1_boot_hal.c       |   6 +-
- .../target/arm/corstone1000/bl2_boot_hal.c    |   8 +-
- .../corstone1000/fw_update_agent/fwu_agent.c  | 102 ++++++++++++++++++
- .../corstone1000/fw_update_agent/fwu_agent.h  |   5 +-
- 5 files changed, 117 insertions(+), 6 deletions(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-index 81623f16ff..a2191c835f 100644
---- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-@@ -109,6 +109,7 @@ target_sources(platform_bl2
-         Native_Driver/uart_pl011_drv.c
-         fip_parser/fip_parser.c
-         bl2_boot_hal.c
-+        fw_update_agent/fwu_agent.c
- )
- 
- if (PLATFORM_IS_FVP)
-@@ -155,6 +156,7 @@ target_include_directories(platform_bl2
-         ${MCUBOOT_PATH}/boot/bootutil/include # for fault_injection_hardening.h only
-         ${CMAKE_BINARY_DIR}/bl2/ext/mcuboot # for mcuboot_config.h only
-         $<BUILD_INTERFACE:${BL2_SOURCE}/ext/mcuboot/include>
-+        fw_update_agent
- )
- 
- #========================= BL1 component =======================================#
-diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-index 54042495d7..2af5b8c846 100644
---- a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-@@ -587,7 +587,7 @@ extern void add_bank_offset_to_image_offset(uint32_t bank_offset);
- int32_t boot_platform_init(void)
- {
-     int32_t result;
--    uint32_t bank_offset = BANK_0_PARTITION_OFFSET;
-+    uint32_t bank_offset;
- 
- #if !(PLATFORM_IS_FVP)
-     setup_mpu();
-@@ -596,7 +596,6 @@ int32_t boot_platform_init(void)
- #if !(PLATFORM_IS_FVP)
-     setup_host_firewall();
- #endif
--    add_bank_offset_to_image_offset(bank_offset);
- 
-     result = FLASH_DEV_NAME.Initialize(NULL);
-     if (result != ARM_DRIVER_OK) {
-@@ -630,6 +629,9 @@ int32_t boot_platform_init(void)
-         }
-     }
- 
-+    bl1_get_boot_bank(&bank_offset);
-+    add_bank_offset_to_image_offset(bank_offset);
-+
-     return 0;
- }
- 
-diff --git a/platform/ext/target/arm/corstone1000/bl2_boot_hal.c b/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
-index 75d2cb60d8..4f5b48a2e0 100644
---- a/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
-+++ b/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
-@@ -18,6 +18,7 @@
- #include <string.h>
- #include "tfm_plat_otp.h"
- #include "tfm_plat_provisioning.h"
-+#include "fwu_agent.h"
- 
- #ifdef PLATFORM_PSA_ADAC_SECURE_DEBUG
- #include "psa_adac_platform.h"
-@@ -112,15 +113,13 @@ int32_t boot_platform_init(void)
- {
-     int32_t result;
-     enum tfm_plat_err_t plat_err;
--    uint32_t bank_offset = BANK_0_PARTITION_OFFSET;
-+    uint32_t bank_offset;
- 
-     result = fill_bl2_flash_map_by_parsing_fips(BANK_0_PARTITION_OFFSET);
-     if (result) {
-         return 1;
-     }
- 
--    add_bank_offset_to_image_offset(bank_offset);
--
-     result = FLASH_DEV_NAME.Initialize(NULL);
-     if (result != ARM_DRIVER_OK) {
-         return 1;
-@@ -154,6 +153,9 @@ int32_t boot_platform_init(void)
-     }
- #endif
- 
-+    bl2_get_boot_bank(&bank_offset);
-+    add_bank_offset_to_image_offset(bank_offset);
-+
-     return 0;
- }
- 
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-index 7fa64db0f7..23a15ee71b 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-@@ -75,8 +75,12 @@ struct fwu_private_metadata {
-        /* boot_index: the bank from which system is booted from */
-        uint32_t boot_index;
- 
-+       /* counter: tracking number of boot attempted so far */
-+       uint32_t boot_attempted;
-+
- } __packed;
- 
-+#define MAX_BOOT_ATTEMPTS_PER_BANK 3
- 
- struct fwu_metadata _metadata;
- 
-@@ -315,6 +319,7 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
-     memset(&priv_metadata, 0, sizeof(struct fwu_private_metadata));
- 
-     priv_metadata.boot_index = BANK_0;
-+    priv_metadata.boot_attempted = 0;
- 
-     ret = private_metadata_write(&priv_metadata);
-     if (ret) {
-@@ -532,3 +537,100 @@ out:
-     return ret;
- }
- 
-+void bl1_get_boot_bank(uint32_t *bank_offset)
-+{
-+    struct fwu_private_metadata priv_metadata;
-+    enum fwu_agent_state_t current_state;
-+    uint32_t boot_attempted;
-+    uint32_t boot_index;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    if (fwu_metadata_init()) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    if (private_metadata_read(&priv_metadata)) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    if (metadata_read(&_metadata)) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    current_state = get_fwu_agent_state(&_metadata, &priv_metadata);
-+
-+    if (current_state == FWU_AGENT_STATE_REGULAR) {
-+        boot_index = _metadata.active_index;
-+        FWU_ASSERT(boot_index == priv_metadata.boot_index);
-+        boot_attempted = 0;
-+    } else if (current_state == FWU_AGENT_STATE_TRIAL) {
-+        boot_attempted = (++priv_metadata.boot_attempted);
-+        FWU_LOG_MSG("%s: attempting boot number = %u\n\r",
-+                                        __func__, boot_attempted);
-+        if (boot_attempted <= MAX_BOOT_ATTEMPTS_PER_BANK) {
-+            boot_index = _metadata.active_index;
-+            FWU_LOG_MSG("%s: booting from trial bank: %u\n\r",
-+                                        __func__, boot_index);
-+        } else if (boot_attempted <= (2 * MAX_BOOT_ATTEMPTS_PER_BANK)) {
-+            boot_index = _metadata.previous_active_index;
-+            FWU_LOG_MSG("%s: gave up booting from trial bank\n\r", __func__);
-+            FWU_LOG_MSG("%s: booting from previous active bank: %u\n\r",
-+                                        __func__, boot_index);
-+        } else {
-+            FWU_LOG_MSG("%s: cannot boot system from any bank, halting...\n\r", __func__);
-+            FWU_ASSERT(0);
-+        }
-+    } else {
-+        FWU_ASSERT(0);
-+    }
-+
-+    priv_metadata.boot_index = boot_index;
-+    if (private_metadata_write(&priv_metadata)) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    if (boot_index == BANK_0) {
-+        *bank_offset = BANK_0_PARTITION_OFFSET;
-+    } else if (boot_index == BANK_1) {
-+        *bank_offset = BANK_1_PARTITION_OFFSET;
-+    } else {
-+        FWU_ASSERT(0);
-+    }
-+
-+    FWU_LOG_MSG("%s: exit: booting from bank = %u, offset = %x\n\r", __func__,
-+                        boot_index, *bank_offset);
-+
-+    return;
-+}
-+
-+void bl2_get_boot_bank(uint32_t *bank_offset)
-+{
-+    uint32_t boot_index;
-+    struct fwu_private_metadata priv_metadata;
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    if (fwu_metadata_init()) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    if (private_metadata_read(&priv_metadata)) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    boot_index = priv_metadata.boot_index;
-+
-+    if (boot_index == BANK_0) {
-+        *bank_offset = BANK_0_PARTITION_OFFSET;
-+    } else if (boot_index == BANK_1) {
-+        *bank_offset = BANK_1_PARTITION_OFFSET;
-+    } else {
-+        FWU_ASSERT(0);
-+    }
-+
-+    FWU_LOG_MSG("%s: exit: booting from bank = %u, offset = %x\n\r", __func__,
-+                        boot_index, *bank_offset);
-+
-+    return;
-+}
-+
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-index f5ab877ef1..389381c326 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-@@ -38,5 +38,8 @@ enum fwu_agent_error_t fwu_metadata_init(void);
-  */
- enum fwu_agent_error_t corstone1000_fwu_flash_image(void);
- 
--#endif /* FWU_AGENT_H */
- 
-+void bl1_get_boot_bank(uint32_t *bank_offset);
-+void bl2_get_boot_bank(uint32_t *bank_offset);
-+
-+#endif /* FWU_AGENT_H */
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0007-corstone1000-integrate-watchdog-driver.patch

@@ -1,645 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From d8c6e41ee040d19748915d2c598df1c4b90a93a8 Mon Sep 17 00:00:00 2001
-From: Harry Moulton <harry.moulton@arm.com>
-Date: Tue, 5 Oct 2021 12:40:57 +0100
-Subject: [PATCH 07/15] corstone1000: integrate watchdog driver
-
-This change integrates and enables the watchdog timer driver
-inside the BL1, BL2 and TF-M. SoC and SE watchdogs are enabled,
-meaning the system should get reset if software becomes
-unresponsive.
-
-Signed-off-by: Harry Moulton <harry.moulton@arm.com>
-Change-Id: Iab957a58025aac98140bb71289a269443529e8ed
----
- .../target/arm/corstone1000/CMakeLists.txt    |   4 +
- .../Native_Driver/arm_watchdog_drv.c          | 190 ++++++++++++++++++
- .../Native_Driver/arm_watchdog_drv.h          | 179 +++++++++++++++++
- .../arm/corstone1000/Native_Driver/watchdog.c |  81 ++++++++
- .../arm/corstone1000/Native_Driver/watchdog.h |  32 +++
- .../arm/corstone1000/bl1/CMakeLists.txt       |   2 +
- .../arm/corstone1000/bl1/bl1_boot_hal.c       |   6 +
- .../target/arm/corstone1000/bl2_boot_hal.c    |   6 +
- .../arm/corstone1000/tfm_hal_platform.c       |   5 +
- 9 files changed, 505 insertions(+)
- create mode 100644 platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.c
- create mode 100644 platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.h
- create mode 100644 platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
- create mode 100644 platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
-
-diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-index a2191c835f..cb66bd48d6 100644
---- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-@@ -62,6 +62,8 @@ target_sources(platform_s
-         Device/Source/system_core_init.c
-         Native_Driver/uart_pl011_drv.c
-         Native_Driver/mhu_v2_x.c
-+        Native_Driver/watchdog.c
-+        Native_Driver/arm_watchdog_drv.c
-         spm_hal.c
-         tfm_hal_multi_core.c
-         tfm_hal_isolation.c
-@@ -107,6 +109,8 @@ target_sources(platform_bl2
-         Device/Source/device_definition.c
-         Device/Source/system_core_init.c
-         Native_Driver/uart_pl011_drv.c
-+        Native_Driver/watchdog.c
-+        Native_Driver/arm_watchdog_drv.c
-         fip_parser/fip_parser.c
-         bl2_boot_hal.c
-         fw_update_agent/fwu_agent.c
-diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.c b/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.c
-new file mode 100644
-index 0000000000..b6323c99a5
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.c
-@@ -0,0 +1,190 @@
-+/*
-+ * Copyright (c) 2016-2020 Arm Limited
-+ *
-+ * Licensed under the Apache License, Version 2.0 (the "License");
-+ * you may not use this file except in compliance with the License.
-+ * You may obtain a copy of the License at
-+ *
-+ *     http://www.apache.org/licenses/LICENSE-2.0
-+ *
-+ * Unless required by applicable law or agreed to in writing, software
-+ * distributed under the License is distributed on an "AS IS" BASIS,
-+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-+ * See the License for the specific language governing permissions and
-+ * limitations under the License.
-+ */
-+
-+#include "arm_watchdog_drv.h"
-+
-+/* Watchdog control definitions */
-+#define ARM_WATCHDOG_CTRL_INTEN        (0x1UL << 0)
-+#define ARM_WATCHDOG_CTRL_RESEN        (0x1UL << 1)
-+#define ARM_WATCHDOG_INTCLR            1UL
-+#define ARM_WATCHDOG_RAWINTSTAT        1UL
-+#define ARM_WATCHDOG_MASKINTSTAT       1UL
-+#define ARM_WATCHDOG_UNLOCK_VALUE      0x1ACCE551
-+#define ARM_WATCHDOG_LOCK_VALUE        0x00000001
-+#define ARM_WATCHDOG_INTEGTESTEN       1UL
-+#define ARM_WATCHDOG_INTEGTESTOUTSET   1UL
-+#define ARM_WATCHDOG_MAX_VALUE         0xFFFFFFFF
-+
-+/* Watchdog state definitions */
-+#define ARM_WATCHDOG_INITIALIZED  (1ul << 0)
-+#define ARM_WATCHDOG_ENABLED      (1ul << 1)
-+
-+/* ARM watchdog memory mapped register access structure */
-+struct arm_watchdog_t {
-+    volatile uint32_t  load;          /* Offset: 0x000 (R/W) Load register */
-+    volatile uint32_t  value;         /* Offset: 0x004 (R/ ) Value register */
-+    volatile uint32_t  ctrl;          /* Offset: 0x008 (R/W) Control register */
-+    volatile uint32_t  intclr;        /* Offset: 0x00C ( /W) Clear interrupt
-+                                       *                     register */
-+    volatile uint32_t  rawintstat;    /* Offset: 0x010 (R/ ) Raw interrupt
-+                                       *                     status register */
-+    volatile uint32_t  maskintstat;   /* Offset: 0x014 (R/ ) Interrupt status
-+                                       *                     register */
-+    volatile uint32_t  reserved0[762];
-+    volatile uint32_t  lock;          /* Offset: 0xC00 (R/W) Lock register */
-+    volatile uint32_t  reserved1[191];
-+    volatile uint32_t  itcr;          /* Offset: 0xF00 (R/W) Integration test
-+                                       *                     control register */
-+    volatile uint32_t  itop;          /* Offset: 0xF04 ( /W) Integration Test
-+                                       *                     output set
-+                                       *                     register */
-+};
-+
-+void arm_watchdog_init(struct arm_watchdog_dev_t* dev, uint32_t timeout)
-+{
-+    /*
-+     * The init function leaves the watchdog in a clean state:
-+     *  - initialized;
-+     *  - disabled;
-+     *  - locked.
-+     */
-+    if (arm_watchdog_is_enabled(dev)) {
-+        arm_watchdog_unlock(dev);
-+        (void)arm_watchdog_disable(dev);
-+    }
-+    arm_watchdog_lock(dev);
-+
-+    if (timeout == 0)
-+        dev->data->timeout = ARM_WATCHDOG_MAX_VALUE;
-+    else
-+        dev->data->timeout = timeout;
-+
-+    dev->data->state = ARM_WATCHDOG_INITIALIZED;
-+}
-+
-+enum arm_watchdog_error_t arm_watchdog_feed(struct arm_watchdog_dev_t* dev)
-+{
-+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
-+
-+    if (!arm_watchdog_is_enabled(dev))
-+        return ARM_WATCHDOG_ERR_NOT_ENAB;
-+
-+    if (arm_watchdog_is_locked(dev))
-+        return ARM_WATCHDOG_ERR_LOCKED;
-+
-+    p_wdog->load = dev->data->timeout;
-+
-+    return ARM_WATCHDOG_ERR_NONE;
-+}
-+
-+enum arm_watchdog_error_t
-+arm_watchdog_clear_interrupt_and_refresh_counter(struct arm_watchdog_dev_t* dev)
-+{
-+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
-+
-+    if (!arm_watchdog_is_enabled(dev))
-+        return ARM_WATCHDOG_ERR_NOT_ENAB;
-+
-+    if (arm_watchdog_is_locked(dev))
-+        return ARM_WATCHDOG_ERR_LOCKED;
-+
-+    p_wdog->intclr = ARM_WATCHDOG_INTCLR;
-+
-+    return ARM_WATCHDOG_ERR_NONE;
-+}
-+
-+enum arm_watchdog_error_t arm_watchdog_enable(struct arm_watchdog_dev_t* dev)
-+{
-+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
-+
-+    if (!arm_watchdog_is_initialized(dev))
-+        return ARM_WATCHDOG_ERR_NOT_INIT;
-+
-+    if (arm_watchdog_is_locked(dev))
-+        return ARM_WATCHDOG_ERR_LOCKED;
-+
-+    p_wdog->load = dev->data->timeout;
-+
-+    /* Starts the watchdog counter */
-+    p_wdog->ctrl = (ARM_WATCHDOG_CTRL_RESEN | ARM_WATCHDOG_CTRL_INTEN);
-+    dev->data->state |= ARM_WATCHDOG_ENABLED;
-+
-+    return ARM_WATCHDOG_ERR_NONE;
-+}
-+
-+uint32_t arm_watchdog_is_enabled(struct arm_watchdog_dev_t* dev)
-+{
-+    return (dev->data->state & ARM_WATCHDOG_ENABLED);
-+}
-+
-+enum arm_watchdog_error_t arm_watchdog_disable(struct arm_watchdog_dev_t* dev)
-+{
-+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
-+
-+    if (!arm_watchdog_is_enabled(dev))
-+        return ARM_WATCHDOG_ERR_NOT_ENAB;
-+
-+    if (arm_watchdog_is_locked(dev))
-+        return ARM_WATCHDOG_ERR_LOCKED;
-+
-+    /* Stops the watchdog */
-+    p_wdog->ctrl &= ~(ARM_WATCHDOG_CTRL_RESEN | ARM_WATCHDOG_CTRL_INTEN);
-+    dev->data->state &= ~ARM_WATCHDOG_ENABLED;
-+
-+    return ARM_WATCHDOG_ERR_NONE;
-+}
-+
-+void arm_watchdog_lock(struct arm_watchdog_dev_t* dev)
-+{
-+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
-+
-+    /* Prevents writing to all of the registers */
-+    p_wdog->lock = ARM_WATCHDOG_LOCK_VALUE;
-+}
-+
-+uint32_t arm_watchdog_is_locked(struct arm_watchdog_dev_t* dev)
-+{
-+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
-+
-+    /* The lock register can only return 0 or 1 when read */
-+    return p_wdog->lock;
-+}
-+
-+void arm_watchdog_unlock(struct arm_watchdog_dev_t* dev)
-+{
-+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
-+
-+    p_wdog->lock = ARM_WATCHDOG_UNLOCK_VALUE;
-+}
-+
-+inline uint32_t arm_watchdog_is_initialized(struct arm_watchdog_dev_t* dev)
-+{
-+    return (dev->data->state & ARM_WATCHDOG_INITIALIZED);
-+}
-+
-+uint32_t arm_watchdog_get_remaining_time(struct arm_watchdog_dev_t* dev)
-+{
-+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
-+
-+    if (!arm_watchdog_is_enabled(dev))
-+        return 0;
-+
-+    if (arm_watchdog_is_locked(dev))
-+        return 0;
-+
-+    return p_wdog->value;
-+}
-+
-diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.h b/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.h
-new file mode 100644
-index 0000000000..3b163625f5
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.h
-@@ -0,0 +1,179 @@
-+/*
-+ * Copyright (c) 2016-2020 ARM Limited
-+ *
-+ * Licensed under the Apache License, Version 2.0 (the "License");
-+ * you may not use this file except in compliance with the License.
-+ * You may obtain a copy of the License at
-+ *
-+ *     http://www.apache.org/licenses/LICENSE-2.0
-+ *
-+ * Unless required by applicable law or agreed to in writing, software
-+ * distributed under the License is distributed on an "AS IS" BASIS,
-+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-+ * See the License for the specific language governing permissions and
-+ * limitations under the License.
-+ */
-+
-+/**
-+ * \file arm_watchdog_drv.h
-+ * \brief Generic driver for ARM watchdogs.
-+ */
-+
-+#ifndef __ARM_WATCHDOG_DRV_H__
-+#define __ARM_WATCHDOG_DRV_H__
-+
-+#include <stdint.h>
-+
-+#ifdef __cplusplus
-+extern "C" {
-+#endif
-+
-+enum arm_watchdog_error_t {
-+    ARM_WATCHDOG_ERR_NONE = 0,  /*!< No error */
-+    ARM_WATCHDOG_ERR_NOT_INIT,  /*!< Watchdog is not initialized */
-+    ARM_WATCHDOG_ERR_NOT_ENAB,  /*!< Watchdog is not enabled */
-+    ARM_WATCHDOG_ERR_LOCKED     /*!< Watchdog is locked */
-+};
-+
-+/* ARM watchdog device configuration structure */
-+struct arm_watchdog_dev_cfg_t {
-+    const uint32_t base;  /*!< Watchdog base address */
-+};
-+
-+/* ARM watchdog device data structure */
-+struct arm_watchdog_dev_data_t {
-+    uint32_t state;    /*!< Indicates if the watchdog
-+                            is initialized and enabled */
-+    uint32_t timeout;  /*!< Timeout to reset in cycles */
-+};
-+
-+/* ARM watchdog device structure */
-+struct arm_watchdog_dev_t {
-+    const struct arm_watchdog_dev_cfg_t* const cfg;  /*!< Watchdog
-+                                                          configuration */
-+    struct arm_watchdog_dev_data_t* const data;      /*!< Watchdog data */
-+};
-+
-+/**
-+ * \brief Initializes a watchdog hardware.
-+ *
-+ * \param[in] dev      Watchdog to be initialized \ref arm_watchdog_dev_t
-+ * \param[in] timeout  Timeout in cycles - 0 assings timeout to max value.
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ *       This function leaves the watchdog locked. Before any further
-+ *       operations, it needs to be unlocked and locked again.
-+ */
-+void arm_watchdog_init(struct arm_watchdog_dev_t* dev, uint32_t timeout);
-+
-+/**
-+ * \brief Feeds the watchdog to not cause a reset.
-+ *
-+ * \param[in] dev  Watchdog to be fed \ref arm_watchdog_dev_t
-+ *
-+ * \return Returns error code as specified in \ref arm_watchdog_error_t
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ */
-+enum arm_watchdog_error_t arm_watchdog_feed(struct arm_watchdog_dev_t* dev);
-+
-+/**
-+ * \brief Clear the interrupt and load timeout value to the load register.
-+ *
-+ * \param[in] dev   Watchdog to be fed \ref arm_watchdog_dev_t
-+ *
-+ * \return Returns error code as specified in \ref arm_watchdog_error_t
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ */
-+enum arm_watchdog_error_t
-+arm_watchdog_clear_interrupt_and_refresh_counter(
-+    struct arm_watchdog_dev_t* dev);
-+
-+/**
-+ * \brief Enables the watchdog.
-+ *
-+ * \param[in] dev  Watchdog to be enabled \ref arm_watchdog_dev_t
-+ *
-+ * \return Returns error code as specified in \ref arm_watchdog_error_t
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ */
-+enum arm_watchdog_error_t arm_watchdog_enable(struct arm_watchdog_dev_t* dev);
-+
-+/**
-+ * \brief Checks if the watchdog is enabled
-+ *
-+ * \param[in] dev Watchdog to be checked \ref arm_watchdog_dev_t
-+ *
-+ * \return 1 if watchdog is enabled, 0 otherwise.
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ */
-+uint32_t arm_watchdog_is_enabled(struct arm_watchdog_dev_t* dev);
-+
-+/**
-+ * \brief Disables the watchdog.
-+ *
-+ * \param[in] dev  Watchdog to be disabled \ref arm_watchdog_dev_t
-+ *
-+ * \return 1 if watchdog is enabled, 0 otherwise.
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ */
-+enum arm_watchdog_error_t arm_watchdog_disable(struct arm_watchdog_dev_t* dev);
-+
-+/**
-+ * \brief Locks the registers to not be written again.
-+ *
-+ * \param[in] dev  Watchdog to be locked \ref arm_watchdog_dev_t
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ */
-+void arm_watchdog_lock(struct arm_watchdog_dev_t* dev);
-+
-+/**
-+ * \brief Checks if the watchdog registers are locked
-+ *
-+ * \param[in] dev Watchdog to be checked \ref arm_watchdog_dev_t
-+ *
-+ * \return 1 if the registers are locked, 0 otherwise
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ */
-+uint32_t arm_watchdog_is_locked(struct arm_watchdog_dev_t* dev);
-+
-+/**
-+ * \brief Unlocks the registers to configure the watchdog again.
-+ *
-+ * \param[in] dev  Watchdog to be unlocked \ref arm_watchdog_dev_t
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ */
-+void arm_watchdog_unlock(struct arm_watchdog_dev_t* dev);
-+
-+/**
-+ * \brief Gets if watchdog driver is initialized
-+ *
-+ * \param[in] dev  Watchdog to be initialized \ref arm_watchdog_dev_t
-+ *
-+ * \returns 1 if watchdog driver is initialized. Otherwise 0.
-+ */
-+uint32_t arm_watchdog_is_initialized(struct arm_watchdog_dev_t* dev);
-+
-+/**
-+ * \brief Provides watchdog remaining time before reset.
-+ *
-+ * \param[in] dev  Watchdog to get the remaining time \ref arm_watchdog_dev_t
-+ *
-+ * \return 0 if watchdog is disabled.
-+ *
-+ * \note This function doesn't check if dev is NULL.
-+ */
-+uint32_t arm_watchdog_get_remaining_time(struct arm_watchdog_dev_t* dev);
-+
-+#ifdef __cplusplus
-+}
-+#endif
-+#endif /* __ARM_WATCHDOG_DRV_H__ */
-+
-diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
-new file mode 100644
-index 0000000000..d375af3afb
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
-@@ -0,0 +1,81 @@
-+/*
-+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+
-+#include "watchdog.h"
-+
-+#include "arm_watchdog_drv.h"
-+#include "platform_base_address.h"
-+#include "Driver_Common.h"
-+#include "cmsis.h"
-+#include <stdio.h>
-+
-+/* SoC watchdog config */
-+struct arm_watchdog_dev_cfg_t SOC_WD_DEV_CFG = {CORSTONE1000_SOC_WATCHDOG_BASE};
-+struct arm_watchdog_dev_data_t SOC_WD_DEV_DATA;
-+struct arm_watchdog_dev_t SOC_WD_DEV = {&SOC_WD_DEV_CFG, &SOC_WD_DEV_DATA};
-+#define SOC_WD_TIMEOUT 0x00030000
-+
-+/* SE watchdog config */
-+struct arm_watchdog_dev_cfg_t SE_WD_DEV_CFG = {CORSTONE1000_WATCHDOG_TIMER_BASE};
-+struct arm_watchdog_dev_data_t SE_WD_DEV_DATA;
-+struct arm_watchdog_dev_t SE_WD_DEV = {&SE_WD_DEV_CFG, &SE_WD_DEV_DATA};
-+#define SE_WD_TIMEOUT 0x0FFFFFFF
-+#define SE_WD_IRQn SE_WATCHDOG_TIMER_IRQn
-+
-+
-+/* SoC watchdog */
-+void NMI_Handler(void)
-+{
-+    /* Unlock, clear and lock the watchdog timer */
-+    arm_watchdog_unlock(&SOC_WD_DEV);
-+    arm_watchdog_clear_interrupt_and_refresh_counter(&SOC_WD_DEV);
-+    arm_watchdog_lock(&SOC_WD_DEV);
-+}
-+
-+/* SE watchdog */
-+void SE_WATCHDOG_TIMER_IRQHandler(void)
-+{
-+    /* Unlock, clear and lock the watchdog timer */
-+    arm_watchdog_unlock(&SE_WD_DEV);
-+    arm_watchdog_clear_interrupt_and_refresh_counter(&SE_WD_DEV);
-+    arm_watchdog_lock(&SE_WD_DEV);
-+}
-+
-+int corstone1000_watchdog_init()
-+{
-+    __disable_irq();
-+
-+    /* SoC Watchdog setup */
-+    arm_watchdog_init(&SOC_WD_DEV, SOC_WD_TIMEOUT);
-+    arm_watchdog_unlock(&SOC_WD_DEV);
-+    arm_watchdog_enable(&SOC_WD_DEV);
-+    arm_watchdog_lock(&SOC_WD_DEV);
-+
-+    if (!arm_watchdog_is_initialized(&SOC_WD_DEV))
-+        return ARM_DRIVER_ERROR_UNSUPPORTED;
-+
-+    if (!arm_watchdog_is_enabled(&SOC_WD_DEV))
-+        return ARM_DRIVER_ERROR_UNSUPPORTED;
-+
-+    /* SE Watchdog setup */
-+    arm_watchdog_init(&SE_WD_DEV, SE_WD_TIMEOUT);
-+    arm_watchdog_unlock(&SE_WD_DEV);
-+    arm_watchdog_enable(&SE_WD_DEV);
-+    arm_watchdog_lock(&SE_WD_DEV);
-+
-+    NVIC_EnableIRQ(SE_WD_IRQn);
-+
-+    if (!arm_watchdog_is_initialized(&SE_WD_DEV))
-+        return ARM_DRIVER_ERROR_UNSUPPORTED;
-+
-+    if (!arm_watchdog_is_enabled(&SE_WD_DEV))
-+        return ARM_DRIVER_ERROR_UNSUPPORTED;
-+
-+    __enable_irq();
-+    
-+    return ARM_DRIVER_OK;
-+}
-diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
-new file mode 100644
-index 0000000000..fd1b7cf124
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
-@@ -0,0 +1,32 @@
-+/*
-+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+
-+#ifndef WATCHDOG_H
-+#define WATCHDOG_H
-+
-+#include <stddef.h>
-+#include <stdint.h>
-+
-+#include "Driver_Common.h"
-+#include "arm_watchdog_drv.h"
-+#include "platform_base_address.h"
-+
-+/**
-+ *  \brief Initializes Secure Enclave & SoC Watchdog.
-+ *
-+ *  \returns ARM Driver return code.
-+ */
-+int corstone1000_watchdog_init();
-+
-+/**
-+ *  \brief Reset the Secure Enclave & SoC Watchdog's.
-+ * 
-+ *  \returns ARM Driver return code.
-+ */
-+int corstone1000_watchdog_reset_timer();
-+
-+#endif /* watchdog_h */
-diff --git a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
-index 92a78c1168..1737fbee91 100644
---- a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
-@@ -239,6 +239,8 @@ target_sources(bl1_main
-         ../Native_Driver/firewall.c
-         ../Native_Driver/uart_pl011_drv.c
-         ../fw_update_agent/fwu_agent.c
-+        ../Native_Driver/arm_watchdog_drv.c
-+        ../Native_Driver/watchdog.c
-         bl1_boot_hal.c
-         bl1_flash_map.c
-         bl1_security_cnt.c
-diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-index 2af5b8c846..edde6fb24e 100644
---- a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
-@@ -14,6 +14,7 @@
- #include "bootutil/fault_injection_hardening.h"
- #include "bootutil/bootutil_log.h"
- #include "firewall.h"
-+#include "watchdog.h"
- #include "mpu_config.h"
- #include "tfm_plat_otp.h"
- #include "tfm_plat_provisioning.h"
-@@ -589,6 +590,11 @@ int32_t boot_platform_init(void)
-     int32_t result;
-     uint32_t bank_offset;
- 
-+    result = corstone1000_watchdog_init();
-+    if (result != ARM_DRIVER_OK) {
-+        return 1;
-+    }
-+
- #if !(PLATFORM_IS_FVP)
-     setup_mpu();
- #endif
-diff --git a/platform/ext/target/arm/corstone1000/bl2_boot_hal.c b/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
-index 4f5b48a2e0..5c6b78ffb3 100644
---- a/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
-+++ b/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
-@@ -15,6 +15,7 @@
- #include "bootutil/bootutil_log.h"
- #include "fip_parser.h"
- #include "flash_map/flash_map.h"
-+#include "watchdog.h"
- #include <string.h>
- #include "tfm_plat_otp.h"
- #include "tfm_plat_provisioning.h"
-@@ -115,6 +116,11 @@ int32_t boot_platform_init(void)
-     enum tfm_plat_err_t plat_err;
-     uint32_t bank_offset;
- 
-+    result = corstone1000_watchdog_init();
-+    if (result != ARM_DRIVER_OK) {
-+        return 1;
-+    }
-+
-     result = fill_bl2_flash_map_by_parsing_fips(BANK_0_PARTITION_OFFSET);
-     if (result) {
-         return 1;
-diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
-index 0072b5b928..7faa71eb63 100644
---- a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
-+++ b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
-@@ -9,12 +9,17 @@
- #include "tfm_hal_platform.h"
- #include "uart_stdout.h"
- #include "fwu_agent.h"
-+#include "watchdog.h"
- 
- enum tfm_hal_status_t tfm_hal_platform_init(void)
- {
-     __enable_irq();
-     stdio_init();
- 
-+    if (corstone1000_watchdog_init()) {
-+        return TFM_HAL_ERROR_GENERIC;
-+    }
-+
-     if (fwu_metadata_init()) {
-         return TFM_HAL_ERROR_GENERIC;
-     }
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0008-corstone1000-impelment-accept-image-logic.patch

@@ -1,119 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 9b2b4e284d36d0433f5aa0af6f13e7eda5c783c0 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Thu, 14 Oct 2021 05:08:04 +0100
-Subject: [PATCH 08/15] corstone1000: impelment accept image logic
-
-Until all new images in the update/trial bank is accepted,
-the firmware update state of the system remains in the trial
-state. The state changes automatically to regular state when
-all new images in the trial bank is accepted.
-
-This commit adds the logic to accept one of the image type.
-
-Change-Id: I1f18d77b185f2e5dd26d6e02bed792689019b7b8
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../corstone1000/fw_update_agent/fwu_agent.c  | 70 +++++++++++++++++++
- .../services/src/tfm_platform_system.c        |  2 +-
- 2 files changed, 71 insertions(+), 1 deletion(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-index 23a15ee71b..a70638e993 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-@@ -537,6 +537,76 @@ out:
-     return ret;
- }
- 
-+static enum fwu_agent_error_t accept_full_capsule(
-+          struct fwu_metadata* metadata,
-+          struct fwu_private_metadata* priv_metadata)
-+{
-+    uint32_t active_index = metadata->active_index;
-+    enum fwu_agent_error_t ret;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
-+        metadata->img_entry[i].img_props[active_index].accepted =
-+                                                            IMAGE_ACCEPTED;
-+    }
-+
-+    priv_metadata->boot_attempted = 0;
-+
-+    ret = private_metadata_write(priv_metadata);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    ret = metadata_write(metadata);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    FWU_LOG_MSG("%s: exit: fwu state is changed to regular\n\r", __func__);
-+    return FWU_AGENT_SUCCESS;
-+}
-+
-+static enum fwu_agent_error_t fwu_accept_image(struct efi_guid* guid,
-+        struct fwu_metadata *metadata,
-+        struct fwu_private_metadata *priv_metadata)
-+{
-+    enum fwu_agent_state_t current_state;
-+    int image_index;
-+    uint32_t image_bank_offset;
-+    enum fwu_agent_error_t ret;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    /* it is expected to receive this call only when
-+       in trial state */
-+    current_state = get_fwu_agent_state(metadata, priv_metadata);
-+    if (current_state != FWU_AGENT_STATE_TRIAL) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    /* booted from previous_active_bank, not expected
-+     * to receive this call in this state, rather host should
-+     * call corstone1000_fwu_select_previous */
-+    if (metadata->active_index != priv_metadata->boot_index) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    image_index = get_image_info_in_bank(guid, &image_bank_offset);
-+    switch(image_index) {
-+        case IMAGE_ALL:
-+            ret = accept_full_capsule(metadata, priv_metadata);
-+            break;
-+        default:
-+            FWU_LOG_MSG("%s: sent image not recognized\n\r", __func__);
-+            ret = FWU_AGENT_ERROR;
-+            break;
-+    }
-+
-+    FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
-+    return ret;
-+}
-+
- void bl1_get_boot_bank(uint32_t *bank_offset)
- {
-     struct fwu_private_metadata priv_metadata;
-diff --git a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
-index f9629a1688..16ad975c32 100644
---- a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
-+++ b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
-@@ -21,7 +21,7 @@ enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
-                                                psa_outvec *out_vec)
- {
-     int32_t ret = TFM_PLATFORM_ERR_SUCCESS;
--    const corstone1000_ioctl_in_params_t *in_params =
-+    corstone1000_ioctl_in_params_t *in_params =
-                                     (corstone1000_ioctl_in_params_t *)in_vec->base;
-     corstone1000_ioctl_out_params_t *out_params = (corstone1000_ioctl_out_params_t *)out_vec->base;
- 
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0009-corstone1000-implement-select-previous-bank-logic.patch

@@ -1,91 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From a565999300cf5d40c772d3ff29e2020b786a2a10 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Sat, 16 Oct 2021 09:07:17 +0100
-Subject: [PATCH 09/15] corstone1000: implement select previous bank logic
-
-When firmware update process is not successful, the commit logic
-reverts the system state to previous active bank. With this,
-the state of the system also changes from the trial to regular
-state. System gets reverted back to its previous known good state.
-
-Change-Id: I265635ea984ae9542518a0e389c98e1242e78d10
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../corstone1000/fw_update_agent/fwu_agent.c  | 58 +++++++++++++++++++
- 1 file changed, 58 insertions(+)
-
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-index a70638e993..89f0a08eb5 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-@@ -607,6 +607,64 @@ static enum fwu_agent_error_t fwu_accept_image(struct efi_guid* guid,
-     return ret;
- }
- 
-+static enum fwu_agent_error_t fwu_select_previous(
-+        struct fwu_metadata *metadata,
-+        struct fwu_private_metadata *priv_metadata)
-+{
-+    enum fwu_agent_error_t ret;
-+    enum fwu_agent_state_t current_state;
-+    uint32_t index;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    /* it is expected to receive this call only when
-+       in trial state */
-+    current_state = get_fwu_agent_state(metadata, priv_metadata);
-+    if (current_state != FWU_AGENT_STATE_TRIAL) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    /* not expected to receive this call in this state, system
-+     * did not boot from previous active index */
-+    if (metadata->previous_active_index != priv_metadata->boot_index) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    FWU_LOG_MSG("%s: trial state: active index = %u, previous active = %u\n\r",
-+            __func__, metadata->active_index, metadata->previous_active_index);
-+
-+    index = metadata->previous_active_index;
-+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
-+        if (metadata->img_entry[i].img_props[index].accepted != IMAGE_ACCEPTED)
-+        {
-+            FWU_ASSERT(0);
-+        }
-+    }
-+
-+    index = metadata->active_index;
-+    metadata->active_index = metadata->previous_active_index;
-+    metadata->previous_active_index = index;
-+
-+    priv_metadata->boot_attempted = 0;
-+
-+    ret = private_metadata_write(priv_metadata);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    ret = metadata_write(metadata);
-+    if (ret) {
-+        return ret;
-+    }
-+
-+    FWU_LOG_MSG("%s: in regular state by choosing previous active bank\n\r",
-+                 __func__);
-+
-+    FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
-+    return ret;
-+
-+}
-+
- void bl1_get_boot_bank(uint32_t *bank_offset)
- {
-     struct fwu_private_metadata priv_metadata;
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0010-corstone1000-implement-corstone1000_fwu_host_ack.patch

@@ -1,136 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 0a4c27173e9ac31e6bfe424b6856c4dc612e247a Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Tue, 16 Nov 2021 04:56:52 +0000
-Subject: [PATCH 10/15] corstone1000: implement corstone1000_fwu_host_ack
-
-The host uses the api 'corstone1000_fwu_host_ack' to acknowledge its
-successful boot to the secure enclave. Based on the fwu state of
-the system, the secure enalve decides where to move in the fwu state
-machine. If in regular state, there is nothing to be done. If in
-trial state and firmware update is a success, state moves to regular
-by accepting images in the trial/update bank. Finaly if in trial
-state and firmware update is a failure, state moves to regular by
-reverting to previous known state.
-
-Change-Id: I16657537909916bd19520eac3899501fdb14ecb4
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../corstone1000/fw_update_agent/fwu_agent.c  | 47 +++++++++++++++++++
- .../corstone1000/fw_update_agent/fwu_agent.h  |  5 ++
- .../services/src/tfm_platform_system.c        | 14 +++++-
- 3 files changed, 64 insertions(+), 2 deletions(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-index 89f0a08eb5..5e87fd8d5e 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-@@ -762,3 +762,50 @@ void bl2_get_boot_bank(uint32_t *bank_offset)
-     return;
- }
- 
-+enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
-+{
-+    enum fwu_agent_error_t ret;
-+    struct fwu_private_metadata priv_metadata;
-+    enum fwu_agent_state_t current_state;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    if (!is_initialized) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    Select_Write_Mode_For_Shared_Flash();
-+
-+    if (metadata_read(&_metadata)) {
-+        ret = FWU_AGENT_ERROR;
-+        goto out;
-+    }
-+
-+    if (private_metadata_read(&priv_metadata)) {
-+        ret = FWU_AGENT_ERROR;
-+        goto out;
-+    }
-+
-+    current_state = get_fwu_agent_state(&_metadata, &priv_metadata);
-+    if (current_state == FWU_AGENT_STATE_REGULAR) {
-+        ret = FWU_AGENT_SUCCESS; /* nothing to be done */
-+        goto out;
-+    } else if (current_state != FWU_AGENT_STATE_TRIAL) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    if (_metadata.active_index != priv_metadata.boot_index) {
-+        /* firmware update failed, revert back to previous bank */
-+        ret = fwu_select_previous(&_metadata, &priv_metadata);
-+    } else {
-+        /* firmware update successful */
-+        ret = fwu_accept_image(&full_capsule_image_guid, &_metadata,
-+                                &priv_metadata);
-+    }
-+
-+out:
-+    Select_XIP_Mode_For_Shared_Flash();
-+
-+    FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
-+    return ret;
-+}
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-index 389381c326..b8f7c676d7 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-@@ -38,6 +38,11 @@ enum fwu_agent_error_t fwu_metadata_init(void);
-  */
- enum fwu_agent_error_t corstone1000_fwu_flash_image(void);
- 
-+/* host to secure enclave:
-+ * host responds with this api to acknowledge its successful
-+ * boot.
-+ */
-+enum fwu_agent_error_t corstone1000_fwu_host_ack(void);
- 
- void bl1_get_boot_bank(uint32_t *bank_offset);
- void bl2_get_boot_bank(uint32_t *bank_offset);
-diff --git a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
-index 16ad975c32..068234dcda 100644
---- a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
-+++ b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
-@@ -21,20 +21,30 @@ enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
-                                                psa_outvec *out_vec)
- {
-     int32_t ret = TFM_PLATFORM_ERR_SUCCESS;
-+
-     corstone1000_ioctl_in_params_t *in_params =
--                                    (corstone1000_ioctl_in_params_t *)in_vec->base;
--    corstone1000_ioctl_out_params_t *out_params = (corstone1000_ioctl_out_params_t *)out_vec->base;
-+                              (corstone1000_ioctl_in_params_t *)in_vec->base;
-+
-+    corstone1000_ioctl_out_params_t *out_params =
-+                              (corstone1000_ioctl_out_params_t *)out_vec->base;
- 
-     switch(in_params->ioctl_id) {
-+
-         case IOCTL_CORSTONE1000_FWU_FLASH_IMAGES:
-             out_params->result = corstone1000_fwu_flash_image();
-             if (!out_params->result) {
-                 NVIC_SystemReset();
-             }
-             break;
-+
-+        case IOCTL_CORSTONE1000_FWU_HOST_ACK:
-+            out_params->result = corstone1000_fwu_host_ack();
-+            break;
-+
-         default:
-             ret = TFM_PLATFORM_ERR_NOT_SUPPORTED;
-             break;
-+
-     }
- 
-     return ret;
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0011-SPM-multiple-core-initailize-multi-core-communicatio.patch

@@ -1,39 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 35ab33099d7b091630ec677cbad57abd60105f91 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Sun, 14 Nov 2021 11:49:11 +0000
-Subject: [PATCH 11/15] SPM: multiple core: initailize multi-core communication
- before the non-secure core is out of rest
-
-Tf-m should be ready to receive the communication before non-secure
-has been taken out of rest.
-
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-Change-Id: I0b609fffbed0fc2f09b521389fd50f4e992ad00d
----
- secure_fw/spm/cmsis_psa/tfm_multi_core.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/secure_fw/spm/cmsis_psa/tfm_multi_core.c b/secure_fw/spm/cmsis_psa/tfm_multi_core.c
-index f830a6f5f7..946d1a60eb 100644
---- a/secure_fw/spm/cmsis_psa/tfm_multi_core.c
-+++ b/secure_fw/spm/cmsis_psa/tfm_multi_core.c
-@@ -25,11 +25,11 @@ void tfm_nspm_thread_entry(void)
-     SPMLOG_DBGMSG("Enabling non-secure core...");
- #endif
- 
-+    tfm_inter_core_comm_init();
-+
-     tfm_hal_boot_ns_cpu(tfm_spm_hal_get_ns_VTOR());
-     tfm_hal_wait_for_ns_cpu_ready();
- 
--    tfm_inter_core_comm_init();
--
-     /*
-      * TODO
-      * The infinite-loop can be replaced with platform-specific low-power sleep
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0012-corstone1000-implement-timer-to-track-host-progress.patch

@@ -1,169 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 1a891fc818526bfb8b546c86a93b81353330a466 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Mon, 8 Nov 2021 18:10:44 +0000
-Subject: [PATCH 12/15] corstone1000: implement timer to track host progress
-
-When in fwu trial state, the secure enclave starts the timer to
-keep track of host progress. Secure enclave expects that the host
-acknowledges before the timer expires. If host fails to do so,
-the secure enclave resets the system.
-
-Change-Id: Ib63778b6c813f1b0d3517e0c05226d6f88927b04
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../corstone1000/fw_update_agent/fwu_agent.c  | 78 +++++++++++++++++++
- .../corstone1000/fw_update_agent/fwu_agent.h  |  7 ++
- .../arm/corstone1000/tfm_hal_multi_core.c     |  5 +-
- 3 files changed, 89 insertions(+), 1 deletion(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-index 5e87fd8d5e..e8686704b8 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-@@ -15,6 +15,7 @@
- #include "uefi_capsule_parser.h"
- #include "flash_common.h"
- #include "platform_base_address.h"
-+#include "platform_description.h"
- 
- /* Properties of image in a bank */
- struct fwu_image_properties {
-@@ -127,6 +128,8 @@ struct efi_guid full_capsule_image_guid = {
- /* Import the CMSIS flash device driver */
- extern ARM_DRIVER_FLASH FWU_METADATA_FLASH_DEV;
- 
-+#define HOST_ACK_TIMEOUT_SEC    (6 * 60) /* ~seconds, not exact */
-+
- static enum fwu_agent_error_t private_metadata_read(
-         struct fwu_private_metadata* p_metadata)
- {
-@@ -762,6 +765,13 @@ void bl2_get_boot_bank(uint32_t *bank_offset)
-     return;
- }
- 
-+static void disable_host_ack_timer(void)
-+{
-+    FWU_LOG_MSG("%s: timer to reset is disabled\n\r", __func__);
-+    SysTick->CTRL &= (~SysTick_CTRL_ENABLE_Msk);
-+}
-+
-+
- enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
- {
-     enum fwu_agent_error_t ret;
-@@ -803,9 +813,77 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
-                                 &priv_metadata);
-     }
- 
-+    if (ret == FWU_AGENT_SUCCESS) {
-+        disable_host_ack_timer();
-+    }
-+
- out:
-     Select_XIP_Mode_For_Shared_Flash();
- 
-     FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
-     return ret;
- }
-+
-+static int systic_counter = 0;
-+
-+void SysTick_Handler(void)
-+{
-+    systic_counter++;
-+    if ((systic_counter % 10) == 0) {
-+        FWU_LOG_MSG("%s: counted = %d, expiring on = %u\n\r", __func__,
-+                                systic_counter, HOST_ACK_TIMEOUT_SEC);
-+    }
-+    if (systic_counter == HOST_ACK_TIMEOUT_SEC) {
-+        FWU_LOG_MSG("%s, timer expired, reseting the system\n\r", __func__);
-+        NVIC_SystemReset();
-+    }
-+}
-+
-+/* When in trial state, start the timer for host to respond.
-+ * Diable timer when host responds back either by calling
-+ * corstone1000_fwu_accept_image or corstone1000_fwu_select_previous.
-+ * Otherwise, resets the system.
-+ */
-+void host_acknowledgement_timer_to_reset(void)
-+{
-+    struct fwu_private_metadata priv_metadata;
-+    enum fwu_agent_state_t current_state;
-+    uint32_t boot_attempted;
-+    uint32_t boot_index;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    Select_Write_Mode_For_Shared_Flash();
-+
-+    if (!is_initialized) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    if (private_metadata_read(&priv_metadata)) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    if (metadata_read(&_metadata)) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    Select_XIP_Mode_For_Shared_Flash();
-+
-+    current_state = get_fwu_agent_state(&_metadata, &priv_metadata);
-+
-+    if (current_state == FWU_AGENT_STATE_TRIAL) {
-+        FWU_LOG_MSG("%s: in trial state, starting host ack timer\n\r",
-+                        __func__);
-+        systic_counter = 0;
-+        if (SysTick_Config(SysTick_LOAD_RELOAD_Msk)) {
-+            FWU_LOG_MSG("%s: timer init failed\n\r", __func__);
-+            FWU_ASSERT(0);
-+        } else {
-+            FWU_LOG_MSG("%s: timer started: seconds to expire : %u\n\r",
-+                        __func__, HOST_ACK_TIMEOUT_SEC);
-+        }
-+    }
-+
-+    FWU_LOG_MSG("%s: exit\n\r", __func__);
-+    return;
-+}
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-index b8f7c676d7..80f72e2bd6 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-@@ -47,4 +47,11 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void);
- void bl1_get_boot_bank(uint32_t *bank_offset);
- void bl2_get_boot_bank(uint32_t *bank_offset);
- 
-+/* When in trial state, start the timer for host to respond.
-+ * Diable timer when host responds back either by calling
-+ * corstone1000_fwu_accept_image or corstone1000_fwu_select_previous.
-+ * Otherwise, resets the system.
-+ */
-+void host_acknowledgement_timer_to_reset(void);
-+
- #endif /* FWU_AGENT_H */
-diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
-index 834ebc33e3..cc94055b94 100644
---- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
-+++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
-@@ -56,7 +56,10 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
- 
- void tfm_hal_wait_for_ns_cpu_ready(void)
- {
--    /* Synchronization between Host and SE is done by OpenAMP */
-+    /* start the reset timer if firwmare update process is ongoing */
-+#if !(PLATFORM_IS_FVP)
-+    host_acknowledgement_timer_to_reset();
-+#endif
- }
- 
- void tfm_hal_get_mem_security_attr(const void *p, size_t s,
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0013-corstone1000-fwu-nv-counter-anti-rollback-support.patch

@@ -1,369 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From eb02f01cd9095f11bbd737db8b1723358e463d73 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Wed, 17 Nov 2021 07:30:26 +0000
-Subject: [PATCH 13/15] corstone1000: fwu nv-counter anti-rollback support
-
-The patch implements anti-rollback protection on the nv-counters.
-The nv-counters are staged onto the flash, and only updated when
-firmware update process is successful. Before update, one more
-time verification is performed.
-
-Change-Id: Ibe9df7f65c7aecdb9d712bd76c4dbff4e8fd1023
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- .../target/arm/corstone1000/CMakeLists.txt    |   1 +
- .../arm/corstone1000/bl1/bl1_security_cnt.c   |  20 ++-
- .../arm/corstone1000/bl2_security_cnt.c       | 114 ++++++++++++++++++
- .../ext/target/arm/corstone1000/config.cmake  |   2 +
- .../corstone1000/fw_update_agent/fwu_agent.c  |  95 +++++++++++++++
- .../corstone1000/fw_update_agent/fwu_agent.h  |  16 +++
- 6 files changed, 245 insertions(+), 3 deletions(-)
- create mode 100644 platform/ext/target/arm/corstone1000/bl2_security_cnt.c
-
-diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-index cb66bd48d6..7b1ee53b15 100644
---- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
-@@ -114,6 +114,7 @@ target_sources(platform_bl2
-         fip_parser/fip_parser.c
-         bl2_boot_hal.c
-         fw_update_agent/fwu_agent.c
-+        bl2_security_cnt.c
- )
- 
- if (PLATFORM_IS_FVP)
-diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c b/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c
-index f275cbfecb..e56defa09a 100644
---- a/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c
-+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c
-@@ -10,6 +10,8 @@
- #include "tfm_plat_defs.h"
- #include "bootutil/fault_injection_hardening.h"
- #include <stdint.h>
-+#include "tfm_plat_provisioning.h"
-+#include "fwu_agent.h"
- 
- fih_int boot_nv_security_counter_init(void)
- {
-@@ -47,14 +49,26 @@ int32_t boot_nv_security_counter_update(uint32_t image_id,
-                                         uint32_t img_security_cnt)
- {
-     enum tfm_plat_err_t err;
-+    enum fwu_agent_error_t fwu_err;
- 
-     if (image_id != 0) {
-         return -1;
-     }
- 
--    err = tfm_plat_set_nv_counter(PLAT_NV_COUNTER_BL1_0, img_security_cnt);
--    if (err != TFM_PLAT_ERR_SUCCESS) {
--        return -1;
-+    if (tfm_plat_provisioning_is_required()) {
-+
-+        err = tfm_plat_set_nv_counter(PLAT_NV_COUNTER_BL1_0, img_security_cnt);
-+        if (err != TFM_PLAT_ERR_SUCCESS) {
-+            return -1;
-+        }
-+
-+    } else {
-+
-+        fwu_err = fwu_stage_nv_counter(FWU_BL2_NV_COUNTER, img_security_cnt);
-+        if (fwu_err != FWU_AGENT_SUCCESS) {
-+            return -1;
-+        }
-+
-     }
- 
-     return 0;
-diff --git a/platform/ext/target/arm/corstone1000/bl2_security_cnt.c b/platform/ext/target/arm/corstone1000/bl2_security_cnt.c
-new file mode 100644
-index 0000000000..adb0c13039
---- /dev/null
-+++ b/platform/ext/target/arm/corstone1000/bl2_security_cnt.c
-@@ -0,0 +1,114 @@
-+/*
-+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
-+ *
-+ * SPDX-License-Identifier: BSD-3-Clause
-+ *
-+ */
-+
-+#include "bootutil/security_cnt.h"
-+#include "tfm_plat_nv_counters.h"
-+#include "tfm_plat_defs.h"
-+#include "bootutil/fault_injection_hardening.h"
-+#include <stdint.h>
-+#include "tfm_plat_provisioning.h"
-+#include "fwu_agent.h"
-+
-+#define TFM_BOOT_NV_COUNTER_0    PLAT_NV_COUNTER_BL2_0   /* NV counter of Image 0 */
-+#define TFM_BOOT_NV_COUNTER_1    PLAT_NV_COUNTER_BL2_1   /* NV counter of Image 1 */
-+#define TFM_BOOT_NV_COUNTER_2    PLAT_NV_COUNTER_BL2_2   /* NV counter of Image 2 */
-+#define TFM_BOOT_NV_COUNTER_MAX  PLAT_NV_COUNTER_BL2_2 + 1
-+
-+static enum tfm_nv_counter_t get_nv_counter_from_image_id(uint32_t image_id)
-+{
-+    uint32_t nv_counter;
-+
-+    /* Avoid integer overflow */
-+    if ((UINT32_MAX - TFM_BOOT_NV_COUNTER_0) < image_id) {
-+        return TFM_BOOT_NV_COUNTER_MAX;
-+    }
-+
-+    nv_counter = TFM_BOOT_NV_COUNTER_0 + image_id;
-+
-+    /* Check the existence of the enumerated counter value */
-+    if (nv_counter >= TFM_BOOT_NV_COUNTER_MAX) {
-+        return TFM_BOOT_NV_COUNTER_MAX;
-+    }
-+
-+    return (enum tfm_nv_counter_t)nv_counter;
-+}
-+
-+fih_int boot_nv_security_counter_init(void)
-+{
-+    fih_int fih_rc = FIH_FAILURE;
-+
-+    fih_rc = fih_int_encode_zero_equality(tfm_plat_init_nv_counter());
-+
-+    FIH_RET(fih_rc);
-+}
-+
-+fih_int boot_nv_security_counter_get(uint32_t image_id, fih_int *security_cnt)
-+{
-+    enum tfm_nv_counter_t nv_counter;
-+    fih_int fih_rc = FIH_FAILURE;
-+    uint32_t security_cnt_soft;
-+
-+    /* Check if it's a null-pointer. */
-+    if (!security_cnt) {
-+        FIH_RET(FIH_FAILURE);
-+    }
-+
-+    nv_counter = get_nv_counter_from_image_id(image_id);
-+    if (nv_counter >= TFM_BOOT_NV_COUNTER_MAX) {
-+        FIH_RET(FIH_FAILURE);
-+    }
-+
-+    fih_rc = fih_int_encode_zero_equality(
-+             tfm_plat_read_nv_counter(nv_counter,
-+                                      sizeof(security_cnt_soft),
-+                                      (uint8_t *)&security_cnt_soft));
-+    *security_cnt = fih_int_encode(security_cnt_soft);
-+
-+    printf("%s: security_cnt=%d\n\r", __func__, *security_cnt);
-+
-+    FIH_RET(fih_rc);
-+}
-+
-+int32_t boot_nv_security_counter_update(uint32_t image_id,
-+                                        uint32_t img_security_cnt)
-+{
-+    enum tfm_nv_counter_t nv_counter;
-+    enum tfm_plat_err_t err;
-+    enum fwu_agent_error_t fwu_err;
-+
-+    nv_counter = get_nv_counter_from_image_id(image_id);
-+    if (nv_counter >= TFM_BOOT_NV_COUNTER_MAX) {
-+        return -1;
-+    }
-+
-+    printf("%s: security_cnt=%u:%u\n\r", __func__, nv_counter, img_security_cnt);
-+
-+    if (tfm_plat_provisioning_is_required()) {
-+
-+        err = tfm_plat_set_nv_counter(nv_counter, img_security_cnt);
-+        if (err != TFM_PLAT_ERR_SUCCESS) {
-+            return -1;
-+        }
-+
-+    } else {
-+
-+        if (nv_counter == PLAT_NV_COUNTER_BL2_0) {
-+            fwu_err = fwu_stage_nv_counter(FWU_TFM_NV_COUNTER, img_security_cnt);
-+        } else if (nv_counter == PLAT_NV_COUNTER_BL2_1) {
-+            fwu_err = fwu_stage_nv_counter(FWU_TFA_NV_COUNTER, img_security_cnt);
-+        } else {
-+            return -1;
-+        }
-+
-+        if (fwu_err != FWU_AGENT_SUCCESS) {
-+            return -1;
-+        }
-+
-+    }
-+
-+    return 0;
-+}
-diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
-index 203e6b79a6..d6f3ef7d21 100644
---- a/platform/ext/target/arm/corstone1000/config.cmake
-+++ b/platform/ext/target/arm/corstone1000/config.cmake
-@@ -39,3 +39,5 @@ if (${PLATFORM_IS_FVP})
- else()
-     set(PLATFORM_PSA_ADAC_SECURE_DEBUG      FALSE        CACHE BOOL      "Whether to use psa-adac secure debug.")
- endif()
-+
-+set(DEFAULT_MCUBOOT_SECURITY_COUNTERS   OFF          CACHE BOOL      "Whether to use the default security counter configuration defined by TF-M project")
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-index e8686704b8..cd7f901287 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
-@@ -16,6 +16,8 @@
- #include "flash_common.h"
- #include "platform_base_address.h"
- #include "platform_description.h"
-+#include "tfm_plat_nv_counters.h"
-+#include "tfm_plat_defs.h"
- 
- /* Properties of image in a bank */
- struct fwu_image_properties {
-@@ -79,6 +81,9 @@ struct fwu_private_metadata {
-        /* counter: tracking number of boot attempted so far */
-        uint32_t boot_attempted;
- 
-+       /* staged nv_counter: temprary location before written to the otp */
-+       uint32_t nv_counter[NR_OF_IMAGES_IN_FW_BANK];
-+
- } __packed;
- 
- #define MAX_BOOT_ATTEMPTS_PER_BANK 3
-@@ -771,6 +776,56 @@ static void disable_host_ack_timer(void)
-     SysTick->CTRL &= (~SysTick_CTRL_ENABLE_Msk);
- }
- 
-+static enum fwu_agent_error_t update_nv_counters(
-+                        struct fwu_private_metadata* priv_metadata)
-+{
-+    enum tfm_plat_err_t err;
-+    uint32_t security_cnt;
-+    enum tfm_nv_counter_t tfm_nv_counter_i;
-+
-+    FWU_LOG_MSG("%s: enter\n\r", __func__);
-+
-+    for (int i = 0; i <= FWU_MAX_NV_COUNTER_INDEX; i++) {
-+
-+        switch (i) {
-+            case FWU_BL2_NV_COUNTER:
-+                tfm_nv_counter_i = PLAT_NV_COUNTER_BL1_0;
-+                break;
-+            case FWU_TFM_NV_COUNTER:
-+                tfm_nv_counter_i = PLAT_NV_COUNTER_BL2_0;
-+                break;
-+            case FWU_TFA_NV_COUNTER:
-+                tfm_nv_counter_i = PLAT_NV_COUNTER_BL2_1;
-+                break;
-+            default:
-+                FWU_ASSERT(0);
-+                break;
-+        }
-+
-+        err = tfm_plat_read_nv_counter(tfm_nv_counter_i,
-+                        sizeof(security_cnt), (uint8_t *)&security_cnt);
-+        if (err != TFM_PLAT_ERR_SUCCESS) {
-+            return FWU_AGENT_ERROR;
-+        }
-+
-+        if (priv_metadata->nv_counter[i] < security_cnt) {
-+            return FWU_AGENT_ERROR;
-+        } else if (priv_metadata->nv_counter[i] > security_cnt) {
-+            FWU_LOG_MSG("%s: updaing index = %u nv counter = %u->%u\n\r",
-+                        __func__, i, security_cnt,
-+                        priv_metadata->nv_counter[FWU_BL2_NV_COUNTER]);
-+            err = tfm_plat_set_nv_counter(tfm_nv_counter_i,
-+                                    priv_metadata->nv_counter[FWU_BL2_NV_COUNTER]);
-+            if (err != TFM_PLAT_ERR_SUCCESS) {
-+                return FWU_AGENT_ERROR;
-+            }
-+        }
-+
-+    }
-+
-+    FWU_LOG_MSG("%s: exit\n\r", __func__);
-+    return FWU_AGENT_SUCCESS;
-+}
- 
- enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
- {
-@@ -811,6 +866,9 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
-         /* firmware update successful */
-         ret = fwu_accept_image(&full_capsule_image_guid, &_metadata,
-                                 &priv_metadata);
-+        if (!ret) {
-+            ret = update_nv_counters(&priv_metadata);
-+        }
-     }
- 
-     if (ret == FWU_AGENT_SUCCESS) {
-@@ -887,3 +945,40 @@ void host_acknowledgement_timer_to_reset(void)
-     FWU_LOG_MSG("%s: exit\n\r", __func__);
-     return;
- }
-+
-+/* stage nv counter into private metadata section of the flash.
-+ * staged nv counters are written to the otp when firmware update
-+ * is successful
-+ * the function assumes that the api is called in the boot loading
-+ * stage
-+ */
-+enum fwu_agent_error_t fwu_stage_nv_counter(enum fwu_nv_counter_index_t index,
-+        uint32_t img_security_cnt)
-+{
-+    struct fwu_private_metadata priv_metadata;
-+
-+    FWU_LOG_MSG("%s: enter: index = %u, val = %u\n\r", __func__,
-+                                index, img_security_cnt);
-+
-+    if (!is_initialized) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    if (index > FWU_MAX_NV_COUNTER_INDEX) {
-+        return FWU_AGENT_ERROR;
-+    }
-+
-+    if (private_metadata_read(&priv_metadata)) {
-+        FWU_ASSERT(0);
-+    }
-+
-+    if (priv_metadata.nv_counter[index] != img_security_cnt) {
-+        priv_metadata.nv_counter[index] = img_security_cnt;
-+        if (private_metadata_write(&priv_metadata)) {
-+            FWU_ASSERT(0);
-+        }
-+    }
-+
-+    FWU_LOG_MSG("%s: exit\n\r", __func__);
-+    return FWU_AGENT_SUCCESS;
-+}
-diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-index 80f72e2bd6..57b07e8d2c 100644
---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
-@@ -54,4 +54,20 @@ void bl2_get_boot_bank(uint32_t *bank_offset);
-  */
- void host_acknowledgement_timer_to_reset(void);
- 
-+enum fwu_nv_counter_index_t {
-+    FWU_BL2_NV_COUNTER = 0,
-+    FWU_TFM_NV_COUNTER,
-+    FWU_TFA_NV_COUNTER,
-+    FWU_MAX_NV_COUNTER_INDEX = FWU_TFA_NV_COUNTER
-+};
-+
-+/* stage nv counter into private metadata section of the flash.
-+ * staged nv counters are written to the otp when firmware update
-+ * is successful
-+ * the function assumes that the api is called in the boot loading
-+ * stage
-+ */
-+enum fwu_agent_error_t fwu_stage_nv_counter(enum fwu_nv_counter_index_t index,
-+        uint32_t img_security_cnt);
-+
- #endif /* FWU_AGENT_H */
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0014-corstone1000-bug-fix-in-openamp-version.patch

@@ -1,50 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From 55d0c63bf6b097b6853e93355f5a1524df56f47b Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Mon, 1 Nov 2021 08:03:42 +0000
-Subject: [PATCH 14/15] corstone1000: bug fix in openamp version
-
-Typing mistake in openamp version parameter, leads the cmake
-to fetch the head of the master branch.
-
-Also, the previous hash used for code version is deleted from the
-openamp github. New hash from the master branch is in use.
-
-Change-Id: Iee5980ba14f8bb9b964eb10c71ebb68664c1d441
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
----
- platform/ext/target/arm/corstone1000/config.cmake               | 2 +-
- .../arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt      | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
-index d6f3ef7d21..2dab210e0a 100644
---- a/platform/ext/target/arm/corstone1000/config.cmake
-+++ b/platform/ext/target/arm/corstone1000/config.cmake
-@@ -32,7 +32,7 @@ set(LIBMETAL_SRC_PATH                   "DOWNLOAD"  CACHE PATH      "Path to Lib
- set(LIBMETAL_VERSION                    "f252f0e007fbfb8b3a52b1d5901250ddac96baad"  CACHE STRING    "The version of libmetal to use")
- 
- set(LIBOPENAMP_SRC_PATH                 "DOWNLOAD"  CACHE PATH      "Path to Libopenamp (or DOWNLOAD to fetch automatically")
--set(OPENAMP_VERSION                     "33037b04e0732e58fc0fa36afc244999ef632e10"  CACHE STRING    "The version of openamp to use")
-+set(OPENAMP_VERSION                     "347397decaa43372fc4d00f965640ebde042966d"  CACHE STRING    "The version of openamp to use")
- 
- if (${PLATFORM_IS_FVP})
-     set(PLATFORM_PSA_ADAC_SECURE_DEBUG      FALSE        CACHE BOOL      "Whether to use psa-adac secure debug.")
-diff --git a/platform/ext/target/arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt b/platform/ext/target/arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt
-index d91dc7d845..9b1602a04f 100644
---- a/platform/ext/target/arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt
-+++ b/platform/ext/target/arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt
-@@ -16,7 +16,7 @@ endif()
- if ("${LIBOPENAMP_SRC_PATH}" STREQUAL "DOWNLOAD")
-     FetchContent_Declare(libopenamp
-         GIT_REPOSITORY https://github.com/OpenAMP/open-amp.git
--        GIT_TAG ${OEPNAMP_VERSION}
-+        GIT_TAG ${OPENAMP_VERSION}
-     )
- 
-     FetchContent_GetProperties(libopenamp)
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0015-corstone1000-secure-host-watchdog-interrupt-handler.patch

@@ -1,80 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
-
-From c33289422948ccb0bd6985512e5d0fc6936c0cd1 Mon Sep 17 00:00:00 2001
-From: Satish Kumar <satish.kumar01@arm.com>
-Date: Thu, 18 Nov 2021 12:49:10 +0000
-Subject: [PATCH 15/15] corstone1000: secure host watchdog interrupt handler
-
-With this commit, the host secure watchdog interrupt 1
-(WS1) will be handled by the secure enclave. The commit
-implements and enables the SECURE_WATCHDOG_WS1_IRQHandler
-in NVIC controller. The host can now trigger a reboot
-using the secure watchdog.
-
-Change-Id: Ied82cc04496f5daf678ad1cdc7bcf6d3a7879186
-Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
----
- .../arm/corstone1000/Native_Driver/watchdog.c   | 17 +++++++++++++++++
- .../arm/corstone1000/Native_Driver/watchdog.h   |  9 +++++++++
- .../target/arm/corstone1000/tfm_hal_platform.c  |  2 ++
- 3 files changed, 28 insertions(+)
-
-diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
-index d375af3afb..d7faa3067d 100644
---- a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
-+++ b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
-@@ -79,3 +79,20 @@ int corstone1000_watchdog_init()
-     
-     return ARM_DRIVER_OK;
- }
-+
-+/* Secure Host Watchdog WS1 Handler 
-+ * efi_reset_system from the host triggers "Secure 
-+ * watchdog WS1 interrupt" to reset the system. Host 
-+ * cannot access this interrupt by design, so SE 
-+ * resets the system using this handler
-+ * */ 
-+void SECURE_WATCHDOG_WS1_IRQHandler(void){
-+    NVIC_SystemReset();
-+}
-+
-+/*Enable Secure Watchdog WS1 Interrupt
-+ * in NVIC controller (asserted by host)*/
-+void corstone1000_host_watchdog_handler_init(){
-+    NVIC_EnableIRQ(SECURE_WATCHDOG_WS1_IRQn);
-+}
-+
-diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
-index fd1b7cf124..cd9bed3f63 100644
---- a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
-+++ b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
-@@ -29,4 +29,13 @@ int corstone1000_watchdog_init();
-  */
- int corstone1000_watchdog_reset_timer();
- 
-+/**
-+ *  \brief Initializes Interrupt Handler for
-+ *   Secure Host Watchdog (WS1).
-+ *
-+ *  \returns  VOID
-+ */
-+void corstone1000_host_watchdog_handler_init();
-+
-+
- #endif /* watchdog_h */
-diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
-index 7faa71eb63..e3c6b78950 100644
---- a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
-+++ b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
-@@ -24,5 +24,7 @@ enum tfm_hal_status_t tfm_hal_platform_init(void)
-         return TFM_HAL_ERROR_GENERIC;
-     }
- 
-+    corstone1000_host_watchdog_handler_init();
-+
-     return TFM_HAL_SUCCESS;
- }
--- 
-2.17.1
-

meta-arm-bsp/recipes-bsp/u-boot/u-boot-2020.07/juno/0002-configs-vexpress-modify-to-boot-compressed-initramfs.patch

@@ -0,0 +1,27 @@
+From 097a43223da4fa42335944295903ede2755e2dfd Mon Sep 17 00:00:00 2001
+From: Jon Mason <jdmason@kudzu.us>
+Date: Mon, 19 Dec 2022 11:36:04 -0500
+Subject: [PATCH] configs: vexpress: modify to boot compressed initramfs
+
+Signed-off-by: Jon Mason <jdmason@kudzu.us>
+Upstream-Status: Inappropriate
+---
+ include/configs/vexpress_aemv8a.h       | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8a.h
+index cd7f6c1b9ba0..c2f5eb302076 100644
+--- a/include/configs/vexpress_aemv8a.h
++++ b/include/configs/vexpress_aemv8a.h
+@@ -164,6 +164,8 @@
+ 				"kernel_name=norkern\0"	\
+ 				"kernel_alt_name=Image\0"	\
+ 				"kernel_addr_r=0x80080000\0" \
++				"kernel_comp_addr_r=0x90000000\0" \
++				"kernel_comp_size=0x3000000\0" \
+ 				"initrd_name=ramdisk.img\0"	\
+ 				"initrd_addr_r=0x88000000\0"	\
+ 				"fdtfile=board.dtb\0" \
+-- 
+2.30.2
+

meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0028-corstone1000-use-a-compressed-kernel.patch

@@ -0,0 +1,35 @@
+From 348cdb4bab63ad0a6b373396ad522f1bcc2d6bdb Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Mon, 17 Oct 2022 15:41:20 +0100
+Subject: [PATCH] corstone1000: use a compressed kernel
+
+The corstone1000 kernel has become too large to fit in the available
+storage.  Swtiching to a compressed kernel avoids the problem, but
+requires uncompressing it.  Add this decompression to the default boot
+instructions.
+
+Signed-off-by: Jon Mason <jon.mason@arm.com>
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Upstream-Status: Pending [Not submitted to upstream yet]
+
+---
+ include/configs/corstone1000.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index d9855bf91e..a66e3a8c10 100644
+--- a/include/configs/corstone1000.h
++++ b/include/configs/corstone1000.h
+@@ -126,7 +126,8 @@
+ #define CONFIG_BOOTCOMMAND								\
+ 				"run retrieve_kernel_load_addr;"			\
+ 				"echo Loading kernel from $kernel_addr to memory ... ;"	\
+-				"loadm $kernel_addr $kernel_addr_r 0xc00000;"		\
++				"unzip $kernel_addr 0x90000000;"                        \
++				"loadm 0x90000000 $kernel_addr_r 0xd00000;"		\
+ 				"usb start; usb reset;"					\
+ 				"run distro_bootcmd;"					\
+ 				"bootefi $kernel_addr_r $fdtcontroladdr;"
+-- 
+2.17.1
+

meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0014-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch

@@ -0,0 +1,105 @@
+From c4abb74e62817c5adf32c011db93f6bfc2deabaf Mon Sep 17 00:00:00 2001
+From: Peter Hoyes <Peter.Hoyes@arm.com>
+Date: Wed, 18 May 2022 15:24:19 +0100
+Subject: [PATCH 1/2] armv8: Allow PRBAR MPU attributes to be configured
+
+In a previous patch, support was added to initialize an S-EL2 MPU on
+armv8r64 machines. This implementation allowed the PRLAR attribute
+index to be configured, but not the shareability and access permission
+attributes in PRBAR. These attributes were hard-coded as "outer
+shareable" and "read/write at EL1 and EL0".
+
+Add separate prlar_attrs and prbar_attrs to the MPU region struct so
+that these attributes can be configured on a per-region basis.
+
+For the BASER_FVP, ensure the MPU memory attributes match those in the
+existing vexpress64 board MMU configuration ("non shareable" for device
+memory and "inner shareable" for normal memory).
+
+Issue-Id: SCM-4641
+Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
+Upstream-Status: Inappropriate [other]
+  Implementation pending further discussion
+Change-Id: I6b72aead91ad12412262aa32c61a53e12eab3984
+---
+ arch/arm/cpu/armv8/cache_v8.c        | 12 ++++++++----
+ arch/arm/include/asm/armv8/mpu.h     |  3 ++-
+ board/armltd/vexpress64/vexpress64.c |  9 ++++++---
+ 3 files changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
+index f6e0ad0075..981aca4a0f 100644
+--- a/arch/arm/cpu/armv8/cache_v8.c
++++ b/arch/arm/cpu/armv8/cache_v8.c
+@@ -370,7 +370,9 @@ static void mpu_clear_regions(void)
+ {
+ 	int i;
+ 
+-	for (i = 0; mpu_mem_map[i].end || mpu_mem_map[i].attrs; i++) {
++	for (i = 0; mpu_mem_map[i].end ||
++	     mpu_mem_map[i].prbar_attrs ||
++	     mpu_mem_map[i].prlar_attrs; i++) {
+ 		setup_el2_mpu_region(i, 0, 0);
+ 	}
+ }
+@@ -390,12 +392,14 @@ static void mpu_setup(void)
+ 
+ 	asm volatile("msr MAIR_EL2, %0" : : "r" MEMORY_ATTRIBUTES);
+ 
+-	for (i = 0; mpu_mem_map[i].end || mpu_mem_map[i].attrs; i++) {
++	for (i = 0; mpu_mem_map[i].end ||
++	     mpu_mem_map[i].prbar_attrs ||
++	     mpu_mem_map[i].prlar_attrs; i++) {
+ 		setup_el2_mpu_region(i,
+ 			PRBAR_ADDRESS(mpu_mem_map[i].start)
+-				| PRBAR_OUTER_SH | PRBAR_AP_RW_ANY,
++				| mpu_mem_map[i].prbar_attrs,
+ 			PRLAR_ADDRESS(mpu_mem_map[i].end)
+-				| mpu_mem_map[i].attrs | PRLAR_EN_BIT
++				| mpu_mem_map[i].prlar_attrs | PRLAR_EN_BIT
+ 			);
+ 	}
+ 
+diff --git a/arch/arm/include/asm/armv8/mpu.h b/arch/arm/include/asm/armv8/mpu.h
+index 8de627cafd..dd4c689ea6 100644
+--- a/arch/arm/include/asm/armv8/mpu.h
++++ b/arch/arm/include/asm/armv8/mpu.h
+@@ -51,7 +51,8 @@ static inline void setup_el2_mpu_region(uint8_t region, uint64_t base, uint64_t
+ struct mpu_region {
+ 	u64 start;
+ 	u64 end;
+-	u64 attrs;
++	u64 prbar_attrs;
++	u64 prlar_attrs;
+ };
+ 
+ extern struct mpu_region *mpu_mem_map;
+diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c
+index 3f1ac04bac..31ff2f7b2d 100644
+--- a/board/armltd/vexpress64/vexpress64.c
++++ b/board/armltd/vexpress64/vexpress64.c
+@@ -41,15 +41,18 @@ static struct mpu_region vexpress64_aemv8r_mem_map[] = {
+        {
+                .start = 0x0UL,
+                .end = 0x7fffffffUL,
+-               .attrs = PRLAR_ATTRIDX(MT_NORMAL)
++	       .prbar_attrs = PRBAR_INNER_SH | PRBAR_AP_RW_ANY,
++	       .prlar_attrs = PRLAR_ATTRIDX(MT_NORMAL)
+        }, {
+                .start = 0x80000000UL,
+                .end = 0xffffffffUL,
+-               .attrs = PRLAR_ATTRIDX(MT_DEVICE_NGNRNE)
++	       .prbar_attrs = PRBAR_OUTER_SH | PRBAR_AP_RW_ANY,
++	       .prlar_attrs = PRLAR_ATTRIDX(MT_DEVICE_NGNRNE)
+        }, {
+                .start = 0x100000000UL,
+                .end = 0xffffffffffUL,
+-               .attrs = PRLAR_ATTRIDX(MT_NORMAL)
++	       .prbar_attrs = PRBAR_INNER_SH | PRBAR_AP_RW_ANY,
++	       .prlar_attrs = PRLAR_ATTRIDX(MT_NORMAL)
+        }, {
+                /* List terminator */
+                0,
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0015-armv8-Enable-icache-when-switching-exception-levels-.patch

@@ -0,0 +1,63 @@
+From a5790fe98179b2490500cde629f7a48fbbe341df Mon Sep 17 00:00:00 2001
+From: Peter Hoyes <Peter.Hoyes@arm.com>
+Date: Thu, 19 May 2022 09:02:32 +0100
+Subject: [PATCH 2/2] armv8: Enable icache when switching exception levels in
+ bootefi
+
+bootefi calls the function switch_to_non_secure_mode before calling the
+UEFI payload to handle the case where U-Boot is running at EL3.
+
+For AArch64, the UEFI specification states that:
+   The core will be configured as follows:
+     * MMU enabled
+     * Instruction and data caches enabled
+
+These requirements should be followed when switching exception levels
+for EFI applications.
+
+This function already disables and re-enables the data cache prior to
+switching exception levels, but omits the instruction cache, meaning
+the function returns with the instruction cache disabled at the new
+exception level. Fix this by calling icache_disable prior to switching
+exception levels and icache_enable afterwards.
+
+Issue-Id: SCM-4641
+Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
+Upstream-Status: Inappropriate [other]
+  Implementation pending further discussion
+Change-Id: I678cd5ba39b56e124ab7854608289cd14651ce65
+---
+ arch/arm/cpu/armv8/exception_level.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/exception_level.c b/arch/arm/cpu/armv8/exception_level.c
+index 4aad1550f4..0a3e5428e7 100644
+--- a/arch/arm/cpu/armv8/exception_level.c
++++ b/arch/arm/cpu/armv8/exception_level.c
+@@ -27,6 +27,7 @@
+ static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
+ {
+ 	dcache_enable();
++	icache_enable();
+ 	debug("Reached non-secure mode\n");
+ 
+ 	/* Restore stack and registers saved in switch_to_non_secure_mode() */
+@@ -61,6 +62,7 @@ void switch_to_non_secure_mode(void)
+ 		if (setjmp(&non_secure_jmp))
+ 			return;
+ 		dcache_disable();	/* flush cache before switch to EL2 */
++		icache_disable();
+ 		/* Move into EL2 and keep running there */
+ 		armv8_switch_to_el2((uintptr_t)&non_secure_jmp, 0, 0, 0,
+ 				    (uintptr_t)entry_non_secure, ES_TO_AARCH64);
+@@ -68,6 +70,7 @@ void switch_to_non_secure_mode(void)
+ 		if (setjmp(&non_secure_jmp))
+ 			return;
+ 		dcache_disable();	/* flush cache before switch to EL1 */
++		icache_disable();
+ 		/* Move into EL1 and keep running there */
+ 		armv8_switch_to_el1((uintptr_t)&non_secure_jmp, 0, 0, 0,
+ 				    (uintptr_t)entry_non_secure, ES_TO_AARCH64);
+-- 
+2.25.1
+

meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend

@@ -44,6 +44,7 @@ SRC_URI:append:corstone1000 = " \
         file://0025-efi_loader-send-bootcomplete-message-to-secure-encla.patch \
         file://0026-efi_loader-fix-null-pointer-exception-with-get_image.patch \
         file://0027-arm-corstone1000-add-mmc-for-fvp.patch \
+        file://0028-corstone1000-use-a-compressed-kernel.patch \
       "
 
 #
@@ -73,6 +74,8 @@ SRC_URI:append:fvp-baser-aemv8r64 = " \
     file://0011-vexpress64-Add-BASER_FVP-vexpress-board-variant.patch \
     file://0012-vexpress64-Configure-memory-using-device-tree.patch \
     file://0013-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch \
+    file://0014-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch \
+    file://0015-armv8-Enable-icache-when-switching-exception-levels-.patch \
     "
 
 #

meta-arm-bsp/recipes-bsp/u-boot/u-boot_2020.07.bbappend

@@ -6,4 +6,7 @@ FILESEXTRAPATHS:prepend = "${THIS_DIR}/${BP}:"
 #
 # Juno KMACHINE
 #
-SRC_URI:append:juno = " file://u-boot_vexpress_uenv.patch"
+SRC_URI:append:juno = " \
+    file://u-boot_vexpress_uenv.patch \
+    file://0002-configs-vexpress-modify-to-boot-compressed-initramfs.patch \
+    "

meta-arm-bsp/recipes-bsp/uefi/edk2-firmware-n1sdp.inc

@@ -11,6 +11,12 @@ COMPATIBLE_MACHINE = "n1sdp"
 EFIDIR             = "/EFI/BOOT"
 EFI_BOOT_IMAGE     = "bootaa64.efi"
 
+FILESEXTRAPATHS:prepend := "${THISDIR}/files/edk2-platforms:"
+
+SRC_URI:append = "\
+    file://add-nt-fw-config.patch;patchdir=edk2-platforms \
+"
+
 do_deploy:append() {
     EFIPATH=$(echo "${EFIDIR}" | sed 's/\//\\/g')
     printf 'FS2:%s\%s\n' "$EFIPATH" "${EFI_BOOT_IMAGE}" > ${DEPLOYDIR}/startup.nsh

meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/add-nt-fw-config.patch

@@ -0,0 +1,474 @@
+From cc58709b32d74273736886ccfc08e4723a436ea4 Mon Sep 17 00:00:00 2001
+From: sahil <sahil@arm.com>
+Date: Thu, 17 Mar 2022 16:28:05 +0530
+Subject: [PATCH] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG
+
+NT_FW_CONFIG DTB contains platform information passed by
+Tf-A boot stage.
+This information is used for Virtual memory map generation
+during PEI phase and passed on to DXE phase as a HOB, where
+it is used in ConfigurationManagerDxe.
+
+Upstream-Status: Pending
+Signed-off-by: Adam Johnston <adam.johnston@arm.com>
+Signed-off-by: sahil <sahil@arm.com>
+Change-Id: Ib82571280bf1ca5febe5766e618de09e7b70bb02
+
+---
+ .../ConfigurationManager.c                    |  24 ++--
+ .../ConfigurationManagerDxe.inf               |   3 +-
+ .../ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h |  16 +--
+ .../Library/PlatformLib/AArch64/Helper.S      |   4 +-
+ .../Library/PlatformLib/PlatformLib.c         |  12 +-
+ .../Library/PlatformLib/PlatformLib.inf       |   8 +-
+ .../Library/PlatformLib/PlatformLibMem.c      | 103 +++++++++++++++++-
+ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec   |   7 +-
+ 8 files changed, 152 insertions(+), 25 deletions(-)
+
+diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+index f50623ae3f..e023d47cfd 100644
+--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+@@ -1,7 +1,7 @@
+ /** @file
+   Configuration Manager Dxe
+ 
+-  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
++  Copyright (c) 2021 - 2022, ARM Limited. All rights reserved.<BR>
+ 
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+ 
+@@ -16,6 +16,7 @@
+ #include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+ #include <Library/ArmLib.h>
+ #include <Library/DebugLib.h>
++#include <Library/HobLib.h>
+ #include <Library/IoLib.h>
+ #include <Library/PcdLib.h>
+ #include <Library/UefiBootServicesTableLib.h>
+@@ -28,6 +29,7 @@
+ #include "Platform.h"
+ 
+ extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat;
++static NEOVERSEN1SOC_PLAT_INFO *PlatInfo;
+ 
+ /** The platform configuration repository information.
+ */
+@@ -1242,13 +1244,11 @@ InitializePlatformRepository (
+   IN  EDKII_PLATFORM_REPOSITORY_INFO  * CONST PlatRepoInfo
+   )
+ {
+-  NEOVERSEN1SOC_PLAT_INFO       *PlatInfo;
+   UINT64                        Dram2Size;
+   UINT64                        RemoteDdrSize;
+ 
+   RemoteDdrSize = 0;
+ 
+-  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+   Dram2Size = ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB);
+ 
+   PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size;
+@@ -1512,7 +1512,6 @@ GetGicCInfo (
+   )
+ {
+   EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+-  NEOVERSEN1SOC_PLAT_INFO           *PlatInfo;
+   UINT32                            TotalObjCount;
+   UINT32                            ObjIndex;
+ 
+@@ -1523,7 +1522,6 @@ GetGicCInfo (
+   }
+ 
+   PlatformRepo = This->PlatRepoInfo;
+-  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+ 
+   if (PlatInfo->MultichipMode == 1) {
+     TotalObjCount = PLAT_CPU_COUNT * 2;
+@@ -1623,7 +1621,6 @@ GetStandardNameSpaceObject (
+ {
+   EFI_STATUS                        Status;
+   EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+-  NEOVERSEN1SOC_PLAT_INFO           *PlatInfo;
+   UINT32                            AcpiTableCount;
+ 
+   if ((This == NULL) || (CmObject == NULL)) {
+@@ -1634,7 +1631,7 @@ GetStandardNameSpaceObject (
+ 
+   Status = EFI_NOT_FOUND;
+   PlatformRepo = This->PlatRepoInfo;
+-  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
++
+   AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList);
+   if (PlatInfo->MultichipMode == 0)
+         AcpiTableCount -= 1;
+@@ -1697,7 +1694,6 @@ GetArmNameSpaceObject (
+ {
+   EFI_STATUS                        Status;
+   EDKII_PLATFORM_REPOSITORY_INFO  * PlatformRepo;
+-  NEOVERSEN1SOC_PLAT_INFO           *PlatInfo;
+   UINT32                            GicRedistCount;
+   UINT32                            GicCpuCount;
+   UINT32                            ProcHierarchyInfoCount;
+@@ -1718,8 +1714,6 @@ GetArmNameSpaceObject (
+   Status = EFI_NOT_FOUND;
+   PlatformRepo = This->PlatRepoInfo;
+ 
+-  // Probe for multi chip information
+-  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
+   if (PlatInfo->MultichipMode == 1) {
+     GicRedistCount = 2;
+     GicCpuCount = PLAT_CPU_COUNT * 2;
+@@ -2162,8 +2156,18 @@ ConfigurationManagerDxeInitialize (
+   IN EFI_SYSTEM_TABLE  * SystemTable
+   )
+ {
++  VOID *PlatInfoHob;
+   EFI_STATUS  Status;
+ 
++  PlatInfoHob = GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescriptorGuid);
++
++  if (PlatInfoHob == NULL) {
++    DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n"));
++    return EFI_NOT_FOUND;
++  }
++
++  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob);
++
+   // Initialize the Platform Configuration Repository before installing the
+   // Configuration Manager Protocol
+   Status = InitializePlatformRepository (
+diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+index 4f8e7f1302..fb59c29501 100644
+--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+@@ -1,7 +1,7 @@
+ ## @file
+ #  Configuration Manager Dxe
+ #
+-#  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
++#  Copyright (c) 2021 - 2022, ARM Limited. All rights reserved.<BR>
+ #
+ #  SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -42,6 +42,7 @@
+ 
+ [LibraryClasses]
+   ArmPlatformLib
++  HobLib
+   PrintLib
+   UefiBootServicesTableLib
+   UefiDriverEntryPoint
+diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
+index 097160c7e2..63cebaf0e0 100644
+--- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
++++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
+@@ -1,6 +1,6 @@
+ /** @file
+ *
+-* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
++* Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+@@ -41,11 +41,6 @@
+ #define NEOVERSEN1SOC_EXP_PERIPH_BASE0               0x1C000000
+ #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ            0x1300000
+ 
+-// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is
+-// pre-populated by a earlier boot stage
+-#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE          (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \
+-                                                      0x00008000)
+-
+ /*
+  * Platform information structure stored in Non-secure SRAM. Platform
+  * information are passed from the trusted firmware with the below structure
+@@ -55,12 +50,17 @@
+ typedef struct {
+   /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */
+   UINT8   MultichipMode;
+-  /*! Slave count in C2C mode */
+-  UINT8   SlaveCount;
++  /*! Secondary chip count in C2C mode */
++  UINT8   SecondaryChipCount;
+   /*! Local DDR memory size in GigaBytes */
+   UINT8   LocalDdrSize;
+   /*! Remote DDR memory size in GigaBytes */
+   UINT8   RemoteDdrSize;
+ } NEOVERSEN1SOC_PLAT_INFO;
+ 
++// NT_FW_CONFIG DT structure
++typedef struct {
++  UINT64                  NtFwConfigDtAddr;
++} NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI;
++
+ #endif
+diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
+index 8d2069dea8..88ed640d29 100644
+--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
+@@ -1,6 +1,6 @@
+ /** @file
+ *
+-*  Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
++*  Copyright (c) 2019 - 2022, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+@@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+ // the UEFI firmware through the CPU registers.
+ //
+ ASM_PFX(ArmPlatformPeiBootAction):
++  adr  x10, NtFwConfigDtBlob
++  str  x0, [x10]
+   ret
+ 
+ //
+diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
+index c0effd37f3..fabe902cd0 100644
+--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
+@@ -1,6 +1,6 @@
+ /** @file
+ 
+-  Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
++  Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.<BR>
+ 
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+ 
+@@ -8,8 +8,12 @@
+ 
+ #include <Library/ArmPlatformLib.h>
+ #include <Library/BaseLib.h>
++#include <NeoverseN1Soc.h>
+ #include <Ppi/ArmMpCoreInfo.h>
+ 
++UINT64 NtFwConfigDtBlob;
++STATIC NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI mNtFwConfigDtInfoPpi;
++
+ STATIC ARM_CORE_INFO mCoreInfoTable[] = {
+   { 0x0, 0x0 }, // Cluster 0, Core 0
+   { 0x0, 0x1 }, // Cluster 0, Core 1
+@@ -46,6 +50,7 @@ ArmPlatformInitialize (
+   IN     UINTN                  MpId
+   )
+ {
++  mNtFwConfigDtInfoPpi.NtFwConfigDtAddr = NtFwConfigDtBlob;
+   return RETURN_SUCCESS;
+ }
+ 
+@@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+     EFI_PEI_PPI_DESCRIPTOR_PPI,
+     &gArmMpCoreInfoPpiGuid,
+     &mMpCoreInfoPpi
++  },
++  {
++    EFI_PEI_PPI_DESCRIPTOR_PPI,
++    &gNtFwConfigDtInfoPpiGuid,
++    &mNtFwConfigDtInfoPpi
+   }
+ };
+ 
+diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+index 96e590cdd8..6f9c9d5ab6 100644
+--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+@@ -1,7 +1,7 @@
+ ## @file
+ #  Platform Library for N1Sdp.
+ #
+-#  Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
++#  Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.<BR>
+ #
+ #  SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -18,10 +18,14 @@
+ [Packages]
+   ArmPkg/ArmPkg.dec
+   ArmPlatformPkg/ArmPlatformPkg.dec
++  EmbeddedPkg/EmbeddedPkg.dec
+   MdeModulePkg/MdeModulePkg.dec
+   MdePkg/MdePkg.dec
+   Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+ 
++[LibraryClasses]
++  FdtLib
++
+ [Sources.common]
+   PlatformLibMem.c
+   PlatformLib.c
+@@ -59,7 +63,9 @@
+   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ 
+ [Guids]
++  gArmNeoverseN1SocPlatformInfoDescriptorGuid
+   gEfiHobListGuid          ## CONSUMES  ## SystemTable
+ 
+ [Ppis]
+   gArmMpCoreInfoPpiGuid
++  gNtFwConfigDtInfoPpiGuid
+diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+index 339fa07b32..b58bda4b76 100644
+--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+@@ -1,6 +1,6 @@
+ /** @file
+ 
+-  Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
++  Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.<BR>
+ 
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+ 
+@@ -10,11 +10,95 @@
+ #include <Library/DebugLib.h>
+ #include <Library/HobLib.h>
+ #include <Library/MemoryAllocationLib.h>
++#include <Library/PeiServicesLib.h>
++#include <libfdt.h>
+ #include <NeoverseN1Soc.h>
+ 
+ // The total number of descriptors, including the final "end-of-table" descriptor.
+ #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19
+ 
++/** A helper function to locate the NtFwConfig PPI and get the base address of
++  NT_FW_CONFIG DT from which values are obtained using FDT helper functions.
++
++  @param [out]  plat_info  Pointer to the NeoverseN1Soc PLATFORM_INFO HOB
++
++  @retval EFI_SUCCESS            Success.
++  returns EFI_INVALID_PARAMETER  A parameter is invalid.
++**/
++EFI_STATUS
++GetNeoverseN1SocPlatInfo (
++  OUT NEOVERSEN1SOC_PLAT_INFO *plat_info
++  )
++{
++  CONST UINT32                   *Property;
++  INT32                          Offset;
++  CONST VOID                     *NtFwCfgDtBlob;
++  NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI  *NtFwConfigInfoPpi;
++  EFI_STATUS                     Status;
++
++  Status = PeiServicesLocatePpi (
++             &gNtFwConfigDtInfoPpiGuid,
++             0,
++             NULL,
++             (VOID **)&NtFwConfigInfoPpi
++             );
++
++  if (EFI_ERROR (Status)) {
++    DEBUG ((
++      DEBUG_ERROR,
++      "PeiServicesLocatePpi failed with error %r\n",
++      Status
++      ));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  NtFwCfgDtBlob = (VOID *)(UINTN)NtFwConfigInfoPpi->NtFwConfigDtAddr;
++  if (fdt_check_header (NtFwCfgDtBlob) != 0) {
++    DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", NtFwCfgDtBlob));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Offset = fdt_subnode_offset (NtFwCfgDtBlob, 0, "platform-info");
++  if (Offset == -FDT_ERR_NOTFOUND) {
++    DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n"));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Property = fdt_getprop (NtFwCfgDtBlob, Offset, "local-ddr-size", NULL);
++  if (Property == NULL) {
++    DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n"));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  plat_info->LocalDdrSize = fdt32_to_cpu (*Property);
++
++  Property = fdt_getprop (NtFwCfgDtBlob, Offset, "remote-ddr-size", NULL);
++  if (Property == NULL) {
++    DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n"));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  plat_info->RemoteDdrSize = fdt32_to_cpu (*Property);
++
++  Property = fdt_getprop (NtFwCfgDtBlob, Offset, "secondary-chip-count", NULL);
++  if (Property == NULL) {
++    DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n"));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  plat_info->SecondaryChipCount = fdt32_to_cpu (*Property);
++
++  Property = fdt_getprop (NtFwCfgDtBlob, Offset, "multichip-mode", NULL);
++  if (Property == NULL) {
++    DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n"));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  plat_info->MultichipMode = fdt32_to_cpu (*Property);
++
++  return EFI_SUCCESS;
++}
++
+ /**
+   Returns the Virtual Memory Map of the platform.
+ 
+@@ -36,9 +120,24 @@ ArmPlatformGetVirtualMemoryMap (
+   NEOVERSEN1SOC_PLAT_INFO       *PlatInfo;
+   UINT64                        DramBlock2Size;
+   UINT64                        RemoteDdrSize;
++  EFI_STATUS                    Status;
+ 
+   Index = 0;
+-  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE;
++
++  // Create platform info HOB
++  PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)BuildGuidHob (
++                                        &gArmNeoverseN1SocPlatformInfoDescriptorGuid,
++                                        sizeof (NEOVERSEN1SOC_PLAT_INFO)
++                                        );
++
++  if (PlatInfo == NULL) {
++    DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n"));
++    ASSERT (FALSE);
++    return;
++  }
++
++  Status = GetNeoverseN1SocPlatInfo (PlatInfo);
++  ASSERT (Status == 0);
+   DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize -
+                              NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) *
+                             (UINT64)SIZE_1GB);
+diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+index d59f25a5b9..4dea8fe1e8 100644
+--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
++++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+@@ -1,7 +1,7 @@
+ ## @file
+ #  Describes the entire platform configuration.
+ #
+-#  Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
++#  Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.<BR>
+ #
+ #  SPDX-License-Identifier: BSD-2-Clause-Patent
+ #
+@@ -22,6 +22,8 @@
+   Include                        # Root include for the package
+ 
+ [Guids.common]
++  # ARM NeoverseN1Soc Platform Info descriptor
++  gArmNeoverseN1SocPlatformInfoDescriptorGuid = { 0x095cb024, 0x1e00, 0x4d6f, { 0xaa, 0x34, 0x4a, 0xf8, 0xaf, 0x0e, 0xad, 0x99 } }
+   gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } }
+ 
+ [PcdsFixedAtBuild]
+@@ -83,3 +85,6 @@
+   gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F
+   gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
+   gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
++
++[Ppis]
++  gNtFwConfigDtInfoPpiGuid =  { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } }
+-- 
+2.17.1
+

meta-arm-bsp/recipes-kernel/linux/files/fvp-baser-aemv8r64/fvp-baser-aemv8r64.dts

@@ -186,7 +186,7 @@
                 interrupts = <0x1 13 0xff08>,
                              <0x1 14 0xff08>,
                              <0x1 11 0xff08>,
-                             <0x1 10 0xff08>;
+                             <0x1  4 0xff08>;
                 clock-frequency = <100000000>;
         };
 

meta-arm-bsp/recipes-kernel/linux/files/juno/juno-dts-mhu-doorbell.patch

@@ -21,10 +21,10 @@ Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
  5 files changed, 96 insertions(+), 85 deletions(-)
 
 diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
-index 6288e104a089..36844f7d861e 100644
+index a00b0f14c222..8da7fe6fd157 100644
 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi
 +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
-@@ -23,11 +23,12 @@ frame@2a830000 {
+@@ -23,12 +23,13 @@ frame@2a830000 {
  	};
  
  	mailbox: mhu@2b1f0000 {
@@ -32,14 +32,15 @@ index 6288e104a089..36844f7d861e 100644
 +		compatible = "arm,mhu-doorbell", "arm,primecell";
  		reg = <0x0 0x2b1f0000 0x0 0x1000>;
  		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
- 			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ 			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ 			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 -		#mbox-cells = <1>;
 +		#mbox-cells = <2>;
 +		mbox-name = "ARM-MHU";
  		clocks = <&soc_refclk100mhz>;
  		clock-names = "apb_pclk";
  	};
-@@ -39,7 +40,7 @@ smmu_gpu: iommu@2b400000 {
+@@ -40,7 +41,7 @@ smmu_gpu: iommu@2b400000 {
  			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  		#iommu-cells = <1>;
  		#global-interrupts = <1>;
@@ -48,7 +49,7 @@ index 6288e104a089..36844f7d861e 100644
  		dma-coherent;
  		status = "disabled";
  	};
-@@ -63,7 +64,7 @@ smmu_etr: iommu@2b600000 {
+@@ -64,7 +65,7 @@ smmu_etr: iommu@2b600000 {
  		#iommu-cells = <1>;
  		#global-interrupts = <1>;
  		dma-coherent;
@@ -57,7 +58,7 @@ index 6288e104a089..36844f7d861e 100644
  	};
  
  	gic: interrupt-controller@2c010000 {
-@@ -123,7 +124,7 @@ etf@20010000 { /* etf0 */
+@@ -124,7 +125,7 @@ etf@20010000 { /* etf0 */
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -66,7 +67,7 @@ index 6288e104a089..36844f7d861e 100644
  
  		in-ports {
  			port {
-@@ -147,7 +148,7 @@ tpiu@20030000 {
+@@ -148,7 +149,7 @@ tpiu@20030000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -75,7 +76,7 @@ index 6288e104a089..36844f7d861e 100644
  		in-ports {
  			port {
  				tpiu_in_port: endpoint {
-@@ -164,7 +165,7 @@ main_funnel: funnel@20040000 {
+@@ -165,7 +166,7 @@ main_funnel: funnel@20040000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -84,7 +85,7 @@ index 6288e104a089..36844f7d861e 100644
  
  		out-ports {
  			port {
-@@ -201,7 +202,7 @@ etr@20070000 {
+@@ -202,7 +203,7 @@ etr@20070000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -93,7 +94,7 @@ index 6288e104a089..36844f7d861e 100644
  		arm,scatter-gather;
  		in-ports {
  			port {
-@@ -220,7 +221,7 @@ stm@20100000 {
+@@ -221,7 +222,7 @@ stm@20100000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -102,7 +103,7 @@ index 6288e104a089..36844f7d861e 100644
  		out-ports {
  			port {
  				stm_out_port: endpoint {
-@@ -235,7 +236,7 @@ replicator@20120000 {
+@@ -236,7 +237,7 @@ replicator@20120000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -111,7 +112,7 @@ index 6288e104a089..36844f7d861e 100644
  
  		out-ports {
  			#address-cells = <1>;
-@@ -270,7 +271,7 @@ cpu_debug0: cpu-debug@22010000 {
+@@ -271,7 +272,7 @@ cpu_debug0: cpu-debug@22010000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -120,7 +121,7 @@ index 6288e104a089..36844f7d861e 100644
  	};
  
  	etm0: etm@22040000 {
-@@ -279,7 +280,7 @@ etm0: etm@22040000 {
+@@ -280,7 +281,7 @@ etm0: etm@22040000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -129,7 +130,7 @@ index 6288e104a089..36844f7d861e 100644
  		out-ports {
  			port {
  				cluster0_etm0_out_port: endpoint {
-@@ -295,7 +296,7 @@ funnel@220c0000 { /* cluster0 funnel */
+@@ -296,7 +297,7 @@ funnel@220c0000 { /* cluster0 funnel */
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -138,7 +139,7 @@ index 6288e104a089..36844f7d861e 100644
  		out-ports {
  			port {
  				cluster0_funnel_out_port: endpoint {
-@@ -330,7 +331,7 @@ cpu_debug1: cpu-debug@22110000 {
+@@ -331,7 +332,7 @@ cpu_debug1: cpu-debug@22110000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -147,7 +148,7 @@ index 6288e104a089..36844f7d861e 100644
  	};
  
  	etm1: etm@22140000 {
-@@ -339,7 +340,7 @@ etm1: etm@22140000 {
+@@ -340,7 +341,7 @@ etm1: etm@22140000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -156,7 +157,7 @@ index 6288e104a089..36844f7d861e 100644
  		out-ports {
  			port {
  				cluster0_etm1_out_port: endpoint {
-@@ -355,7 +356,7 @@ cpu_debug2: cpu-debug@23010000 {
+@@ -356,7 +357,7 @@ cpu_debug2: cpu-debug@23010000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -165,7 +166,7 @@ index 6288e104a089..36844f7d861e 100644
  	};
  
  	etm2: etm@23040000 {
-@@ -364,7 +365,7 @@ etm2: etm@23040000 {
+@@ -365,7 +366,7 @@ etm2: etm@23040000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -174,7 +175,7 @@ index 6288e104a089..36844f7d861e 100644
  		out-ports {
  			port {
  				cluster1_etm0_out_port: endpoint {
-@@ -380,7 +381,7 @@ funnel@230c0000 { /* cluster1 funnel */
+@@ -381,7 +382,7 @@ funnel@230c0000 { /* cluster1 funnel */
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -183,7 +184,7 @@ index 6288e104a089..36844f7d861e 100644
  		out-ports {
  			port {
  				cluster1_funnel_out_port: endpoint {
-@@ -427,7 +428,7 @@ cpu_debug3: cpu-debug@23110000 {
+@@ -428,7 +429,7 @@ cpu_debug3: cpu-debug@23110000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -192,7 +193,7 @@ index 6288e104a089..36844f7d861e 100644
  	};
  
  	etm3: etm@23140000 {
-@@ -436,7 +437,7 @@ etm3: etm@23140000 {
+@@ -437,7 +438,7 @@ etm3: etm@23140000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -201,7 +202,7 @@ index 6288e104a089..36844f7d861e 100644
  		out-ports {
  			port {
  				cluster1_etm1_out_port: endpoint {
-@@ -452,7 +453,7 @@ cpu_debug4: cpu-debug@23210000 {
+@@ -453,7 +454,7 @@ cpu_debug4: cpu-debug@23210000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -210,7 +211,7 @@ index 6288e104a089..36844f7d861e 100644
  	};
  
  	etm4: etm@23240000 {
-@@ -461,7 +462,7 @@ etm4: etm@23240000 {
+@@ -462,7 +463,7 @@ etm4: etm@23240000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -219,7 +220,7 @@ index 6288e104a089..36844f7d861e 100644
  		out-ports {
  			port {
  				cluster1_etm2_out_port: endpoint {
-@@ -477,7 +478,7 @@ cpu_debug5: cpu-debug@23310000 {
+@@ -478,7 +479,7 @@ cpu_debug5: cpu-debug@23310000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -228,7 +229,7 @@ index 6288e104a089..36844f7d861e 100644
  	};
  
  	etm5: etm@23340000 {
-@@ -486,7 +487,7 @@ etm5: etm@23340000 {
+@@ -487,7 +488,7 @@ etm5: etm@23340000 {
  
  		clocks = <&soc_smc50mhz>;
  		clock-names = "apb_pclk";
@@ -237,7 +238,7 @@ index 6288e104a089..36844f7d861e 100644
  		out-ports {
  			port {
  				cluster1_etm3_out_port: endpoint {
-@@ -503,8 +504,8 @@ gpu: gpu@2d000000 {
+@@ -504,8 +505,8 @@ gpu: gpu@2d000000 {
  			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  			     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  		interrupt-names = "job", "mmu", "gpu";
@@ -248,7 +249,7 @@ index 6288e104a089..36844f7d861e 100644
  		dma-coherent;
  		/* The SMMU is only really of interest to bare-metal hypervisors */
  		/* iommus = <&smmu_gpu 0>; */
-@@ -519,14 +520,24 @@ sram: sram@2e000000 {
+@@ -520,14 +521,24 @@ sram: sram@2e000000 {
  		#size-cells = <1>;
  		ranges = <0 0x0 0x2e000000 0x8000>;
  
@@ -341,21 +342,25 @@ index 6288e104a089..36844f7d861e 100644
  		};
  	};
  
-@@ -596,40 +607,40 @@ thermal-zones {
+@@ -596,7 +607,7 @@ thermal-zones {
  		pmic {
  			polling-delay = <1000>;
  			polling-delay-passive = <100>;
 -			thermal-sensors = <&scpi_sensors0 0>;
 +			thermal-sensors = <&scmi_sensors0 0>;
- 		};
- 
+ 			trips {
+ 				pmic_crit0: trip0 {
+ 					temperature = <90000>;
+@@ -609,7 +620,7 @@ pmic_crit0: trip0 {
  		soc {
  			polling-delay = <1000>;
  			polling-delay-passive = <100>;
 -			thermal-sensors = <&scpi_sensors0 3>;
 +			thermal-sensors = <&scmi_sensors0 3>;
- 		};
- 
+ 			trips {
+ 				soc_crit0: trip0 {
+ 					temperature = <80000>;
+@@ -622,28 +633,28 @@ soc_crit0: trip0 {
  		big_cluster_thermal_zone: big-cluster {
  			polling-delay = <1000>;
  			polling-delay-passive = <100>;
@@ -388,7 +393,7 @@ index 6288e104a089..36844f7d861e 100644
  			status = "disabled";
  		};
  	};
-@@ -705,7 +716,7 @@ hdlcd@7ff50000 {
+@@ -719,7 +730,7 @@ hdlcd@7ff50000 {
  		reg = <0 0x7ff50000 0 0x1000>;
  		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
  		iommus = <&smmu_hdlcd1 0>;
@@ -397,7 +402,7 @@ index 6288e104a089..36844f7d861e 100644
  		clock-names = "pxlclk";
  
  		port {
-@@ -720,7 +731,7 @@ hdlcd@7ff60000 {
+@@ -734,7 +745,7 @@ hdlcd@7ff60000 {
  		reg = <0 0x7ff60000 0 0x1000>;
  		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  		iommus = <&smmu_hdlcd0 0>;
@@ -612,5 +617,5 @@ index f00cffbd032c..a28316c65c1b 100644
  			capacity-dmips-mhz = <578>;
  			dynamic-power-coefficient = <140>;
 -- 
-2.25.1
+2.30.2
 

meta-arm-bsp/recipes-kernel/linux/linux-yocto-5.15/n1sdp/0001-iommu-arm-smmu-v3-workaround-for-ATC_INV_SIZE_ALL-in.patch

@@ -1,11 +1,7 @@
-Upstream-Status: Inappropriate [Workaround]
-Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
-
-From 949ba3f12ec1f3177a82a9228dc402ab5d8c9d60 Mon Sep 17 00:00:00 2001
+From f88153a427046f92d52694708adc5ee0eefa8d55 Mon Sep 17 00:00:00 2001
 From: Manoj Kumar <manoj.kumar3@arm.com>
 Date: Mon, 1 Feb 2021 21:36:43 +0530
-Subject: [PATCH 1/5] iommu/arm-smmu-v3: workaround for ATC_INV_SIZE_ALL in
- N1SDP
+Subject: [PATCH] iommu/arm-smmu-v3: workaround for ATC_INV_SIZE_ALL in N1SDP
 
 ATC_INV_SIZE_ALL request should automatically translate to ATS
 address which is not happening in SMMUv3 version gone into
@@ -15,16 +11,19 @@ field to proper value for ATC_INV_SIZE_ALL command.
 Change-Id: If89465be94720a62be85e1e6612f17e93fa9b8a5
 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
 Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
+
+Upstream-Status: Inappropriate [Workaround]
+Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
 ---
  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 +
  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 +
  2 files changed, 2 insertions(+)
 
 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
-index a388e318f86e..ceca576b0bf6 100644
+index 79edfdca6607..ded17e199ee4 100644
 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
 +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
-@@ -1724,6 +1724,7 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,
+@@ -1725,6 +1725,7 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,
  	};
  
  	if (!size) {
@@ -44,6 +43,3 @@ index 4cb136f07914..5615ffd24e46 100644
  		struct {
  			u32			sid;
  			u32			ssid;
--- 
-2.17.1
-

meta-arm-bsp/recipes-kernel/linux/linux-yocto-5.15/n1sdp/0002-n1sdp-pci_quirk-add-acs-override-for-PCI-devices.patch

@@ -1,26 +1,26 @@
-Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
-Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
-
-From e47ab593ee36b2480f8c2196722cded42749629a Mon Sep 17 00:00:00 2001
+From 478d96ce8a4d30ef80975271a2ad89a77012c1b8 Mon Sep 17 00:00:00 2001
 From: Manoj Kumar <manoj.kumar3@arm.com>
 Date: Tue, 31 Aug 2021 16:15:38 +0000
-Subject: [PATCH 2/5] n1sdp: pci_quirk: add acs override for PCI devices
+Subject: [PATCH] n1sdp: pci_quirk: add acs override for PCI devices
 
 Patch taken from:
 https://gitlab.com/Queuecumber/linux-acs-override/raw/master/workspaces/5.4/acso.patch
 
 Change-Id: Ib926bf50524ce9990fbaa2f2f8670fe84bd571f9
 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
+
+Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
+Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
 ---
  .../admin-guide/kernel-parameters.txt         |   8 ++
  drivers/pci/quirks.c                          | 102 ++++++++++++++++++
  2 files changed, 110 insertions(+)
 
 diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
-index 43dc35fe5bc0..a60e454854d7 100644
+index 4445baac48c1..ee90aeeb1dbb 100644
 --- a/Documentation/admin-guide/kernel-parameters.txt
 +++ b/Documentation/admin-guide/kernel-parameters.txt
-@@ -3892,6 +3892,14 @@
+@@ -3935,6 +3935,14 @@
  		nomsi		[MSI] If the PCI_MSI kernel config parameter is
  				enabled, this kernel boot option can be used to
  				disable the use of MSI interrupts system-wide.
@@ -36,10 +36,10 @@ index 43dc35fe5bc0..a60e454854d7 100644
  				Safety option to keep boot IRQs enabled. This
  				should never be necessary.
 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
-index 4537d1ea14fd..984f30d25a6d 100644
+index a531064233f9..ebe192134a97 100644
 --- a/drivers/pci/quirks.c
 +++ b/drivers/pci/quirks.c
-@@ -3588,6 +3588,107 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
+@@ -3600,6 +3600,107 @@ static void quirk_no_bus_reset(struct pci_dev *dev)
  	dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
  }
  
@@ -147,14 +147,11 @@ index 4537d1ea14fd..984f30d25a6d 100644
  /*
   * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
   * prevented for those affected devices.
-@@ -4949,6 +5050,7 @@ static const struct pci_dev_acs_enabled {
- 	{ PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
- 	/* Zhaoxin Root/Downstream Ports */
+@@ -4968,6 +5069,7 @@ static const struct pci_dev_acs_enabled {
  	{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
+ 	/* Wangxun nics */
+ 	{ PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
 +	{ PCI_ANY_ID, PCI_ANY_ID, pcie_acs_overrides },
  	{ 0 }
  };
  
--- 
-2.17.1
-

meta-arm-bsp/recipes-kernel/linux/linux-yocto-5.15/n1sdp/0003-pcie-Add-quirk-for-the-Arm-Neoverse-N1SDP-platform.patch

@@ -1,10 +1,7 @@
-Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
-Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
-
-From 63ee3a71eeb778a632f5683f3b9e404a70760e75 Mon Sep 17 00:00:00 2001
+From 4877796976647a24a3a9102facd0577586f5ac9a Mon Sep 17 00:00:00 2001
 From: Deepak Pandey <Deepak.Pandey@arm.com>
 Date: Fri, 31 May 2019 16:42:43 +0100
-Subject: [PATCH 3/5] pcie: Add quirk for the Arm Neoverse N1SDP platform
+Subject: [PATCH] pcie: Add quirk for the Arm Neoverse N1SDP platform
 
 The Arm N1SDP SoC suffers from some PCIe integration issues, most
 prominently config space accesses to not existing BDFs being answered
@@ -27,6 +24,9 @@ Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
 Signed-off-by: Sudipto Paul <sudipto.paul@arm.com>
 [Andre: fix coding style issues, rewrite some parts, add DT support]
 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+
+Upstream-Status: Inappropriate [will not be submitted as its a workaround to address hardware issue]
+Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
 ---
  arch/arm64/configs/defconfig        |   1 +
  drivers/acpi/pci_mcfg.c             |   7 +
@@ -38,10 +38,10 @@ Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  create mode 100644 drivers/pci/controller/pcie-n1sdp.c
 
 diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index 545197bc0501..57ae850ccdf0 100644
+index c27d0fed2ce2..70ed38cecee9 100644
 --- a/arch/arm64/configs/defconfig
 +++ b/arch/arm64/configs/defconfig
-@@ -212,6 +212,7 @@ CONFIG_NFC_NCI=m
+@@ -209,6 +209,7 @@ CONFIG_NFC_NCI=m
  CONFIG_NFC_S3FWRN5_I2C=m
  CONFIG_PCI=y
  CONFIG_PCIEPORTBUS=y
@@ -50,23 +50,23 @@ index 545197bc0501..57ae850ccdf0 100644
  CONFIG_PCI_PASID=y
  CONFIG_HOTPLUG_PCI=y
 diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
-index 53cab975f612..f31727da21ac 100644
+index 63b98eae5e75..67c34e6c24a7 100644
 --- a/drivers/acpi/pci_mcfg.c
 +++ b/drivers/acpi/pci_mcfg.c
-@@ -169,6 +169,13 @@ static struct mcfg_fixup mcfg_quirks[] = {
- 	ALTRA_ECAM_QUIRK(1, 13),
- 	ALTRA_ECAM_QUIRK(1, 14),
- 	ALTRA_ECAM_QUIRK(1, 15),
-+
+@@ -152,6 +152,13 @@ static struct mcfg_fixup mcfg_quirks[] = {
+ 	XGENE_V2_ECAM_MCFG(4, 1),
+ 	XGENE_V2_ECAM_MCFG(4, 2),
+ 
 +#define N1SDP_ECAM_MCFG(rev, seg, ops) \
 +	{"ARMLTD", "ARMN1SDP", rev, seg, MCFG_BUS_ANY, ops }
 +
 +	/* N1SDP SoC with v1 PCIe controller */
 +	N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
 +	N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
- };
++
+ #define ALTRA_ECAM_QUIRK(rev, seg) \
+ 	{ "Ampere", "Altra   ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
  
- static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
 diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
 index 326f7d13024f..f9700d037c46 100644
 --- a/drivers/pci/controller/Kconfig
@@ -318,6 +318,3 @@ index adea5a4771cf..e6bbc037cef8 100644
  #endif
  
  #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
--- 
-2.17.1
-

meta-arm-bsp/recipes-kernel/linux/linux-yocto-5.15/n1sdp/0004-n1sdp-pcie-add-quirk-support-enabling-remote-chip-PC.patch

@@ -1,10 +1,7 @@
-Upstream-Status: Inappropriate [will not be submitted as its an hack required to fix the hardware issue]
-Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
-
-From 4d69e38213bf52a48f2f0239da8c7b76501428b2 Mon Sep 17 00:00:00 2001
+From 7a5147f51f2eb80ecb6f62a28b8bd86aa5ceebf7 Mon Sep 17 00:00:00 2001
 From: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
 Date: Wed, 9 Feb 2022 20:37:43 +0530
-Subject: [PATCH 4/5] n1sdp: pcie: add quirk support enabling remote chip PCIe
+Subject: [PATCH] n1sdp: pcie: add quirk support enabling remote chip PCIe
 
 Base address mapping for remote chip Root PCIe ECAM space.
 
@@ -19,6 +16,9 @@ Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
 Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
 Signed-off-by: sahil <sahil@arm.com>
+
+Upstream-Status: Inappropriate [will not be submitted as its an hack required to fix the hardware issue]
+Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
 ---
  drivers/acpi/pci_mcfg.c             |  1 +
  drivers/pci/controller/pcie-n1sdp.c | 32 +++++++++++++++++++++++++----
@@ -26,17 +26,17 @@ Signed-off-by: sahil <sahil@arm.com>
  3 files changed, 30 insertions(+), 4 deletions(-)
 
 diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
-index f31727da21ac..58f59b5fffa2 100644
+index 67c34e6c24a7..4584a5a2ca20 100644
 --- a/drivers/acpi/pci_mcfg.c
 +++ b/drivers/acpi/pci_mcfg.c
-@@ -176,6 +176,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
+@@ -158,6 +158,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
  	/* N1SDP SoC with v1 PCIe controller */
  	N1SDP_ECAM_MCFG(0x20181101, 0, &pci_n1sdp_pcie_ecam_ops),
  	N1SDP_ECAM_MCFG(0x20181101, 1, &pci_n1sdp_ccix_ecam_ops),
 +	N1SDP_ECAM_MCFG(0x20181101, 2, &pci_n1sdp_remote_pcie_ecam_ops),
- };
  
- static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
+ #define ALTRA_ECAM_QUIRK(rev, seg) \
+ 	{ "Ampere", "Altra   ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
 diff --git a/drivers/pci/controller/pcie-n1sdp.c b/drivers/pci/controller/pcie-n1sdp.c
 index 408699b9dcb1..a03665dd056a 100644
 --- a/drivers/pci/controller/pcie-n1sdp.c
@@ -121,17 +121,14 @@ index 408699b9dcb1..a03665dd056a 100644
  	{ .compatible = "arm,n1sdp-pcie", .data = &pci_n1sdp_pcie_ecam_ops },
  	{ },
 diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
-index e6bbc037cef8..7bd8c1d702ee 100644
+index e6bbc037cef8..d936d3f14bce 100644
 --- a/include/linux/pci-ecam.h
 +++ b/include/linux/pci-ecam.h
-@@ -89,6 +89,7 @@ extern const struct pci_ecam_ops al_pcie_ops;	/* Amazon Annapurna Labs PCIe */
- extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
- extern const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
+@@ -91,6 +91,7 @@ extern const struct pci_ecam_ops pci_n1sdp_pcie_ecam_ops; /* Arm N1SDP PCIe */
  extern const struct pci_ecam_ops pci_n1sdp_ccix_ecam_ops; /* Arm N1SDP PCIe */
-+extern const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops; /* Arm N1SDP PCIe */
  #endif
  
++extern const struct pci_ecam_ops pci_n1sdp_remote_pcie_ecam_ops; /* Arm N1SDP PCIe */
  #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
--- 
-2.17.1
-
+ /* for DT-based PCI controllers that support ECAM */
+ int pci_host_common_probe(struct platform_device *pdev);

meta-arm-bsp/recipes-kernel/linux/linux-yocto-5.15/n1sdp/0005-arm64-kpti-Whitelist-early-Arm-Neoverse-N1-revisions.patch

@@ -1,10 +1,7 @@
-Upstream-Status: Inappropriate
-Signed-off-by: Andre Przywara <andre.przywara@arm.com>
-
-From d20f5afffadcdbaca7032f547cce80720d8a414a Mon Sep 17 00:00:00 2001
+From 85581abbfc7e3df12091c5004788b0729cfd99f1 Mon Sep 17 00:00:00 2001
 From: Andre Przywara <andre.przywara@arm.com>
 Date: Fri, 17 May 2019 17:39:27 +0100
-Subject: [PATCH 5/5] arm64: kpti: Whitelist early Arm Neoverse N1 revisions
+Subject: [PATCH] arm64: kpti: Whitelist early Arm Neoverse N1 revisions
 
 Early revisions (r1p0) of the Neoverse N1 core did not feature the
 CSV3 field in ID_AA64PFR0_EL1 to advertise they are not affected by
@@ -12,16 +9,19 @@ the Spectre variant 3 (aka Meltdown) vulnerability.
 
 Add this particular revision to the whitelist to avoid enabling KPTI.
 
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+
+Upstream-Status: Inappropriate
 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
 ---
  arch/arm64/kernel/cpufeature.c | 1 +
  1 file changed, 1 insertion(+)
 
 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
-index 6ec7036ef7e1..ceba98773608 100644
+index 3e52a9e8b50b..2e64bc4689a0 100644
 --- a/arch/arm64/kernel/cpufeature.c
 +++ b/arch/arm64/kernel/cpufeature.c
-@@ -1509,6 +1509,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
+@@ -1530,6 +1530,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
  		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
  		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
  		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
@@ -29,6 +29,3 @@ index 6ec7036ef7e1..ceba98773608 100644
  		{ /* sentinel */ }
  	};
  	char const *str = "kpti command line option";
--- 
-2.17.1
-

meta-arm-bsp/recipes-security/trusted-services/secure-partitions/corstone1000/0007-Add-openamp-to-SE-proxy-deployment.patch

@@ -53,7 +53,7 @@ new file mode 100644
 index 0000000..840683a
 --- /dev/null
 +++ b/deployments/se-proxy/opteesp/lse.S
-@@ -0,0 +1,19 @@
+@@ -0,0 +1,28 @@
 +// SPDX-License-Identifier: BSD-3-Clause
 +/*
 + * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
@@ -61,18 +61,27 @@ index 0000000..840683a
 +
 +.text
 +.globl __aarch64_cas4_acq_rel
++.globl __aarch64_cas4_sync
 +
 +__aarch64_cas4_acq_rel:
-+	mov	w16, w0
-+	ldaxr	w0, [x2]
-+	cmp	w0, w16
-+0:	bne	1f
++       mov     w16, w0
++       ldaxr   w0, [x2]
++       cmp     w0, w16
++0:     bne     1f
 +
-+	stlxr	w17, w1, [x2]
-+	cbnz	w17, 0b
-+1:	ret
++       stlxr   w17, w1, [x2]
++       cbnz    w17, 0b
++1:     ret
 +
++__aarch64_cas4_sync:
++       mov     w16, w0
++       ldxr    w0, [x2]
++       cmp     w0, w16
++0:     bne     1f
 +
++       stlxr   w17, w1, [x2]
++       cbnz    w17, 0b
++1:     ret
 diff --git a/external/openamp/libmetal.cmake b/external/openamp/libmetal.cmake
 new file mode 100644
 index 0000000..3a647e6

meta-arm-bsp/wic/corstone1000-image.corstone1000.wks

@@ -12,4 +12,4 @@ part --source rawcopy --sourceparams="file=tfm_s_signed.bin" --align 1 --no-tabl
 part --source rawcopy --sourceparams="file=signed_fip-corstone1000.bin" --align 1 --no-table --fixed-size 2
 
 # Rawcopy of kernel with initramfs
-part --source rawcopy --sourceparams="file=Image-initramfs-${MACHINE}.bin" --no-table --fixed-size 12
+part --source rawcopy --sourceparams="file=Image.gz-initramfs-${MACHINE}.bin" --no-table --fixed-size 12

meta-arm-toolchain/conf/layer.conf

@@ -10,9 +10,3 @@ BBFILE_PRIORITY_arm-toolchain = "5"
 
 LAYERDEPENDS_arm-toolchain = "core"
 LAYERSERIES_COMPAT_arm-toolchain = "kirkstone"
-
-# do not error out on bbappends for missing recipes
-BB_DANGLINGAPPENDS_WARNONLY = "true"
-
-# These variables are used for armcompiler license
-BB_BASEHASH_IGNORE_VARS:append = " ARM_TOOL_VARIANT ARMLMD_LICENSE_FILE LM_LICENSE_FILE"

meta-arm-toolchain/recipes-devtools/external-arm-toolchain/armcompiler/no-uname.patch

@@ -1,14 +0,0 @@
-The install script has an explicit check that the current host is x86-64, which
-means we can't build armcompiler for x86-64 targets on arm64. Pad the
-replacement host with whitespace so that the installer offset doesn't change.
-
-Upstream-Status: Inappropriate
-Signed-off-by: Ross Burton <ross.burton@arm.com>
-
---- a/install_x86_64.sh.orig	2021-07-06 14:11:47.632155370 +0100
-+++ b/install_x86_64.sh	2021-07-06 14:11:58.393163350 +0100
-@@ -470,3 +470,3 @@
- fi
--host=`/bin/uname -m`
-+host=x86_64         
- echo --- Host target check...[${host}]

meta-arm-toolchain/recipes-devtools/external-arm-toolchain/armcompiler_6.17.bb

@@ -1,55 +0,0 @@
-# SPDX-License-Identifier: MIT
-#
-# Copyright (c) 2020 Arm Limited
-#
-
-require arm-binary-toolchain.inc
-
-SUMMARY = "Baremetal Armcompiler for Cortex-A, Cortex-R and Cortex-M processors"
-HOMEPAGE = "https://developer.arm.com/tools-and-software/embedded/arm-compiler/downloads/version-6"
-
-# Certain features of armcompiler requires a license. For more information, please refer to the armcompiler user guide:
-# https://developer.arm.com/tools-and-software/software-development-tools/license-management/resources/product-and-toolkit-configuration
-# Usually set and export of these variables are required:
-# ARM_TOOL_VARIANT, ARMLMD_LICENSE_FILE, LM_LICENSE_FILE
-
-LICENSE = "Armcompiler-License-agreement & Armcompiler-Redistributables & \
-           Armcompiler-Supplementary-terms & Armcompiler-Third-party-licenses"
-
-NO_GENERIC_LICENSE[Armcompiler-License-agreement] = "license_terms/license_agreement.txt"
-NO_GENERIC_LICENSE[Armcompiler-Redistributables] = "license_terms/redistributables.txt"
-NO_GENERIC_LICENSE[Armcompiler-Supplementary-terms] = "license_terms/supplementary_terms.txt"
-NO_GENERIC_LICENSE[Armcompiler-Third-party-licenses] = "license_terms/third_party_licenses.txt"
-
-# The Arm Compiler is under a EULA, read this at the homepage above and if you
-# agree add 'armcompiler' to your LICENSE_FLAGS_ACCEPTED.
-LICENSE_FLAGS = "armcompiler"
-
-LIC_FILES_CHKSUM = "file://license_terms/license_agreement.txt;md5=19faf912b534478d28f60dfa24659c17 \
-                    file://license_terms/redistributables.txt;md5=c22d8d2388d8e592f4b135f87bb243da \
-                    file://license_terms/supplementary_terms.txt;md5=e2443a4a7c520e79ebb603c8ba509076 \
-                    file://license_terms/third_party_licenses.txt;md5=53b42e7d31259bdc174b9c03651ed1b7 "
-
-ARMCLANG_VERSION = "DS500-BN-00026-r5p0-19rel0"
-
-COMPATIBLE_HOST = "x86_64.*-linux"
-
-SRC_URI = "https://developer.arm.com/-/media/Files/downloads/compiler/${ARMCLANG_VERSION}.tgz;subdir=${ARMCLANG_VERSION} \
-           file://no-uname.patch"
-SRC_URI[sha256sum] = "0ed2c3a2e416f07b892250fcbcca4b27353b046a030a433bf6dddc0db802885c"
-
-UPSTREAM_CHECK_URI = "https://developer.arm.com/tools-and-software/embedded/arm-compiler/downloads/"
-UPSTREAM_CHECK_REGEX = "Download Arm Compiler.*,(?P<pver>[\d\.]+)"
-
-S = "${WORKDIR}/${ARMCLANG_VERSION}"
-
-do_install() {
-    install -d ${D}${bindir} ${D}${libexecdir}/${BPN}/
-    # Commercial license flag set, so recipe will only install when explicitly agreed to it already
-    ${S}/install_x86_64.sh --i-agree-to-the-contained-eula -d ${D}${libexecdir}/${BPN}/ --no-interactive
-
-    # Symlink all executables into bindir
-    for f in ${D}${libexecdir}/${BPN}/bin/*; do
-        ln -rs $f ${D}${bindir}/$(basename $f)
-    done
-}

meta-arm-toolchain/recipes-devtools/external-arm-toolchain/external-arm-toolchain.bb

@@ -75,7 +75,7 @@ do_install() {
 	install -d ${D}${includedir}
 	install -d ${D}/include
 	install -d ${D}${libdir}/${TARGET_SYS}/${EAT_VER_GCC}
-	install -d ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}
+	install -d ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/include
 
 	CP_ARGS="-Prf --preserve=mode,timestamps --no-preserve=ownership"
 	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/${EAT_TARGET_SYS}/${EAT_LIBDIR}/*  ${D}${base_libdir}
@@ -104,7 +104,11 @@ do_install() {
 	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/crt*.o ${D}${libdir}/${TARGET_SYS}/${EAT_VER_GCC}/
 	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/libgcc* ${D}${libdir}/${TARGET_SYS}/${EAT_VER_GCC}/
 	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/libgcov* ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/
-	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/include ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/
+	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/include/ssp ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/include || true
+	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/include/sanitizers ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/include || true
+	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/include/quadmath* ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/include || true
+	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/include/omp.h ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/include || true
+	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/include/openacc.h ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/include || true
 	cp ${CP_ARGS} ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/finclude ${D}${libdir}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/
 
 	# fix up the copied symlinks (they are still pointing to the multiarch directory)
@@ -495,7 +499,6 @@ FILES:libgcc-dev = "\
     ${@oe.utils.conditional('BASETARGET_SYS', '${TARGET_SYS}', '', '${libdir}/${BASETARGET_SYS}', d)} \
     ${libdir}/${TARGET_SYS}/${BINV}* \
     ${libdir}/${TARGET_ARCH}${TARGET_VENDOR}* \
-    ${libdir}/gcc/${TARGET_SYS}/${BINV}/include \
 "
 
 FILES:linux-libc-headers = ""

meta-arm-toolchain/recipes-devtools/gcc/gcc-arm-common.inc

@@ -12,7 +12,7 @@
 do_install:prepend:class-target () {
 	if [ "${TCMODE}" = "external-arm" -a ! -f ${STAGING_LIBDIR_NATIVE}/${TARGET_SYS}/gcc/${TARGET_SYS}/${BINV}/include/unwind.h ]; then
 		install -d ${STAGING_LIBDIR_NATIVE}/${TARGET_SYS}/gcc/${TARGET_SYS}/${BINV}/include/
-		install ${STAGING_LIBDIR}/gcc/${TARGET_SYS}/${EAT_VER_GCC}/include/unwind.h ${STAGING_LIBDIR_NATIVE}/${TARGET_SYS}/gcc/${TARGET_SYS}/${BINV}/include/
+		install ${EXTERNAL_TOOLCHAIN}/lib/gcc/${EAT_TARGET_SYS}/${EAT_VER_GCC}/include/unwind.h ${STAGING_LIBDIR_NATIVE}/${TARGET_SYS}/gcc/${TARGET_SYS}/${BINV}/include/
 	fi
 }
 

meta-arm/classes/fvpboot.bbclass

@@ -18,8 +18,13 @@ FVP_APPLICATIONS ?= ""
 FVP_TERMINALS ?= ""
 # What terminal should be considered the primary console
 FVP_CONSOLE ?= ""
+# Flags for console names, as they appear in the FVP output. Flag name is an
+# application-specific id for the console for use in test cases
+FVP_CONSOLES[default] ?= "${FVP_CONSOLE}"
 # Arbitrary extra arguments
 FVP_EXTRA_ARGS ?= ""
+# Bitbake variables to pass to the FVP environment
+FVP_ENV_PASSTHROUGH ?= ""
 
 EXTRA_IMAGEDEPENDS += "${FVP_PROVIDER}"
 
@@ -59,10 +64,14 @@ python do_write_fvpboot_conf() {
     data["parameters"] = getFlags("FVP_CONFIG")
     data["data"] = shlex.split(d.getVar("FVP_DATA") or "")
     data["applications"] = getFlags("FVP_APPLICATIONS")
-    data["console"] = d.getVar("FVP_CONSOLE")
+    data["consoles"] = getFlags("FVP_CONSOLES")
     data["terminals"] = getFlags("FVP_TERMINALS")
     data["args"] = shlex.split(d.getVar("FVP_EXTRA_ARGS") or "")
 
+    data["env"] = {}
+    for var in d.getVar("FVP_ENV_PASSTHROUGH").split():
+        data["env"][var] = d.getVar(var)
+
     os.makedirs(os.path.dirname(conffile), exist_ok=True)
     with open(conffile, "wt") as f:
         json.dump(data, f)

meta-arm/conf/machine/microbit-v1.conf

@@ -16,6 +16,7 @@ QB_MACHINE = "-machine microbit"
 QB_CPU = "-cpu cortex-m0"
 QB_OPT_APPEND = "-nographic -vga none"
 QB_RNG = ""
+QB_OPT_APPEND = "-icount shift=6,align=off,sleep=on -rtc clock=vm"
 
 # Zephyr RTOS settings
 ZEPHYR_BOARD = "qemu_cortex_m0"

meta-arm/conf/machine/qemuarm64-secureboot.conf

@@ -23,5 +23,3 @@ WKS_FILE_DEPENDS = "trusted-firmware-a"
 IMAGE_BOOT_FILES = "${KERNEL_IMAGETYPE}"
 
 MACHINE_FEATURES += "optee-ftpm"
-
-PREFERRED_VERSION_linux-yocto ?= "5.10%"

meta-arm/lib/fvp/conffile.py

@@ -0,0 +1,59 @@
+import json
+import pathlib
+import os
+
+
+def get_image_directory(machine=None):
+    """
+    Get the DEPLOY_DIR_IMAGE for the specified machine
+    (or the configured machine if not set).
+    """
+    try:
+        import bb.tinfoil
+    except ImportError as e:
+        raise RuntimeError("Cannot connect to BitBake, did you oe-init-build-env?") from e
+
+    if machine:
+        os.environ["MACHINE"] = machine
+
+    with bb.tinfoil.Tinfoil() as tinfoil:
+        tinfoil.prepare(config_only=True)
+        image_dir = tinfoil.config_data.getVar("DEPLOY_DIR_IMAGE")
+        return pathlib.Path(image_dir)
+
+def find(machine):
+    image_dir = get_image_directory(machine)
+    # All .fvpconf configuration files
+    configs = image_dir.glob("*.fvpconf")
+    # Just the files
+    configs = [p for p in configs if p.is_file() and not p.is_symlink()]
+    if not configs:
+            print(f"Cannot find any .fvpconf in {image_dir}")
+            raise RuntimeError()
+    # Sorted by modification time
+    configs = sorted(configs, key=lambda p: p.stat().st_mtime)
+    return configs[-1]
+
+
+def load(config_file):
+    with open(config_file) as f:
+        config = json.load(f)
+
+    # Ensure that all expected keys are present
+    def sanitise(key, value):
+        if key not in config or config[key] is None:
+            config[key] = value
+    sanitise("fvp-bindir", "")
+    sanitise("exe", "")
+    sanitise("parameters", {})
+    sanitise("data", {})
+    sanitise("applications", {})
+    sanitise("terminals", {})
+    sanitise("args", [])
+    sanitise("consoles", {})
+    sanitise("env", {})
+
+    if not config["exe"]:
+        raise ValueError("Required value FVP_EXE not set in machine configuration")
+
+    return config

meta-arm/lib/fvp/runner.py

@@ -0,0 +1,142 @@
+import asyncio
+import re
+import subprocess
+import os
+import shutil
+import sys
+
+from .terminal import terminals
+
+
+def cli_from_config(config, terminal_choice):
+    cli = []
+    if config["fvp-bindir"]:
+        cli.append(os.path.join(config["fvp-bindir"], config["exe"]))
+    else:
+        cli.append(config["exe"])
+
+    for param, value in config["parameters"].items():
+        cli.extend(["--parameter", f"{param}={value}"])
+
+    for value in config["data"]:
+        cli.extend(["--data", value])
+
+    for param, value in config["applications"].items():
+        cli.extend(["--application", f"{param}={value}"])
+
+    for terminal, name in config["terminals"].items():
+        # If terminals are enabled and this terminal has been named
+        if terminal_choice != "none" and name:
+            # TODO if raw mode
+            # cli.extend(["--parameter", f"{terminal}.mode=raw"])
+            # TODO put name into terminal title
+            cli.extend(["--parameter", f"{terminal}.terminal_command={terminals[terminal_choice].command}"])
+        else:
+            # Disable terminal
+            cli.extend(["--parameter", f"{terminal}.start_telnet=0"])
+
+    cli.extend(config["args"])
+
+    return cli
+
+def check_telnet():
+    # Check that telnet is present
+    if not bool(shutil.which("telnet")):
+        raise RuntimeError("Cannot find telnet, this is needed to connect to the FVP.")
+
+class FVPRunner:
+    def __init__(self, logger):
+        self._terminal_ports = {}
+        self._line_callbacks = []
+        self._logger = logger
+        self._fvp_process = None
+        self._telnets = []
+        self._pexpects = []
+
+    def add_line_callback(self, callback):
+        self._line_callbacks.append(callback)
+
+    async def start(self, config, extra_args=[], terminal_choice="none"):
+        cli = cli_from_config(config, terminal_choice)
+        cli += extra_args
+        self._logger.debug(f"Constructed FVP call: {cli}")
+        self._fvp_process = await asyncio.create_subprocess_exec(
+            *cli,
+            stdin=subprocess.DEVNULL, stdout=subprocess.PIPE, stderr=subprocess.STDOUT,
+            env=config['env'])
+
+        def detect_terminals(line):
+            m = re.match(r"^(\S+): Listening for serial connection on port (\d+)$", line)
+            if m:
+                terminal = m.group(1)
+                port = int(m.group(2))
+                self._terminal_ports[terminal] = port
+        self.add_line_callback(detect_terminals)
+
+    async def stop(self):
+        if self._fvp_process:
+            self._logger.debug(f"Terminating FVP PID {self._fvp_process.pid}")
+            try:
+                self._fvp_process.terminate()
+                await asyncio.wait_for(self._fvp_process.wait(), 10.0)
+            except asyncio.TimeoutError:
+                self._logger.debug(f"Killing FVP PID {self._fvp_process.pid}")
+                self._fvp_process.kill()
+            except ProcessLookupError:
+                pass
+
+        for telnet in self._telnets:
+            try:
+                telnet.terminate()
+                await asyncio.wait_for(telnet.wait(), 10.0)
+            except asyncio.TimeoutError:
+                telnet.kill()
+            except ProcessLookupError:
+                pass
+
+        for console in self._pexpects:
+            import pexpect
+            # Ensure pexpect logs all remaining output to the logfile
+            console.expect(pexpect.EOF, timeout=5.0)
+            console.close()
+
+        if self._fvp_process and self._fvp_process.returncode:
+            self._logger.info(f"FVP quit with code {self._fvp_process.returncode}")
+            return self._fvp_process.returncode
+        else:
+            return 0
+
+    async def run(self, until=None):
+        if until and until():
+            return
+
+        async for line in self._fvp_process.stdout:
+            line = line.strip().decode("utf-8", errors="replace")
+            for callback in self._line_callbacks:
+                callback(line)
+            if until and until():
+                return
+
+    async def _get_terminal_port(self, terminal, timeout):
+        def terminal_exists():
+            return terminal in self._terminal_ports
+        await asyncio.wait_for(self.run(terminal_exists), timeout)
+        return self._terminal_ports[terminal]
+
+    async def create_telnet(self, terminal, timeout=15.0):
+        check_telnet()
+        port = await self._get_terminal_port(terminal, timeout)
+        telnet = await asyncio.create_subprocess_exec("telnet", "localhost", str(port), stdin=sys.stdin, stdout=sys.stdout)
+        self._telnets.append(telnet)
+        return telnet
+
+    async def create_pexpect(self, terminal, timeout=15.0, **kwargs):
+        check_telnet()
+        import pexpect
+        port = await self._get_terminal_port(terminal, timeout)
+        instance = pexpect.spawn(f"telnet localhost {port}", **kwargs)
+        self._pexpects.append(instance)
+        return instance
+
+    def pid(self):
+        return self._fvp_process.pid

meta-arm/lib/fvp/terminal.py

@@ -0,0 +1,59 @@
+import shutil
+import collections
+import pathlib
+import os
+
+from typing import List, Optional
+
+
+def get_config_dir() -> pathlib.Path:
+    value = os.environ.get("XDG_CONFIG_HOME")
+    if value and os.path.isabs(value):
+        return pathlib.Path(value)
+    else:
+        return pathlib.Path.home() / ".config"
+
+class Terminals:
+    Terminal = collections.namedtuple("Terminal", ["priority", "name", "command"])
+
+    def __init__(self):
+        self.terminals = []
+
+    def add_terminal(self, priority, name, command):
+        self.terminals.append(Terminals.Terminal(priority, name, command))
+        # Keep this list sorted by priority
+        self.terminals.sort(reverse=True, key=lambda t: t.priority)
+        self.name_map = {t.name: t for t in self.terminals}
+
+    def configured_terminal(self) -> Optional[str]:
+        import configparser
+
+        config = configparser.ConfigParser()
+        config.read(get_config_dir() / "runfvp.conf")
+        return config.get("RunFVP", "Terminal", fallback=None)
+
+    def preferred_terminal(self) -> str:
+        import shlex
+
+        preferred = self.configured_terminal()
+        if preferred:
+            return preferred
+
+        for t in self.terminals:
+            if t.command and shutil.which(shlex.split(t.command)[0]):
+                return t.name
+        return self.terminals[-1].name
+
+    def all_terminals(self) -> List[str]:
+        return self.name_map.keys()
+
+    def __getitem__(self, name: str):
+        return self.name_map[name]
+
+terminals = Terminals()
+# TODO: option to switch between telnet and netcat
+connect_command = "telnet localhost %port"
+terminals.add_terminal(2, "tmux", f"tmux new-window -n \"%title\" \"{connect_command}\""),
+terminals.add_terminal(2, "gnome-terminal", f"gnome-terminal --window --title \"%title\" --command \"{connect_command}\""),
+terminals.add_terminal(1, "xterm", f"xterm -title \"%title\" -e {connect_command}"),
+terminals.add_terminal(0, "none", None)

meta-arm/lib/oeqa/controllers/fvp.py

@@ -1,73 +1,47 @@
 import asyncio
-import os
 import pathlib
-import signal
-import subprocess
+import pexpect
+import os
 
-import oeqa.core.target.ssh
+from oeqa.core.target.ssh import OESSHTarget
+from fvp import conffile, runner
 
-class OEFVPTarget(oeqa.core.target.ssh.OESSHTarget):
-
-    # meta-arm/scripts isn't on PATH, so work out where it is
-    metaarm = pathlib.Path(__file__).parents[4]
 
+class OEFVPSSHTarget(OESSHTarget):
+    """
+    Base class for meta-arm FVP targets.
+    Contains common logic to start and stop an FVP.
+    """
     def __init__(self, logger, target_ip, server_ip, timeout=300, user='root',
-                 port=None, server_port=0, dir_image=None, rootfs=None, bootlog=None,
-                 **kwargs):
+                 port=None, dir_image=None, rootfs=None, **kwargs):
         super().__init__(logger, target_ip, server_ip, timeout, user, port)
         image_dir = pathlib.Path(dir_image)
         # rootfs may have multiple extensions so we need to strip *all* suffixes
         basename = pathlib.Path(rootfs)
         basename = basename.name.replace("".join(basename.suffixes), "")
         self.fvpconf = image_dir / (basename + ".fvpconf")
+        self.config = conffile.load(self.fvpconf)
 
         if not self.fvpconf.exists():
             raise FileNotFoundError(f"Cannot find {self.fvpconf}")
-        # FVPs boot slowly, so allow ten minutes
-        self.boot_timeout = 10 * 60
-
-        self.logfile = bootlog and open(bootlog, "wb") or None
 
     async def boot_fvp(self):
-        cmd = [OEFVPTarget.metaarm / "scripts" / "runfvp", "--console", "--verbose", self.fvpconf]
-        # Python 3.7 needs the command items to be str
-        cmd = [str(c) for c in cmd]
-        self.logger.debug(f"Starting {cmd}")
+        self.fvp = runner.FVPRunner(self.logger)
+        await self.fvp.start(self.config)
+        self.logger.debug(f"Started FVP PID {self.fvp.pid()}")
+        await self._after_start()
 
-        # TODO: refactor runfvp so this can import it and directly hook to the
-        # console callback, then use telnetlib directly to access the console.
+    async def _after_start(self):
+        pass
 
-        # As we're using --console, telnet expects stdin to be readable too.
-        self.fvp = await asyncio.create_subprocess_exec(*cmd, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, stdin=subprocess.PIPE)
-        self.logger.debug(f"Started runfvp PID {self.fvp.pid}")
+    async def _after_stop(self):
+        pass
 
-        async def wait_for_login(bootlog):
-            while True:
-                line = await self.fvp.stdout.read(1024)
-                if not line:
-                    self.logger.debug("runfvp terminated")
-                    return False
+    async def stop_fvp(self):
+        returncode = await self.fvp.stop()
+        await self._after_stop()
 
-                self.logger.debug(f"Read line [{line}]")
-
-                bootlog += line
-                if self.logfile:
-                    self.logfile.write(line)
-
-                if b" login:" in bootlog:
-                    self.logger.debug("Found login prompt")
-                    return True
-
-        bootlog = bytearray()
-        try:
-            found = await asyncio.wait_for(wait_for_login(bootlog), self.boot_timeout)
-            if found:
-                return
-        except asyncio.TimeoutError:
-            self.logger.info("Timed out waiting for login prompt.")
-        self.logger.info("Boot log follows:")
-        self.logger.info(b"\n".join(bootlog.splitlines()[-200:]).decode("utf-8", errors="replace"))
-        raise RuntimeError("Failed to start FVP.")
+        self.logger.debug(f"Stopped FVP with return code {returncode}")
 
     def start(self, **kwargs):
         # When we can assume Py3.7+, this can simply be asyncio.run()
@@ -76,15 +50,98 @@ class OEFVPTarget(oeqa.core.target.ssh.OESSHTarget):
 
     def stop(self, **kwargs):
         loop = asyncio.get_event_loop()
+        loop.run_until_complete(asyncio.gather(self.stop_fvp()))
 
+
+class OEFVPTarget(OEFVPSSHTarget):
+    """
+    For compatibility with OE-core test cases, this target's start() method
+    waits for a Linux shell before returning to ensure that SSH commands work
+    with the default test dependencies.
+    """
+    def __init__(self, logger, target_ip, server_ip, bootlog=None, **kwargs):
+        super().__init__(logger, target_ip, server_ip, **kwargs)
+        self.logfile = bootlog and open(bootlog, "wb") or None
+
+        # FVPs boot slowly, so allow ten minutes
+        self.boot_timeout = 10 * 60
+
+    async def _after_start(self):
+        self.logger.debug(f"Awaiting console on terminal {self.config['consoles']['default']}")
+        console = await self.fvp.create_pexpect(self.config['consoles']['default'])
         try:
-            # Kill the process group so that the telnet and FVP die too
-            gid = os.getpgid(self.fvp.pid)
-            self.logger.debug(f"Sending SIGTERM to {gid}")
-            os.killpg(gid, signal.SIGTERM)
-            loop.run_until_complete(asyncio.wait_for(self.fvp.wait(), 10))
-        except TimeoutError:
-            self.logger.debug(f"Timed out, sending SIGKILL to {gid}")
-            os.killpg(gid, signal.SIGKILL)
-        except ProcessLookupError:
-            return
+            console.expect("login\\:", timeout=self.boot_timeout)
+            self.logger.debug("Found login prompt")
+        except pexpect.TIMEOUT:
+            self.logger.info("Timed out waiting for login prompt.")
+            self.logger.info("Boot log follows:")
+            self.logger.info(b"\n".join(console.before.splitlines()[-200:]).decode("utf-8", errors="replace"))
+            raise RuntimeError("Failed to start FVP.")
+
+
+class OEFVPSerialTarget(OEFVPSSHTarget):
+    """
+    This target is intended for interaction with the target over one or more
+    telnet consoles using pexpect.
+    
+    This still depends on OEFVPSSHTarget so SSH commands can still be run on
+    the target, but note that this class does not inherently guarantee that
+    the SSH server is running prior to running test cases. Test cases that use
+    SSH should first validate that SSH is available, e.g. by depending on the
+    "linuxboot" test case in meta-arm.
+    """
+    DEFAULT_CONSOLE = "default"
+
+    def __init__(self, logger, target_ip, server_ip, bootlog=None, **kwargs):
+        super().__init__(logger, target_ip, server_ip, **kwargs)
+        self.terminals = {}
+
+        self.test_log_path = pathlib.Path(bootlog).parent
+        self.test_log_suffix = pathlib.Path(bootlog).suffix
+        self.bootlog = bootlog
+
+    async def _add_terminal(self, name, fvp_name):
+        logfile = self._create_logfile(name)
+        self.logger.info(f'Creating terminal {name} on {fvp_name}')
+        self.terminals[name] = \
+            await self.fvp.create_pexpect(fvp_name, logfile=logfile)
+
+    def _create_logfile(self, name):
+        fvp_log_file = f"{name}_log{self.test_log_suffix}"
+        fvp_log_path = pathlib.Path(self.test_log_path, fvp_log_file)
+        fvp_log_symlink = pathlib.Path(self.test_log_path, f"{name}_log")
+        try:
+            os.remove(fvp_log_symlink)
+        except:
+            pass
+        os.symlink(fvp_log_file, fvp_log_symlink)
+        return open(fvp_log_path, 'wb')
+
+    async def _after_start(self):
+        for name, console in self.config["consoles"].items():
+            await self._add_terminal(name, console)
+
+            # testimage.bbclass expects to see a log file at `bootlog`,
+            # so make a symlink to the 'default' log file
+            if name == 'default':
+                default_test_file = f"{name}_log{self.test_log_suffix}"
+                os.symlink(default_test_file, self.bootlog)
+
+    def _get_terminal(self, name):
+        return self.terminals[name]
+
+    def __getattr__(self, name):
+        """
+        Magic method which automatically exposes the whole pexpect API on the
+        target, with the first argument being the terminal name.
+
+        e.g. self.target.expect(self.target.DEFAULT_CONSOLE, "login\\:")
+        """
+        def call_pexpect(terminal, *args, **kwargs):
+            attr = getattr(self.terminals[terminal], name)
+            if callable(attr):
+                return attr(*args, **kwargs)
+            else:
+                return attr
+
+        return call_pexpect

meta-arm/lib/oeqa/runtime/cases/linuxboot.py

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: MIT
+
+from oeqa.runtime.case import OERuntimeTestCase
+
+
+class LinuxBootTest(OERuntimeTestCase):
+    """
+    This test case is only compatible with the OEFVPSerialTarget as it uses
+    the pexpect interface. It waits for a Linux login prompt on the default
+    console.
+    """
+
+    def setUp(self):
+        self.console = self.target.DEFAULT_CONSOLE
+        self.timeout = int(self.td.get('TEST_FVP_LINUX_BOOT_TIMEOUT') or 10*60)
+
+    def test_linux_boot(self):
+        self.logger.info(f"{self.console}: Waiting for login prompt")
+        self.target.expect(self.console, r"login\:", self.timeout)

meta-arm/lib/oeqa/runtime/cases/noop.py

@@ -1,12 +0,0 @@
-# SPDX-License-Identifier: MIT
-
-from oeqa.runtime.case import OERuntimeTestCase
-
-class NoopTest(OERuntimeTestCase):
-    """
-    This is a test case which does nothing.  Useful when you want to use
-    testimage to verify that an image boots, but you don't have networking so
-    none of the existing test cases are suitable.
-    """
-    def test_no_op(self):
-        return

meta-arm/lib/oeqa/selftest/cases/runfvp.py

@@ -1,6 +1,9 @@
+import asyncio
 import os
 import pathlib
 import subprocess
+import tempfile
+import unittest.mock
 
 from oeqa.selftest.case import OESelftestTestCase
 
@@ -17,11 +20,10 @@ class RunFVPTests(OESelftestTestCase):
         on exit code 0 or fail the test, otherwise return the CompletedProcess
         instance.
         """
-        # Put the test directory in PATH so that any mock FVPs are found first
-        newenv = {"PATH": str(testdir) + ":" + os.environ["PATH"]}
         cli = [runfvp,] + list(args)
         print(f"Calling {cli}")
-        ret = subprocess.run(cli, env=newenv, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, universal_newlines=True)
+        # Set cwd to testdir so that any mock FVPs are found
+        ret = subprocess.run(cli, cwd=testdir, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, universal_newlines=True)
         if should_succeed:
             self.assertEqual(ret.returncode, 0, f"runfvp exit {ret.returncode}, output: {ret.stdout}")
             return ret.stdout
@@ -37,8 +39,6 @@ class RunFVPTests(OESelftestTestCase):
         self.run_fvp("--this-is-an-invalid-option", should_succeed=False)
 
     def test_run_auto_tests(self):
-        newenv = {"PATH": str(testdir) + ":" + os.environ["PATH"]}
-
         cases = list(testdir.glob("auto-*.json"))
         if not cases:
             self.fail("No tests found")
@@ -49,3 +49,61 @@ class RunFVPTests(OESelftestTestCase):
     def test_fvp_options(self):
         # test-parameter sets one argument, add another manually
         self.run_fvp(testdir / "test-parameter.json", "--", "--parameter", "board.dog=woof")
+
+class ConfFileTests(OESelftestTestCase):
+    def test_no_exe(self):
+        from fvp import conffile
+        with tempfile.NamedTemporaryFile('w') as tf:
+            tf.write('{}')
+            tf.flush()
+
+            with self.assertRaises(ValueError):
+                conffile.load(tf.name)
+
+    def test_minimal(self):
+        from fvp import conffile
+        with tempfile.NamedTemporaryFile('w') as tf:
+            tf.write('{"exe": "FVP_Binary"}')
+            tf.flush()
+
+            conf = conffile.load(tf.name)
+            self.assertTrue('fvp-bindir' in conf)
+            self.assertTrue('fvp-bindir' in conf)
+            self.assertTrue("exe" in conf)
+            self.assertTrue("parameters" in conf)
+            self.assertTrue("data" in conf)
+            self.assertTrue("applications" in conf)
+            self.assertTrue("terminals" in conf)
+            self.assertTrue("args" in conf)
+            self.assertTrue("consoles" in conf)
+            self.assertTrue("env" in conf)
+
+
+class RunnerTests(OESelftestTestCase):
+    def create_mock(self):
+        return unittest.mock.patch("asyncio.create_subprocess_exec")
+
+    def test_start(self):
+        from fvp import runner
+        with self.create_mock() as m:
+            fvp = runner.FVPRunner(self.logger)
+            asyncio.run(fvp.start({
+                "fvp-bindir": "/usr/bin",
+                "exe": "FVP_Binary",
+                "parameters": {'foo': 'bar'},
+                "data": ['data1'],
+                "applications": {'a1': 'file'},
+                "terminals": {},
+                "args": ['--extra-arg'],
+                "env": {"FOO": "BAR"}
+            }))
+
+            m.assert_called_once_with('/usr/bin/FVP_Binary',
+                '--parameter', 'foo=bar',
+                '--data', 'data1',
+                '--application', 'a1=file',
+                '--extra-arg',
+                stdin=unittest.mock.ANY,
+                stdout=unittest.mock.ANY,
+                stderr=unittest.mock.ANY,
+                env={"FOO":"BAR"})

meta-arm/lib/oeqa/selftest/cases/tests/auto-basic.json

@@ -1,3 +1,4 @@
 {
+    "fvp-bindir": ".",
     "exe": "auto-basic.sh"
 }

meta-arm/lib/oeqa/selftest/cases/tests/auto-parameters.json

@@ -1,4 +1,5 @@
 {
+    "fvp-bindir": ".",
     "exe": "test-parameters.py",
     "parameters": {
         "board.cow": "moo",

meta-arm/lib/oeqa/selftest/cases/tests/test-parameter.json

@@ -1,4 +1,5 @@
 {
+    "fvp-bindir": ".",
     "exe": "test-parameters.py",
     "parameters": {
         "board.cow": "moo"

meta-arm/recipes-bsp/boot-wrapper-aarch64/boot-wrapper-aarch64_git.bb

@@ -3,7 +3,7 @@ LICENSE = "BSD-3-Clause"
 
 LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=bb63326febfb5fb909226c8e7ebcef5c"
 
-SRC_URI = "git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git;branch=master"
+SRC_URI = "git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git;branch=master;protocol=https"
 SRCREV = "1044c77062573985f7c994c3b6cef5695f57e955"
 
 PV = "git${SRCPV}"

meta-arm/recipes-bsp/trusted-firmware-a/tf-a-tests_2.6.bb

@@ -0,0 +1,53 @@
+DESCRIPTION = "Trusted Firmware-A tests(aka TFTF)"
+LICENSE = "BSD-3-Clause & NCSA"
+
+LIC_FILES_CHKSUM += "file://docs/license.rst;md5=6175cc0aa2e63b6d21a32aa0ee7d1b4a"
+
+inherit deploy
+
+COMPATIBLE_MACHINE ?= "invalid"
+
+SRC_URI = "git://git.trustedfirmware.org/TF-A/tf-a-tests.git;protocol=https;branch=master"
+# post v2.6 snapshot
+SRCREV ?= "af5a517ae9f295455122109100fe5d55668e8eaf"
+PV .= "+git${SRCPV}"
+
+DEPENDS += "optee-os"
+
+EXTRA_OEMAKE += "USE_NVM=0"
+EXTRA_OEMAKE += "SHELL_COLOR=1"
+EXTRA_OEMAKE += "DEBUG=1"
+
+# Platform must be set for each machine
+TFA_PLATFORM ?= "invalid"
+
+EXTRA_OEMAKE += "ARCH=aarch64"
+EXTRA_OEMAKE += "LOG_LEVEL=50"
+
+S = "${WORKDIR}/git"
+B = "${WORKDIR}/build"
+
+# Add platform parameter
+EXTRA_OEMAKE += "BUILD_BASE=${B} PLAT=${TFA_PLATFORM}"
+
+# Requires CROSS_COMPILE set by hand as there is no configure script
+export CROSS_COMPILE="${TARGET_PREFIX}"
+
+do_compile() {
+    oe_runmake -C ${S} tftf
+}
+
+do_compile[cleandirs] = "${B}"
+
+FILES:${PN} = "/firmware/tftf.bin"
+SYSROOT_DIRS += "/firmware"
+
+do_install() {
+    install -d -m 755 ${D}/firmware
+    install -m 0644 ${B}/${TFA_PLATFORM}/debug/tftf.bin ${D}/firmware/tftf.bin
+}
+
+do_deploy() {
+    cp -rf ${D}/firmware/* ${DEPLOYDIR}/
+}
+addtask deploy after do_install

meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc

@@ -101,9 +101,9 @@ def remove_options_tail (in_string):
     from itertools import takewhile
     return ' '.join(takewhile(lambda x: not x.startswith('-'), in_string.split(' ')))
 
-EXTRA_OEMAKE += "LD=${@remove_options_tail(d.getVar('LD'))}"
+EXTRA_OEMAKE += "LD='${@remove_options_tail(d.getVar('LD'))}'"
 
-EXTRA_OEMAKE += "CC=${@remove_options_tail(d.getVar('CC'))}"
+EXTRA_OEMAKE += "CC='${@remove_options_tail(d.getVar('CC'))}'"
 
 # Verbose builds, no -Werror
 EXTRA_OEMAKE += "V=1 E=0"
@@ -135,6 +135,10 @@ EXTRA_OEMAKE += "${@bb.utils.contains('TFA_UBOOT', '1', 'BL33=${DEPLOY_DIR_IMAGE
 DEPENDS += " ${@bb.utils.contains('TFA_UEFI', '1', 'edk2-firmware', '', d)}"
 EXTRA_OEMAKE += "${@bb.utils.contains('TFA_UEFI', '1', 'BL33=${RECIPE_SYSROOT}/firmware/uefi.bin', '', d)}"
 
+# TFTF test support
+DEPENDS += " ${@bb.utils.contains('TFTF_TESTS', '1', 'tf-a-tests', '', d)}"
+EXTRA_OEMAKE += "${@bb.utils.contains('TFTF_TESTS', '1', 'BL33=${RECIPE_SYSROOT}/firmware/tftf.bin', '',d)}"
+
 # Hafnium support
 SEL2_SPMC = "${@'${TFA_SPMD_SPM_AT_SEL2}' if d.getVar('TFA_SPD', True) == 'spmd' else ''}"
 

meta-arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.7.bb

@@ -0,0 +1,15 @@
+require trusted-firmware-a.inc
+
+# TF-A v2.7
+SRCREV_tfa = "35f4c7295bafeb32c8bcbdfb6a3f2e74a57e732b"
+
+LIC_FILES_CHKSUM += "file://docs/license.rst;md5=b2c740efedc159745b9b31f88ff03dde"
+
+# mbed TLS v2.28.0
+SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls;branch=mbedtls-2.28"
+SRCREV_mbedtls = "8b3f26a5ac38d4fdccbc5c5366229f3e01dafcc0"
+
+LIC_FILES_CHKSUM_MBEDTLS = "file://mbedtls/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57"
+
+# Disable by default
+DEFAULT_PREFERENCE = "-1"

meta-arm/recipes-bsp/trusted-firmware-m/trusted-firmware-m_1.5.0.bb

@@ -15,8 +15,8 @@ LIC_FILES_CHKSUM = "file://license.rst;md5=07f368487da347f3c7bd0fc3085f3afa \
                     file://../mbedtls/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \
                     file://../mcuboot/LICENSE;md5=b6ee33f1d12a5e6ee3de1e82fb51eeb8"
 
-SRC_URI  = "git://git.trustedfirmware.org/TF-M/trusted-firmware-m.git;protocol=https;branch=${SRCBRANCH_tfm};name=tfm;destsuffix=git/tfm \
-            git://git.trustedfirmware.org/TF-M/tf-m-tests.git;protocol=https;branch=release/1.5.x;name=tfm-tests;destsuffix=git/tf-m-tests \
+SRC_URI  = "git://git.trustedfirmware.org/TF-M/trusted-firmware-m.git;protocol=https;nobranch=1;name=tfm;destsuffix=git/tfm \
+            git://git.trustedfirmware.org/TF-M/tf-m-tests.git;protocol=https;nobranch=1;name=tfm-tests;destsuffix=git/tf-m-tests \
             git://github.com/ARMmbed/mbedtls.git;protocol=https;branch=master;name=mbedtls;destsuffix=git/mbedtls \
             git://github.com/mcu-tools/mcuboot.git;protocol=https;branch=main;name=mcuboot;destsuffix=git/mcuboot \
             file://cbor2.patch;patchdir=../mcuboot \
@@ -24,7 +24,6 @@ SRC_URI  = "git://git.trustedfirmware.org/TF-M/trusted-firmware-m.git;protocol=h
 
 # The required dependencies are documented in tf-m/config/config_default.cmake
 # TF-Mv1.5.0
-SRCBRANCH_tfm = "release/1.5.x"
 SRCREV_tfm = "6fb14a14140f94150f959c88e3b880f48372da06"
 # mbedtls-3.0.0
 SRCREV_mbedtls = "8df2f8e7b9c7bb9390ac74bb7bace27edca81a2b"
@@ -49,6 +48,7 @@ PACKAGE_ARCH = "${MACHINE_ARCH}"
 
 DEPENDS += "cmake-native \
             ninja-native \
+            gcc-arm-none-eabi-native \
             python3-intelhex-native \
             python3-jinja2-native \
             python3-pyyaml-native \
@@ -69,14 +69,14 @@ python() {
         raise bb.parse.SkipRecipe("TFM_PLATFORM needs to be set")
 }
 
-PACKAGECONFIG ??= "cc-gnuarm"
-# What compiler to use
-PACKAGECONFIG[cc-gnuarm] = "-DTFM_TOOLCHAIN_FILE=${S}/toolchain_GNUARM.cmake,,gcc-arm-none-eabi-native"
-PACKAGECONFIG[cc-armclang] = "-DTFM_TOOLCHAIN_FILE=${S}/toolchain_ARMCLANG.cmake,,armcompiler-native"
+PACKAGECONFIG ??= ""
 # Whether to integrate the test suite
 PACKAGECONFIG[test-secure] = "-DTEST_S=ON,-DTEST_S=OFF"
 PACKAGECONFIG[test-nonsecure] = "-DTEST_NS=ON,-DTEST_NS=OFF"
 
+# Currently we only support using the Arm binary GCC
+EXTRA_OECMAKE += "-DTFM_TOOLCHAIN_FILE=${S}/toolchain_GNUARM.cmake"
+
 # Don't let FetchContent download more sources during do_configure
 EXTRA_OECMAKE += "-DFETCHCONTENT_FULLY_DISCONNECTED=ON"
 

meta-arm/recipes-bsp/uefi/edk2-firmware.inc

@@ -18,6 +18,9 @@ SRC_URI = "\
     ${EDK2_SRC_URI};name=edk2;destsuffix=edk2;nobranch=1 \
     ${EDK2_PLATFORMS_SRC_URI};name=edk2-platforms;destsuffix=edk2/edk2-platforms;nobranch=1 \
     file://unaligned.patch \
+    file://0001-Basetools-turn-off-gcc12-warning.patch \
+    file://0002-BaseTools-fix-gcc12-warning.patch \
+    file://0003-BaseTools-fix-gcc12-warning.patch \
 "
 
 SRCREV_FORMAT         = "edk2_edk2-platforms"
@@ -74,9 +77,14 @@ export BTOOLS_PATH = "${EDK_TOOLS_PATH}/BinWrappers/PosixLike"
 
 EDK_COMPILER ?= "GCC5"
 export GCC5_AARCH64_PREFIX = "${TARGET_PREFIX}"
+export GCC5_ARM_PREFIX = "${TARGET_PREFIX}"
 
 EDK_COMPILER:toolchain-clang = "CLANG38"
 export CLANG38_AARCH64_PREFIX = "${TARGET_PREFIX}"
+export CLANG38_ARM_PREFIX = "${TARGET_PREFIX}"
+
+#FIXME - arm32 doesn't work with clang due to a linker issue
+TOOLCHAIN:arm = "gcc"
 
 do_configure:prepend() {
     sed -i -e "s#-target ${HOST_ARCH}-linux-gnu*#-target ${HOST_SYS}#" ${S}/BaseTools/Conf/tools_def.template

meta-arm/recipes-bsp/uefi/edk2-firmware_%.bbappend

@@ -3,6 +3,15 @@ EDK2_PLATFORM:qemuarm64-secureboot      = "ArmVirtQemu-AARCH64"
 EDK2_PLATFORM_DSC:qemuarm64-secureboot  = "ArmVirtPkg/ArmVirtQemu.dsc"
 EDK2_BIN_NAME:qemuarm64-secureboot      = "QEMU_EFI.fd"
 
+COMPATIBLE_MACHINE:qemuarm64 = "qemuarm64"
+EDK2_PLATFORM:qemuarm64      = "ArmVirtQemu-AARCH64"
+EDK2_PLATFORM_DSC:qemuarm64  = "ArmVirtPkg/ArmVirtQemu.dsc"
+EDK2_BIN_NAME:qemuarm64      = "QEMU_EFI.fd"
+
+COMPATIBLE_MACHINE:qemuarm = "qemuarm"
+EDK2_PLATFORM:qemuarm      = "ArmVirtQemu-ARM"
+EDK2_PLATFORM_DSC:qemuarm  = "ArmVirtPkg/ArmVirtQemu.dsc"
+EDK2_BIN_NAME:qemuarm      = "QEMU_EFI.fd"
 
 COMPATIBLE_MACHINE:qemu-generic-arm64   = "qemu-generic-arm64"
 DEPENDS:append:qemu-generic-arm64       = " trusted-firmware-a coreutils-native"
@@ -21,3 +30,11 @@ do_install:append:qemu-generic-arm64() {
     # QEMU requires that the images be minimum of 256M in size
     truncate -s 256M ${D}/firmware/SBSA_FLASH*.fd
 }
+
+do_install:append:qemuarm64() {
+    install ${B}/Build/${EDK2_PLATFORM}/${EDK2_BUILD_MODE}_${EDK_COMPILER}/FV/${EDK2_BIN_NAME} ${D}/firmware/
+}
+
+do_install:append:qemuarm() {
+    install ${B}/Build/${EDK2_PLATFORM}/${EDK2_BUILD_MODE}_${EDK_COMPILER}/FV/${EDK2_BIN_NAME} ${D}/firmware/
+}

meta-arm/recipes-bsp/uefi/files/0001-Basetools-turn-off-gcc12-warning.patch

@@ -0,0 +1,39 @@
+From 22130dcd98b4d4b76ac8d922adb4a2dbc86fa52c Mon Sep 17 00:00:00 2001
+From: Gerd Hoffmann <kraxel@redhat.com>
+Date: Thu, 24 Mar 2022 20:04:36 +0800
+Subject: [PATCH] Basetools: turn off gcc12 warning
+
+In function ?SetDevicePathEndNode?,
+    inlined from ?FileDevicePath? at DevicePathUtilities.c:857:5:
+DevicePathUtilities.c:321:3: error: writing 4 bytes into a region of size 1 [-Werror=stringop-overflow=]
+  321 |   memcpy (Node, &mUefiDevicePathLibEndDevicePath, sizeof (mUefiDevicePathLibEndDevicePath));
+      |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+In file included from UefiDevicePathLib.h:22,
+                 from DevicePathUtilities.c:16:
+../Include/Protocol/DevicePath.h: In function ?FileDevicePath?:
+../Include/Protocol/DevicePath.h:51:9: note: destination object ?Type? of size 1
+   51 |   UINT8 Type;       ///< 0x01 Hardware Device Path.
+      |         ^~~~
+
+Upstream-Status: Backport
+Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
+Reviewed-by: Bob Feng <bob.c.feng@intel.com>
+Signed-off-by: Maciej Borzecki <maciek@thing.com>
+---
+ BaseTools/Source/C/DevicePath/GNUmakefile | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/BaseTools/Source/C/DevicePath/GNUmakefile b/BaseTools/Source/C/DevicePath/GNUmakefile
+index 7ca08af9662d..b05d2bddfa68 100644
+--- a/BaseTools/Source/C/DevicePath/GNUmakefile
++++ b/BaseTools/Source/C/DevicePath/GNUmakefile
+@@ -13,6 +13,9 @@ OBJECTS = DevicePath.o UefiDevicePathLib.o DevicePathFromText.o  DevicePathUtili
+ 
+ include $(MAKEROOT)/Makefiles/app.makefile
+ 
++# gcc 12 trips over device path handling
++BUILD_CFLAGS += -Wno-error=stringop-overflow
++
+ LIBS = -lCommon
+ ifeq ($(CYGWIN), CYGWIN)
+   LIBS += -L/lib/e2fsprogs -luuid

meta-arm/recipes-bsp/uefi/files/0002-BaseTools-fix-gcc12-warning.patch

@@ -0,0 +1,49 @@
+From 85021f8cf22d1bd4114803c6c610dea5ef0059f1 Mon Sep 17 00:00:00 2001
+From: Gerd Hoffmann <kraxel@redhat.com>
+Date: Thu, 24 Mar 2022 20:04:35 +0800
+Subject: [PATCH] BaseTools: fix gcc12 warning
+
+Sdk/C/LzmaEnc.c: In function ?LzmaEnc_CodeOneMemBlock?:
+Sdk/C/LzmaEnc.c:2828:19: error: storing the address of local variable ?outStream? in ?*p.rc.outStream? [-Werror=dangling-pointer=]
+ 2828 |   p->rc.outStream = &outStream.vt;
+      |   ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
+Sdk/C/LzmaEnc.c:2811:28: note: ?outStream? declared here
+ 2811 |   CLzmaEnc_SeqOutStreamBuf outStream;
+      |                            ^~~~~~~~~
+Sdk/C/LzmaEnc.c:2811:28: note: ?pp? declared here
+Sdk/C/LzmaEnc.c:2828:19: error: storing the address of local variable ?outStream? in ?*(CLzmaEnc *)pp.rc.outStream? [-Werror=dangling-pointer=]
+ 2828 |   p->rc.outStream = &outStream.vt;
+      |   ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
+Sdk/C/LzmaEnc.c:2811:28: note: ?outStream? declared here
+ 2811 |   CLzmaEnc_SeqOutStreamBuf outStream;
+      |                            ^~~~~~~~~
+Sdk/C/LzmaEnc.c:2811:28: note: ?pp? declared here
+cc1: all warnings being treated as errors
+
+Upstream-Status: Backport
+Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
+Reviewed-by: Bob Feng <bob.c.feng@intel.com>
+Signed-off-by: Maciej Borzecki <maciek@thing.com>
+---
+ BaseTools/Source/C/LzmaCompress/Sdk/C/LzmaEnc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/BaseTools/Source/C/LzmaCompress/Sdk/C/LzmaEnc.c b/BaseTools/Source/C/LzmaCompress/Sdk/C/LzmaEnc.c
+index 4e9b499f8d80..4b9f5fa69248 100644
+--- a/BaseTools/Source/C/LzmaCompress/Sdk/C/LzmaEnc.c
++++ b/BaseTools/Source/C/LzmaCompress/Sdk/C/LzmaEnc.c
+@@ -2825,12 +2825,13 @@ SRes LzmaEnc_CodeOneMemBlock(CLzmaEncHandle pp, BoolInt reInit,
+ 
+   nowPos64 = p->nowPos64;
+   RangeEnc_Init(&p->rc);
+-  p->rc.outStream = &outStream.vt;
+ 
+   if (desiredPackSize == 0)
+     return SZ_ERROR_OUTPUT_EOF;
+ 
++  p->rc.outStream = &outStream.vt;
+   res = LzmaEnc_CodeOneBlock(p, desiredPackSize, *unpackSize);
++  p->rc.outStream = NULL;
+ 
+   *unpackSize = (UInt32)(p->nowPos64 - nowPos64);
+   *destLen -= outStream.rem;

meta-arm/recipes-bsp/uefi/files/0003-BaseTools-fix-gcc12-warning.patch

@@ -0,0 +1,47 @@
+From 7b005f344e533cd913c3ca05b266f9872df886d1 Mon Sep 17 00:00:00 2001
+From: Gerd Hoffmann <kraxel@redhat.com>
+Date: Thu, 24 Mar 2022 20:04:34 +0800
+Subject: [PATCH] BaseTools: fix gcc12 warning
+
+GenFfs.c:545:5: error: pointer ?InFileHandle? used after ?fclose? [-Werror=use-after-free]
+  545 |     Error(NULL, 0, 4001, "Resource", "memory cannot be allocated  of %s", InFileHandle);
+      |     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+GenFfs.c:544:5: note: call to ?fclose? here
+  544 |     fclose (InFileHandle);
+      |     ^~~~~~~~~~~~~~~~~~~~~
+
+Upstream-Status: Backport
+Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
+Reviewed-by: Bob Feng <bob.c.feng@intel.com>
+Signed-off-by: Maciej Borzecki <maciek@thing.com>
+---
+ BaseTools/Source/C/GenFfs/GenFfs.c | 2 +-
+ BaseTools/Source/C/GenSec/GenSec.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/BaseTools/Source/C/GenFfs/GenFfs.c b/BaseTools/Source/C/GenFfs/GenFfs.c
+index 949025c33325..d78d62ab3689 100644
+--- a/BaseTools/Source/C/GenFfs/GenFfs.c
++++ b/BaseTools/Source/C/GenFfs/GenFfs.c
+@@ -542,7 +542,7 @@ GetAlignmentFromFile(char *InFile, UINT32 *Alignment)
+   PeFileBuffer = (UINT8 *) malloc (PeFileSize);
+   if (PeFileBuffer == NULL) {
+     fclose (InFileHandle);
+-    Error(NULL, 0, 4001, "Resource", "memory cannot be allocated  of %s", InFileHandle);
++    Error(NULL, 0, 4001, "Resource", "memory cannot be allocated for %s", InFile);
+     return EFI_OUT_OF_RESOURCES;
+   }
+   fread (PeFileBuffer, sizeof (UINT8), PeFileSize, InFileHandle);
+diff --git a/BaseTools/Source/C/GenSec/GenSec.c b/BaseTools/Source/C/GenSec/GenSec.c
+index d54a4f9e0a7d..b1d05367ec0b 100644
+--- a/BaseTools/Source/C/GenSec/GenSec.c
++++ b/BaseTools/Source/C/GenSec/GenSec.c
+@@ -1062,7 +1062,7 @@ GetAlignmentFromFile(char *InFile, UINT32 *Alignment)
+   PeFileBuffer = (UINT8 *) malloc (PeFileSize);
+   if (PeFileBuffer == NULL) {
+     fclose (InFileHandle);
+-    Error(NULL, 0, 4001, "Resource", "memory cannot be allocated  of %s", InFileHandle);
++    Error(NULL, 0, 4001, "Resource", "memory cannot be allocated for %s", InFile);
+     return EFI_OUT_OF_RESOURCES;
+   }
+   fread (PeFileBuffer, sizeof (UINT8), PeFileSize, InFileHandle);

meta-arm/recipes-devtools/fvp/fvp-base-r-aem_11.17.21.bb

@@ -1,10 +0,0 @@
-require fvp-envelope.inc
-
-SUMMARY = "Arm Fixed Virtual Platform - Armv8-R Base Architecture Envelope Model FVP"
-LIC_FILES_CHKSUM = "file://license_terms/license_agreement.txt;md5=1a33828e132ba71861c11688dbb0bd16 \
-                    file://license_terms/third_party_licenses.txt;md5=41029e71051b1c786bae3112a29905a7"
-
-SRC_URI = "https://developer.arm.com/-/media/Files/downloads/ecosystem-models/${MODEL_CODE}_${PV_URL}.tgz;subdir=${BP}"
-SRC_URI[sha256sum] = "483ec3c2c6569e3e7e0c4c46329662c0d19475dee8e8947c24fa3de4b00da488"
-
-MODEL_CODE = "FVP_Base_AEMv8R"