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gcc-4.5: Remove

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Signed-off-by: Khem Raj <raj.khem@gmail.com>
This commit is contained in:
Khem Raj
2012-05-15 14:45:57 -07:00
parent 93898b626e
commit 6291c6fd12
242 changed files with 0 additions and 122182 deletions
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toolchain-layer/recipes-devtools/gcc/gcc-4.5.inc
-274
View File
@@ -1,274 +0,0 @@
require recipes-devtools/gcc/gcc-common.inc
ARM_INSTRUCTION_SET = "arm"
DEPENDS =+ "mpfr gmp libmpc elfutils"
NATIVEDEPS = "mpfr-native gmp-native gettext-native libmpc-native elfutils-native"
LICENSE="GPL-3.0-with-GCC-exception & GPLv2 & GPLv3 & LGPLv2.1 & LGPLv3"
LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
file://COPYING3;md5=d32239bcb673463ab874e80d47fae504 \
file://COPYING3.LIB;md5=6a6a8e020838b23406c81b19c1d46df6 \
file://COPYING.LIB;md5=2d5025d4aa3495befef8f17206a5b0a1 \
file://COPYING.RUNTIME;md5=fe60d87048567d4fe8c8a0ed2448bcc8"
PV = "4.5"
PR = "r49"
# BINV should be incremented after updating to a revision
# after a minor gcc release (e.g. 4.5.1 or 4.5.2) has been made
# the value will be minor-release+1 e.g. if minor release was
# 4.5.1 then the value below will be 2 which will mean 4.5.2
# which will be next minor release and so on.
BINV = "${PV}.4"
SRCREV = "184907"
BRANCH = "gcc-4_5-branch"
PR_append = "+svnr${SRCPV}"
SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
file://gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch \
file://100-uclibc-conf.patch \
file://gcc-uclibc-locale-ctype_touplow_t.patch \
file://cache-amnesia.patch \
file://gcc-flags-for-build.patch \
file://libstdc++-emit-__cxa_end_cleanup-in-text.patch \
file://Makefile.in.patch \
file://gcc-armv4-pass-fix-v4bx-to-ld.patch \
file://sh4-multilib.patch \
file://arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch \
file://cpp-honour-sysroot.patch \
\
file://linaro/gcc-4.5-linaro-r99297.patch \
file://linaro/gcc-4.5-linaro-r99298.patch \
file://linaro/gcc-4.5-linaro-r99299.patch \
file://linaro/gcc-4.5-linaro-r99300.patch \
file://linaro/gcc-4.5-linaro-r99301.patch \
file://linaro/gcc-4.5-linaro-r99302.patch \
file://linaro/gcc-4.5-linaro-r99303.patch \
file://linaro/gcc-4.5-linaro-r99304.patch \
file://linaro/gcc-4.5-linaro-r99305.patch \
file://linaro/gcc-4.5-linaro-r99306.patch \
file://linaro/gcc-4.5-linaro-r99307.patch \
file://linaro/gcc-4.5-linaro-r99308.patch \
file://linaro/gcc-4.5-linaro-r99310.patch \
file://linaro/gcc-4.5-linaro-r99312.patch \
file://linaro/gcc-4.5-linaro-r99313.patch \
file://linaro/gcc-4.5-linaro-r99314.patch \
file://linaro/gcc-4.5-linaro-r99315.patch \
file://linaro/gcc-4.5-linaro-r99316.patch \
file://linaro/gcc-4.5-linaro-r99318.patch \
file://linaro/gcc-4.5-linaro-r99319.patch \
file://linaro/gcc-4.5-linaro-r99320.patch \
file://linaro/gcc-4.5-linaro-r99321.patch \
file://linaro/gcc-4.5-linaro-r99322.patch \
file://linaro/gcc-4.5-linaro-r99323.patch \
file://linaro/gcc-4.5-linaro-r99324.patch \
file://linaro/gcc-4.5-linaro-r99325.patch \
file://linaro/gcc-4.5-linaro-r99326.patch \
file://linaro/gcc-4.5-linaro-r99327.patch \
file://linaro/gcc-4.5-linaro-r99332.patch \
file://linaro/gcc-4.5-linaro-r99335.patch \
file://linaro/gcc-4.5-linaro-r99336.patch \
file://linaro/gcc-4.5-linaro-r99337.patch \
file://linaro/gcc-4.5-linaro-r99338.patch \
file://linaro/gcc-4.5-linaro-r99339.patch \
file://linaro/gcc-4.5-linaro-r99340.patch \
file://linaro/gcc-4.5-linaro-r99341.patch \
file://linaro/gcc-4.5-linaro-r99342.patch \
file://linaro/gcc-4.5-linaro-r99343.patch \
file://linaro/gcc-4.5-linaro-r99344.patch \
file://linaro/gcc-4.5-linaro-r99345.patch \
file://linaro/gcc-4.5-linaro-r99346.patch \
file://linaro/gcc-4.5-linaro-r99348.patch \
file://linaro/gcc-4.5-linaro-r99349.patch \
file://linaro/gcc-4.5-linaro-r99351.patch \
file://linaro/gcc-4.5-linaro-r99352.patch \
file://linaro/gcc-4.5-linaro-r99353.patch \
file://linaro/gcc-4.5-linaro-r99354.patch \
file://linaro/gcc-4.5-linaro-r99355.patch \
file://linaro/gcc-4.5-linaro-r99356.patch \
file://linaro/gcc-4.5-linaro-r99357.patch \
file://linaro/gcc-4.5-linaro-r99358.patch \
file://linaro/gcc-4.5-linaro-r99359.patch \
file://linaro/gcc-4.5-linaro-r99360.patch \
file://linaro/gcc-4.5-linaro-r99361.patch \
file://linaro/gcc-4.5-linaro-r99363.patch \
file://linaro/gcc-4.5-linaro-r99364.patch \
file://linaro/gcc-4.5-linaro-r99365.patch \
file://linaro/gcc-4.5-linaro-r99366.patch \
file://linaro/gcc-4.5-linaro-r99367.patch \
file://linaro/gcc-4.5-linaro-r99368.patch \
file://linaro/gcc-4.5-linaro-r99369.patch \
file://linaro/gcc-4.5-linaro-r99371.patch \
file://linaro/gcc-4.5-linaro-r99372.patch \
file://linaro/gcc-4.5-linaro-r99373.patch \
file://linaro/gcc-4.5-linaro-r99374.patch \
file://linaro/gcc-4.5-linaro-r99375.patch \
file://linaro/gcc-4.5-linaro-r99376.patch \
file://linaro/gcc-4.5-linaro-r99377.patch \
file://linaro/gcc-4.5-linaro-r99378.patch \
file://linaro/gcc-4.5-linaro-r99379.patch \
file://linaro/gcc-4.5-linaro-r99380.patch \
file://linaro/gcc-4.5-linaro-r99381.patch \
file://linaro/gcc-4.5-linaro-r99383.patch \
file://linaro/gcc-4.5-linaro-r99384.patch \
file://linaro/gcc-4.5-linaro-r99385.patch \
file://linaro/gcc-4.5-linaro-r99388.patch \
file://linaro/gcc-4.5-linaro-r99391.patch \
file://linaro/gcc-4.5-linaro-r99392.patch \
file://linaro/gcc-4.5-linaro-r99393.patch \
file://linaro/gcc-4.5-linaro-r99395.patch \
file://linaro/gcc-4.5-linaro-r99396.patch \
file://linaro/gcc-4.5-linaro-r99397.patch \
file://linaro/gcc-4.5-linaro-r99398.patch \
file://linaro/gcc-4.5-linaro-r99402.patch \
file://linaro/gcc-4.5-linaro-r99403.patch \
file://linaro/gcc-4.5-linaro-r99404.patch \
file://linaro/gcc-4.5-linaro-r99405.patch \
file://linaro/gcc-4.5-linaro-r99406.patch \
file://linaro/gcc-4.5-linaro-r99407.patch \
file://linaro/gcc-4.5-linaro-r99408.patch \
file://linaro/gcc-4.5-linaro-r99409.patch \
file://linaro/gcc-4.5-linaro-r99410.patch \
file://linaro/gcc-4.5-linaro-r99411.patch \
file://linaro/gcc-4.5-linaro-r99412.patch \
file://linaro/gcc-4.5-linaro-r99413.patch \
file://linaro/gcc-4.5-linaro-r99415.patch \
file://linaro/gcc-4.5-linaro-r99416.patch \
file://linaro/gcc-4.5-linaro-r99417.patch \
file://linaro/gcc-4.5-linaro-r99418.patch \
file://linaro/gcc-4.5-linaro-r99419.patch \
file://linaro/gcc-4.5-linaro-r99420.patch \
file://linaro/gcc-4.5-linaro-r99421.patch \
file://linaro/gcc-4.5-linaro-r99423.patch \
file://linaro/gcc-4.5-linaro-r99424.patch \
file://linaro/gcc-4.5-linaro-r99425.patch \
file://linaro/gcc-4.5-linaro-r99426.patch \
file://linaro/gcc-4.5-linaro-r99429.patch \
file://linaro/gcc-4.5-linaro-r99432.patch \
file://linaro/gcc-4.5-linaro-r99433.patch \
file://linaro/gcc-4.5-linaro-r99434.patch \
file://linaro/gcc-4.5-linaro-r99435.patch \
file://linaro/gcc-4.5-linaro-r99436.patch \
file://linaro/gcc-4.5-linaro-r99437.patch \
file://linaro/gcc-4.5-linaro-r99439.patch \
file://linaro/gcc-4.5-linaro-r99440.patch \
file://linaro/gcc-4.5-linaro-r99441.patch \
file://linaro/gcc-4.5-linaro-r99442.patch \
file://linaro/gcc-4.5-linaro-r99443.patch \
file://linaro/gcc-4.5-linaro-r99444.patch \
file://linaro/gcc-4.5-linaro-r99449.patch \
file://linaro/gcc-4.5-linaro-r99450.patch \
file://linaro/gcc-4.5-linaro-r99451.patch \
file://linaro/gcc-4.5-linaro-r99452.patch \
file://linaro/gcc-4.5-linaro-r99453.patch \
file://linaro/gcc-4.5-linaro-r99454.patch \
file://linaro/gcc-4.5-linaro-r99455.patch \
file://linaro/gcc-4.5-linaro-r99464.patch \
file://linaro/gcc-4.5-linaro-r99465.patch \
file://linaro/gcc-4.5-linaro-r99466.patch \
file://linaro/gcc-4.5-linaro-r99468.patch \
file://linaro/gcc-4.5-linaro-r99473.patch \
file://linaro/gcc-4.5-linaro-r99475.patch \
file://linaro/gcc-4.5-linaro-r99478.patch \
file://linaro/gcc-4.5-linaro-r99479.patch \
file://linaro/gcc-4.5-linaro-r99480.patch \
file://linaro/gcc-4.5-linaro-r99483.patch \
file://linaro/gcc-4.5-linaro-r99488.patch \
file://linaro/gcc-4.5-linaro-r99489.patch \
file://linaro/gcc-4.5-linaro-r99494.patch \
file://linaro/gcc-4.5-linaro-r99495.patch \
file://linaro/gcc-4.5-linaro-r99498.patch \
file://linaro/gcc-4.5-linaro-r99502.patch \
file://linaro/gcc-4.5-linaro-r99503.patch \
file://linaro/gcc-4.5-linaro-r99504.patch \
file://linaro/gcc-4.5-linaro-r99506.patch \
file://linaro/gcc-4.5-linaro-r99507.patch \
file://linaro/gcc-4.5-linaro-r99510.patch \
file://linaro/gcc-4.5-linaro-r99511.patch \
file://linaro/gcc-4.5-linaro-r99514.patch \
file://linaro/gcc-4.5-linaro-r99516.patch \
file://linaro/gcc-4.5-linaro-r99519.patch \
file://linaro/gcc-4.5-linaro-r99521.patch \
file://linaro/gcc-4.5-linaro-r99522.patch \
file://linaro/gcc-4.5-linaro-r99523.patch \
file://linaro/gcc-4.5-linaro-r99524.patch \
file://linaro/gcc-4.5-linaro-r99525.patch \
file://linaro/gcc-4.5-linaro-r99528.patch \
file://linaro/gcc-4.5-linaro-r99529.patch \
file://linaro/gcc-4.5-linaro-r99530.patch \
file://linaro/gcc-4.5-linaro-r99531.patch \
file://linaro/gcc-4.5-linaro-r99532.patch \
file://linaro/gcc-4.5-linaro-r99533.patch \
file://linaro/gcc-4.5-linaro-r99534.patch \
file://linaro/gcc-4.5-linaro-r99536.patch \
file://linaro/gcc-4.5-linaro-r99537.patch \
file://linaro/gcc-4.5-linaro-r99540.patch \
file://linaro/gcc-4.5-linaro-r99548.patch \
file://linaro/gcc-4.5-linaro-r99549.patch \
\
file://more-epilogues.patch \
file://gcc-scalar-widening-pr45847.patch \
file://gcc-arm-volatile-bitfield-fix.patch \
\
file://fedora/gcc43-c++-builtin-redecl.patch;striplevel=0 \
file://fedora/gcc43-ia64-libunwind.patch;striplevel=0 \
file://fedora/gcc43-java-nomulti.patch;striplevel=0 \
file://fedora/gcc43-ppc32-retaddr.patch;striplevel=0 \
file://fedora/gcc43-pr32139.patch;striplevel=0 \
file://fedora/gcc43-pr33763.patch;striplevel=0 \
file://fedora/gcc43-rh330771.patch;striplevel=0 \
file://fedora/gcc43-rh341221.patch;striplevel=0 \
file://fedora/gcc43-java-debug-iface-type.patch;striplevel=0 \
file://fedora/gcc43-i386-libgomp.patch;striplevel=0 \
file://fedora/gcc45-no-add-needed.patch;striplevel=0 \
file://optional_libstdc.patch \
file://64bithack.patch \
file://COLLECT_GCC_OPTIONS.patch \
file://gcc-poison-dir-extend.patch \
file://gcc-poison-parameters.patch \
file://gcc-ppc-config-fix.patch \
file://use-defaults.h-and-t-oe-in-B.patch \
file://gcc-with-linker-hash-style.patch \
file://GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch \
\
file://fortran-cross-compile-hack.patch \
"
# Language Overrides
FORTRAN = ""
JAVA = ""
S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/${BRANCH}"
B = "${WORKDIR}/${BRANCH}/build.${HOST_SYS}.${TARGET_SYS}"
#EXTRA_OECONF_BASE = " --enable-cheaders=c_std \
# --enable-libssp \
# --disable-bootstrap \
# --disable-libgomp \
# --disable-libmudflap"
EXTRA_OECONF_BASE = "--enable-lto \
--enable-libssp \
--disable-bootstrap \
--disable-libgomp \
--disable-libmudflap \
--with-linker-hash-style=${LINKER_HASH_STYLE} \
--with-ppl=no \
--with-cloog=no \
--enable-cheaders=c_global "
EXTRA_OECONF_INITIAL = "--disable-libmudflap \
--disable-libgomp \
--disable-libssp \
--enable-decimal-float=no"
EXTRA_OECONF_INTERMEDIATE = "--disable-libmudflap \
--disable-libgomp \
--disable-libssp"
EXTRA_OECONF_append_libc-uclibc = " --disable-decimal-float "
EXTRA_OECONF_append_mips64 = " --with-arch-64=mips64 --with-tune-64=mips64"
EXTRA_OECONF_append_mips64el = " --with-arch-64=mips64 --with-tune-64=mips64"
toolchain-layer/recipes-devtools/gcc/gcc-4.5/100-uclibc-conf.patch
-37
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@@ -1,37 +0,0 @@
Index: gcc-4.3.1/contrib/regression/objs-gcc.sh
===================================================================
--- gcc-4.3.1.orig/contrib/regression/objs-gcc.sh 2007-12-24 15:18:57.000000000 -0800
+++ gcc-4.3.1/contrib/regression/objs-gcc.sh 2008-08-16 01:15:12.000000000 -0700
@@ -105,6 +105,10 @@
then
make all-gdb all-dejagnu all-ld || exit 1
make install-gdb install-dejagnu install-ld || exit 1
+elif [ $H_REAL_TARGET = $H_REAL_HOST -a $H_REAL_TARGET = i686-pc-linux-uclibc ]
+ then
+ make all-gdb all-dejagnu all-ld || exit 1
+ make install-gdb install-dejagnu install-ld || exit 1
elif [ $H_REAL_TARGET = $H_REAL_HOST ] ; then
make bootstrap || exit 1
make install || exit 1
Index: gcc-4.3.1/libjava/classpath/ltconfig
===================================================================
--- gcc-4.3.1.orig/libjava/classpath/ltconfig 2007-06-03 16:18:43.000000000 -0700
+++ gcc-4.3.1/libjava/classpath/ltconfig 2008-08-16 01:15:12.000000000 -0700
@@ -603,7 +603,7 @@
# Transform linux* to *-*-linux-gnu*, to support old configure scripts.
case $host_os in
-linux-gnu*) ;;
+linux-gnu*|linux-uclibc*) ;;
linux*) host=`echo $host | sed 's/^\(.*-.*-linux\)\(.*\)$/\1-gnu\2/'`
esac
@@ -1251,7 +1251,7 @@
;;
# This must be Linux ELF.
-linux-gnu*)
+linux*)
version_type=linux
need_lib_prefix=no
need_version=no
toolchain-layer/recipes-devtools/gcc/gcc-4.5/602-sdk-libstdc++-includes.patch
-20
View File
@@ -1,20 +0,0 @@
--- gcc-4.1.0/libstdc++-v3/fragment.am 2005-03-21 11:40:14.000000000 -0600
+++ gcc-4.1.0-patched/libstdc++-v3/fragment.am 2005-04-25 20:14:39.856251785 -0500
@@ -21,5 +21,5 @@
$(WARN_FLAGS) $(WERROR) -fdiagnostics-show-location=once
# -I/-D flags to pass when compiling.
-AM_CPPFLAGS = $(GLIBCXX_INCLUDES)
+AM_CPPFLAGS = $(GLIBCXX_INCLUDES) -I$(toplevel_srcdir)/include
--- gcc-4.1.0/libstdc++-v3/libmath/Makefile.am 2005-03-21 11:40:18.000000000 -0600
+++ gcc-4.1.0-patched/libstdc++-v3/libmath/Makefile.am 2005-04-25 20:14:39.682280735 -0500
@@ -35,7 +35,7 @@
libmath_la_SOURCES = stubs.c
-AM_CPPFLAGS = $(CANADIAN_INCLUDES)
+AM_CPPFLAGS = $(CANADIAN_INCLUDES) -I$(toplevel_srcdir)/include
# Only compiling "C" sources in this directory.
LIBTOOL = @LIBTOOL@ --tag CC
toolchain-layer/recipes-devtools/gcc/gcc-4.5/64bithack.patch
-68
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@@ -1,68 +0,0 @@
Upstream-Status: Inappropriate [embedded specific]
GCC has internal multilib handling code but it assumes a very specific rigid directory
layout. The build system implementation of multilib layout is very generic and allows
complete customisation of the library directories.
This patch is a partial solution to allow any custom directories to be passed into gcc
and handled correctly. It forces gcc to use the base_libdir (which is the current
directory, "."). We need to do this for each multilib that is configured as we don't
know which compiler options may be being passed into the compiler. Since we have a compiler
per mulitlib at this point that isn't an issue.
The one problem is the target compiler is only going to work for the default multlilib at
this point. Ideally we'd figure out which multilibs were being enabled with which paths
and be able to patch these entries with a complete set of correct paths but this we
don't have such code at this point. This is something the target gcc recipe should do
and override these platform defaults in its build config.
RP 15/8/11
Index: gcc-4_5-branch/gcc/config/i386/t-linux64
===================================================================
--- gcc-4_5-branch.orig/gcc/config/i386/t-linux64 2011-09-22 11:37:51.188913390 -0700
+++ gcc-4_5-branch/gcc/config/i386/t-linux64 2011-09-22 11:37:56.818913303 -0700
@@ -24,8 +24,8 @@
# MULTILIB_OSDIRNAMES according to what is found on the target.
MULTILIB_OPTIONS = m64/m32
-MULTILIB_DIRNAMES = 64 32
-MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)
+MULTILIB_DIRNAMES = . .
+MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
LIBGCC = stmp-multilib
INSTALL_LIBGCC = install-multilib
Index: gcc-4_5-branch/gcc/config/mips/t-linux64
===================================================================
--- gcc-4_5-branch.orig/gcc/config/mips/t-linux64 2011-06-16 17:59:02.000000000 -0700
+++ gcc-4_5-branch/gcc/config/mips/t-linux64 2011-09-22 11:37:56.838913302 -0700
@@ -17,8 +17,8 @@
# <http://www.gnu.org/licenses/>.
MULTILIB_OPTIONS = mabi=n32/mabi=32/mabi=64
-MULTILIB_DIRNAMES = n32 32 64
-MULTILIB_OSDIRNAMES = ../lib32 ../lib ../lib64
+MULTILIB_DIRNAMES = . . .
+MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o
Index: gcc-4_5-branch/gcc/config/rs6000/t-linux64
===================================================================
--- gcc-4_5-branch.orig/gcc/config/rs6000/t-linux64 2011-06-16 17:58:58.000000000 -0700
+++ gcc-4_5-branch/gcc/config/rs6000/t-linux64 2011-09-22 11:37:56.838913302 -0700
@@ -32,11 +32,11 @@ TARGET_LIBGCC2_CFLAGS += -mno-minimal-to
# MULTILIB_OSDIRNAMES according to what is found on the target.
MULTILIB_OPTIONS = m64/m32 msoft-float
-MULTILIB_DIRNAMES = 64 32 nof
+MULTILIB_DIRNAMES = . . .
MULTILIB_EXTRA_OPTS = fPIC mstrict-align
MULTILIB_EXCEPTIONS = m64/msoft-float
MULTILIB_EXCLUSIONS = m64/!m32/msoft-float
-MULTILIB_OSDIRNAMES = ../lib64 $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib) nof
+MULTILIB_OSDIRNAMES = ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir)) ../$(shell basename $(base_libdir))
MULTILIB_MATCHES = $(MULTILIB_MATCHES_FLOAT)
softfp_wrap_start := '\#ifndef __powerpc64__'
toolchain-layer/recipes-devtools/gcc/gcc-4.5/740-sh-pr24836.patch
-29
View File
@@ -1,29 +0,0 @@
http://sourceforge.net/mailarchive/forum.php?thread_id=8959304&forum_id=5348
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=24836
Index: gcc-4.5.0/gcc/configure.ac
===================================================================
--- gcc-4.5.0.orig/gcc/configure.ac 2010-03-25 22:40:32.000000000 -0700
+++ gcc-4.5.0/gcc/configure.ac 2010-06-25 11:02:48.489057877 -0700
@@ -2784,7 +2784,7 @@
tls_first_minor=14
tls_as_opt="-m64 -Aesame --fatal-warnings"
;;
- sh-*-* | sh[34]-*-*)
+ sh-*-* | sh[34]*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25
Index: gcc-4.5.0/gcc/configure
===================================================================
--- gcc-4.5.0.orig/gcc/configure 2010-03-25 22:40:32.000000000 -0700
+++ gcc-4.5.0/gcc/configure 2010-06-25 11:02:48.508381845 -0700
@@ -22156,7 +22156,7 @@
tls_first_minor=14
tls_as_opt="-m64 -Aesame --fatal-warnings"
;;
- sh-*-* | sh[34]-*-*)
+ sh-*-* | sh[34]*-*-*)
conftest_s='
.section ".tdata","awT",@progbits
foo: .long 25
toolchain-layer/recipes-devtools/gcc/gcc-4.5/800-arm-bigendian.patch
-34
View File
@@ -1,34 +0,0 @@
By Lennert Buytenhek <buytenh@wantstofly.org>
Adds support for arm*b-linux* big-endian ARM targets
See http://gcc.gnu.org/PR16350
Index: gcc-4.5.0/gcc/config/arm/linux-elf.h
===================================================================
--- gcc-4.5.0.orig/gcc/config/arm/linux-elf.h 2009-11-05 06:47:45.000000000 -0800
+++ gcc-4.5.0/gcc/config/arm/linux-elf.h 2010-06-25 11:03:06.997132728 -0700
@@ -51,7 +51,7 @@
#undef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS \
- { "marm", "mlittle-endian", "mhard-float", "mno-thumb-interwork" }
+ { "marm", TARGET_ENDIAN_OPTION, "mhard-float", "mno-thumb-interwork" }
/* Now we define the strings used to build the spec file. */
#undef LIB_SPEC
Index: gcc-4.5.0/gcc/config.gcc
===================================================================
--- gcc-4.5.0.orig/gcc/config.gcc 2010-06-25 10:40:33.321880880 -0700
+++ gcc-4.5.0/gcc/config.gcc 2010-06-25 11:03:07.013133525 -0700
@@ -734,6 +734,11 @@
esac
tmake_file="${tmake_file} t-linux arm/t-arm"
case ${target} in
+ arm*b-*)
+ tm_defines="${tm_defines} TARGET_BIG_ENDIAN_DEFAULT=1"
+ ;;
+ esac
+ case ${target} in
arm*-*-linux-*eabi)
tm_file="$tm_file arm/bpabi.h arm/linux-eabi.h"
tmake_file="$tmake_file arm/t-arm-elf arm/t-bpabi arm/t-linux-eabi t-slibgcc-libgcc"
toolchain-layer/recipes-devtools/gcc/gcc-4.5/904-flatten-switch-stmt-00.patch
-74
View File
@@ -1,74 +0,0 @@
Hi,
The attached patch makes sure that we create smaller object code for
simple switch statements. We just make sure to flatten the switch
statement into an if-else chain, basically.
This fixes a size-regression as compared to gcc-3.4, as can be seen
below.
2007-04-15 Bernhard Fischer <..>
* stmt.c (expand_case): Do not create a complex binary tree when
optimizing for size but rather use the simple ordered list.
(emit_case_nodes): do not emit jumps to the default_label when
optimizing for size.
Not regtested so far.
Comments?
Attached is the test switch.c mentioned below.
$ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
gcc-$i -DCHAIN -Os -o switch-CHAIN-$i.o -c switch.c ;done
$ for i in 2.95 3.3 3.4 4.0 4.1 4.2.orig-HEAD 4.3.orig-HEAD 4.3-HEAD;do
gcc-$i -UCHAIN -Os -o switch-$i.o -c switch.c ;done
$ size switch-*.o
text data bss dec hex filename
169 0 0 169 a9 switch-2.95.o
115 0 0 115 73 switch-3.3.o
103 0 0 103 67 switch-3.4.o
124 0 0 124 7c switch-4.0.o
124 0 0 124 7c switch-4.1.o
124 0 0 124 7c switch-4.2.orig-HEAD.o
95 0 0 95 5f switch-4.3-HEAD.o
124 0 0 124 7c switch-4.3.orig-HEAD.o
166 0 0 166 a6 switch-CHAIN-2.95.o
111 0 0 111 6f switch-CHAIN-3.3.o
95 0 0 95 5f switch-CHAIN-3.4.o
95 0 0 95 5f switch-CHAIN-4.0.o
95 0 0 95 5f switch-CHAIN-4.1.o
95 0 0 95 5f switch-CHAIN-4.2.orig-HEAD.o
95 0 0 95 5f switch-CHAIN-4.3-HEAD.o
95 0 0 95 5f switch-CHAIN-4.3.orig-HEAD.o
Content-Type: text/x-diff; charset=us-ascii
Content-Disposition: attachment; filename="gcc-4.3.gcc-flatten-switch-stmt.00.diff"
Index: gcc-4.5.0/gcc/stmt.c
===================================================================
--- gcc-4.5.0.orig/gcc/stmt.c 2010-02-19 01:53:51.000000000 -0800
+++ gcc-4.5.0/gcc/stmt.c 2010-06-25 11:05:31.816881094 -0700
@@ -2440,7 +2440,11 @@
default code is emitted. */
use_cost_table = estimate_case_costs (case_list);
- balance_case_nodes (&case_list, NULL);
+ /* When optimizing for size, we want a straight list to avoid
+ jumps as much as possible. This basically creates an if-else
+ chain. */
+ if (!optimize_size)
+ balance_case_nodes (&case_list, NULL);
emit_case_nodes (index, case_list, default_label, index_type);
if (default_label)
emit_jump (default_label);
@@ -3008,6 +3012,7 @@
{
if (!node_has_low_bound (node, index_type))
{
+ if (!optimize_size) /* don't jl to the .default_label. */
emit_cmp_and_jump_insns (index,
convert_modes
(mode, imode,
toolchain-layer/recipes-devtools/gcc/gcc-4.5/COLLECT_GCC_OPTIONS.patch
-23
View File
@@ -1,23 +0,0 @@
#This patck added --sysroot into COLLECT_GCC_OPTIONS which is used to
#invoke collect2.
Index: gcc-4_5-branch/gcc/gcc.c
===================================================================
--- gcc-4_5-branch.orig/gcc/gcc.c
+++ gcc-4_5-branch/gcc/gcc.c
@@ -4667,6 +4667,15 @@ set_collect_gcc_options (void)
sizeof ("COLLECT_GCC_OPTIONS=") - 1);
first_time = TRUE;
+#ifdef HAVE_LD_SYSROOT
+ if (target_system_root_changed && target_system_root)
+ {
+ obstack_grow (&collect_obstack, "'--sysroot=", sizeof("'--sysroot=")-1);
+ obstack_grow (&collect_obstack, target_system_root,strlen(target_system_root));
+ obstack_grow (&collect_obstack, "'", 1);
+ first_time = FALSE;
+ }
+#endif
for (i = 0; (int) i < n_switches; i++)
{
const char *const *args;
toolchain-layer/recipes-devtools/gcc/gcc-4.5/GPLUSPLUS_INCLUDE_DIR_with_sysroot.patch
-178
View File
@@ -1,178 +0,0 @@
source: http://patchwork.ozlabs.org/patch/129800/
Upstream-Status: Submitted
ChangeLog
* Makefile.in (gcc_gxx_include_dir_add_sysroot): New.
(PREPROCESSOR_DEFINES): Define GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT.
* cppdefault.c (cpp_include_defaults): replace hard coded "1" with
GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT for "add_sysroot" field.
* configure.ac (AC_SUBST): Add gcc_gxx_include_dir_add_sysroot to
control whether sysroot should be prepended to gxx include dir.
* configure: Regenerate.
Hi, this is a follow up for issue "http://codereview.appspot.com/4641076".
The rationale for the patch copied from previous thread:
=======================================
The setup:
Configuring a toolchain targeting x86-64 GNU Linux (Ubuntu Lucid), as a
cross-compiler. Using a sysroot to provide the Lucid headers+libraries,
with the sysroot path being within the GCC install tree. Want to use the
Lucid system libstdc++ and headers, which means that I'm not
building/installing libstdc++-v3.
So, configuring with:
--with-sysroot="$SYSROOT"
--disable-libstdc++-v3 \
--with-gxx-include-dir="$SYSROOT/usr/include/c++/4.4" \
(among other options).
Hoping to support two usage models with this configuration, w.r.t. use of
the sysroot:
(1) somebody installs the sysroot in the normal location relative to the
GCC install, and relocates the whole bundle (sysroot+GCC). This works
great AFAICT, GCC finds its includes (including the C++ includes) thanks
to the add_standard_paths iprefix handling.
(2) somebody installs the sysroot in a non-standard location, and uses
--sysroot to try to access it. This works fine for the C headers, but
doesn't work.
For the C headers, add_standard_paths prepends the sysroot location to
the /usr/include path (since that's what's specified in cppdefault.c for
that path). It doesn't do the same for the C++ include path, though
(again, as specified in cppdefault.c).
add_standard_paths doesn't attempt to relocate built-in include paths that
start with the compiled-in sysroot location (e.g., the g++ include dir, in
this case). This isn't surprising really: normally you either prepend the
sysroot location or you don't (as specified by cppdefault.c); none of the
built-in paths normally *start* with the sysroot location and need to be
relocated. However, in this odd-ball case of trying to use the C++ headers
from the sysroot, one of the paths *does* need to be relocated in this way.
===========================
--- a/gcc/Makefile.in
+++ b/gcc/Makefile.in
@@ -585,6 +585,7 @@ slibdir = @slibdir@
build_tooldir = $(exec_prefix)/$(target_noncanonical)
# Directory in which the compiler finds target-independent g++ includes.
gcc_gxx_include_dir = @gcc_gxx_include_dir@
+gcc_gxx_include_dir_add_sysroot = @gcc_gxx_include_dir_add_sysroot@
# Directory to search for site-specific includes.
local_includedir = $(local_prefix)/include
includedir = $(prefix)/include
@@ -3788,6 +3789,7 @@ PREPROCESSOR_DEFINES = \
-DGCC_INCLUDE_DIR=\"$(libsubdir)/include\" \
-DFIXED_INCLUDE_DIR=\"$(libsubdir)/include-fixed\" \
-DGPLUSPLUS_INCLUDE_DIR=\"$(gcc_gxx_include_dir)\" \
+ -DGPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT=$(gcc_gxx_include_dir_add_sysroot) \
-DGPLUSPLUS_TOOL_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/$(target_noncanonical)\" \
-DGPLUSPLUS_BACKWARD_INCLUDE_DIR=\"$(gcc_gxx_include_dir)/backward\" \
-DLOCAL_INCLUDE_DIR=\"$(local_includedir)\" \
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -144,6 +144,15 @@ if test x${gcc_gxx_include_dir} = x; the
fi
fi
+gcc_gxx_include_dir_add_sysroot=0
+if test "${with_sysroot+set}" = set; then :
+ gcc_gxx_without_sysroot=`expr "${gcc_gxx_include_dir}" : "${with_sysroot}"'\(.*\)'`
+ if test "${gcc_gxx_without_sysroot}"; then :
+ gcc_gxx_include_dir="${gcc_gxx_without_sysroot}"
+ gcc_gxx_include_dir_add_sysroot=1
+ fi
+fi
+
AC_ARG_WITH(cpp_install_dir,
[ --with-cpp-install-dir=DIR
install the user visible C preprocessor in DIR
@@ -4492,6 +4501,7 @@ AC_SUBST(extra_programs)
AC_SUBST(float_h_file)
AC_SUBST(gcc_config_arguments)
AC_SUBST(gcc_gxx_include_dir)
+AC_SUBST(gcc_gxx_include_dir_add_sysroot)
AC_SUBST(host_exeext)
AC_SUBST(host_xm_file_list)
AC_SUBST(host_xm_include_list)
--- a/gcc/cppdefault.c
+++ b/gcc/cppdefault.c
@@ -48,15 +48,18 @@ const struct default_include cpp_include
= {
#ifdef GPLUSPLUS_INCLUDE_DIR
/* Pick up GNU C++ generic include files. */
- { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, 0, 0 },
+ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1,
+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
#endif
#ifdef GPLUSPLUS_TOOL_INCLUDE_DIR
/* Pick up GNU C++ target-dependent include files. */
- { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, 0, 1 },
+ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1,
+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 },
#endif
#ifdef GPLUSPLUS_BACKWARD_INCLUDE_DIR
/* Pick up GNU C++ backward and deprecated include files. */
- { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, 0, 0 },
+ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1,
+ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
#endif
#ifdef LOCAL_INCLUDE_DIR
/* /usr/local/include comes before the fixincluded header files. */
--- a/gcc/configure
+++ b/gcc/configure
@@ -639,6 +639,7 @@ host_xm_defines
host_xm_include_list
host_xm_file_list
host_exeext
+gcc_gxx_include_dir_add_sysroot
gcc_gxx_include_dir
gcc_config_arguments
float_h_file
@@ -3282,6 +3283,15 @@ if test x${gcc_gxx_include_dir} = x; the
fi
fi
+gcc_gxx_include_dir_add_sysroot=0
+if test "${with_sysroot+set}" = set; then :
+ gcc_gxx_without_sysroot=`expr "${gcc_gxx_include_dir}" : "${with_sysroot}"'\(.*\)'`
+ if test "${gcc_gxx_without_sysroot}"; then :
+ gcc_gxx_include_dir="${gcc_gxx_without_sysroot}"
+ gcc_gxx_include_dir_add_sysroot=1
+ fi
+fi
+
# Check whether --with-cpp_install_dir was given.
if test "${with_cpp_install_dir+set}" = set; then :
@@ -17118,7 +17128,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 17121 "configure"
+#line 17131 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -17224,7 +17234,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 17227 "configure"
+#line 17237 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -25381,6 +25391,7 @@ fi
+
toolchain-layer/recipes-devtools/gcc/gcc-4.5/Makefile.in.patch
-30
View File
@@ -1,30 +0,0 @@
Index: gcc-4.5/gcc/Makefile.in
===================================================================
--- gcc-4.5.orig/gcc/Makefile.in
+++ gcc-4.5/gcc/Makefile.in
@@ -656,7 +656,7 @@ LIBGCC2_INCLUDES =
TARGET_LIBGCC2_CFLAGS =
# Options to use when compiling crtbegin/end.
-CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -g0 \
+CRTSTUFF_CFLAGS = -O2 $(GCC_CFLAGS) $(TARGET_INCLUDES) $(MULTILIB_CFLAGS) -g0 \
-finhibit-size-directive -fno-inline -fno-exceptions \
-fno-zero-initialized-in-bss -fno-toplevel-reorder -fno-tree-vectorize \
$(INHIBIT_LIBC_CFLAGS)
@@ -1038,10 +1038,14 @@ BUILD_ERRORS = build/errors.o
# -I$(@D) and -I$(srcdir)/$(@D) cause the subdirectory of the file
# currently being compiled, in both source trees, to be examined as well.
# libintl.h will be found in ../intl if we are using the included libintl.
-INCLUDES = -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \
+#
+# TARGET_INCLUDES is added to avoid that GMPINC (which points to the host
+# include dir) is used for compiling libgcc.a
+TARGET_INCLUDES = -I. -I$(@D) -I$(srcdir) -I$(srcdir)/$(@D) \
-I$(srcdir)/../include @INCINTL@ \
- $(CPPINC) $(GMPINC) $(DECNUMINC) \
+ $(CPPINC) $(DECNUMINC) \
$(PPLINC) $(CLOOGINC) $(LIBELFINC)
+INCLUDES = $(TARGET_INCLUDES) $(GMPINC)
.c.o:
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $< $(OUTPUT_OPTION)
toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-lib1funcs.as-fix-mismatch-between-conditions-of-an-IT-block.patch
-18
View File
@@ -1,18 +0,0 @@
Fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43999
http://patchwork.ozlabs.org/patch/72260/ is the patch that made into
upstream gcc
diff --git a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm
index 085e690..2e76c01 100644
--- a/gcc/config/arm/lib1funcs.asm
+++ b/gcc/config/arm/lib1funcs.asm
@@ -641,7 +641,7 @@ pc .req r15
subhs \dividend, \dividend, \divisor, lsr #3
orrhs \result, \result, \curbit, lsr #3
cmp \dividend, #0 @ Early termination?
- do_it hs, t
+ do_it ne, t
movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
movne \divisor, \divisor, lsr #4
bne 1b
toolchain-layer/recipes-devtools/gcc/gcc-4.5/arm-unbreak-eabi-armv4t.dpatch
-36
View File
@@ -1,36 +0,0 @@
#! /bin/sh -e
# DP: Fix armv4t build on ARM
dir=
if [ $# -eq 3 -a "$2" = '-d' ]; then
pdir="-d $3"
dir="$3/"
elif [ $# -ne 1 ]; then
echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
exit 1
fi
case "$1" in
-patch)
patch $pdir -f --no-backup-if-mismatch -p1 < $0
;;
-unpatch)
patch $pdir -f --no-backup-if-mismatch -R -p1 < $0
;;
*)
echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
exit 1
esac
exit 0
--- src/gcc/config/arm/linux-eabi.h.orig 2007-11-24 12:37:38.000000000 +0000
+++ src/gcc/config/arm/linux-eabi.h 2007-11-24 12:39:41.000000000 +0000
@@ -44,7 +44,7 @@
The ARM10TDMI core is the default for armv5t, so set
SUBTARGET_CPU_DEFAULT to achieve this. */
#undef SUBTARGET_CPU_DEFAULT
-#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm10tdmi
+#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm9tdmi
/* TARGET_BIG_ENDIAN_DEFAULT is set in
config.gcc for big endian configurations. */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/cache-amnesia.patch
-31
View File
@@ -1,31 +0,0 @@
---
gcc/configure | 2 +-
gcc/configure.ac | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Index: gcc-4.5+svnr155514/gcc/configure
===================================================================
--- gcc-4.5+svnr155514.orig/gcc/configure 2009-12-29 22:00:40.000000000 -0800
+++ gcc-4.5+svnr155514/gcc/configure 2009-12-29 23:52:43.381592113 -0800
@@ -10467,7 +10467,7 @@ else
saved_CFLAGS="${CFLAGS}"
CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
LDFLAGS="${LDFLAGS_FOR_BUILD}" \
- ${realsrcdir}/configure \
+ CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \
--enable-languages=${enable_languages-all} \
--target=$target_alias --host=$build_alias --build=$build_alias
CFLAGS="${saved_CFLAGS}"
Index: gcc-4.5+svnr155514/gcc/configure.ac
===================================================================
--- gcc-4.5+svnr155514.orig/gcc/configure.ac 2009-12-29 22:00:40.000000000 -0800
+++ gcc-4.5+svnr155514/gcc/configure.ac 2009-12-29 23:51:54.589091778 -0800
@@ -1458,7 +1458,7 @@ else
saved_CFLAGS="${CFLAGS}"
CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \
LDFLAGS="${LDFLAGS_FOR_BUILD}" \
- ${realsrcdir}/configure \
+ CONFIG_SITE= ${realsrcdir}/configure --cache-file=./other.cache \
--enable-languages=${enable_languages-all} \
--target=$target_alias --host=$build_alias --build=$build_alias
CFLAGS="${saved_CFLAGS}"
toolchain-layer/recipes-devtools/gcc/gcc-4.5/cpp-honour-sysroot.patch
-36
View File
@@ -1,36 +0,0 @@
Currently, if the gcc toolchain is relocated and installed from sstate, then you try and compile
preprocessed source (.i or .ii files), the compiler will try and access the builtin sysroot location
rather than the --sysroot option specified on the commandline. If access to that directory is
permission denied (unreadable), gcc will error.
This happens when ccache is in use due to the fact it uses preprocessed source files.
The fix below adds %I to the cpp-output spec macro so the default substitutions for -iprefix,
-isystem, -isysroot happen and the correct sysroot is used.
[YOCTO #2074]
Upstream-Status: Pending
RP 2012/04/13
--- a/gcc/gcc.c
+++ b/gcc/gcc.c
@@ -1106,7 +1106,7 @@ static const struct compiler default_com
%W{o*:--output-pch=%*}%V}}}}}}", 0, 0, 0},
{".i", "@cpp-output", 0, 1, 0},
{"@cpp-output",
- "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 1, 0},
+ "%{!M:%{!MM:%{!E:cc1 -fpreprocessed %i %I %(cc1_options) %{!fsyntax-only:%(invoke_as)}}}}", 0, 1, 0},
{".s", "@assembler", 0, 1, 0},
{"@assembler",
"%{!M:%{!MM:%{!E:%{!S:as %(asm_debug) %(asm_options) %i %A }}}}", 0, 1, 0},
--- a/gcc/cp/lang-specs.h
+++ b/gcc/cp/lang-specs.h
@@ -63,5 +63,5 @@ along with GCC; see the file COPYING3.
{".ii", "@c++-cpp-output", 0, 0, 0},
{"@c++-cpp-output",
"%{!M:%{!MM:%{!E:\
- cc1plus -fpreprocessed %i %(cc1_options) %2 %{+e*}\
+ cc1plus -fpreprocessed %i %I %(cc1_options) %2 %{+e*}\
%{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 0},
toolchain-layer/recipes-devtools/gcc/gcc-4.5/disable_relax_pic_calls_flag.patch
-44
View File
@@ -1,44 +0,0 @@
GCC: disable MASK_RELAX_PIC_CALLS bit
The new feature added after 4.3.3
"http://www.pubbs.net/200909/gcc/94048-patch-add-support-for-rmipsjalr.html"
will cause cc1plus eat up all the system memory when build webkit-gtk.
The function mips_get_pic_call_symbol keeps on recursively calling itself.
Disable this feature to walk aside the bug.
Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
diff -ruN gcc-4.5.0-orig/gcc/configure gcc-4.5.0/gcc/configure
--- gcc-4.5.0-orig/gcc/configure 2010-09-17 23:30:21.000000000 +0800
+++ gcc-4.5.0/gcc/configure 2010-09-19 18:21:28.000000000 +0800
@@ -23945,13 +23945,6 @@
rm -f conftest.*
fi
fi
- if test $gcc_cv_as_ld_jalr_reloc = yes; then
- if test x$target_cpu_default = x; then
- target_cpu_default=MASK_RELAX_PIC_CALLS
- else
- target_cpu_default="($target_cpu_default)|MASK_RELAX_PIC_CALLS"
- fi
- fi
{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_ld_jalr_reloc" >&5
$as_echo "$gcc_cv_as_ld_jalr_reloc" >&6; }
diff -ruN gcc-4.5.0-orig/gcc/configure.ac gcc-4.5.0/gcc/configure.ac
--- gcc-4.5.0-orig/gcc/configure.ac 2010-09-17 23:30:21.000000000 +0800
+++ gcc-4.5.0/gcc/configure.ac 2010-09-19 18:21:11.000000000 +0800
@@ -3467,13 +3467,6 @@
rm -f conftest.*
fi
fi
- if test $gcc_cv_as_ld_jalr_reloc = yes; then
- if test x$target_cpu_default = x; then
- target_cpu_default=MASK_RELAX_PIC_CALLS
- else
- target_cpu_default="($target_cpu_default)|MASK_RELAX_PIC_CALLS"
- fi
- fi
AC_MSG_RESULT($gcc_cv_as_ld_jalr_reloc)
AC_CACHE_CHECK([linker for .eh_frame personality relaxation],
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-c++-builtin-redecl.patch
-114
View File
@@ -1,114 +0,0 @@
2007-10-02 Jakub Jelinek <jakub@redhat.com>
* decl.c (duplicate_decls): When redeclaring a builtin function,
keep the merged decl builtin whenever types match, even if new
decl defines a function.
* gcc.dg/builtins-65.c: New test.
* g++.dg/ext/builtin10.C: New test.
Index: gcc/cp/decl.c
===================================================================
--- gcc/cp/decl.c.orig 2010-04-01 11:48:46.000000000 -0700
+++ gcc/cp/decl.c 2010-06-25 10:10:54.749131719 -0700
@@ -2021,23 +2021,21 @@
DECL_ARGUMENTS (olddecl) = DECL_ARGUMENTS (newdecl);
DECL_RESULT (olddecl) = DECL_RESULT (newdecl);
}
+ /* If redeclaring a builtin function, it stays built in. */
+ if (types_match && DECL_BUILT_IN (olddecl))
+ {
+ DECL_BUILT_IN_CLASS (newdecl) = DECL_BUILT_IN_CLASS (olddecl);
+ DECL_FUNCTION_CODE (newdecl) = DECL_FUNCTION_CODE (olddecl);
+ /* If we're keeping the built-in definition, keep the rtl,
+ regardless of declaration matches. */
+ COPY_DECL_RTL (olddecl, newdecl);
+ }
if (new_defines_function)
/* If defining a function declared with other language
linkage, use the previously declared language linkage. */
SET_DECL_LANGUAGE (newdecl, DECL_LANGUAGE (olddecl));
else if (types_match)
{
- /* If redeclaring a builtin function, and not a definition,
- it stays built in. */
- if (DECL_BUILT_IN (olddecl))
- {
- DECL_BUILT_IN_CLASS (newdecl) = DECL_BUILT_IN_CLASS (olddecl);
- DECL_FUNCTION_CODE (newdecl) = DECL_FUNCTION_CODE (olddecl);
- /* If we're keeping the built-in definition, keep the rtl,
- regardless of declaration matches. */
- COPY_DECL_RTL (olddecl, newdecl);
- }
-
DECL_RESULT (newdecl) = DECL_RESULT (olddecl);
/* Don't clear out the arguments if we're just redeclaring a
function. */
Index: gcc/testsuite/gcc.dg/builtins-65.c
===================================================================
--- gcc/testsuite/gcc.dg/builtins-65.c.orig 2009-06-26 02:02:04.000000000 -0700
+++ gcc/testsuite/gcc.dg/builtins-65.c 2010-06-25 10:10:54.784464429 -0700
@@ -1,3 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef __SIZE_TYPE__ size_t;
+extern void __chk_fail (void);
+extern int snprintf (char *, size_t, const char *, ...);
+extern inline __attribute__((gnu_inline, always_inline)) int snprintf (char *a, size_t b, const char *fmt, ...)
+{
+ if (__builtin_object_size (a, 0) != -1UL && __builtin_object_size (a, 0) < b)
+ __chk_fail ();
+ return __builtin_snprintf (a, b, fmt, __builtin_va_arg_pack ());
+}
+extern int snprintf (char *, size_t, const char *, ...) __asm ("mysnprintf");
+
+char buf[10];
+
+int
+main (void)
+{
+ snprintf (buf, 10, "%d%d\n", 10, 10);
+ return 0;
+}
+
+/* { dg-final { scan-assembler "mysnprintf" } } */
+/* { dg-final { scan-assembler-not "__chk_fail" } } */
/* { dg-do link } */
/* { dg-options "-O2 -ffast-math" } */
/* { dg-require-effective-target c99_runtime } */
Index: gcc/testsuite/g++.dg/ext/builtin10.C
===================================================================
--- gcc/testsuite/g++.dg/ext/builtin10.C.orig 2009-02-02 03:27:50.000000000 -0800
+++ gcc/testsuite/g++.dg/ext/builtin10.C 2010-06-25 10:10:54.816467202 -0700
@@ -1,3 +1,30 @@
+// { dg-do compile }
+// { dg-options "-O2" }
+
+typedef __SIZE_TYPE__ size_t;
+extern "C" {
+extern void __chk_fail (void);
+extern int snprintf (char *, size_t, const char *, ...);
+extern inline __attribute__((gnu_inline, always_inline)) int snprintf (char *a, size_t b, const char *fmt, ...)
+{
+ if (__builtin_object_size (a, 0) != -1UL && __builtin_object_size (a, 0) < b)
+ __chk_fail ();
+ return __builtin_snprintf (a, b, fmt, __builtin_va_arg_pack ());
+}
+extern int snprintf (char *, size_t, const char *, ...) __asm ("mysnprintf");
+}
+
+char buf[10];
+
+int
+main (void)
+{
+ snprintf (buf, 10, "%d%d\n", 10, 10);
+ return 0;
+}
+
+// { dg-final { scan-assembler "mysnprintf" } }
+// { dg-final { scan-assembler-not "__chk_fail" } }
// { dg-do compile { target correct_iso_cpp_string_wchar_protos } }
// { dg-options "-O2 -fdump-tree-optimized" }
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-cpp-pragma.patch
-284
View File
@@ -1,284 +0,0 @@
2008-02-26 Jakub Jelinek <jakub@redhat.com>
* c-ppoutput.c (scan_translation_unit): Handle CPP_PRAGMA
and CPP_PRAGMA_EOL.
* c-pragma.c (pragma_ns_name): New typedef.
(registered_pp_pragmas): New variable.
(c_pp_lookup_pragma): New function.
(c_register_pragma_1): If flag_preprocess_only, do nothing
for non-expanded pragmas, for expanded ones push pragma's
namespace and name into registered_pp_pragmas vector.
(c_invoke_pragma_handler): Register OpenMP pragmas even when
flag_preprocess_only, don't register GCC pch_preprocess
pragma if flag_preprocess_only.
* c-opts.c (c_common_init): Call init_pragma even if
flag_preprocess_only.
* c-pragma.c (c_pp_lookup_pragma): New prototype.
* config/darwin.h (DARWIN_REGISTER_TARGET_PRAGMAS): Don't call
cpp_register_pragma if flag_preprocess_only.
* gcc.dg/gomp/preprocess-1.c: New test.
--- gcc/c-ppoutput.c.jj 2008-01-26 18:01:16.000000000 +0100
+++ gcc/c-ppoutput.c 2008-02-26 22:54:57.000000000 +0100
@@ -1,6 +1,6 @@
/* Preprocess only, using cpplib.
- Copyright (C) 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007
- Free Software Foundation, Inc.
+ Copyright (C) 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007,
+ 2008 Free Software Foundation, Inc.
Written by Per Bothner, 1994-95.
This program is free software; you can redistribute it and/or modify it
@@ -177,7 +177,24 @@ scan_translation_unit (cpp_reader *pfile
avoid_paste = false;
print.source = NULL;
print.prev = token;
- cpp_output_token (token, print.outf);
+ if (token->type == CPP_PRAGMA)
+ {
+ const char *space;
+ const char *name;
+
+ maybe_print_line (token->src_loc);
+ fputs ("#pragma ", print.outf);
+ c_pp_lookup_pragma (token->val.pragma, &space, &name);
+ if (space)
+ fprintf (print.outf, "%s %s", space, name);
+ else
+ fprintf (print.outf, "%s", name);
+ print.printed = 1;
+ }
+ else if (token->type == CPP_PRAGMA_EOL)
+ maybe_print_line (token->src_loc);
+ else
+ cpp_output_token (token, print.outf);
if (token->type == CPP_COMMENT)
account_for_newlines (token->val.str.text, token->val.str.len);
--- gcc/c-pragma.c.jj 2008-02-15 18:43:03.000000000 +0100
+++ gcc/c-pragma.c 2008-02-26 22:59:44.000000000 +0100
@@ -1,6 +1,6 @@
/* Handle #pragma, system V.4 style. Supports #pragma weak and #pragma pack.
Copyright (C) 1992, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
- 2006, 2007 Free Software Foundation, Inc.
+ 2006, 2007, 2008 Free Software Foundation, Inc.
This file is part of GCC.
@@ -872,6 +872,61 @@ DEF_VEC_ALLOC_O (pragma_handler, heap);
static VEC(pragma_handler, heap) *registered_pragmas;
+typedef struct
+{
+ const char *space;
+ const char *name;
+} pragma_ns_name;
+
+DEF_VEC_O (pragma_ns_name);
+DEF_VEC_ALLOC_O (pragma_ns_name, heap);
+
+static VEC(pragma_ns_name, heap) *registered_pp_pragmas;
+
+struct omp_pragma_def { const char *name; unsigned int id; };
+static const struct omp_pragma_def omp_pragmas[] = {
+ { "atomic", PRAGMA_OMP_ATOMIC },
+ { "barrier", PRAGMA_OMP_BARRIER },
+ { "critical", PRAGMA_OMP_CRITICAL },
+ { "flush", PRAGMA_OMP_FLUSH },
+ { "for", PRAGMA_OMP_FOR },
+ { "master", PRAGMA_OMP_MASTER },
+ { "ordered", PRAGMA_OMP_ORDERED },
+ { "parallel", PRAGMA_OMP_PARALLEL },
+ { "section", PRAGMA_OMP_SECTION },
+ { "sections", PRAGMA_OMP_SECTIONS },
+ { "single", PRAGMA_OMP_SINGLE },
+ { "threadprivate", PRAGMA_OMP_THREADPRIVATE }
+};
+
+void
+c_pp_lookup_pragma (unsigned int id, const char **space, const char **name)
+{
+ const int n_omp_pragmas = sizeof (omp_pragmas) / sizeof (*omp_pragmas);
+ int i;
+
+ for (i = 0; i < n_omp_pragmas; ++i)
+ if (omp_pragmas[i].id == id)
+ {
+ *space = "omp";
+ *name = omp_pragmas[i].name;
+ return;
+ }
+
+ if (id >= PRAGMA_FIRST_EXTERNAL
+ && (id < PRAGMA_FIRST_EXTERNAL
+ + VEC_length (pragma_ns_name, registered_pp_pragmas)))
+ {
+ *space = VEC_index (pragma_ns_name, registered_pp_pragmas,
+ id - PRAGMA_FIRST_EXTERNAL)->space;
+ *name = VEC_index (pragma_ns_name, registered_pp_pragmas,
+ id - PRAGMA_FIRST_EXTERNAL)->name;
+ return;
+ }
+
+ gcc_unreachable ();
+}
+
/* Front-end wrappers for pragma registration to avoid dragging
cpplib.h in almost everywhere. */
@@ -881,13 +936,29 @@ c_register_pragma_1 (const char *space,
{
unsigned id;
- VEC_safe_push (pragma_handler, heap, registered_pragmas, &handler);
- id = VEC_length (pragma_handler, registered_pragmas);
- id += PRAGMA_FIRST_EXTERNAL - 1;
-
- /* The C++ front end allocates 6 bits in cp_token; the C front end
- allocates 7 bits in c_token. At present this is sufficient. */
- gcc_assert (id < 64);
+ if (flag_preprocess_only)
+ {
+ pragma_ns_name ns_name;
+
+ if (!allow_expansion)
+ return;
+
+ ns_name.space = space;
+ ns_name.name = name;
+ VEC_safe_push (pragma_ns_name, heap, registered_pp_pragmas, &ns_name);
+ id = VEC_length (pragma_ns_name, registered_pp_pragmas);
+ id += PRAGMA_FIRST_EXTERNAL - 1;
+ }
+ else
+ {
+ VEC_safe_push (pragma_handler, heap, registered_pragmas, &handler);
+ id = VEC_length (pragma_handler, registered_pragmas);
+ id += PRAGMA_FIRST_EXTERNAL - 1;
+
+ /* The C++ front end allocates 6 bits in cp_token; the C front end
+ allocates 7 bits in c_token. At present this is sufficient. */
+ gcc_assert (id < 64);
+ }
cpp_register_deferred_pragma (parse_in, space, name, id,
allow_expansion, false);
@@ -921,24 +992,8 @@ c_invoke_pragma_handler (unsigned int id
void
init_pragma (void)
{
- if (flag_openmp && !flag_preprocess_only)
+ if (flag_openmp)
{
- struct omp_pragma_def { const char *name; unsigned int id; };
- static const struct omp_pragma_def omp_pragmas[] = {
- { "atomic", PRAGMA_OMP_ATOMIC },
- { "barrier", PRAGMA_OMP_BARRIER },
- { "critical", PRAGMA_OMP_CRITICAL },
- { "flush", PRAGMA_OMP_FLUSH },
- { "for", PRAGMA_OMP_FOR },
- { "master", PRAGMA_OMP_MASTER },
- { "ordered", PRAGMA_OMP_ORDERED },
- { "parallel", PRAGMA_OMP_PARALLEL },
- { "section", PRAGMA_OMP_SECTION },
- { "sections", PRAGMA_OMP_SECTIONS },
- { "single", PRAGMA_OMP_SINGLE },
- { "threadprivate", PRAGMA_OMP_THREADPRIVATE }
- };
-
const int n_omp_pragmas = sizeof (omp_pragmas) / sizeof (*omp_pragmas);
int i;
@@ -947,8 +1002,9 @@ init_pragma (void)
omp_pragmas[i].id, true, true);
}
- cpp_register_deferred_pragma (parse_in, "GCC", "pch_preprocess",
- PRAGMA_GCC_PCH_PREPROCESS, false, false);
+ if (!flag_preprocess_only)
+ cpp_register_deferred_pragma (parse_in, "GCC", "pch_preprocess",
+ PRAGMA_GCC_PCH_PREPROCESS, false, false);
#ifdef HANDLE_PRAGMA_PACK
#ifdef HANDLE_PRAGMA_PACK_WITH_EXPANSION
--- gcc/c-opts.c.jj 2008-02-26 22:53:23.000000000 +0100
+++ gcc/c-opts.c 2008-02-26 22:54:57.000000000 +0100
@@ -1,5 +1,5 @@
/* C/ObjC/C++ command line option handling.
- Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007
+ Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008
Free Software Foundation, Inc.
Contributed by Neil Booth.
@@ -1239,6 +1239,9 @@ c_common_init (void)
if (version_flag)
c_common_print_pch_checksum (stderr);
+ /* Has to wait until now so that cpplib has its hash table. */
+ init_pragma ();
+
if (flag_preprocess_only)
{
finish_options ();
@@ -1246,9 +1249,6 @@ c_common_init (void)
return false;
}
- /* Has to wait until now so that cpplib has its hash table. */
- init_pragma ();
-
return true;
}
--- gcc/c-pragma.h.jj 2008-01-26 18:01:16.000000000 +0100
+++ gcc/c-pragma.h 2008-02-26 22:54:57.000000000 +0100
@@ -1,6 +1,6 @@
/* Pragma related interfaces.
Copyright (C) 1995, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
- 2007 Free Software Foundation, Inc.
+ 2007, 2008 Free Software Foundation, Inc.
This file is part of GCC.
@@ -124,4 +124,6 @@ extern enum cpp_ttype pragma_lex (tree *
extern enum cpp_ttype c_lex_with_flags (tree *, location_t *, unsigned char *,
int);
+extern void c_pp_lookup_pragma (unsigned int, const char **, const char **);
+
#endif /* GCC_C_PRAGMA_H */
--- gcc/config/darwin.h.jj 2008-02-11 14:48:12.000000000 +0100
+++ gcc/config/darwin.h 2008-02-26 22:54:57.000000000 +0100
@@ -892,8 +892,9 @@ enum machopic_addr_class {
#define DARWIN_REGISTER_TARGET_PRAGMAS() \
do { \
- cpp_register_pragma (parse_in, NULL, "mark", \
- darwin_pragma_ignore, false); \
+ if (!flag_preprocess_only) \
+ cpp_register_pragma (parse_in, NULL, "mark", \
+ darwin_pragma_ignore, false); \
c_register_pragma (0, "options", darwin_pragma_options); \
c_register_pragma (0, "segment", darwin_pragma_ignore); \
c_register_pragma (0, "unused", darwin_pragma_unused); \
--- gcc/testsuite/gcc.dg/gomp/preprocess-1.c.jj 2008-02-26 22:54:57.000000000 +0100
+++ gcc/testsuite/gcc.dg/gomp/preprocess-1.c 2008-02-26 22:54:57.000000000 +0100
@@ -0,0 +1,16 @@
+/* { dg-do preprocess } */
+
+void foo (void)
+{
+ int i1, j1, k1;
+#define p parallel
+#define P(x) private (x##1)
+#define S(x) shared (x##1)
+#define F(x) firstprivate (x##1)
+#pragma omp p P(i) \
+ S(j) \
+ F(k)
+ ;
+}
+
+/* { dg-final { scan-file preprocess-1.i "(^|\n)#pragma omp parallel private \\(i1\\) shared \\(j1\\) firstprivate \\(k1\\)($|\n)" } } */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-i386-libgomp.patch
-65
View File
@@ -1,65 +0,0 @@
Build i386.rpm libgomp and libsupc++.a(guard.o) as i486+, pre-i486
hardware isn't supported because NPTL doesn't support it anyway.
Index: libgomp/configure.tgt
===================================================================
--- libgomp/configure.tgt.orig 2010-01-28 13:47:59.000000000 -0800
+++ libgomp/configure.tgt 2010-06-25 10:32:26.706135558 -0700
@@ -48,14 +48,14 @@
;;
# Note that bare i386 is not included here. We need cmpxchg.
- i[456]86-*-linux*)
+ i[3456]86-*-linux*)
config_path="linux/x86 linux posix"
case " ${CC} ${CFLAGS} " in
*" -m64 "*)
;;
*)
if test -z "$with_arch"; then
- XCFLAGS="${XCFLAGS} -march=i486 -mtune=${target_cpu}"
+ XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic"
fi
esac
;;
@@ -67,7 +67,7 @@
config_path="linux/x86 linux posix"
case " ${CC} ${CFLAGS} " in
*" -m32 "*)
- XCFLAGS="${XCFLAGS} -march=i486 -mtune=i686"
+ XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic"
;;
esac
;;
Index: libstdc++-v3/libsupc++/guard.cc
===================================================================
--- libstdc++-v3/libsupc++/guard.cc.orig 2009-11-09 14:09:30.000000000 -0800
+++ libstdc++-v3/libsupc++/guard.cc 2010-06-25 10:32:26.710135964 -0700
@@ -30,6 +30,27 @@
#include <new>
#include <ext/atomicity.h>
#include <ext/concurrence.h>
+#if defined __i386__ && !defined _GLIBCXX_ATOMIC_BUILTINS
+# define _GLIBCXX_ATOMIC_BUILTINS 1
+# define __sync_val_compare_and_swap(a, b, c) \
+ ({ \
+ typedef char sltast[sizeof (*a) == sizeof (int) ? 1 : -1]; \
+ int sltas; \
+ __asm __volatile ("lock; cmpxchgl %3, (%1)" \
+ : "=a" (sltas) \
+ : "r" (a), "0" (b), "r" (c) : "memory"); \
+ sltas; \
+ })
+# define __sync_lock_test_and_set(a, b) \
+ ({ \
+ typedef char sltast[sizeof (*a) == sizeof (int) ? 1 : -1]; \
+ int sltas; \
+ __asm __volatile ("xchgl (%1), %0" \
+ : "=r" (sltas) \
+ : "r" (a), "0" (b) : "memory"); \
+ sltas; \
+ })
+#endif
#if defined(__GTHREADS) && defined(__GTHREAD_HAS_COND) \
&& defined(_GLIBCXX_ATOMIC_BUILTINS_4) && defined(_GLIBCXX_HAVE_LINUX_FUTEX)
# include <climits>
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ia64-libunwind.patch
-550
View File
@@ -1,550 +0,0 @@
2004-11-27 Jakub Jelinek <jakub@redhat.com>
* config.gcc (ia64*-*-linux*): If native and libelf is installed,
use ia64/t-glibc-no-libunwind instead of the other t-*unwind*
fragments.
* config/ia64/t-glibc-no-libunwind: New file.
* config/ia64/change-symver.c: New file.
* config/ia64/unwind-ia64.c: If USE_SYMVER_GLOBAL and SHARED,
define _Unwind_* to __symverglobal_Unwind_*.
(alias): Undefine.
(symverglobal): Define. Use it on _Unwind_*.
* config/ia64/mkmap-symver-multi.awk: New file.
* config/ia64/libgcc-ia64-no-libunwind.ver: New file.
Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc.orig 2010-04-07 03:34:00.000000000 -0700
+++ gcc/config.gcc 2010-06-25 10:15:25.133131055 -0700
@@ -1457,9 +1457,16 @@
;;
ia64*-*-linux*)
tm_file="${tm_file} dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h ia64/sysv4.h ia64/linux.h"
- tmake_file="${tmake_file} ia64/t-ia64 t-libunwind ia64/t-glibc"
- if test x$with_system_libunwind != xyes ; then
- tmake_file="${tmake_file} t-libunwind-elf ia64/t-glibc-libunwind"
+ tmake_file="${tmake_file} ia64/t-ia64"
+ if test x${target} = x${host} && test x${target} = x${build} \
+ && grep gelf_getverdef /usr/include/gelf.h > /dev/null 2>&1 \
+ && test -f /usr/lib/libelf.so; then
+ tmake_file="${tmake_file} ia64/t-glibc-no-libunwind"
+ else
+ tmake_file="${tmake_file} t-libunwind ia64/t-glibc"
+ if test x$with_system_libunwind != xyes ; then
+ tmake_file="${tmake_file} t-libunwind-elf ia64/t-glibc-libunwind"
+ fi
fi
target_cpu_default="MASK_GNU_AS|MASK_GNU_LD"
extra_parts="crtbegin.o crtend.o crtbeginS.o crtendS.o crtfastmath.o"
Index: gcc/config/ia64/t-glibc-no-libunwind
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc/config/ia64/t-glibc-no-libunwind 2010-06-25 10:14:32.521880765 -0700
@@ -0,0 +1,30 @@
+# Don't use system libunwind library on IA-64 GLIBC based system,
+# but make _Unwind_* symbols unversioned, so that created programs
+# are usable even when libgcc_s uses libunwind.
+LIB2ADDEH += $(srcdir)/config/ia64/fde-glibc.c
+SHLIB_MAPFILES += $(srcdir)/config/ia64/libgcc-ia64-no-libunwind.ver
+SHLIB_MKMAP = $(srcdir)/config/ia64/mkmap-symver-multi.awk
+
+SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \
+ -Wl,--soname=$(SHLIB_SONAME) \
+ -Wl,--version-script=$(SHLIB_MAP) \
+ -o $(SHLIB_DIR)/$(SHLIB_SONAME).tmp @multilib_flags@ $(SHLIB_OBJS) -lc && \
+ rm -f $(SHLIB_DIR)/$(SHLIB_SOLINK) && \
+ if [ -f $(SHLIB_DIR)/$(SHLIB_SONAME) ]; then \
+ mv -f $(SHLIB_DIR)/$(SHLIB_SONAME) \
+ $(SHLIB_DIR)/$(SHLIB_SONAME).backup; \
+ else true; fi && \
+ gcc -O2 -o $(SHLIB_DIR)/$(SHLIB_SONAME).tweak \
+ $$(gcc_srcdir)/config/ia64/change-symver.c -lelf && \
+ $(SHLIB_DIR)/$(SHLIB_SONAME).tweak $(SHLIB_DIR)/$(SHLIB_SONAME).tmp \
+ GCC_3.4.2 _GLOBAL_ \
+ _Unwind_GetGR _Unwind_RaiseException _Unwind_GetRegionStart _Unwind_SetIP \
+ _Unwind_GetIP _Unwind_GetLanguageSpecificData _Unwind_Resume \
+ _Unwind_DeleteException _Unwind_SetGR _Unwind_ForcedUnwind \
+ _Unwind_Backtrace _Unwind_FindEnclosingFunction _Unwind_GetCFA \
+ _Unwind_Resume_or_Rethrow _Unwind_GetBSP && \
+ rm -f $(SHLIB_DIR)/$(SHLIB_SONAME).tweak && \
+ mv $(SHLIB_DIR)/$(SHLIB_SONAME).tmp $(SHLIB_DIR)/$(SHLIB_SONAME) && \
+ $(LN_S) $(SHLIB_SONAME) $(SHLIB_DIR)/$(SHLIB_SOLINK)
+
+TARGET_LIBGCC2_CFLAGS += -DUSE_SYMVER_GLOBAL
Index: gcc/config/ia64/change-symver.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc/config/ia64/change-symver.c 2010-06-25 10:14:32.521880765 -0700
@@ -0,0 +1,211 @@
+#define _GNU_SOURCE 1
+#define _FILE_OFFSET_BITS 64
+#include <endian.h>
+#include <errno.h>
+#include <error.h>
+#include <fcntl.h>
+#include <fnmatch.h>
+#include <gelf.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+int
+compute_veridx (const char *name, Elf *elf, Elf_Data *verd, GElf_Shdr *verd_shdr)
+{
+ if (strcmp (name, "_GLOBAL_") == 0)
+ return 1;
+
+ int cnt;
+ size_t offset = 0;
+ for (cnt = verd_shdr->sh_info; --cnt >= 0; )
+ {
+ GElf_Verdef defmem;
+ GElf_Verdef *def;
+ GElf_Verdaux auxmem;
+ GElf_Verdaux *aux;
+ unsigned int auxoffset;
+
+ /* Get the data at the next offset. */
+ def = gelf_getverdef (verd, offset, &defmem);
+ if (def == NULL)
+ break;
+
+ auxoffset = offset + def->vd_aux;
+ aux = gelf_getverdaux (verd, auxoffset, &auxmem);
+ if (aux == NULL)
+ break;
+
+ if (strcmp (name, elf_strptr (elf, verd_shdr->sh_link,
+ aux->vda_name)) == 0)
+ return def->vd_ndx;
+
+ /* Find the next offset. */
+ offset += def->vd_next;
+ }
+
+ return -1;
+}
+
+int
+main (int argc, char **argv)
+{
+ if (argc < 4)
+ error (1, 0, "Usage: change_symver library from_symver to_symver symbol...\nExample: change_symver libfoo.so FOO_1.0 *global* bar baz");
+
+ const char *fname = argv[1];
+
+ /* Open the file. */
+ int fd;
+ fd = open (fname, O_RDWR);
+ if (fd == -1)
+ error (1, errno, fname);
+
+ elf_version (EV_CURRENT);
+
+ /* Now get the ELF descriptor. */
+ Elf *elf = elf_begin (fd, ELF_C_READ_MMAP, NULL);
+ if (elf == NULL || elf_kind (elf) != ELF_K_ELF)
+ error (1, 0, "Couldn't open %s: %s", fname, elf_errmsg (-1));
+
+ size_t shstrndx;
+ /* Get the section header string table index. */
+ if (elf_getshstrndx (elf, &shstrndx) < 0)
+ error (1, 0, "cannot get shstrndx from %s", fname);
+
+ GElf_Ehdr ehdr_mem;
+ GElf_Ehdr *ehdr;
+
+ /* We need the ELF header in a few places. */
+ ehdr = gelf_getehdr (elf, &ehdr_mem);
+ if (ehdr == NULL)
+ error (1, 0, "couldn't get ELF headers %s: %s", fname, elf_errmsg (-1));
+
+ Elf_Scn *scn = NULL;
+ GElf_Shdr shdr_mem, verd_shdr, ver_shdr, dynsym_shdr;
+ Elf_Data *ver = NULL, *verd = NULL, *dynsym = NULL;
+
+ while ((scn = elf_nextscn (elf, scn)) != NULL)
+ {
+ GElf_Shdr *shdr = gelf_getshdr (scn, &shdr_mem);
+
+ if (shdr == NULL)
+ error (1, 0, "couldn't get shdr from %s", fname);
+
+ if ((shdr->sh_flags & SHF_ALLOC) != 0)
+ {
+ const char *name = elf_strptr (elf, shstrndx, shdr->sh_name);
+ Elf_Data **p;
+
+ if (strcmp (name, ".gnu.version") == 0)
+ {
+ p = &ver;
+ ver_shdr = *shdr;
+ }
+ else if (strcmp (name, ".gnu.version_d") == 0)
+ {
+ p = &verd;
+ verd_shdr = *shdr;
+ }
+ else if (strcmp (name, ".dynsym") == 0)
+ {
+ p = &dynsym;
+ dynsym_shdr = *shdr;
+ }
+ else
+ continue;
+
+ if (*p != NULL)
+ error (1, 0, "Two %s sections in %s", name, fname);
+ *p = elf_getdata (scn, NULL);
+ if (*p == NULL || elf_getdata (scn, *p) != NULL)
+ error (1, 0, "No data or non-contiguous data in %s section in %s",
+ name, fname);
+ }
+ }
+
+ if (ver == NULL || verd == NULL || dynsym == NULL)
+ error (1, 0, "Couldn't find one of the needed sections in %s", fname);
+
+ int from_idx = compute_veridx (argv[2], elf, verd, &verd_shdr);
+ if (from_idx == -1)
+ error (1, 0, "Could not find symbol version %s in %s", argv[2], fname);
+
+ int to_idx = compute_veridx (argv[3], elf, verd, &verd_shdr);
+ if (to_idx == -1)
+ error (1, 0, "Could not find symbol version %s in %s", argv[3], fname);
+
+ if (dynsym_shdr.sh_entsize != gelf_fsize (elf, ELF_T_SYM, 1, ehdr->e_version)
+ || dynsym_shdr.sh_size % dynsym_shdr.sh_entsize
+ || ver_shdr.sh_entsize != 2
+ || (ver_shdr.sh_size & 1)
+ || dynsym_shdr.sh_size / dynsym_shdr.sh_entsize != ver_shdr.sh_size / 2)
+ error (1, 0, "Unexpected sh_size or sh_entsize in %s", fname);
+
+ size_t nentries = ver_shdr.sh_size / 2;
+ size_t cnt;
+ GElf_Versym array[nentries];
+ for (cnt = 0; cnt < nentries; ++cnt)
+ {
+ GElf_Versym vsymmem;
+ GElf_Versym *vsym;
+
+ vsym = gelf_getversym (ver, cnt, &vsymmem);
+ if (vsym == NULL)
+ error (1, 0, "gelt_getversym failed in %s: %s", fname, elf_errmsg (-1));
+
+ array[cnt] = *vsym;
+ if (*vsym != from_idx)
+ continue;
+
+ GElf_Sym sym_mem;
+ GElf_Sym *sym;
+ sym = gelf_getsym (dynsym, cnt, &sym_mem);
+ if (sym == NULL)
+ error (1, 0, "gelt_getsym failed in %s: %s", fname, elf_errmsg (-1));
+
+ const char *name = elf_strptr (elf, dynsym_shdr.sh_link, sym->st_name);
+
+ int argn;
+ for (argn = 4; argn < argc; ++argn)
+ if (fnmatch (argv[argn], name, 0) == 0)
+ {
+ array[cnt] = to_idx;
+ break;
+ }
+ }
+
+ if (sizeof (array[0]) != 2)
+ abort ();
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+ if (ehdr->e_ident[EI_DATA] == ELFDATA2LSB)
+ ;
+ else if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
+#elif __BYTE_ORDER == __BIG_ENDIAN
+ if (ehdr->e_ident[EI_DATA] == ELFDATA2MSB)
+ ;
+ else if (ehdr->e_ident[EI_DATA] == ELFDATA2LSB)
+#else
+# error Unsupported endianity
+#endif
+ {
+ for (cnt = 0; cnt < nentries; ++cnt)
+ array[cnt] = ((array[cnt] & 0xff) << 8) | ((array[cnt] & 0xff00) >> 8);
+ }
+ else
+ error (1, 0, "Unknown EI_DATA %d in %s", ehdr->e_ident[EI_DATA], fname);
+
+ if (elf_end (elf) != 0)
+ error (1, 0, "couldn't close %s: %s", fname, elf_errmsg (-1));
+
+ if (lseek (fd, ver_shdr.sh_offset, SEEK_SET) != (off_t) ver_shdr.sh_offset)
+ error (1, 0, "failed to seek to %zd in %s", (size_t) ver_shdr.sh_offset,
+ fname);
+
+ if (write (fd, array, 2 * nentries) != (ssize_t) (2 * nentries))
+ error (1, 0, "failed to write .gnu.version section into %s", fname);
+
+ close (fd);
+ return 0;
+}
Index: gcc/config/ia64/unwind-ia64.c
===================================================================
--- gcc/config/ia64/unwind-ia64.c.orig 2009-09-07 08:41:52.000000000 -0700
+++ gcc/config/ia64/unwind-ia64.c 2010-06-25 10:14:32.521880765 -0700
@@ -48,6 +48,51 @@
#define MD_UNW_COMPATIBLE_PERSONALITY_P(HEADER) 1
#endif
+#if defined (USE_SYMVER_GLOBAL) && defined (SHARED)
+extern _Unwind_Reason_Code __symverglobal_Unwind_Backtrace
+ (_Unwind_Trace_Fn, void *);
+extern void __symverglobal_Unwind_DeleteException
+ (struct _Unwind_Exception *);
+extern void * __symverglobal_Unwind_FindEnclosingFunction (void *);
+extern _Unwind_Reason_Code __symverglobal_Unwind_ForcedUnwind
+ (struct _Unwind_Exception *, _Unwind_Stop_Fn, void *);
+extern _Unwind_Word __symverglobal_Unwind_GetCFA
+ (struct _Unwind_Context *);
+extern _Unwind_Word __symverglobal_Unwind_GetBSP
+ (struct _Unwind_Context *);
+extern _Unwind_Word __symverglobal_Unwind_GetGR
+ (struct _Unwind_Context *, int );
+extern _Unwind_Ptr __symverglobal_Unwind_GetIP (struct _Unwind_Context *);
+extern void *__symverglobal_Unwind_GetLanguageSpecificData
+ (struct _Unwind_Context *);
+extern _Unwind_Ptr __symverglobal_Unwind_GetRegionStart
+ (struct _Unwind_Context *);
+extern _Unwind_Reason_Code __symverglobal_Unwind_RaiseException
+ (struct _Unwind_Exception *);
+extern void __symverglobal_Unwind_Resume (struct _Unwind_Exception *);
+extern _Unwind_Reason_Code __symverglobal_Unwind_Resume_or_Rethrow
+ (struct _Unwind_Exception *);
+extern void __symverglobal_Unwind_SetGR
+ (struct _Unwind_Context *, int, _Unwind_Word);
+extern void __symverglobal_Unwind_SetIP
+ (struct _Unwind_Context *, _Unwind_Ptr);
+#define _Unwind_Backtrace __symverglobal_Unwind_Backtrace
+#define _Unwind_DeleteException __symverglobal_Unwind_DeleteException
+#define _Unwind_FindEnclosingFunction __symverglobal_Unwind_FindEnclosingFunction
+#define _Unwind_ForcedUnwind __symverglobal_Unwind_ForcedUnwind
+#define _Unwind_GetBSP __symverglobal_Unwind_GetBSP
+#define _Unwind_GetCFA __symverglobal_Unwind_GetCFA
+#define _Unwind_GetGR __symverglobal_Unwind_GetGR
+#define _Unwind_GetIP __symverglobal_Unwind_GetIP
+#define _Unwind_GetLanguageSpecificData __symverglobal_Unwind_GetLanguageSpecificData
+#define _Unwind_GetRegionStart __symverglobal_Unwind_GetRegionStart
+#define _Unwind_RaiseException __symverglobal_Unwind_RaiseException
+#define _Unwind_Resume __symverglobal_Unwind_Resume
+#define _Unwind_Resume_or_Rethrow __symverglobal_Unwind_Resume_or_Rethrow
+#define _Unwind_SetGR __symverglobal_Unwind_SetGR
+#define _Unwind_SetIP __symverglobal_Unwind_SetIP
+#endif
+
enum unw_application_register
{
UNW_AR_BSP,
@@ -2457,4 +2502,44 @@
alias (_Unwind_SetIP);
#endif
+#if defined (USE_SYMVER_GLOBAL) && defined (SHARED)
+#undef alias
+#define symverglobal(name, version) \
+__typeof (__symverglobal##name) __symverlocal##name \
+ __attribute__ ((alias ("__symverglobal" #name))); \
+__asm__ (".symver __symverglobal" #name"," #name "@@GCC_3.4.2");\
+__asm__ (".symver __symverlocal" #name"," #name "@" #version)
+
+#undef _Unwind_Backtrace
+#undef _Unwind_DeleteException
+#undef _Unwind_FindEnclosingFunction
+#undef _Unwind_ForcedUnwind
+#undef _Unwind_GetBSP
+#undef _Unwind_GetCFA
+#undef _Unwind_GetGR
+#undef _Unwind_GetIP
+#undef _Unwind_GetLanguageSpecificData
+#undef _Unwind_GetRegionStart
+#undef _Unwind_RaiseException
+#undef _Unwind_Resume
+#undef _Unwind_Resume_or_Rethrow
+#undef _Unwind_SetGR
+#undef _Unwind_SetIP
+symverglobal (_Unwind_Backtrace, GCC_3.3);
+symverglobal (_Unwind_DeleteException, GCC_3.0);
+symverglobal (_Unwind_FindEnclosingFunction, GCC_3.3);
+symverglobal (_Unwind_ForcedUnwind, GCC_3.0);
+symverglobal (_Unwind_GetBSP, GCC_3.3.2);
+symverglobal (_Unwind_GetCFA, GCC_3.3);
+symverglobal (_Unwind_GetGR, GCC_3.0);
+symverglobal (_Unwind_GetIP, GCC_3.0);
+symverglobal (_Unwind_GetLanguageSpecificData, GCC_3.0);
+symverglobal (_Unwind_GetRegionStart, GCC_3.0);
+symverglobal (_Unwind_RaiseException, GCC_3.0);
+symverglobal (_Unwind_Resume, GCC_3.0);
+symverglobal (_Unwind_Resume_or_Rethrow, GCC_3.3);
+symverglobal (_Unwind_SetGR, GCC_3.0);
+symverglobal (_Unwind_SetIP, GCC_3.0);
+#endif
+
#endif
Index: gcc/config/ia64/mkmap-symver-multi.awk
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc/config/ia64/mkmap-symver-multi.awk 2010-06-25 10:14:32.521880765 -0700
@@ -0,0 +1,133 @@
+# Generate an ELF symbol version map a-la Solaris and GNU ld.
+# Contributed by Richard Henderson <rth@cygnus.com>
+#
+# This file is part of GCC.
+#
+# GCC is free software; you can redistribute it and/or modify it under
+# the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2, or (at your option) any later
+# version.
+#
+# GCC is distributed in the hope that it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+# License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING. If not, write to the Free
+# Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+# 02110-1301, USA.
+
+BEGIN {
+ state = "nm";
+ sawsymbol = 0;
+}
+
+# Remove comment and blank lines.
+/^ *#/ || /^ *$/ {
+ next;
+}
+
+# We begin with nm input. Collect the set of symbols that are present
+# so that we can not emit them into the final version script -- Solaris
+# complains at us if we do.
+
+state == "nm" && /^%%/ {
+ state = "ver";
+ next;
+}
+
+state == "nm" && ($1 == "U" || $2 == "U") {
+ next;
+}
+
+state == "nm" && NF == 3 {
+ if ($3 ~ /^[^@]*@GCC_[0-9.]*$/) {
+ def[$3] = 1
+ tl=$3
+ sub(/^.*@/,"",tl)
+ ver[$3] = tl
+ } else {
+ sub(/@@?GCC_[0-9.]*$/,"",$3)
+ def[$3] = 1;
+ }
+ sawsymbol = 1;
+ next;
+}
+
+state == "nm" {
+ next;
+}
+
+# Now we process a simplified variant of the Solaris symbol version
+# script. We have one symbol per line, no semicolons, simple markers
+# for beginning and ending each section, and %inherit markers for
+# describing version inheritence. A symbol may appear in more than
+# one symbol version, and the last seen takes effect.
+
+NF == 3 && $1 == "%inherit" {
+ inherit[$2] = $3;
+ next;
+}
+
+NF == 2 && $2 == "{" {
+ libs[$1] = 1;
+ thislib = $1;
+ next;
+}
+
+$1 == "}" {
+ thislib = "";
+ next;
+}
+
+{
+ ver[$1] = thislib;
+ next;
+}
+
+END {
+ if (!sawsymbol)
+ {
+ print "No symbols seen -- broken or mis-installed nm?" | "cat 1>&2";
+ exit 1;
+ }
+ for (l in libs)
+ output(l);
+}
+
+function output(lib) {
+ if (done[lib])
+ return;
+ done[lib] = 1;
+ if (inherit[lib])
+ output(inherit[lib]);
+
+ empty=1
+ for (sym in ver)
+ if ((ver[sym] == lib) && (sym in def))
+ {
+ if (empty)
+ {
+ printf("%s {\n", lib);
+ printf(" global:\n");
+ empty = 0;
+ }
+ symp = sym;
+ sub(/@GCC_[0-9.]*$/,"",symp);
+ printf("\t%s;\n", symp);
+ if (dotsyms)
+ printf("\t.%s;\n", symp);
+ }
+
+ if (empty)
+ {
+ for (l in libs)
+ if (inherit[l] == lib)
+ inherit[l] = inherit[lib];
+ }
+ else if (inherit[lib])
+ printf("} %s;\n", inherit[lib]);
+ else
+ printf ("\n local:\n\t*;\n};\n");
+}
Index: gcc/config/ia64/libgcc-ia64-no-libunwind.ver
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc/config/ia64/libgcc-ia64-no-libunwind.ver 2010-06-25 10:14:32.525880902 -0700
@@ -0,0 +1,17 @@
+GCC_3.4.2 {
+ _Unwind_GetGR
+ _Unwind_RaiseException
+ _Unwind_GetRegionStart
+ _Unwind_SetIP
+ _Unwind_GetIP
+ _Unwind_GetLanguageSpecificData
+ _Unwind_Resume
+ _Unwind_DeleteException
+ _Unwind_SetGR
+ _Unwind_ForcedUnwind
+ _Unwind_Backtrace
+ _Unwind_FindEnclosingFunction
+ _Unwind_GetCFA
+ _Unwind_Resume_or_Rethrow
+ _Unwind_GetBSP
+}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-debug-iface-type.patch
-19
View File
@@ -1,19 +0,0 @@
2008-01-25 Jakub Jelinek <jakub@redhat.com>
* lang.c (java_classify_record): Revert 2007-12-20 change.
Index: gcc/java/lang.c
===================================================================
--- gcc/java/lang.c.orig 2010-01-20 00:17:00.000000000 -0800
+++ gcc/java/lang.c 2010-06-25 10:28:46.569383189 -0700
@@ -881,9 +881,7 @@
if (! CLASS_P (type))
return RECORD_IS_STRUCT;
- /* ??? GDB does not support DW_TAG_interface_type as of December,
- 2007. Re-enable this at a later time. */
- if (0 && CLASS_INTERFACE (TYPE_NAME (type)))
+ if (CLASS_INTERFACE (TYPE_NAME (type)))
return RECORD_IS_INTERFACE;
return RECORD_IS_CLASS;
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-java-nomulti.patch
-48
View File
@@ -1,48 +0,0 @@
Index: libjava/configure.ac
===================================================================
--- libjava/configure.ac.orig 2010-03-21 12:41:37.000000000 -0700
+++ libjava/configure.ac 2010-06-25 10:17:47.489886278 -0700
@@ -139,6 +139,13 @@
[allow rebuilding of .class and .h files]))
AM_CONDITIONAL(JAVA_MAINTAINER_MODE, test "$enable_java_maintainer_mode" = yes)
+AC_ARG_ENABLE(libjava-multilib,
+ AS_HELP_STRING([--enable-libjava-multilib], [build libjava as multilib]))
+if test "$enable_libjava_multilib" = no; then
+ multilib=no
+ ac_configure_args="$ac_configure_args --disable-multilib"
+fi
+
# It may not be safe to run linking tests in AC_PROG_CC/AC_PROG_CXX.
GCC_NO_EXECUTABLES
Index: libjava/configure
===================================================================
--- libjava/configure.orig 2010-04-02 11:18:06.000000000 -0700
+++ libjava/configure 2010-06-25 10:17:47.516381209 -0700
@@ -1609,6 +1609,8 @@
default=yes
--enable-java-maintainer-mode
allow rebuilding of .class and .h files
+ --enable-libjava-multilib
+ build libjava as multilib
--disable-dependency-tracking speeds up one-time build
--enable-dependency-tracking do not reject slow dependency extractors
--enable-maintainer-mode enable make rules and dependencies not useful
@@ -3346,6 +3348,16 @@
fi
+# Check whether --enable-libjava-multilib was given.
+if test "${enable_libjava_multilib+set}" = set; then
+ enableval=$enable_libjava_multilib;
+fi
+
+if test "$enable_libjava_multilib" = no; then
+ multilib=no
+ ac_configure_args="$ac_configure_args --disable-multilib"
+fi
+
# It may not be safe to run linking tests in AC_PROG_CC/AC_PROG_CXX.
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-libgomp-speedup.patch
-2797
View File
File diff suppressed because it is too large Load Diff
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-ppc32-retaddr.patch
-90
View File
@@ -1,90 +0,0 @@
2005-11-28 Jakub Jelinek <jakub@redhat.com>
* config/rs6000/rs6000.c (rs6000_return_addr): If COUNT == 0,
read word RETURN_ADDRESS_OFFSET bytes above arg_pointer_rtx
instead of doing an extran indirection from frame_pointer_rtx.
* gcc.dg/20051128-1.c: New test.
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c.orig 2010-03-27 03:27:39.000000000 -0700
+++ gcc/config/rs6000/rs6000.c 2010-06-25 10:18:04.053381930 -0700
@@ -17646,17 +17646,22 @@
don't try to be too clever here. */
if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
{
+ rtx x;
cfun->machine->ra_needs_full_frame = 1;
- return
- gen_rtx_MEM
- (Pmode,
- memory_address
- (Pmode,
- plus_constant (copy_to_reg
- (gen_rtx_MEM (Pmode,
- memory_address (Pmode, frame))),
- RETURN_ADDRESS_OFFSET)));
+ if (count == 0)
+ {
+ gcc_assert (frame == frame_pointer_rtx);
+ x = arg_pointer_rtx;
+ }
+ else
+ {
+ x = memory_address (Pmode, frame);
+ x = copy_to_reg (gen_rtx_MEM (Pmode, x));
+ }
+
+ x = plus_constant (x, RETURN_ADDRESS_OFFSET);
+ return gen_rtx_MEM (Pmode, memory_address (Pmode, x));
}
cfun->machine->ra_need_lr = 1;
Index: gcc/testsuite/gcc.dg/20051128-1.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc/testsuite/gcc.dg/20051128-1.c 2010-06-25 10:18:04.061382856 -0700
@@ -0,0 +1,41 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fpic" } */
+
+extern void exit (int);
+extern void abort (void);
+
+int b;
+
+struct A
+{
+ void *pad[147];
+ void *ra, *h;
+ long o;
+};
+
+void
+__attribute__((noinline))
+foo (struct A *a, void *x)
+{
+ __builtin_memset (a, 0, sizeof (a));
+ if (!b)
+ exit (0);
+}
+
+void
+__attribute__((noinline))
+bar (void)
+{
+ struct A a;
+
+ __builtin_unwind_init ();
+ foo (&a, __builtin_return_address (0));
+}
+
+int
+main (void)
+{
+ bar ();
+ abort ();
+ return 0;
+}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr27898.patch
-16
View File
@@ -1,16 +0,0 @@
2006-08-18 Jakub Jelinek <jakub@redhat.com>
PR c/27898
* gcc.dg/pr27898.c: New test.
--- gcc/testsuite/gcc.dg/pr27898.c.jj 2006-08-18 09:19:33.000000000 +0200
+++ gcc/testsuite/gcc.dg/pr27898.c 2006-08-18 09:19:27.000000000 +0200
@@ -0,0 +1,8 @@
+/* PR c/27898 */
+/* { dg-do compile } */
+/* { dg-options "--combine" } */
+/* { dg-additional-sources "pr27898.c" } */
+
+union u { struct { int i; }; };
+
+extern int foo (union u *);
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr32139.patch
-19
View File
@@ -1,19 +0,0 @@
2007-06-01 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/32139
* gcc.c-torture/compile/20070531-1.c: New test.
--- gcc/testsuite/gcc.c-torture/compile/20070531-1.c.jj 2007-05-31 13:47:22.000000000 +0200
+++ gcc/testsuite/gcc.c-torture/compile/20070531-1.c 2007-06-01 10:57:15.000000000 +0200
@@ -0,0 +1,11 @@
+/* PR tree-optimization/32139 */
+int foo (void);
+int bar (void) __attribute__ ((const));
+
+int
+test (int x)
+{
+ int a = (x == 10000 ? foo : bar) ();
+ int b = (x == 10000 ? foo : bar) ();
+ return a + b;
+}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-pr33763.patch
-159
View File
@@ -1,159 +0,0 @@
2007-11-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/33763
* gcc.dg/pr33763.c: New test.
* g++.dg/opt/inline13.C: New test.
2007-11-06 Jan Hubicka <jh@suse.cz>
PR tree-optimization/33763
* tree-inline.c (expand_call_inline): Silently ignore always_inline
attribute for redefined extern inline functions.
Index: gcc/tree-inline.c
===================================================================
--- gcc/tree-inline.c.orig 2010-03-18 13:07:13.000000000 -0700
+++ gcc/tree-inline.c 2010-06-25 10:18:51.230139825 -0700
@@ -3545,6 +3545,12 @@
goto egress;
if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (fn))
+ /* For extern inline functions that get redefined we always
+ silently ignored alway_inline flag. Better behaviour would
+ be to be able to keep both bodies and use extern inline body
+ for inlining, but we can't do that because frontends overwrite
+ the body. */
+ && !cg_edge->callee->local.redefined_extern_inline
/* Avoid warnings during early inline pass. */
&& cgraph_global_info_ready)
{
Index: gcc/testsuite/gcc.dg/pr33763.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc/testsuite/gcc.dg/pr33763.c 2010-06-25 10:18:51.234141302 -0700
@@ -0,0 +1,60 @@
+/* PR tree-optimization/33763 */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef struct
+{
+ void *a;
+ void *b;
+} T;
+extern void *foo (const char *, const char *);
+extern void *bar (void *, const char *, T);
+extern int baz (const char *, int);
+
+extern inline __attribute__ ((always_inline, gnu_inline)) int
+baz (const char *x, int y)
+{
+ return 2;
+}
+
+int
+baz (const char *x, int y)
+{
+ return 1;
+}
+
+int xa, xb;
+
+static void *
+inl (const char *x, const char *y)
+{
+ T t = { &xa, &xb };
+ int *f = (int *) __builtin_malloc (sizeof (int));
+ const char *z;
+ int o = 0;
+ void *r = 0;
+
+ for (z = y; *z; z++)
+ {
+ if (*z == 'r')
+ o |= 1;
+ if (*z == 'w')
+ o |= 2;
+ }
+ if (o == 1)
+ *f = baz (x, 0);
+ if (o == 2)
+ *f = baz (x, 1);
+ if (o == 3)
+ *f = baz (x, 2);
+
+ if (o && *f > 0)
+ r = bar (f, "w", t);
+ return r;
+}
+
+void *
+foo (const char *x, const char *y)
+{
+ return inl (x, y);
+}
Index: gcc/testsuite/g++.dg/opt/inline13.C
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc/testsuite/g++.dg/opt/inline13.C 2010-06-25 10:18:51.261052137 -0700
@@ -0,0 +1,60 @@
+// PR tree-optimization/33763
+// { dg-do compile }
+// { dg-options "-O2" }
+
+typedef struct
+{
+ void *a;
+ void *b;
+} T;
+extern void *foo (const char *, const char *);
+extern void *bar (void *, const char *, T);
+extern int baz (const char *, int);
+
+extern inline __attribute__ ((always_inline, gnu_inline)) int
+baz (const char *x, int y)
+{
+ return 2;
+}
+
+int
+baz (const char *x, int y)
+{
+ return 1;
+}
+
+int xa, xb;
+
+static void *
+inl (const char *x, const char *y)
+{
+ T t = { &xa, &xb };
+ int *f = (int *) __builtin_malloc (sizeof (int));
+ const char *z;
+ int o = 0;
+ void *r = 0;
+
+ for (z = y; *z; z++)
+ {
+ if (*z == 'r')
+ o |= 1;
+ if (*z == 'w')
+ o |= 2;
+ }
+ if (o == 1)
+ *f = baz (x, 0);
+ if (o == 2)
+ *f = baz (x, 1);
+ if (o == 3)
+ *f = baz (x, 2);
+
+ if (o && *f > 0)
+ r = bar (f, "w", t);
+ return r;
+}
+
+void *
+foo (const char *x, const char *y)
+{
+ return inl (x, y);
+}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh251682.patch
-89
View File
@@ -1,89 +0,0 @@
2008-04-01 Jakub Jelinek <jakub@redhat.com>
PR pch/13675
* files.c (struct _cpp_file): Remove pch field.
(pch_open_file): Don't set file->pch, just file->pchname.
(should_stack_file): After pfile->cb.read_pch call
free pchname and clear pchname, don't close file->fd.
Test file->pchname instead of file->pch. Don't close fd after cb.
(_cpp_stack_include): Test file->pchname instead of file->pch.
* c-pch.c (c_common_read_pch): On error close (fd) resp. fclose (f).
--- libcpp/files.c.jj 2008-02-18 23:50:17.000000000 +0100
+++ libcpp/files.c 2008-03-31 15:59:01.000000000 +0200
@@ -106,9 +106,6 @@ struct _cpp_file
/* If BUFFER above contains the true contents of the file. */
bool buffer_valid;
-
- /* File is a PCH (on return from find_include_file). */
- bool pch;
};
/* A singly-linked list for all searches for a given file name, with
@@ -322,9 +319,7 @@ pch_open_file (cpp_reader *pfile, _cpp_f
}
closedir (pchdir);
}
- if (valid)
- file->pch = true;
- else
+ if (!valid)
*invalid_pch = true;
}
@@ -703,11 +698,12 @@ should_stack_file (cpp_reader *pfile, _c
return false;
/* Handle PCH files immediately; don't stack them. */
- if (file->pch)
+ if (file->pchname)
{
pfile->cb.read_pch (pfile, file->pchname, file->fd, file->path);
- close (file->fd);
file->fd = -1;
+ free ((void *) file->pchname);
+ file->pchname = NULL;
return false;
}
@@ -916,7 +912,7 @@ _cpp_stack_include (cpp_reader *pfile, c
complicates LAST_SOURCE_LINE_LOCATION. This does not apply if we
found a PCH file (in which case linemap_add is not called) or we
were included from the command-line. */
- if (! file->pch && file->err_no == 0 && type != IT_CMDLINE)
+ if (file->pchname == NULL && file->err_no == 0 && type != IT_CMDLINE)
pfile->line_table->highest_location--;
return _cpp_stack_file (pfile, file, type == IT_IMPORT);
--- gcc/c-pch.c.jj 2008-02-18 23:46:08.000000000 +0100
+++ gcc/c-pch.c 2008-03-31 15:56:00.000000000 +0200
@@ -372,6 +372,7 @@ c_common_read_pch (cpp_reader *pfile, co
if (f == NULL)
{
cpp_errno (pfile, CPP_DL_ERROR, "calling fdopen");
+ close (fd);
return;
}
@@ -380,6 +381,7 @@ c_common_read_pch (cpp_reader *pfile, co
if (fread (&h, sizeof (h), 1, f) != 1)
{
cpp_errno (pfile, CPP_DL_ERROR, "reading");
+ fclose (f);
return;
}
@@ -425,7 +427,10 @@ c_common_read_pch (cpp_reader *pfile, co
gt_pch_restore (f);
if (cpp_read_state (pfile, name, f, smd) != 0)
- return;
+ {
+ fclose (f);
+ return;
+ }
fclose (f);
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh330771.patch
-31
View File
@@ -1,31 +0,0 @@
2007-10-16 Jakub Jelinek <jakub@redhat.com>
* Makefile.am (libgcj_tools_la_LIBADD): Add.
* Makefile.in: Regenerated.
Index: libjava/Makefile.am
===================================================================
--- libjava/Makefile.am.orig 2010-03-21 12:41:37.000000000 -0700
+++ libjava/Makefile.am 2010-06-25 10:22:11.394130458 -0700
@@ -507,6 +507,8 @@
libgcj_tools_la_GCJFLAGS = $(AM_GCJFLAGS) -findirect-dispatch \
-fno-bootstrap-classes -fno-indirect-classes \
-fsource-filename=$(here)/classpath/tools/all-classes.lst
+## See jv_convert_LDADD.
+libgcj_tools_la_LIBADD = -L$(here)/.libs libgcj.la
libgcj_tools_la_LDFLAGS = -rpath $(toolexeclibdir) \
-version-info `grep -v '^\#' $(srcdir)/libtool-version` \
$(LIBGCJ_LD_SYMBOLIC_FUNCTIONS) $(LIBJAVA_LDFLAGS_NOUNDEF)
Index: libjava/Makefile.in
===================================================================
--- libjava/Makefile.in.orig 2010-04-02 11:18:06.000000000 -0700
+++ libjava/Makefile.in 2010-06-25 10:27:41.841708512 -0700
@@ -1190,7 +1190,7 @@
-version-info `grep -v '^\#' $(srcdir)/libtool-version` \
$(LIBGCJ_LD_SYMBOLIC_FUNCTIONS) $(LIBJAVA_LDFLAGS_NOUNDEF)
-libgcj_tools_la_LIBADD = libgcj.la -lm
+libgcj_tools_la_LIBADD = -L$(here)/.libs libgcj.la -lm
libgcj_tools_la_DEPENDENCIES = libgcj.la libgcj.spec $(am__append_22)
libgcj_tools_la_LINK = $(LIBLINK) $(libgcj_tools_la_LDFLAGS)
libjvm_la_SOURCES = jni-libjvm.cc
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc43-rh341221.patch
-32
View File
@@ -1,32 +0,0 @@
2007-10-21 Jakub Jelinek <jakub@redhat.com>
* doc/Makefile.am (POD2MAN): Set date from cp-tools.texinfo
timestamp rather than from current date.
* doc/Makefile.in: Regenerated.
Index: libjava/classpath/doc/Makefile.am
===================================================================
--- libjava/classpath/doc/Makefile.am.orig 2008-10-21 10:55:01.000000000 -0700
+++ libjava/classpath/doc/Makefile.am 2010-06-25 10:28:30.237631599 -0700
@@ -31,7 +31,7 @@
gtnameserv.1 \
gjdoc.1
-POD2MAN = pod2man --center="GNU" --release="$(VERSION)"
+POD2MAN = pod2man --center="GNU" --release="$(VERSION)" --date="$(shell ls --time-style=+%F -l $(srcdir)/cp-tools.texinfo | awk '{print $$6}')"
TEXI2POD = perl $(srcdir)/texi2pod.pl
STAMP = echo timestamp >
Index: libjava/classpath/doc/Makefile.in
===================================================================
--- libjava/classpath/doc/Makefile.in.orig 2010-04-02 11:18:06.000000000 -0700
+++ libjava/classpath/doc/Makefile.in 2010-06-25 10:28:30.245635728 -0700
@@ -376,7 +376,7 @@
gtnameserv.1 \
gjdoc.1
-POD2MAN = pod2man --center="GNU" --release="$(VERSION)"
+POD2MAN = pod2man --center="GNU" --release="$(VERSION)" --date="$(shell ls --time-style=+%F -l $(srcdir)/cp-tools.texinfo | awk '{print $$6}')"
TEXI2POD = perl $(srcdir)/texi2pod.pl
STAMP = echo timestamp >
@GENINSRC_FALSE@STAMP_GENINSRC =
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fedora/gcc45-no-add-needed.patch
-60
View File
@@ -1,60 +0,0 @@
2010-02-08 Roland McGrath <roland@redhat.com>
* config/rs6000/sysv4.h (LINK_EH_SPEC): Pass --no-add-needed to the
linker.
* config/linux.h (LINK_EH_SPEC): Likewise.
* config/alpha/elf.h (LINK_EH_SPEC): Likewise.
* config/ia64/linux.h (LINK_EH_SPEC): Likewise.
Index: gcc/config/alpha/elf.h
===================================================================
--- gcc/config/alpha/elf.h.orig 2011-06-16 17:58:47.000000000 -0700
+++ gcc/config/alpha/elf.h 2011-09-17 11:04:57.033298875 -0700
@@ -441,7 +441,7 @@ extern int alpha_this_gpdisp_sequence_nu
I imagine that other systems will catch up. In the meantime, it
doesn't harm to make sure that the data exists to be used later. */
#if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+#define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} "
#endif
/* A C statement (sans semicolon) to output to the stdio stream STREAM
Index: gcc/config/ia64/linux.h
===================================================================
--- gcc/config/ia64/linux.h.orig 2011-09-17 11:03:19.000000000 -0700
+++ gcc/config/ia64/linux.h 2011-09-17 11:04:57.033298875 -0700
@@ -80,7 +80,7 @@ do { \
Signalize that because we have fde-glibc, we don't need all C shared libs
linked against -lgcc_s. */
#undef LINK_EH_SPEC
-#define LINK_EH_SPEC ""
+#define LINK_EH_SPEC "--no-add-needed "
#define MD_UNWIND_SUPPORT "config/ia64/linux-unwind.h"
Index: gcc/config/linux.h
===================================================================
--- gcc/config/linux.h.orig 2011-09-17 11:03:38.000000000 -0700
+++ gcc/config/linux.h 2011-09-17 11:04:57.033298875 -0700
@@ -101,7 +101,7 @@ see the files COPYING3 and COPYING.RUNTI
} while (0)
#if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+#define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} "
#endif
/* Define this so we can compile MS code for use with WINE. */
Index: gcc/config/rs6000/sysv4.h
===================================================================
--- gcc/config/rs6000/sysv4.h.orig 2011-09-17 11:03:41.000000000 -0700
+++ gcc/config/rs6000/sysv4.h 2011-09-17 11:05:58.653298861 -0700
@@ -908,7 +908,7 @@ SVR4_ASM_SPEC \
#if defined(HAVE_LD_EH_FRAME_HDR)
# undef LINK_EH_SPEC
-# define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+# define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} "
#endif
#define CPP_OS_LINUX_SPEC "-D__unix__ -D__gnu_linux__ -D__linux__ \
toolchain-layer/recipes-devtools/gcc/gcc-4.5/fortran-cross-compile-hack.patch
-30
View File
@@ -1,30 +0,0 @@
* Fortran would have searched for arm-angstrom-gnueabi-gfortran but would have used
used gfortan. For gcc_4.2.2.bb we want to use the gfortran compiler from our cross
directory.
Index: gcc-4.5+svnr155514/libgfortran/configure
===================================================================
--- gcc-4.5+svnr155514.orig/libgfortran/configure 2009-12-29 22:02:01.000000000 -0800
+++ gcc-4.5+svnr155514/libgfortran/configure 2009-12-30 08:12:40.889091657 -0800
@@ -11655,7 +11655,7 @@ CC="$lt_save_CC"
# We need gfortran to compile parts of the library
#AC_PROG_FC(gfortran)
-FC="$GFORTRAN"
+#FC="$GFORTRAN"
ac_ext=${ac_fc_srcext-f}
ac_compile='$FC -c $FCFLAGS $ac_fcflags_srcext conftest.$ac_ext >&5'
ac_link='$FC -o conftest$ac_exeext $FCFLAGS $LDFLAGS $ac_fcflags_srcext conftest.$ac_ext $LIBS >&5'
Index: gcc-4.5+svnr155514/libgfortran/configure.ac
===================================================================
--- gcc-4.5+svnr155514.orig/libgfortran/configure.ac 2009-12-29 22:02:01.000000000 -0800
+++ gcc-4.5+svnr155514/libgfortran/configure.ac 2009-12-30 08:12:13.453094218 -0800
@@ -187,7 +187,7 @@ AC_SUBST(enable_static)
# We need gfortran to compile parts of the library
#AC_PROG_FC(gfortran)
-FC="$GFORTRAN"
+#FC="$GFORTRAN"
AC_PROG_FC(gfortran)
# extra LD Flags which are required for targets
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.0.2-e300c2c3.patch
-319
View File
@@ -1,319 +0,0 @@
Adds support for Freescale Power architecture e300c2 and e300c3 cores.
http://www.bitshrine.org/gpp/tc-fsl-x86lnx-e300c3-nptl-4.0.2-2.src.rpm
Leon Woestenberg <leonw@mailcan.com>
---
gcc/config.gcc | 2
gcc/config/rs6000/e300c2c3.md | 189 ++++++++++++++++++++++++++++++++++++++++++
gcc/config/rs6000/rs6000.c | 24 +++++
gcc/config/rs6000/rs6000.h | 4
gcc/config/rs6000/rs6000.md | 3
5 files changed, 220 insertions(+), 2 deletions(-)
Index: gcc-4.3.1/gcc/config/rs6000/e300c2c3.md
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc-4.3.1/gcc/config/rs6000/e300c2c3.md 2008-08-23 16:51:33.000000000 -0700
@@ -0,0 +1,189 @@
+;; Pipeline description for Motorola PowerPC e300c3 core.
+;; Copyright (C) 2003 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the
+;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+;; MA 02111-1307, USA.
+
+(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire")
+(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most")
+
+;; We don't simulate general issue queue (GIC). If we have SU insn
+;; and then SU1 insn, they can not be issued on the same cycle
+;; (although SU1 insn and then SU insn can be issued) because the SU
+;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle
+;; multipass insn scheduling will find the situation and issue the SU1
+;; insn and then the SU insn.
+(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most")
+
+;; We could describe completion buffers slots in combination with the
+;; retirement units and the order of completion but the result
+;; automaton would behave in the same way because we can not describe
+;; real latency time with taking in order completion into account.
+;; Actually we could define the real latency time by querying reserved
+;; automaton units but the current scheduler uses latency time before
+;; issuing insns and making any reservations.
+;;
+;; So our description is aimed to achieve a insn schedule in which the
+;; insns would not wait in the completion buffer.
+(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire")
+
+;; Branch unit:
+(define_cpu_unit "ppce300c3_bu" "ppce300c3_most")
+
+;; IU:
+(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most")
+
+;; IU: This used to describe non-pipelined division.
+(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long")
+
+;; SRU:
+(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most")
+
+;; Here we simplified LSU unit description not describing the stages.
+(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most")
+
+;; FPU:
+(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most")
+
+;; The following units are used to make automata deterministic
+(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most")
+(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most")
+(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire")
+(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most")
+
+;; The following sets to make automata deterministic when option ndfa is used.
+(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0")
+(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0")
+(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0")
+(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0")
+
+;; Some useful abbreviations.
+(define_reservation "ppce300c3_decode"
+ "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0")
+(define_reservation "ppce300c3_issue"
+ "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0")
+(define_reservation "ppce300c3_retire"
+ "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0")
+(define_reservation "ppce300c3_iu_stage0"
+ "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0")
+
+;; Compares can be executed either one of the IU or SRU
+(define_insn_reservation "ppce300c3_cmp" 1
+ (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
+ +ppce300c3_retire")
+
+;; Other one cycle IU insns
+(define_insn_reservation "ppce300c3_iu" 1
+ (and (eq_attr "type" "integer,insert_word")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
+
+;; Branch. Actually this latency time is not used by the scheduler.
+(define_insn_reservation "ppce300c3_branch" 1
+ (and (eq_attr "type" "jmpreg,branch")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire")
+
+;; Multiply is non-pipelined but can be executed in any IU
+(define_insn_reservation "ppce300c3_multiply" 2
+ (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
+ ppce300c3_iu_stage0+ppce300c3_retire")
+
+;; Divide. We use the average latency time here. We omit reserving a
+;; retire unit because of the result automata will be huge.
+(define_insn_reservation "ppce300c3_divide" 20
+ (and (eq_attr "type" "idiv")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\
+ ppce300c3_mu_div*19")
+
+;; CR logical
+(define_insn_reservation "ppce300c3_cr_logical" 1
+ (and (eq_attr "type" "cr_logical,delayed_cr")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
+
+;; Mfcr
+(define_insn_reservation "ppce300c3_mfcr" 1
+ (and (eq_attr "type" "mfcr")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
+
+;; Mtcrf
+(define_insn_reservation "ppce300c3_mtcrf" 1
+ (and (eq_attr "type" "mtcr")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
+
+;; Mtjmpr
+(define_insn_reservation "ppce300c3_mtjmpr" 1
+ (and (eq_attr "type" "mtjmpr,mfjmpr")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire")
+
+;; Float point instructions
+(define_insn_reservation "ppce300c3_fpcompare" 3
+ (and (eq_attr "type" "fpcompare")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
+
+(define_insn_reservation "ppce300c3_fp" 3
+ (and (eq_attr "type" "fp")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire")
+
+(define_insn_reservation "ppce300c3_dmul" 4
+ (and (eq_attr "type" "dmul")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire")
+
+; Divides are not pipelined
+(define_insn_reservation "ppce300c3_sdiv" 18
+ (and (eq_attr "type" "sdiv")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17")
+
+(define_insn_reservation "ppce300c3_ddiv" 33
+ (and (eq_attr "type" "ddiv")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32")
+
+;; Loads
+(define_insn_reservation "ppce300c3_load" 2
+ (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
+
+(define_insn_reservation "ppce300c3_fpload" 2
+ (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
+
+;; Stores.
+(define_insn_reservation "ppce300c3_store" 2
+ (and (eq_attr "type" "store,store_ux,store_u")
+ (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
+
+(define_insn_reservation "ppce300c3_fpstore" 2
+ (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
+ (eq_attr "cpu" "ppce300c3"))
+ "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire")
Index: gcc-4.3.1/gcc/config/rs6000/rs6000.c
===================================================================
--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.c 2008-08-23 16:49:39.000000000 -0700
+++ gcc-4.3.1/gcc/config/rs6000/rs6000.c 2008-08-23 16:54:25.000000000 -0700
@@ -669,6 +669,21 @@ struct processor_costs ppc8540_cost = {
1, /* prefetch streams /*/
};
+/* Instruction costs on E300C2 and E300C3 cores. */
+static const
+struct processor_costs ppce300c2c3_cost = {
+ COSTS_N_INSNS (4), /* mulsi */
+ COSTS_N_INSNS (4), /* mulsi_const */
+ COSTS_N_INSNS (4), /* mulsi_const9 */
+ COSTS_N_INSNS (4), /* muldi */
+ COSTS_N_INSNS (19), /* divsi */
+ COSTS_N_INSNS (19), /* divdi */
+ COSTS_N_INSNS (3), /* fp */
+ COSTS_N_INSNS (4), /* dmul */
+ COSTS_N_INSNS (18), /* sdiv */
+ COSTS_N_INSNS (33), /* ddiv */
+};
+
/* Instruction costs on POWER4 and POWER5 processors. */
static const
struct processor_costs power4_cost = {
@@ -1420,6 +1435,8 @@ rs6000_override_options (const char *def
{"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
/* 8548 has a dummy entry for now. */
{"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
+ {"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
+ {"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
{"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
{"970", PROCESSOR_POWER4,
POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
@@ -1845,6 +1862,11 @@ rs6000_override_options (const char *def
rs6000_cost = &ppc8540_cost;
break;
+ case PROCESSOR_PPCE300C2:
+ case PROCESSOR_PPCE300C3:
+ rs6000_cost = &ppce300c2c3_cost;
+ break;
+
case PROCESSOR_POWER4:
case PROCESSOR_POWER5:
rs6000_cost = &power4_cost;
@@ -18606,6 +18628,8 @@ rs6000_issue_rate (void)
case CPU_PPC7400:
case CPU_PPC8540:
case CPU_CELL:
+ case CPU_PPCE300C2:
+ case CPU_PPCE300C3:
return 2;
case CPU_RIOS2:
case CPU_PPC604:
Index: gcc-4.3.1/gcc/config/rs6000/rs6000.h
===================================================================
--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.h 2008-01-26 09:18:35.000000000 -0800
+++ gcc-4.3.1/gcc/config/rs6000/rs6000.h 2008-08-23 16:55:30.000000000 -0700
@@ -117,6 +117,8 @@
%{mcpu=G5: -mpower4 -maltivec} \
%{mcpu=8540: -me500} \
%{mcpu=8548: -me500} \
+%{mcpu=e300c2: -mppc} \
+%{mcpu=e300c3: -mppc -mpmr} \
%{maltivec: -maltivec} \
-many"
@@ -262,6 +264,8 @@ enum processor_type
PROCESSOR_PPC7400,
PROCESSOR_PPC7450,
PROCESSOR_PPC8540,
+ PROCESSOR_PPCE300C2,
+ PROCESSOR_PPCE300C3,
PROCESSOR_POWER4,
PROCESSOR_POWER5,
PROCESSOR_POWER6,
Index: gcc-4.3.1/gcc/config/rs6000/rs6000.md
===================================================================
--- gcc-4.3.1.orig/gcc/config/rs6000/rs6000.md 2008-02-13 16:14:45.000000000 -0800
+++ gcc-4.3.1/gcc/config/rs6000/rs6000.md 2008-08-23 16:57:29.000000000 -0700
@@ -133,7 +133,7 @@
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
-(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
+(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell,ppce300c2,ppce300c3"
(const (symbol_ref "rs6000_cpu_attr")))
@@ -166,6 +166,7 @@
(include "7xx.md")
(include "7450.md")
(include "8540.md")
+(include "e300c2c3.md")
(include "power4.md")
(include "power5.md")
(include "power6.md")
Index: gcc-4.3.1/gcc/config.gcc
===================================================================
--- gcc-4.3.1.orig/gcc/config.gcc 2008-08-23 16:49:43.000000000 -0700
+++ gcc-4.3.1/gcc/config.gcc 2008-08-23 17:03:55.000000000 -0700
@@ -3144,7 +3144,7 @@ case "${target}" in
| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 505 \
| 601 | 602 | 603 | 603e | ec603e | 604 \
- | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
+ | 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
| 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
# OK
;;
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch
-31
View File
@@ -1,31 +0,0 @@
---
configure | 2 +-
configure.ac | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Index: gcc-4.3.1/configure.ac
===================================================================
--- gcc-4.3.1.orig/configure.ac 2008-07-21 12:29:18.000000000 -0700
+++ gcc-4.3.1/configure.ac 2008-07-21 12:29:35.000000000 -0700
@@ -2352,7 +2352,7 @@ fi
# for target_alias and gcc doesn't manage it consistently.
target_configargs="--cache-file=./config.cache ${target_configargs}"
-FLAGS_FOR_TARGET=
+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
case " $target_configdirs " in
*" newlib "*)
case " $target_configargs " in
Index: gcc-4.3.1/configure
===================================================================
--- gcc-4.3.1.orig/configure 2008-07-21 12:29:48.000000000 -0700
+++ gcc-4.3.1/configure 2008-07-21 12:29:59.000000000 -0700
@@ -5841,7 +5841,7 @@ fi
# for target_alias and gcc doesn't manage it consistently.
target_configargs="--cache-file=./config.cache ${target_configargs}"
-FLAGS_FOR_TARGET=
+FLAGS_FOR_TARGET="$ARCH_FLAGS_FOR_TARGET"
case " $target_configdirs " in
*" newlib "*)
case " $target_configargs " in
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-4.5.0_to_svn_162697.patch.bz2
BIN
View File
Binary file not shown.
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-arm-volatile-bitfield-fix.patch
-103
View File
@@ -1,103 +0,0 @@
Date: Mon, 22 Nov 2010 13:28:54 +0000
From: Julian Brown <julian at codesourcery dot com>
To: gcc-patches at gcc dot gnu dot org
Cc: DJ Delorie <dj at redhat dot com>
Subject: [PATCH] Volatile bitfields vs. inline asm memory constraints
Message-ID: <20101122132854.0aca431a@rex.config>
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Hi,
This patch fixes the issue in the (Launchpad, not GCC) bug tracker:
https://bugs.launchpad.net/gcc-linaro/+bug/675347
The problem was introduced by the patch from DJ to honour volatile
bitfield types:
http://gcc.gnu.org/ml/gcc-patches/2010-06/msg01167.html
but not exposed (on ARM) until the option was made the default (on the
Linaro branch) -- it's not yet the default on mainline.
The issue is as follows: after DJ's patch and with
-fstrict-volatile-bitfields, in expr.c:expand_expr_real_1, the if
condition with the comment "In cases where an aligned union has an
unaligned object as a field, we might be extracting a BLKmode value
from an integer-mode (e.g., SImode) object [...]" triggers for a normal
(non-bitfield) volatile field of a struct/class.
But, this appears to be over-eager: in the particular case mentioned
above, when expanding a "volatile int" struct field used as a memory
constraint for an inline asm, we end up with something which is no
longer addressable (I think because of the actions of
extract_bit_field). So, compilation aborts.
My proposed fix is to restrict the conditional by only making it execute
for -fstrict-volatile-bitfields only for non-naturally-aligned accesses:
this appears to work (fixes test in question, and no regressions for
cross to ARM Linux, gcc/g++/libstdc++, with -fstrict-volatile-bitfields
turned on), but I don't know if there will be unintended consequences.
DJ, does it look sane to you?
Incidentally the constraints in the inline asm in the Launchpad
testcase might be slightly dubious (attempting to force (mem (reg)) by
using both "+m" (var) and "r" (&var) constraints), but replacing
them with e.g.:
asm volatile("0:\n"
"ldrex %[newValue], %[_q_value]\n"
"sub %[newValue], %[newValue], #1\n"
"strex %[result], %[newValue], %[_q_value]\n"
"teq %[result], #0\n"
"bne 0b\n"
: [newValue] "=&r" (newValue),
[result] "=&r" (result)
: [_q_value] "Q" (_q_value)
: "cc", "memory");
still leads to a warning (not an error) with trunk and
-fstrict-volatile-bitfields:
atomic-changed.cc:24:35: warning: use of memory input without lvalue in
asm operand 2 is deprecated [enabled by default]
The warning goes away with the attached patch. So, I don't think the
problem is purely that the original inline asm is invalid.
OK to apply, or any comments?
Julian
ChangeLog
gcc/
* expr.c (expand_expr_real_1): Only use BLKmode for volatile
accesses which are not naturally aligned.
Index: gcc-4_5-branch/gcc/expr.c
===================================================================
--- gcc-4_5-branch.orig/gcc/expr.c 2010-12-23 00:42:11.690101002 -0800
+++ gcc-4_5-branch/gcc/expr.c 2010-12-24 15:07:39.400101000 -0800
@@ -9029,7 +9029,8 @@
&& modifier != EXPAND_INITIALIZER)
/* If the field is volatile, we always want an aligned
access. */
- || (volatilep && flag_strict_volatile_bitfields > 0)
+ || (volatilep && flag_strict_volatile_bitfields > 0
+ && (bitpos % GET_MODE_ALIGNMENT (mode) != 0))
/* If the field isn't aligned enough to fetch as a memref,
fetch it as a bit field. */
|| (mode1 != BLKmode
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-armv4-pass-fix-v4bx-to-ld.patch
-29
View File
@@ -1,29 +0,0 @@
The LINK_SPEC for linux gets overwritten by linux-eabi.h which
means the value of TARGET_FIX_V4BX_SPEC gets lost and as a result
the option is not passed to linker when chosing march=armv4
This patch redefines this in linux-eabi.h and reinserts it
for eabi defaulting toolchains.
We might want to send it upstream
-Khem
Index: gcc-4.5/gcc/config/arm/linux-eabi.h
===================================================================
--- gcc-4.5.orig/gcc/config/arm/linux-eabi.h
+++ gcc-4.5/gcc/config/arm/linux-eabi.h
@@ -63,10 +63,14 @@
#undef GLIBC_DYNAMIC_LINKER
#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.3"
+/* For armv4 we pass --fix-v4bx to linker to support EABI */
+#undef TARGET_FIX_V4BX_SPEC
+#define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}"
+
/* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
use the GNU/Linux version, not the generic BPABI version. */
#undef LINK_SPEC
-#define LINK_SPEC LINUX_TARGET_LINK_SPEC BE8_LINK_SPEC
+#define LINK_SPEC LINUX_TARGET_LINK_SPEC BE8_LINK_SPEC TARGET_FIX_V4BX_SPEC
/* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we
do not use -lfloat. */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-flags-for-build.patch
-178
View File
@@ -1,178 +0,0 @@
Index: gcc-4.5/Makefile.def
===================================================================
--- gcc-4.5.orig/Makefile.def
+++ gcc-4.5/Makefile.def
@@ -240,6 +240,7 @@ flags_to_pass = { flag= AWK ; };
flags_to_pass = { flag= BISON ; };
flags_to_pass = { flag= CC_FOR_BUILD ; };
flags_to_pass = { flag= CFLAGS_FOR_BUILD ; };
+flags_to_pass = { flag= CPPFLAGS_FOR_BUILD ; };
flags_to_pass = { flag= CXX_FOR_BUILD ; };
flags_to_pass = { flag= EXPECT ; };
flags_to_pass = { flag= FLEX ; };
Index: gcc-4.5/gcc/Makefile.in
===================================================================
--- gcc-4.5.orig/gcc/Makefile.in
+++ gcc-4.5/gcc/Makefile.in
@@ -766,7 +766,7 @@ BUILD_LINKERFLAGS = $(BUILD_CFLAGS)
# Native linker and preprocessor flags. For x-fragment overrides.
BUILD_LDFLAGS=@BUILD_LDFLAGS@
-BUILD_CPPFLAGS=$(ALL_CPPFLAGS)
+BUILD_CPPFLAGS=$(INCLUDES) @BUILD_CPPFLAGS@ $(X_CPPFLAGS)
# Actual name to use when installing a native compiler.
GCC_INSTALL_NAME := $(shell echo gcc|sed '$(program_transform_name)')
Index: gcc-4.5/gcc/configure.ac
===================================================================
--- gcc-4.5.orig/gcc/configure.ac
+++ gcc-4.5/gcc/configure.ac
@@ -1798,16 +1798,18 @@ AC_SUBST(inhibit_libc)
# Also, we cannot run fixincludes.
# These are the normal (build=host) settings:
-CC_FOR_BUILD='$(CC)' AC_SUBST(CC_FOR_BUILD)
-BUILD_CFLAGS='$(ALL_CFLAGS)' AC_SUBST(BUILD_CFLAGS)
-BUILD_LDFLAGS='$(LDFLAGS)' AC_SUBST(BUILD_LDFLAGS)
-STMP_FIXINC=stmp-fixinc AC_SUBST(STMP_FIXINC)
+CC_FOR_BUILD='$(CC)' AC_SUBST(CC_FOR_BUILD)
+BUILD_CFLAGS='$(ALL_CFLAGS)' AC_SUBST(BUILD_CFLAGS)
+BUILD_LDFLAGS='$(LDFLAGS)' AC_SUBST(BUILD_LDFLAGS)
+BUILD_CPPFLAGS='$(ALL_CPPFLAGS)' AC_SUBST(BUILD_CPPFLAGS)
+STMP_FIXINC=stmp-fixinc AC_SUBST(STMP_FIXINC)
# And these apply if build != host, or we are generating coverage data
if test x$build != x$host || test "x$coverage_flags" != x
then
BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'
BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'
+ BUILD_CPPFLAGS='$(CPPFLAGS_FOR_BUILD)'
fi
# Expand extra_headers to include complete path.
Index: gcc-4.5/Makefile.in
===================================================================
--- gcc-4.5.orig/Makefile.in
+++ gcc-4.5/Makefile.in
@@ -333,6 +333,7 @@ AR_FOR_BUILD = @AR_FOR_BUILD@
AS_FOR_BUILD = @AS_FOR_BUILD@
CC_FOR_BUILD = @CC_FOR_BUILD@
CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@
+CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@
CXXFLAGS_FOR_BUILD = @CXXFLAGS_FOR_BUILD@
CXX_FOR_BUILD = @CXX_FOR_BUILD@
DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
@@ -662,6 +663,7 @@ BASE_FLAGS_TO_PASS = \
"BISON=$(BISON)" \
"CC_FOR_BUILD=$(CC_FOR_BUILD)" \
"CFLAGS_FOR_BUILD=$(CFLAGS_FOR_BUILD)" \
+ "CPPFLAGS_FOR_BUILD=$(CPPFLAGS_FOR_BUILD)" \
"CXX_FOR_BUILD=$(CXX_FOR_BUILD)" \
"EXPECT=$(EXPECT)" \
"FLEX=$(FLEX)" \
Index: gcc-4.5/gcc/configure
===================================================================
--- gcc-4.5.orig/gcc/configure
+++ gcc-4.5/gcc/configure
@@ -707,6 +707,7 @@ SED
LIBTOOL
collect2
STMP_FIXINC
+BUILD_CPPFLAGS
BUILD_LDFLAGS
BUILD_CFLAGS
CC_FOR_BUILD
@@ -10982,6 +10983,7 @@ fi
CC_FOR_BUILD='$(CC)'
BUILD_CFLAGS='$(ALL_CFLAGS)'
BUILD_LDFLAGS='$(LDFLAGS)'
+BUILD_CPPFLAGS='$(ALL_CPPFLAGS)'
STMP_FIXINC=stmp-fixinc
# And these apply if build != host, or we are generating coverage data
@@ -10989,6 +10991,7 @@ if test x$build != x$host || test "x$cov
then
BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)'
BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)'
+ BUILD_CPPFLAGS='$(CPPFLAGS_FOR_BUILD)'
fi
# Expand extra_headers to include complete path.
@@ -17108,7 +17111,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 17111 "configure"
+#line 17114 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -17214,7 +17217,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 17217 "configure"
+#line 17220 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
Index: gcc-4.5/Makefile.tpl
===================================================================
--- gcc-4.5.orig/Makefile.tpl
+++ gcc-4.5/Makefile.tpl
@@ -336,6 +336,7 @@ AR_FOR_BUILD = @AR_FOR_BUILD@
AS_FOR_BUILD = @AS_FOR_BUILD@
CC_FOR_BUILD = @CC_FOR_BUILD@
CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@
+CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@
CXXFLAGS_FOR_BUILD = @CXXFLAGS_FOR_BUILD@
CXX_FOR_BUILD = @CXX_FOR_BUILD@
DLLTOOL_FOR_BUILD = @DLLTOOL_FOR_BUILD@
Index: gcc-4.5/configure
===================================================================
--- gcc-4.5.orig/configure
+++ gcc-4.5/configure
@@ -651,6 +651,7 @@ GCJ_FOR_BUILD
DLLTOOL_FOR_BUILD
CXX_FOR_BUILD
CXXFLAGS_FOR_BUILD
+CPPFLAGS_FOR_BUILD
CFLAGS_FOR_BUILD
CC_FOR_BUILD
AS_FOR_BUILD
@@ -8036,6 +8037,7 @@ esac
# our build compiler if desired.
if test x"${build}" = x"${host}" ; then
CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}}
+ CPPFLAGS_FOR_BUILD=${CPPFLAGS_FOR_BUILD-${CPPFLAGS}}
CXXFLAGS_FOR_BUILD=${CXXFLAGS_FOR_BUILD-${CXXFLAGS}}
LDFLAGS_FOR_BUILD=${LDFLAGS_FOR_BUILD-${LDFLAGS}}
fi
@@ -8101,6 +8103,7 @@ done
+
Index: gcc-4.5/configure.ac
===================================================================
--- gcc-4.5.orig/configure.ac
+++ gcc-4.5/configure.ac
@@ -3089,6 +3089,7 @@ esac
# our build compiler if desired.
if test x"${build}" = x"${host}" ; then
CFLAGS_FOR_BUILD=${CFLAGS_FOR_BUILD-${CFLAGS}}
+ CPPFLAGS_FOR_BUILD=${CPPFLAGS_FOR_BUILD-${CPPFLAGS}}
CXXFLAGS_FOR_BUILD=${CXXFLAGS_FOR_BUILD-${CXXFLAGS}}
LDFLAGS_FOR_BUILD=${LDFLAGS_FOR_BUILD-${LDFLAGS}}
fi
@@ -3155,6 +3156,7 @@ AC_SUBST(AR_FOR_BUILD)
AC_SUBST(AS_FOR_BUILD)
AC_SUBST(CC_FOR_BUILD)
AC_SUBST(CFLAGS_FOR_BUILD)
+AC_SUBST(CPPFLAGS_FOR_BUILD)
AC_SUBST(CXXFLAGS_FOR_BUILD)
AC_SUBST(CXX_FOR_BUILD)
AC_SUBST(DLLTOOL_FOR_BUILD)
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ice-hack.dpatch
-331
View File
@@ -1,331 +0,0 @@
#! /bin/sh -e
# DP: Retry the build on an ice, save the calling options and preprocessed
# DP: source when the ice is reproducible.
dir=
if [ $# -eq 3 -a "$2" = '-d' ]; then
pdir="-d $3"
dir="$3/"
elif [ $# -ne 1 ]; then
echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
exit 1
fi
case "$1" in
-patch)
patch $pdir -f --no-backup-if-mismatch -p0 < $0
;;
-unpatch)
patch $pdir -f --no-backup-if-mismatch -R -p0 < $0
;;
*)
echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
exit 1
esac
exit 0
2004-01-23 Jakub Jelinek <jakub@redhat.com>
* system.h (ICE_EXIT_CODE): Define.
* gcc.c (execute): Don't free first string early, but at the end
of the function. Call retry_ice if compiler exited with
ICE_EXIT_CODE.
(retry_ice): New function.
* diagnostic.c (diagnostic_count_diagnostic,
diagnostic_action_after_output, error_recursion): Exit with
ICE_EXIT_CODE instead of FATAL_EXIT_CODE.
--- gcc/diagnostic.c.orig 2007-09-30 10:48:13.000000000 +0000
+++ gcc/diagnostic.c 2007-09-30 10:49:57.000000000 +0000
@@ -244,7 +244,7 @@
fnotice (stderr, "Please submit a full bug report,\n"
"with preprocessed source if appropriate.\n"
"See %s for instructions.\n", bug_report_url);
- exit (ICE_EXIT_CODE);
+ exit (FATAL_EXIT_CODE);
case DK_FATAL:
if (context->abort_on_error)
--- gcc/gcc.c.orig 2007-09-30 10:48:13.000000000 +0000
+++ gcc/gcc.c 2007-09-30 10:48:39.000000000 +0000
@@ -357,6 +357,9 @@
#if defined(HAVE_TARGET_OBJECT_SUFFIX) || defined(HAVE_TARGET_EXECUTABLE_SUFFIX)
static const char *convert_filename (const char *, int, int);
#endif
+#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
+static void retry_ice (const char *prog, const char **argv);
+#endif
static const char *getenv_spec_function (int, const char **);
static const char *if_exists_spec_function (int, const char **);
@@ -2999,7 +3002,7 @@
}
}
- if (string != commands[i].prog)
+ if (i && string != commands[i].prog)
free (CONST_CAST (char *, string));
}
@@ -3056,6 +3059,16 @@
else if (WIFEXITED (status)
&& WEXITSTATUS (status) >= MIN_FATAL_STATUS)
{
+#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
+ /* For ICEs in cc1, cc1obj, cc1plus see if it is
+ reproducible or not. */
+ char *p;
+ if (WEXITSTATUS (status) == ICE_EXIT_CODE
+ && i == 0
+ && (p = strrchr (commands[0].argv[0], DIR_SEPARATOR))
+ && ! strncmp (p + 1, "cc1", 3))
+ retry_ice (commands[0].prog, commands[0].argv);
+#endif
if (WEXITSTATUS (status) > greatest_status)
greatest_status = WEXITSTATUS (status);
ret_code = -1;
@@ -3076,6 +3089,9 @@
}
}
+ if (commands[0].argv[0] != commands[0].prog)
+ free ((PTR) commands[0].argv[0]);
+
return ret_code;
}
}
@@ -6016,6 +6032,224 @@
switches[switchnum].validated = 1;
}
+#if !(defined (__MSDOS__) || defined (OS2) || defined (VMS))
+#define RETRY_ICE_ATTEMPTS 2
+
+static void
+retry_ice (const char *prog, const char **argv)
+{
+ int nargs, out_arg = -1, quiet = 0, attempt;
+ int pid, retries, sleep_interval;
+ const char **new_argv;
+ char *temp_filenames[RETRY_ICE_ATTEMPTS * 2 + 2];
+
+ if (input_filename == NULL || ! strcmp (input_filename, "-"))
+ return;
+
+ for (nargs = 0; argv[nargs] != NULL; ++nargs)
+ /* Only retry compiler ICEs, not preprocessor ones. */
+ if (! strcmp (argv[nargs], "-E"))
+ return;
+ else if (argv[nargs][0] == '-' && argv[nargs][1] == 'o')
+ {
+ if (out_arg == -1)
+ out_arg = nargs;
+ else
+ return;
+ }
+ /* If the compiler is going to output any time information,
+ it might vary between invocations. */
+ else if (! strcmp (argv[nargs], "-quiet"))
+ quiet = 1;
+ else if (! strcmp (argv[nargs], "-ftime-report"))
+ return;
+
+ if (out_arg == -1 || !quiet)
+ return;
+
+ memset (temp_filenames, '\0', sizeof (temp_filenames));
+ new_argv = alloca ((nargs + 3) * sizeof (const char *));
+ memcpy (new_argv, argv, (nargs + 1) * sizeof (const char *));
+ new_argv[nargs++] = "-frandom-seed=0";
+ new_argv[nargs] = NULL;
+ if (new_argv[out_arg][2] == '\0')
+ new_argv[out_arg + 1] = "-";
+ else
+ new_argv[out_arg] = "-o-";
+
+ for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS + 1; ++attempt)
+ {
+ int fd = -1;
+ int status;
+
+ temp_filenames[attempt * 2] = make_temp_file (".out");
+ temp_filenames[attempt * 2 + 1] = make_temp_file (".err");
+
+ if (attempt == RETRY_ICE_ATTEMPTS)
+ {
+ int i;
+ int fd1, fd2;
+ struct stat st1, st2;
+ size_t n, len;
+ char *buf;
+
+ buf = xmalloc (8192);
+
+ for (i = 0; i < 2; ++i)
+ {
+ fd1 = open (temp_filenames[i], O_RDONLY);
+ fd2 = open (temp_filenames[2 + i], O_RDONLY);
+
+ if (fd1 < 0 || fd2 < 0)
+ {
+ i = -1;
+ close (fd1);
+ close (fd2);
+ break;
+ }
+
+ if (fstat (fd1, &st1) < 0 || fstat (fd2, &st2) < 0)
+ {
+ i = -1;
+ close (fd1);
+ close (fd2);
+ break;
+ }
+
+ if (st1.st_size != st2.st_size)
+ {
+ close (fd1);
+ close (fd2);
+ break;
+ }
+
+ len = 0;
+ for (n = st1.st_size; n; n -= len)
+ {
+ len = n;
+ if (len > 4096)
+ len = 4096;
+
+ if (read (fd1, buf, len) != (int) len
+ || read (fd2, buf + 4096, len) != (int) len)
+ {
+ i = -1;
+ break;
+ }
+
+ if (memcmp (buf, buf + 4096, len) != 0)
+ break;
+ }
+
+ close (fd1);
+ close (fd2);
+
+ if (n)
+ break;
+ }
+
+ free (buf);
+ if (i == -1)
+ break;
+
+ if (i != 2)
+ {
+ notice ("The bug is not reproducible, so it is likely a hardware or OS problem.\n");
+ break;
+ }
+
+ fd = open (temp_filenames[attempt * 2], O_RDWR);
+ if (fd < 0)
+ break;
+ write (fd, "//", 2);
+ for (i = 0; i < nargs; i++)
+ {
+ write (fd, " ", 1);
+ write (fd, new_argv[i], strlen (new_argv[i]));
+ }
+ write (fd, "\n", 1);
+ new_argv[nargs] = "-E";
+ new_argv[nargs + 1] = NULL;
+ }
+
+ /* Fork a subprocess; wait and retry if it fails. */
+ sleep_interval = 1;
+ pid = -1;
+ for (retries = 0; retries < 4; retries++)
+ {
+ pid = fork ();
+ if (pid >= 0)
+ break;
+ sleep (sleep_interval);
+ sleep_interval *= 2;
+ }
+
+ if (pid < 0)
+ break;
+ else if (pid == 0)
+ {
+ if (attempt != RETRY_ICE_ATTEMPTS)
+ fd = open (temp_filenames[attempt * 2], O_RDWR);
+ if (fd < 0)
+ exit (-1);
+ if (fd != 1)
+ {
+ close (1);
+ dup (fd);
+ close (fd);
+ }
+
+ fd = open (temp_filenames[attempt * 2 + 1], O_RDWR);
+ if (fd < 0)
+ exit (-1);
+ if (fd != 2)
+ {
+ close (2);
+ dup (fd);
+ close (fd);
+ }
+
+ if (prog == new_argv[0])
+ execvp (prog, (char *const *) new_argv);
+ else
+ execv (new_argv[0], (char *const *) new_argv);
+ exit (-1);
+ }
+
+ if (waitpid (pid, &status, 0) < 0)
+ break;
+
+ if (attempt < RETRY_ICE_ATTEMPTS
+ && (! WIFEXITED (status) || WEXITSTATUS (status) != ICE_EXIT_CODE))
+ {
+ notice ("The bug is not reproducible, so it is likely a hardware or OS problem.\n");
+ break;
+ }
+ else if (attempt == RETRY_ICE_ATTEMPTS)
+ {
+ close (fd);
+ if (WIFEXITED (status)
+ && WEXITSTATUS (status) == SUCCESS_EXIT_CODE)
+ {
+ notice ("Preprocessed source stored into %s file, please attach this to your bugreport.\n",
+ temp_filenames[attempt * 2]);
+ /* Make sure it is not deleted. */
+ free (temp_filenames[attempt * 2]);
+ temp_filenames[attempt * 2] = NULL;
+ break;
+ }
+ }
+ }
+
+ for (attempt = 0; attempt < RETRY_ICE_ATTEMPTS * 2 + 2; attempt++)
+ if (temp_filenames[attempt])
+ {
+ unlink (temp_filenames[attempt]);
+ free (temp_filenames[attempt]);
+ }
+}
+#endif
+
/* Search for a file named NAME trying various prefixes including the
user's -B prefix and some standard ones.
Return the absolute file name found. If nothing is found, return NAME. */
--- gcc/Makefile.in.orig 2007-09-30 10:48:13.000000000 +0000
+++ gcc/Makefile.in 2007-09-30 10:48:39.000000000 +0000
@@ -192,6 +192,7 @@
build/gengtype-lex.o-warn = -Wno-error
# SYSCALLS.c misses prototypes
SYSCALLS.c.X-warn = -Wno-strict-prototypes -Wno-error
+build/gcc.o-warn = -Wno-error
# All warnings have to be shut off in stage1 if the compiler used then
# isn't gcc; configure determines that. WARN_CFLAGS will be either
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-dir-extend.patch
-25
View File
@@ -1,25 +0,0 @@
Add /sw/include and /opt/include based on the original
zecke-no-host-includes.patch patch. The original patch checked for
/usr/include, /sw/include and /opt/include and then triggered a failure and
aborted.
Instead, we add the two missing items to the current scan. If the user
wants this to be a failure, they can add "-Werror=poison-system-directories".
Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
Index: gcc-4_5-branch/gcc/incpath.c
===================================================================
--- gcc-4_5-branch.orig/gcc/incpath.c
+++ gcc-4_5-branch/gcc/incpath.c
@@ -365,7 +365,9 @@ merge_include_chains (const char *sysroo
{
if ((!strncmp (p->name, "/usr/include", 12))
|| (!strncmp (p->name, "/usr/local/include", 18))
- || (!strncmp (p->name, "/usr/X11R6/include", 18)))
+ || (!strncmp (p->name, "/usr/X11R6/include", 18))
+ || (!strncmp (p->name, "/sw/include", 11))
+ || (!strncmp (p->name, "/opt/include", 12)))
warning (OPT_Wpoison_system_directories,
"include location \"%s\" is unsafe for "
"cross-compilation",
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-parameters.patch
-83
View File
@@ -1,83 +0,0 @@
gcc: add poison parameters detection
Add the logic that, if not configured with "--enable-target-optspace",
gcc will meet error when build target app with "-Os" option.
This could avoid potential binary crash.
Signed-off-by: Dongxiao Xu <dongxiao.xu@intel.com>
Index: gcc-4_5-branch/gcc/config.in
===================================================================
--- gcc-4_5-branch.orig/gcc/config.in
+++ gcc-4_5-branch/gcc/config.in
@@ -138,6 +138,12 @@
#endif
+/* Define to enable target optspace support. */
+#ifndef USED_FOR_TARGET
+#undef ENABLE_TARGET_OPTSPACE
+#endif
+
+
/* Define if you want all operations on RTL (the basic data structure of the
optimizer and back end) to be checked for dynamic type safety at runtime.
This is quite expensive. */
Index: gcc-4_5-branch/gcc/configure
===================================================================
--- gcc-4_5-branch.orig/gcc/configure
+++ gcc-4_5-branch/gcc/configure
@@ -915,6 +915,7 @@ enable_version_specific_runtime_libs
with_slibdir
enable_poison_system_directories
enable_plugin
+enable_target_optspace
'
ac_precious_vars='build_alias
host_alias
@@ -25658,6 +25659,13 @@ $as_echo "#define ENABLE_PLUGIN 1" >>con
fi
+if test x"$enable_target_optspace" != x; then :
+
+$as_echo "#define ENABLE_TARGET_OPTSPACE 1" >>confdefs.h
+
+fi
+
+
# Configure the subdirectories
# AC_CONFIG_SUBDIRS($subdirs)
Index: gcc-4_5-branch/gcc/configure.ac
===================================================================
--- gcc-4_5-branch.orig/gcc/configure.ac
+++ gcc-4_5-branch/gcc/configure.ac
@@ -4659,6 +4659,11 @@ if test x"$enable_plugin" = x"yes"; then
AC_DEFINE(ENABLE_PLUGIN, 1, [Define to enable plugin support.])
fi
+AC_SUBST(enable_target_optspace)
+if test x"$enable_target_optspace" != x; then
+ AC_DEFINE(ENABLE_TARGET_OPTSPACE, 1, [Define to enable target optspace support.])
+fi
+
# Configure the subdirectories
# AC_CONFIG_SUBDIRS($subdirs)
Index: gcc-4_5-branch/gcc/opts.c
===================================================================
--- gcc-4_5-branch.orig/gcc/opts.c
+++ gcc-4_5-branch/gcc/opts.c
@@ -953,6 +953,11 @@ decode_options (unsigned int argc, const
else
set_param_value ("min-crossjump-insns", initial_min_crossjump_insns);
+#ifndef ENABLE_TARGET_OPTSPACE
+ if (optimize_size == 1)
+ error ("Do not use -Os option if --enable-target-optspace is not set.");
+#endif
+
if (first_time_p)
{
/* Initialize whether `char' is signed. */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-poison-system-directories.patch
-201
View File
@@ -1,201 +0,0 @@
gcc/
2008-07-02 Joseph Myers <joseph@codesourcery.com>
* c-incpath.c: Include toplev.h.
(merge_include_chains): Use warning instead of cpp_error for
system directory poisoning diagnostic.
* Makefile.in (c-incpath.o): Depend on toplev.h.
* gcc.c (LINK_COMMAND_SPEC): Pass
--error-poison-system-directories if
-Werror=poison-system-directories.
2007-06-13 Joseph Myers <joseph@codesourcery.com>
* common.opt (--Wno-poison-system-directories): New.
* doc/invoke.texi (-Wno-poison-system-directories): Document.
* c-incpath.c: Include flags.h.
(merge_include_chains): Check flag_poison_system_directories.
* gcc.c (LINK_COMMAND_SPEC): Pass --no-poison-system-directories
to linker if -Wno-poison-system-directories.
* Makefile.in (c-incpath.o): Depend on $(FLAGS_H).
2007-03-20 Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure.ac (--enable-poison-system-directories): New option.
* configure, config.in: Regenerate.
* c-incpath.c (merge_include_chains): If
ENABLE_POISON_SYSTEM_DIRECTORIES defined, warn for use of
/usr/include, /usr/local/include or /usr/X11R6/include.
Index: gcc-4.5.0/gcc/common.opt
===================================================================
--- gcc-4.5.0.orig/gcc/common.opt 2010-03-17 20:01:09.000000000 -0700
+++ gcc-4.5.0/gcc/common.opt 2010-06-25 11:35:39.965383734 -0700
@@ -152,6 +152,10 @@
Common Var(warn_padded) Warning
Warn when padding is required to align structure members
+Wpoison-system-directories
+Common Var(flag_poison_system_directories) Init(1) Warning
+Warn for -I and -L options using system directories if cross compiling
+
Wshadow
Common Var(warn_shadow) Warning
Warn when one local variable shadows another
Index: gcc-4.5.0/gcc/config.in
===================================================================
--- gcc-4.5.0.orig/gcc/config.in 2010-04-14 02:30:07.000000000 -0700
+++ gcc-4.5.0/gcc/config.in 2010-06-25 11:35:39.969383588 -0700
@@ -132,6 +132,12 @@
#endif
+/* Define to warn for use of native system header directories */
+#ifndef USED_FOR_TARGET
+#undef ENABLE_POISON_SYSTEM_DIRECTORIES
+#endif
+
+
/* Define if you want all operations on RTL (the basic data structure of the
optimizer and back end) to be checked for dynamic type safety at runtime.
This is quite expensive. */
Index: gcc-4.5.0/gcc/configure.ac
===================================================================
--- gcc-4.5.0.orig/gcc/configure.ac 2010-06-25 11:34:01.433382161 -0700
+++ gcc-4.5.0/gcc/configure.ac 2010-06-25 11:35:39.969383588 -0700
@@ -4276,6 +4276,16 @@
fi)
AC_SUBST(slibdir)
+AC_ARG_ENABLE([poison-system-directories],
+ AS_HELP_STRING([--enable-poison-system-directories],
+ [warn for use of native system header directories]),,
+ [enable_poison_system_directories=no])
+if test "x${enable_poison_system_directories}" = "xyes"; then
+ AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES],
+ [1],
+ [Define to warn for use of native system header directories])
+fi
+
# Substitute configuration variables
AC_SUBST(subdirs)
AC_SUBST(srcdir)
Index: gcc-4.5.0/gcc/doc/invoke.texi
===================================================================
--- gcc-4.5.0.orig/gcc/doc/invoke.texi 2010-04-06 07:02:22.000000000 -0700
+++ gcc-4.5.0/gcc/doc/invoke.texi 2010-06-25 11:35:39.992666345 -0700
@@ -252,6 +252,7 @@
-Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol
-Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol
-Wpointer-arith -Wno-pointer-to-int-cast @gol
+-Wno-poison-system-directories @gol
-Wredundant-decls @gol
-Wreturn-type -Wsequence-point -Wshadow @gol
-Wsign-compare -Wsign-conversion -Wstack-protector @gol
@@ -3603,6 +3604,14 @@
option will @emph{not} warn about unknown pragmas in system
headers---for that, @option{-Wunknown-pragmas} must also be used.
+@item -Wno-poison-system-directories
+@opindex Wno-poison-system-directories
+Do not warn for @option{-I} or @option{-L} options using system
+directories such as @file{/usr/include} when cross compiling. This
+option is intended for use in chroot environments when such
+directories contain the correct headers and libraries for the target
+system rather than the host.
+
@item -Wfloat-equal
@opindex Wfloat-equal
@opindex Wno-float-equal
Index: gcc-4.5.0/gcc/gcc.c
===================================================================
--- gcc-4.5.0.orig/gcc/gcc.c 2010-02-11 04:23:08.000000000 -0800
+++ gcc-4.5.0/gcc/gcc.c 2010-06-25 11:35:40.009381858 -0700
@@ -792,6 +792,8 @@
%{flto} %{fwhopr} %l " LINK_PIE_SPEC \
"%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\
%{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\
+ %{Wno-poison-system-directories:--no-poison-system-directories}\
+ %{Werror=poison-system-directories:--error-poison-system-directories}\
%{static:} %{L*} %(mfwrap) %(link_libgcc) %o\
%{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)\
%{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\
Index: gcc-4.5.0/gcc/incpath.c
===================================================================
--- gcc-4.5.0.orig/gcc/incpath.c 2009-11-25 02:55:54.000000000 -0800
+++ gcc-4.5.0/gcc/incpath.c 2010-06-25 11:35:40.017209818 -0700
@@ -353,6 +353,24 @@
}
fprintf (stderr, _("End of search list.\n"));
}
+
+#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES
+ if (flag_poison_system_directories)
+ {
+ struct cpp_dir *p;
+
+ for (p = heads[QUOTE]; p; p = p->next)
+ {
+ if ((!strncmp (p->name, "/usr/include", 12))
+ || (!strncmp (p->name, "/usr/local/include", 18))
+ || (!strncmp (p->name, "/usr/X11R6/include", 18)))
+ warning (OPT_Wpoison_system_directories,
+ "include location \"%s\" is unsafe for "
+ "cross-compilation",
+ p->name);
+ }
+ }
+#endif
}
/* Use given -I paths for #include "..." but not #include <...>, and
diff -ur gcc-4.5.0.orig/gcc/Makefile.in gcc-4.5.0/gcc/Makefile.in
--- gcc-4.5.0.orig/gcc/Makefile.in 2010-09-29 17:13:49.164088845 -0500
+++ gcc-4.5.0/gcc/Makefile.in 2010-09-29 18:48:19.300178501 -0500
@@ -1965,7 +1965,7 @@
incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \
intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \
- $(MACHMODE_H)
+ $(MACHMODE_H) $(FLAGS_H) toplev.h
c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \
$(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \
diff -ur gcc-4.5.0.orig/gcc/configure gcc-4.5.0/gcc/configure
--- gcc-4.5.0.orig/gcc/configure 2010-09-29 14:58:31.702054881 -0500
+++ gcc-4.5.0/gcc/configure 2010-09-29 18:46:31.486068500 -0500
@@ -913,6 +913,7 @@
enable_maintainer_mode
enable_version_specific_runtime_libs
with_slibdir
+enable_poison_system_directories
enable_plugin
enable_target_optspace
'
@@ -1621,6 +1622,8 @@
--enable-version-specific-runtime-libs
specify that runtime libraries should be
installed in a compiler-specific directory
+ --enable-poison-system-directories
+ warn for use of native system header directories
--enable-plugin enable plugin support
Optional Packages:
@@ -25339,6 +25377,19 @@
+# Check whether --enable-poison-system-directories was given.
+if test "${enable_poison_system_directories+set}" = set; then :
+ enableval=$enable_poison_system_directories;
+else
+ enable_poison_system_directories=no
+fi
+
+if test "x${enable_poison_system_directories}" = "xyes"; then
+
+$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h
+
+fi
+
# Substitute configuration variables
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-ppc-config-fix.patch
-221
View File
@@ -1,221 +0,0 @@
commit de784bee66a1ec1d0dad00d9eedbe9b1667dd883
Author: jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Mon Dec 20 15:29:31 2010 +0000
* config/rs6000/freebsd.h (SVR4_ASM_SPEC): Don't define.
(DBX_REGISTER_NUMBER): Define.
* config/rs6000/lynx.h (DBX_REGISTER_NUMBER): Define.
* config/rs6000/netbsd.h (DBX_REGISTER_NUMBER): Define.
* config/rs6000/sysv4.h (SIZE_TYPE): Define.
(ASM_SPEC): Define without using SVR4_ASM_SPEC.
(DBX_REGISTER_NUMBER): Undefine.
* config.gcc (powerpc-*-eabispe*, powerpc-*-eabisimaltivec*,
powerpc-*-eabisim*, powerpc-*-elf*, powerpc-*-eabialtivec*,
powerpc-xilinx-eabi*, powerpc-*-eabi*, powerpc-*-rtems*,
powerpc-*-linux* | powerpc64-*-linux*, powerpc64-*-gnu*,
powerpc-*-gnu-gnualtivec*, powerpc-*-gnu*,
powerpc-wrs-vxworks|powerpc-wrs-vxworksae, powerpcle-*-elf*,
powerpcle-*-eabisim*, powerpcle-*-eabi*): Don't use svr4.h.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@168085 138bc75d-0d04-0410-961f-82ee72b054a4
Index: gcc-4_5-branch/gcc/config.gcc
===================================================================
--- gcc-4_5-branch.orig/gcc/config.gcc 2011-09-17 11:11:28.000000000 -0700
+++ gcc-4_5-branch/gcc/config.gcc 2011-09-17 11:16:32.543298716 -0700
@@ -1989,48 +1989,48 @@ powerpc-*-netbsd*)
extra_options="${extra_options} rs6000/sysv4.opt"
;;
powerpc-*-eabispe*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabispe.h"
+ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabispe.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-spe rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-eabisimaltivec*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h rs6000/eabialtivec.h"
+ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h rs6000/eabialtivec.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-eabisim*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-elf*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
;;
powerpc-*-eabialtivec*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h"
+ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-xilinx-eabi*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm rs6000/t-xilinx"
use_gcc_stdint=wrap
;;
powerpc-*-eabi*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-rtems*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h"
+ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-rtems t-rtems rs6000/t-ppccomm"
;;
@@ -2079,12 +2079,12 @@ powerpc-*-linux* | powerpc64-*-linux*)
fi
;;
powerpc64-*-gnu*)
- tm_file="${tm_file} elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/default64.h rs6000/linux64.h rs6000/gnu.h glibc-stdint.h"
+ tm_file="${tm_file} elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/default64.h rs6000/linux64.h rs6000/gnu.h glibc-stdint.h"
extra_options="${extra_options} rs6000/sysv4.opt rs6000/linux64.opt"
tmake_file="t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu"
;;
powerpc-*-gnu-gnualtivec*)
- tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h glibc-stdint.h"
+ tm_file="${cpu_type}/${cpu_type}.h elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h glibc-stdint.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcos t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu rs6000/t-ppccomm"
if test x$enable_threads = xyes; then
@@ -2092,7 +2092,7 @@ powerpc-*-gnu-gnualtivec*)
fi
;;
powerpc-*-gnu*)
- tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/gnu.h glibc-stdint.h"
+ tm_file="${cpu_type}/${cpu_type}.h elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/gnu.h glibc-stdint.h"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcos t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu rs6000/t-ppccomm"
extra_options="${extra_options} rs6000/sysv4.opt"
if test x$enable_threads = xyes; then
@@ -2100,7 +2100,7 @@ powerpc-*-gnu*)
fi
;;
powerpc-wrs-vxworks|powerpc-wrs-vxworksae)
- tm_file="${tm_file} elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h"
+ tm_file="${tm_file} elfos.h freebsd-spec.h rs6000/sysv4.h"
tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppccomm rs6000/t-vxworks"
extra_options="${extra_options} rs6000/sysv4.opt"
extra_headers=ppc-asm.h
@@ -2126,18 +2126,18 @@ powerpc-*-lynxos*)
gas=yes
;;
powerpcle-*-elf*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
extra_options="${extra_options} rs6000/sysv4.opt"
;;
powerpcle-*-eabisim*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
extra_options="${extra_options} rs6000/sysv4.opt"
use_gcc_stdint=wrap
;;
powerpcle-*-eabi*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
extra_options="${extra_options} rs6000/sysv4.opt"
use_gcc_stdint=wrap
Index: gcc-4_5-branch/gcc/config/rs6000/freebsd.h
===================================================================
--- gcc-4_5-branch.orig/gcc/config/rs6000/freebsd.h 2011-06-16 17:58:58.000000000 -0700
+++ gcc-4_5-branch/gcc/config/rs6000/freebsd.h 2011-09-17 11:13:13.623298761 -0700
@@ -69,6 +69,4 @@
/* Override rs6000.h definition. */
#undef ASM_APP_OFF
#define ASM_APP_OFF "#NO_APP\n"
-/* Define SVR4_ASM_SPEC, we use GAS by default. See svr4.h for details. */
-#define SVR4_ASM_SPEC \
- "%{v:-V} %{Wa,*:%*}"
+#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
Index: gcc-4_5-branch/gcc/config/rs6000/lynx.h
===================================================================
--- gcc-4_5-branch.orig/gcc/config/rs6000/lynx.h 2011-06-16 17:58:58.000000000 -0700
+++ gcc-4_5-branch/gcc/config/rs6000/lynx.h 2011-09-17 11:13:13.623298761 -0700
@@ -1,5 +1,5 @@
/* Definitions for Rs6000 running LynxOS.
- Copyright (C) 1995, 1996, 2000, 2002, 2003, 2004, 2005, 2007
+ Copyright (C) 1995, 1996, 2000, 2002, 2003, 2004, 2005, 2007, 2010
Free Software Foundation, Inc.
Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com)
Rewritten by Adam Nemet, LynuxWorks Inc.
@@ -105,6 +105,8 @@
#undef HAVE_AS_TLS
#define HAVE_AS_TLS 0
+#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
+
#ifdef CRT_BEGIN
/* This function is part of crtbegin*.o which is at the beginning of
the link and is called from .fini which is usually toward the end
Index: gcc-4_5-branch/gcc/config/rs6000/netbsd.h
===================================================================
--- gcc-4_5-branch.orig/gcc/config/rs6000/netbsd.h 2011-06-16 17:58:58.000000000 -0700
+++ gcc-4_5-branch/gcc/config/rs6000/netbsd.h 2011-09-17 11:13:13.623298761 -0700
@@ -1,6 +1,6 @@
/* Definitions of target machine for GNU compiler,
for PowerPC NetBSD systems.
- Copyright 2002, 2003, 2007, 2008 Free Software Foundation, Inc.
+ Copyright 2002, 2003, 2007, 2008, 2010 Free Software Foundation, Inc.
Contributed by Wasabi Systems, Inc.
This file is part of GCC.
@@ -89,3 +89,5 @@
#undef TARGET_VERSION
#define TARGET_VERSION fprintf (stderr, " (NetBSD/powerpc ELF)");
+
+#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
Index: gcc-4_5-branch/gcc/config/rs6000/sysv4.h
===================================================================
--- gcc-4_5-branch.orig/gcc/config/rs6000/sysv4.h 2011-09-17 11:11:29.000000000 -0700
+++ gcc-4_5-branch/gcc/config/rs6000/sysv4.h 2011-09-17 11:13:13.623298761 -0700
@@ -293,6 +293,10 @@ do { \
#define RESTORE_FP_PREFIX "_restfpr_"
#define RESTORE_FP_SUFFIX ""
+/* Type used for size_t, as a string used in a declaration. */
+#undef SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
/* Type used for ptrdiff_t, as a string used in a declaration. */
#define PTRDIFF_TYPE "int"
@@ -588,9 +592,8 @@ extern int fixuplabelno;
/* Override svr4.h definition. */
#undef ASM_SPEC
#define ASM_SPEC "%(asm_cpu) \
-%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}" \
-SVR4_ASM_SPEC \
-"%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \
+%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}} \
+%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \
%{memb|msdata=eabi: -memb} \
%{mlittle|mlittle-endian:-mlittle; \
mbig|mbig-endian :-mbig; \
@@ -1120,3 +1123,5 @@ ncrtn.o%s"
/* This target uses the sysv4.opt file. */
#define TARGET_USES_SYSV4_OPT 1
+
+#undef DBX_REGISTER_NUMBER
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-pr43698-arm-rev-instr.patch
-117
View File
@@ -1,117 +0,0 @@
backport http://gcc.gnu.org/viewcvs?view=revision&revision=162404
from trunk
Which fixes http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43698
2010-07-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/43698
* config/arm/arm.md: Split arm_rev into *arm_rev
and *thumb1_rev. Set *arm_rev to be predicable.
2010-07-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/43698
* gcc.target/arm/pr43698.c: New test.
/scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
Usage: date [OPTION]... [+FORMAT]
Display the current time in the given FORMAT.
-d, --date=STRING display time described by STRING, not `now'
-f, --file=DATEFILE like --date once for each line of DATEFILE
-R, --rfc-822 output RFC-822 compliant date string
-u, --utc, --universal print or set Coordinated Universal Time
--help display this help and exit
date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
date is /bin/date
date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
date is /bin/date
date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
date is /bin/date
date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
date is /scratch/oe/sysroots/i686-linux/usr/share/quilt/compat/date
date is /bin/date
date
Khem
Index: gcc-4.5/gcc/config/arm/arm.md
===================================================================
--- gcc-4.5.orig/gcc/config/arm/arm.md 2010-07-20 20:31:25.000000000 -0700
+++ gcc-4.5/gcc/config/arm/arm.md 2010-07-22 14:55:54.303169081 -0700
@@ -11197,15 +11197,21 @@
(set_attr "length" "4")]
)
-(define_insn "arm_rev"
+(define_insn "*arm_rev"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_EITHER && arm_arch6"
- "rev\t%0, %1"
- [(set (attr "length")
- (if_then_else (eq_attr "is_thumb" "yes")
- (const_int 2)
- (const_int 4)))]
+ "TARGET_32BIT && arm_arch6"
+ "rev%?\t%0, %1"
+ [(set_attr "predicable" "yes")
+ (set_attr "length" "4")]
+)
+
+(define_insn "*thumb1_rev"
+ [(set (match_operand:SI 0 "s_register_operand" "=l")
+ (bswap:SI (match_operand:SI 1 "s_register_operand" "l")))]
+ "TARGET_THUMB1 && arm_arch6"
+ "rev\t%0, %1"
+ [(set_attr "length" "2")]
)
(define_expand "arm_legacy_rev"
Index: gcc-4.5/gcc/testsuite/gcc.target/arm/pr43698.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc-4.5/gcc/testsuite/gcc.target/arm/pr43698.c 2010-07-22 14:56:35.406670213 -0700
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-Os -march=armv7-a" } */
+#include <stdint.h>
+#include <stdlib.h>
+
+
+char do_reverse_endian = 0;
+
+# define bswap_32(x) \
+ ((((x) & 0xff000000) >> 24) | \
+ (((x) & 0x00ff0000) >> 8) | \
+ (((x) & 0x0000ff00) << 8) | \
+ (((x) & 0x000000ff) << 24))
+
+#define EGET(X) \
+ (__extension__ ({ \
+ uint64_t __res; \
+ if (!do_reverse_endian) { __res = (X); \
+ } else if (sizeof(X) == 4) { __res = bswap_32((X)); \
+ } \
+ __res; \
+ }))
+
+void __attribute__((noinline)) X(char **phdr, char **data, int *phoff)
+{
+ *phdr = *data + EGET(*phoff);
+}
+
+int main()
+{
+ char *phdr;
+ char *data = (char *)0x40164000;
+ int phoff = 0x34;
+ X(&phdr, &data, &phoff);
+ if (phdr != (char *)0x40164034)
+ abort ();
+ exit (0);
+}
+
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-scalar-widening-pr45847.patch
-63
View File
@@ -1,63 +0,0 @@
Hi,
The attached patch fixes Bugzilla 45847
(http://gcc.gnu.org/bugzilla/show_bug.cgi?id=45847). When compiling
without -mvectorize-with-neon-quad and vectorizing scalar widening
operations that widen words to double words, there are no corresponding
vector types for DI scalar types. For this scenario, a call to
get_vect_type_for_scalar_type() returns NULL and an absent NULL-check
caused this segfault. The attached patch adds this NULL-check. Also,
this is consistent with all the other places where a NULL-check follows
a call to get_vect_type_for_scalar_type() in tree-vect-patterns.c.
Regression tested with arm-linux-gnueabi. OK?
--
Tejas Belagod
ARM.
gcc/
2010-10-05 Tejas Belagod <tejas.belagod@arm.com>
* tree-vect-patterns.c (vect_recog_widen_mult_pattern): Add NULL
check for vectype_out returned by get_vectype_for_scalar_type().
testsuite/
2010-10-05 Tejas Belagod <tejas.belagod@arm.com>
* gcc.dg/vect/pr45847.c: New test.
Index: gcc-4.5/gcc/testsuite/gcc.dg/vect/pr45847.c
===================================================================
--- /dev/null
+++ gcc-4.5/gcc/testsuite/gcc.dg/vect/pr45847.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+
+
+long long foo (long long *__restrict a, int *__restrict b, int *__restrict c )
+{
+ int i;
+ long long sum=0;
+ for (i=0;i<256;i++)
+ sum += (long long)b[i] * c[i];
+
+ return sum;
+}
+
+/* { dg-final { cleanup-tree-dump "vect" } } */
+
Index: gcc-4.5/gcc/tree-vect-patterns.c
===================================================================
--- gcc-4.5.orig/gcc/tree-vect-patterns.c
+++ gcc-4.5/gcc/tree-vect-patterns.c
@@ -411,6 +411,7 @@ vect_recog_widen_mult_pattern (gimple la
/* Check target support */
vectype = get_vectype_for_scalar_type (half_type0);
if (!vectype
+ || !get_vectype_for_scalar_type (type)
|| !supportable_widening_operation (WIDEN_MULT_EXPR, last_stmt, vectype,
&dummy, &dummy, &dummy_code,
&dummy_code, &dummy_int, &dummy_vec))
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-uclibc-locale-ctype_touplow_t.patch
-67
View File
@@ -1,67 +0,0 @@
Index: gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.h
===================================================================
--- gcc-4.5.orig/libstdc++-v3/config/locale/generic/c_locale.h 2010-06-30 22:30:53.993316002 -0700
+++ gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.h 2010-06-30 22:31:26.043316001 -0700
@@ -41,12 +41,17 @@
#include <clocale>
#include <cstddef>
+#include <features.h>
+#include <ctype.h>
#define _GLIBCXX_NUM_CATEGORIES 0
_GLIBCXX_BEGIN_NAMESPACE(std)
-
- typedef int* __c_locale;
+#ifdef __UCLIBC__
+ typedef __ctype_touplow_t* __c_locale;
+#else
+ typedef int* __c_locale;
+#endif
// Convert numeric value of type double and long double to string and
// return length of string. If vsnprintf is available use it, otherwise
Index: gcc-4.5/libstdc++-v3/config/os/gnu-linux/ctype_base.h
===================================================================
--- gcc-4.5.orig/libstdc++-v3/config/os/gnu-linux/ctype_base.h 2010-06-30 22:30:54.013316002 -0700
+++ gcc-4.5/libstdc++-v3/config/os/gnu-linux/ctype_base.h 2010-06-30 22:31:26.053316001 -0700
@@ -33,14 +33,21 @@
*/
// Information as gleaned from /usr/include/ctype.h
-
+
+#include <features.h>
+#include <ctype.h>
+
_GLIBCXX_BEGIN_NAMESPACE(std)
/// @brief Base class for ctype.
struct ctype_base
{
// Non-standard typedefs.
- typedef const int* __to_type;
+#ifdef __UCLIBC__
+ typedef const __ctype_touplow_t* __to_type;
+#else
+ typedef const int* __to_type;
+#endif
// NB: Offsets into ctype<char>::_M_table force a particular size
// on the mask type. Because of this, we don't use an enum.
Index: gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.cc
===================================================================
--- gcc-4.5.orig/libstdc++-v3/config/locale/generic/c_locale.cc 2010-06-28 12:12:42.000000000 -0700
+++ gcc-4.5/libstdc++-v3/config/locale/generic/c_locale.cc 2010-06-30 22:31:26.063316001 -0700
@@ -256,5 +256,10 @@ _GLIBCXX_END_NAMESPACE
#ifdef _GLIBCXX_LONG_DOUBLE_COMPAT
#define _GLIBCXX_LDBL_COMPAT(dbl, ldbl) \
extern "C" void ldbl (void) __attribute__ ((alias (#dbl)))
+#ifdef __UCLIBC__
+// This is because __c_locale is of type __ctype_touplow_t* which is short on uclibc. for glibc its int*
+_GLIBCXX_LDBL_COMPAT(_ZSt14__convert_to_vIdEvPKcRT_RSt12_Ios_IostateRKPs, _ZSt14__convert_to_vIeEvPKcRT_RSt12_Ios_IostateRKPs);
+#else
_GLIBCXX_LDBL_COMPAT(_ZSt14__convert_to_vIdEvPKcRT_RSt12_Ios_IostateRKPi, _ZSt14__convert_to_vIeEvPKcRT_RSt12_Ios_IostateRKPi);
+#endif
#endif // _GLIBCXX_LONG_DOUBLE_COMPAT
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc-with-linker-hash-style.patch
-212
View File
@@ -1,212 +0,0 @@
Upstream-Status: Backport
Signed-off-by: Khem Raj <raj.khem@gmail.com>
commit 3cb9bbfa927aa187048534f9069202c017a78e38
Author: ppluzhnikov <ppluzhnikov@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Wed May 11 18:28:14 2011 +0000
2011-05-11 Satoru Takabayashi <satorux@google.com>
Paul Pluzhnikov <ppluzhnikov@google.com>
* gcc/doc/install.texi (Configuration): Document
--with-linker-hash-style.
* gcc/gcc.c (init_spec): Handle LINKER_HASH_STYLE.
* gcc/config.in: Add LINKER_HASH_STYLE.
* gcc/configure.ac: Add --with-linker-hash-style.
* gcc/configure: Regenerate.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173668 138bc75d-0d04-0410-961f-82ee72b054a4
Index: gcc-4_5-branch/gcc/config.in
===================================================================
--- gcc-4_5-branch.orig/gcc/config.in 2011-12-03 13:41:00.000000000 -0800
+++ gcc-4_5-branch/gcc/config.in 2011-12-03 13:44:46.287530329 -0800
@@ -113,6 +113,12 @@
#endif
+/* The linker hash style */
+#ifndef USED_FOR_TARGET
+#undef LINKER_HASH_STYLE
+#endif
+
+
/* Define to enable LTO support. */
#ifndef USED_FOR_TARGET
#undef ENABLE_LTO
Index: gcc-4_5-branch/gcc/configure
===================================================================
--- gcc-4_5-branch.orig/gcc/configure 2011-12-03 13:41:00.000000000 -0800
+++ gcc-4_5-branch/gcc/configure 2011-12-03 13:46:12.747530321 -0800
@@ -600,6 +600,7 @@
ac_subst_vars='LTLIBOBJS
LIBOBJS
+enable_target_optspace
enable_plugin
pluginlibs
LIBELFINC
@@ -915,7 +916,7 @@
with_slibdir
enable_poison_system_directories
enable_plugin
-enable_target_optspace
+with_linker_hash_style
'
ac_precious_vars='build_alias
host_alias
@@ -1663,6 +1664,8 @@
with the compiler
--with-system-zlib use installed libz
--with-slibdir=DIR shared libraries in DIR [LIBDIR]
+ --with-linker-hash-style={sysv,gnu,both}
+ specify the linker hash style
Some influential environment variables:
CC C compiler command
@@ -17115,7 +17118,7 @@
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 17114 "configure"
+#line 17121 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -17221,7 +17224,7 @@
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
-#line 17220 "configure"
+#line 17227 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@@ -25659,12 +25662,42 @@
fi
-if test x"$enable_target_optspace" != x; then :
+
+if test x"$enable_target_optspace" != x; then
$as_echo "#define ENABLE_TARGET_OPTSPACE 1" >>confdefs.h
fi
+# Specify what hash style to use by default.
+
+# Check whether --with-linker-hash-style was given.
+if test "${with_linker_hash_style+set}" = set; then :
+ withval=$with_linker_hash_style; case x"$withval" in
+ xsysv)
+ LINKER_HASH_STYLE=sysv
+ ;;
+ xgnu)
+ LINKER_HASH_STYLE=gnu
+ ;;
+ xboth)
+ LINKER_HASH_STYLE=both
+ ;;
+ *)
+ as_fn_error "$withval is an invalid option to --with-linker-hash-style" "$LINENO" 5
+ ;;
+ esac
+else
+ LINKER_HASH_STYLE=''
+fi
+
+if test x"${LINKER_HASH_STYLE}" != x; then
+
+cat >>confdefs.h <<_ACEOF
+#define LINKER_HASH_STYLE "$LINKER_HASH_STYLE"
+_ACEOF
+
+fi
# Configure the subdirectories
# AC_CONFIG_SUBDIRS($subdirs)
Index: gcc-4_5-branch/gcc/configure.ac
===================================================================
--- gcc-4_5-branch.orig/gcc/configure.ac 2011-12-03 13:41:00.000000000 -0800
+++ gcc-4_5-branch/gcc/configure.ac 2011-12-03 13:41:04.499530358 -0800
@@ -4664,6 +4664,30 @@
AC_DEFINE(ENABLE_TARGET_OPTSPACE, 1, [Define to enable target optspace support.])
fi
+# Specify what hash style to use by default.
+AC_ARG_WITH([linker-hash-style],
+[AC_HELP_STRING([--with-linker-hash-style={sysv,gnu,both}],
+ [specify the linker hash style])],
+[case x"$withval" in
+ xsysv)
+ LINKER_HASH_STYLE=sysv
+ ;;
+ xgnu)
+ LINKER_HASH_STYLE=gnu
+ ;;
+ xboth)
+ LINKER_HASH_STYLE=both
+ ;;
+ *)
+ AC_MSG_ERROR([$withval is an invalid option to --with-linker-hash-style])
+ ;;
+ esac],
+[LINKER_HASH_STYLE=''])
+if test x"${LINKER_HASH_STYLE}" != x; then
+ AC_DEFINE_UNQUOTED(LINKER_HASH_STYLE, "$LINKER_HASH_STYLE",
+ [The linker hash style])
+fi
+
# Configure the subdirectories
# AC_CONFIG_SUBDIRS($subdirs)
Index: gcc-4_5-branch/gcc/doc/install.texi
===================================================================
--- gcc-4_5-branch.orig/gcc/doc/install.texi 2011-12-03 13:15:09.000000000 -0800
+++ gcc-4_5-branch/gcc/doc/install.texi 2011-12-03 13:41:04.499530358 -0800
@@ -1630,6 +1630,11 @@
support @option{--build-id} option, a warning is issued and the
@option{--enable-linker-build-id} option is ignored. The default is off.
+@item --with-linker-hash-style=@var{choice}
+Tells GCC to pass @option{--hash-style=@var{choice}} option to the
+linker for all final links. @var{choice} can be one of
+@samp{sysv}, @samp{gnu}, and @samp{both} where @samp{sysv} is the default.
+
@item --enable-gnu-unique-object
@itemx --disable-gnu-unique-object
Tells GCC to use the gnu_unique_object relocation for C++ template
Index: gcc-4_5-branch/gcc/gcc.c
===================================================================
--- gcc-4_5-branch.orig/gcc/gcc.c 2011-12-03 13:41:00.000000000 -0800
+++ gcc-4_5-branch/gcc/gcc.c 2011-12-03 13:41:04.499530358 -0800
@@ -1917,7 +1917,8 @@
}
#endif
-#if defined LINK_EH_SPEC || defined LINK_BUILDID_SPEC
+#if defined LINK_EH_SPEC || defined LINK_BUILDID_SPEC || \
+ defined LINKER_HASH_STYLE
# ifdef LINK_BUILDID_SPEC
/* Prepend LINK_BUILDID_SPEC to whatever link_spec we had before. */
obstack_grow (&obstack, LINK_BUILDID_SPEC, sizeof(LINK_BUILDID_SPEC) - 1);
@@ -1926,6 +1927,16 @@
/* Prepend LINK_EH_SPEC to whatever link_spec we had before. */
obstack_grow (&obstack, LINK_EH_SPEC, sizeof(LINK_EH_SPEC) - 1);
# endif
+# ifdef LINKER_HASH_STYLE
+ /* Prepend --hash-style=LINKER_HASH_STYLE to whatever link_spec we had
+ before. */
+ {
+ static const char hash_style[] = "--hash-style=";
+ obstack_grow (&obstack, hash_style, sizeof(hash_style) - 1);
+ obstack_grow (&obstack, LINKER_HASH_STYLE, sizeof(LINKER_HASH_STYLE) - 1);
+ obstack_1grow (&obstack, ' ');
+ }
+# endif
obstack_grow0 (&obstack, link_spec, strlen (link_spec));
link_spec = XOBFINISH (&obstack, const char *);
#endif
toolchain-layer/recipes-devtools/gcc/gcc-4.5/gcc_revert_base_version_to_4.5.0.patch
-9
View File
@@ -1,9 +0,0 @@
the svn patch changed the BASE-VER to 4.5.1, bring it back to 4.5.0
- Nitin A Kamble nitin.a.kamble@intel.com
- 2010/07/20
--- gcc-4.5.0/gcc/BASE-VER 2010-07-20 00:57:37.000000000 -0700
+++ gcc-4.5.0.new/gcc/BASE-VER 2010-07-20 01:06:17.000000000 -0700
@@ -1 +1 @@
-4.5.1
+4.5.0
toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-emit-__cxa_end_cleanup-in-text.patch
-40
View File
@@ -1,40 +0,0 @@
2010-06-07 Khem Raj <raj.khem@gmail.com>
* libsupc++/eh_arm.cc (__cxa_end_cleanup): Use .pushsection/.popsection
to emit inline assembly into .text section.
Index: gcc-4.5/libstdc++-v3/libsupc++/eh_arm.cc
===================================================================
--- gcc-4.5.orig/libstdc++-v3/libsupc++/eh_arm.cc 2010-06-04 23:20:18.000000000 -0700
+++ gcc-4.5/libstdc++-v3/libsupc++/eh_arm.cc 2010-06-08 11:27:34.247541722 -0700
@@ -157,22 +157,26 @@ __gnu_end_cleanup(void)
// Assembly wrapper to call __gnu_end_cleanup without clobbering r1-r3.
// Also push r4 to preserve stack alignment.
#ifdef __thumb__
-asm (".global __cxa_end_cleanup\n"
+asm (" .pushsection .text.__cxa_end_cleanup\n"
+" .global __cxa_end_cleanup\n"
" .type __cxa_end_cleanup, \"function\"\n"
" .thumb_func\n"
"__cxa_end_cleanup:\n"
" push\t{r1, r2, r3, r4}\n"
" bl\t__gnu_end_cleanup\n"
" pop\t{r1, r2, r3, r4}\n"
-" bl\t_Unwind_Resume @ Never returns\n");
+" bl\t_Unwind_Resume @ Never returns\n"
+" .popsection\n");
#else
-asm (".global __cxa_end_cleanup\n"
+asm (" .pushsection .text.__cxa_end_cleanup\n"
+" .global __cxa_end_cleanup\n"
" .type __cxa_end_cleanup, \"function\"\n"
"__cxa_end_cleanup:\n"
" stmfd\tsp!, {r1, r2, r3, r4}\n"
" bl\t__gnu_end_cleanup\n"
" ldmfd\tsp!, {r1, r2, r3, r4}\n"
-" bl\t_Unwind_Resume @ Never returns\n");
+" bl\t_Unwind_Resume @ Never returns\n"
+" .popsection\n");
#endif
#endif
toolchain-layer/recipes-devtools/gcc/gcc-4.5/libstdc++-pic.dpatch
-71
View File
@@ -1,71 +0,0 @@
#! /bin/sh -e
# DP: Build and install libstdc++_pic.a library.
dir=
if [ $# -eq 3 -a "$2" = '-d' ]; then
pdir="-d $3"
dir="$3/"
elif [ $# -ne 1 ]; then
echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
exit 1
fi
case "$1" in
-patch)
patch $pdir -f --no-backup-if-mismatch -p0 < $0
;;
-unpatch)
patch $pdir -f --no-backup-if-mismatch -R -p0 < $0
;;
*)
echo >&2 "`basename $0`: script expects -patch|-unpatch as argument"
exit 1
esac
exit 0
diff -ur libstdc++-v3/src/Makefile.am libstdc++-v3/src/Makefile.am
--- libstdc++-v3/src/Makefile.am~ 2004-04-16 21:04:05.000000000 +0200
+++ libstdc++-v3/src/Makefile.am 2004-07-03 20:22:43.000000000 +0200
@@ -210,6 +210,10 @@
$(OPT_LDFLAGS) $(SECTION_LDFLAGS) $(AM_CXXFLAGS) $(LDFLAGS) -o $@
+install-exec-local:
+ $(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o || touch libstdc++_pic.a
+ $(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir)
+
# Added bits to build debug library.
if GLIBCXX_BUILD_DEBUG
all-local: build_debug
diff -ur libstdc++-v3/src/Makefile.in libstdc++-v3/src/Makefile.in
--- libstdc++-v3/src/Makefile.in 2004-07-03 06:41:13.000000000 +0200
+++ libstdc++-v3/src/Makefile.in 2004-07-03 20:25:05.000000000 +0200
@@ -611,7 +611,7 @@
install-data-am: install-data-local
-install-exec-am: install-toolexeclibLTLIBRARIES
+install-exec-am: install-toolexeclibLTLIBRARIES install-exec-local
install-info: install-info-am
@@ -644,6 +644,7 @@
distclean-libtool distclean-tags distdir dvi dvi-am html \
html-am info info-am install install-am install-data \
install-data-am install-data-local install-exec \
+ install-exec-local \
install-exec-am install-info install-info-am install-man \
install-strip install-toolexeclibLTLIBRARIES installcheck \
installcheck-am installdirs maintainer-clean \
@@ -729,6 +730,11 @@
install_debug:
(cd ${debugdir} && $(MAKE) \
toolexeclibdir=$(glibcxx_toolexeclibdir)/debug install)
+
+install-exec-local:
+ $(AR) cru libstdc++_pic.a .libs/*.o $(top_builddir)/libsupc++/*.o || touch libstdc++_pic.a
+ $(INSTALL_DATA) libstdc++_pic.a $(DESTDIR)$(toolexeclibdir)
+
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99297.patch
-207
View File
@@ -1,207 +0,0 @@
2010-06-28 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
gcc/
* doc/invoke.texi (-Wno-poison-system-directories): Document.
* gcc.c (LINK_COMMAND_SPEC): Pass --no-poison-system-directories
if -Wno-poison-system-directories and --error-poison-system-directories
if -Werror=poison-system-directories to linker.
* incpath.c: Include flags.h. Include toplev.h.
(merge_include_chains): If ENABLE_POISON_SYSTEM_DIRECTORIES defined
and flag_poison_system_directories is true, warn for use of
/usr/include, /usr/local/include or /usr/X11R6/include.
* Makefile.in (incpath.o): Depend on $(FLAGS_H) and toplev.h.
* common.opt (--Wno-poison-system-directories): New.
* configure.ac (--enable-poison-system-directories): New option.
* configure: Regenerate.
* config.in: Regenerate.
Index: gcc-4.5/gcc/Makefile.in
===================================================================
--- gcc-4.5.orig/gcc/Makefile.in 2010-09-23 16:44:12.000000000 -0700
+++ gcc-4.5/gcc/Makefile.in 2010-09-23 16:46:33.552416860 -0700
@@ -1969,7 +1969,7 @@ gcc.srcextra: gengtype-lex.c
incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \
intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \
- $(MACHMODE_H)
+ $(MACHMODE_H) $(FLAGS_H) toplev.h
c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \
$(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \
Index: gcc-4.5/gcc/common.opt
===================================================================
--- gcc-4.5.orig/gcc/common.opt 2010-07-11 16:14:47.000000000 -0700
+++ gcc-4.5/gcc/common.opt 2010-09-23 16:46:33.556418045 -0700
@@ -152,6 +152,10 @@ Wpadded
Common Var(warn_padded) Warning
Warn when padding is required to align structure members
+Wpoison-system-directories
+Common Var(flag_poison_system_directories) Init(1)
+Warn for -I and -L options using system directories if cross compiling
+
Wshadow
Common Var(warn_shadow) Warning
Warn when one local variable shadows another
Index: gcc-4.5/gcc/config.in
===================================================================
--- gcc-4.5.orig/gcc/config.in 2010-07-11 16:14:46.000000000 -0700
+++ gcc-4.5/gcc/config.in 2010-09-23 16:46:33.556418045 -0700
@@ -132,6 +132,12 @@
#endif
+/* Define to warn for use of native system header directories */
+#ifndef USED_FOR_TARGET
+#undef ENABLE_POISON_SYSTEM_DIRECTORIES
+#endif
+
+
/* Define if you want all operations on RTL (the basic data structure of the
optimizer and back end) to be checked for dynamic type safety at runtime.
This is quite expensive. */
Index: gcc-4.5/gcc/configure
===================================================================
--- gcc-4.5.orig/gcc/configure 2010-09-23 16:44:11.000000000 -0700
+++ gcc-4.5/gcc/configure 2010-09-23 16:46:33.572415719 -0700
@@ -913,6 +913,7 @@ with_system_zlib
enable_maintainer_mode
enable_version_specific_runtime_libs
with_slibdir
+enable_poison_system_directories
enable_plugin
'
ac_precious_vars='build_alias
@@ -1620,6 +1621,8 @@ Optional Features:
--enable-version-specific-runtime-libs
specify that runtime libraries should be
installed in a compiler-specific directory
+ --enable-poison-system-directories
+ warn for use of native system header directories
--enable-plugin enable plugin support
Optional Packages:
@@ -25345,6 +25348,19 @@ fi
+# Check whether --enable-poison-system-directories was given.
+if test "${enable_poison_system_directories+set}" = set; then :
+ enableval=$enable_poison_system_directories;
+else
+ enable_poison_system_directories=no
+fi
+
+if test "x${enable_poison_system_directories}" = "xyes"; then
+
+$as_echo "#define ENABLE_POISON_SYSTEM_DIRECTORIES 1" >>confdefs.h
+
+fi
+
# Substitute configuration variables
Index: gcc-4.5/gcc/configure.ac
===================================================================
--- gcc-4.5.orig/gcc/configure.ac 2010-09-23 16:44:11.000000000 -0700
+++ gcc-4.5/gcc/configure.ac 2010-09-23 16:46:33.576417624 -0700
@@ -4439,6 +4439,16 @@ else
fi)
AC_SUBST(slibdir)
+AC_ARG_ENABLE([poison-system-directories],
+ AS_HELP_STRING([--enable-poison-system-directories],
+ [warn for use of native system header directories]),,
+ [enable_poison_system_directories=no])
+if test "x${enable_poison_system_directories}" = "xyes"; then
+ AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES],
+ [1],
+ [Define to warn for use of native system header directories])
+fi
+
# Substitute configuration variables
AC_SUBST(subdirs)
AC_SUBST(srcdir)
Index: gcc-4.5/gcc/doc/invoke.texi
===================================================================
--- gcc-4.5.orig/gcc/doc/invoke.texi 2010-09-23 15:33:28.000000000 -0700
+++ gcc-4.5/gcc/doc/invoke.texi 2010-09-23 16:46:33.584416934 -0700
@@ -252,6 +252,7 @@ Objective-C and Objective-C++ Dialects}.
-Woverlength-strings -Wpacked -Wpacked-bitfield-compat -Wpadded @gol
-Wparentheses -Wpedantic-ms-format -Wno-pedantic-ms-format @gol
-Wpointer-arith -Wno-pointer-to-int-cast @gol
+-Wno-poison-system-directories @gol
-Wredundant-decls @gol
-Wreturn-type -Wsequence-point -Wshadow @gol
-Wsign-compare -Wsign-conversion -Wstack-protector @gol
@@ -3603,6 +3604,14 @@ code. However, note that using @option{
option will @emph{not} warn about unknown pragmas in system
headers---for that, @option{-Wunknown-pragmas} must also be used.
+@item -Wno-poison-system-directories
+@opindex Wno-poison-system-directories
+Do not warn for @option{-I} or @option{-L} options using system
+directories such as @file{/usr/include} when cross compiling. This
+option is intended for use in chroot environments when such
+directories contain the correct headers and libraries for the target
+system rather than the host.
+
@item -Wfloat-equal
@opindex Wfloat-equal
@opindex Wno-float-equal
Index: gcc-4.5/gcc/gcc.c
===================================================================
--- gcc-4.5.orig/gcc/gcc.c 2010-07-11 16:14:46.000000000 -0700
+++ gcc-4.5/gcc/gcc.c 2010-09-23 16:46:33.588417920 -0700
@@ -792,6 +792,8 @@ proper position among the other output f
%{flto} %{fwhopr} %l " LINK_PIE_SPEC \
"%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\
%{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\
+ %{Wno-poison-system-directories:--no-poison-system-directories}\
+ %{Werror=poison-system-directories:--error-poison-system-directories}\
%{static:} %{L*} %(mfwrap) %(link_libgcc) %o\
%{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)\
%{fprofile-arcs|fprofile-generate*|coverage:-lgcov}\
Index: gcc-4.5/gcc/incpath.c
===================================================================
--- gcc-4.5.orig/gcc/incpath.c 2010-07-11 16:14:44.000000000 -0700
+++ gcc-4.5/gcc/incpath.c 2010-09-23 16:46:33.588417920 -0700
@@ -30,6 +30,8 @@
#include "intl.h"
#include "incpath.h"
#include "cppdefault.h"
+#include "flags.h"
+#include "toplev.h"
/* Microsoft Windows does not natively support inodes.
VMS has non-numeric inodes. */
@@ -353,6 +355,24 @@ merge_include_chains (const char *sysroo
}
fprintf (stderr, _("End of search list.\n"));
}
+
+#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES
+ if (flag_poison_system_directories)
+ {
+ struct cpp_dir *p;
+
+ for (p = heads[QUOTE]; p; p = p->next)
+ {
+ if ((!strncmp (p->name, "/usr/include", 12))
+ || (!strncmp (p->name, "/usr/local/include", 18))
+ || (!strncmp (p->name, "/usr/X11R6/include", 18)))
+ warning (OPT_Wpoison_system_directories,
+ "include location \"%s\" is unsafe for "
+ "cross-compilation",
+ p->name);
+ }
+ }
+#endif
}
/* Use given -I paths for #include "..." but not #include <...>, and
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99298.patch
-26654
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toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99299.patch
-62
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@@ -1,62 +0,0 @@
2010-07-07 Sandra Loosemore <sandra@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-03-08 Paul Brook <paul@codesourcery.com>
gcc/
* doc/invoke.texi: Document ARM -mcpu=cortex-m4.
* config/arm/arm.c (all_architectures): Change v7e-m default to
cortexm4.
* config/arm/arm-cores.def: Add cortex-m4.
* config/arm/arm-tune.md: Regenerate.
=== modified file 'gcc/config/arm/arm-cores.def'
--- old/gcc/config/arm/arm-cores.def 2009-11-20 17:37:30 +0000
+++ new/gcc/config/arm/arm-cores.def 2010-07-29 15:53:39 +0000
@@ -123,6 +123,7 @@
ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e)
ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e)
ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e)
+ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e)
ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e)
ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e)
ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, 9e)
=== modified file 'gcc/config/arm/arm-tune.md'
--- old/gcc/config/arm/arm-tune.md 2009-11-20 17:37:30 +0000
+++ new/gcc/config/arm/arm-tune.md 2010-07-29 15:53:39 +0000
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from arm-cores.def
(define_attr "tune"
- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1,cortexm0"
+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm4,cortexm3,cortexm1,cortexm0"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-04-02 07:32:00 +0000
+++ new/gcc/config/arm/arm.c 2010-07-29 15:53:39 +0000
@@ -782,7 +782,7 @@
{"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
{"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
{"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
- {"armv7e-m", cortexm3, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL},
+ {"armv7e-m", cortexm4, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL},
{"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
{"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
{"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
=== modified file 'gcc/doc/invoke.texi'
--- old/gcc/doc/invoke.texi 2010-07-29 14:59:35 +0000
+++ new/gcc/doc/invoke.texi 2010-07-29 15:53:39 +0000
@@ -9826,7 +9826,7 @@
@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
@samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9},
-@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m3},
+@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3},
@samp{cortex-m1},
@samp{cortex-m0},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99300.patch
-3094
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toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99301.patch
-674
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@@ -1,674 +0,0 @@
2010-07-02 Daniel Jacobowitz <dan@codesourcery.com>
Julian Brown <julian@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
gcc/
* config/arm/arm.c (arm_canonicalize_comparison): Canonicalize DImode
comparisons. Adjust to take both operands.
(arm_select_cc_mode): Handle DImode comparisons.
(arm_gen_compare_reg): Generate a scratch register for DImode
comparisons which require one. Use xor for Thumb equality checks.
(arm_const_double_by_immediates): New.
(arm_print_operand): Allow 'Q' and 'R' for constants.
(get_arm_condition_code): Handle new CC_CZmode and CC_NCVmode.
* config/arm/arm.h (CANONICALIZE_COMPARISON): Always use
arm_canonicalize_comparison.
* config/arm/arm-modes.def: Add CC_CZmode and CC_NCVmode.
* config/arm/arm-protos.h (arm_canonicalize_comparison): Update
prototype.
(arm_const_double_by_immediates): Declare.
* config/arm/constraints.md (Di): New constraint.
* config/arm/predicates.md (arm_immediate_di_operand)
(arm_di_operand, cmpdi_operand): New.
* config/arm/arm.md (cbranchdi4): Handle non-Cirrus also.
(*arm_cmpdi_insn, *arm_cmpdi_unsigned)
(*arm_cmpdi_zero, *thumb_cmpdi_zero): New insns.
(cstoredi4): Handle non-Cirrus also.
gcc/testsuite/
* gcc.c-torture/execute/20100416-1.c: New test case.
2010-07-08 Sandra Loosemore <sandra@codesourcery.com>
Backport from upstream (originally from Sourcery G++ 4.4):
2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
gcc/
=== modified file 'gcc/config/arm/arm-modes.def'
Index: gcc-4.5.3/gcc/config/arm/arm-modes.def
===================================================================
--- gcc-4.5.3.orig/gcc/config/arm/arm-modes.def
+++ gcc-4.5.3/gcc/config/arm/arm-modes.def
@@ -35,10 +35,16 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_form
CC_NOOVmode should be used with SImode integer equalities.
CC_Zmode should be used if only the Z flag is set correctly
CC_Nmode should be used if only the N (sign) flag is set correctly
+ CC_CZmode should be used if only the C and Z flags are correct
+ (used for DImode unsigned comparisons).
+ CC_NCVmode should be used if only the N, C, and V flags are correct
+ (used for DImode signed comparisons).
CCmode should be used otherwise. */
CC_MODE (CC_NOOV);
CC_MODE (CC_Z);
+CC_MODE (CC_CZ);
+CC_MODE (CC_NCV);
CC_MODE (CC_SWP);
CC_MODE (CCFP);
CC_MODE (CCFPE);
Index: gcc-4.5.3/gcc/config/arm/arm-protos.h
===================================================================
--- gcc-4.5.3.orig/gcc/config/arm/arm-protos.h
+++ gcc-4.5.3/gcc/config/arm/arm-protos.h
@@ -49,8 +49,7 @@ extern int arm_hard_regno_mode_ok (unsig
extern int const_ok_for_arm (HOST_WIDE_INT);
extern int arm_split_constant (RTX_CODE, enum machine_mode, rtx,
HOST_WIDE_INT, rtx, rtx, int);
-extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, enum machine_mode,
- rtx *);
+extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *, rtx *);
extern int legitimate_pic_operand_p (rtx);
extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
extern rtx legitimize_tls_address (rtx, rtx);
@@ -116,6 +115,7 @@ extern void arm_reload_in_hi (rtx *);
extern void arm_reload_out_hi (rtx *);
extern int arm_const_double_inline_cost (rtx);
extern bool arm_const_double_by_parts (rtx);
+extern bool arm_const_double_by_immediates (rtx);
extern const char *fp_immediate_constant (rtx);
extern void arm_emit_call_insn (rtx, rtx);
extern const char *output_call (rtx *);
Index: gcc-4.5.3/gcc/config/arm/arm.c
===================================================================
--- gcc-4.5.3.orig/gcc/config/arm/arm.c
+++ gcc-4.5.3/gcc/config/arm/arm.c
@@ -3191,13 +3191,82 @@ arm_gen_constant (enum rtx_code code, en
immediate value easier to load. */
enum rtx_code
-arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
- rtx * op1)
+arm_canonicalize_comparison (enum rtx_code code, rtx *op0, rtx *op1)
{
- unsigned HOST_WIDE_INT i = INTVAL (*op1);
- unsigned HOST_WIDE_INT maxval;
+ enum machine_mode mode;
+ unsigned HOST_WIDE_INT i, maxval;
+
+ mode = GET_MODE (*op0);
+ if (mode == VOIDmode)
+ mode = GET_MODE (*op1);
+
maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
+ /* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode
+ we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either
+ reversed or (for constant OP1) adjusted to GE/LT. Similarly
+ for GTU/LEU in Thumb mode. */
+ if (mode == DImode)
+ {
+ rtx tem;
+
+ /* To keep things simple, always use the Cirrus cfcmp64 if it is
+ available. */
+ if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
+ return code;
+
+ if (code == GT || code == LE
+ || (!TARGET_ARM && (code == GTU || code == LEU)))
+ {
+ /* Missing comparison. First try to use an available
+ comparison. */
+ if (GET_CODE (*op1) == CONST_INT)
+ {
+ i = INTVAL (*op1);
+ switch (code)
+ {
+ case GT:
+ case LE:
+ if (i != maxval
+ && arm_const_double_by_immediates (GEN_INT (i + 1)))
+ {
+ *op1 = GEN_INT (i + 1);
+ return code == GT ? GE : LT;
+ }
+ break;
+ case GTU:
+ case LEU:
+ if (i != ~((unsigned HOST_WIDE_INT) 0)
+ && arm_const_double_by_immediates (GEN_INT (i + 1)))
+ {
+ *op1 = GEN_INT (i + 1);
+ return code == GTU ? GEU : LTU;
+ }
+ break;
+ default:
+ gcc_unreachable ();
+ }
+ }
+
+ /* If that did not work, reverse the condition. */
+ tem = *op0;
+ *op0 = *op1;
+ *op1 = tem;
+ return swap_condition (code);
+ }
+
+ return code;
+ }
+
+ /* Comparisons smaller than DImode. Only adjust comparisons against
+ an out-of-range constant. */
+ if (GET_CODE (*op1) != CONST_INT
+ || const_ok_for_arm (INTVAL (*op1))
+ || const_ok_for_arm (- INTVAL (*op1)))
+ return code;
+
+ i = INTVAL (*op1);
+
switch (code)
{
case EQ:
@@ -9913,6 +9982,55 @@ arm_select_cc_mode (enum rtx_code op, rt
&& (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
return CC_Cmode;
+ if (GET_MODE (x) == DImode || GET_MODE (y) == DImode)
+ {
+ /* To keep things simple, always use the Cirrus cfcmp64 if it is
+ available. */
+ if (TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK)
+ return CCmode;
+
+ switch (op)
+ {
+ case EQ:
+ case NE:
+ /* A DImode comparison against zero can be implemented by
+ or'ing the two halves together. */
+ if (y == const0_rtx)
+ return CC_Zmode;
+
+ /* We can do an equality test in three Thumb instructions. */
+ if (!TARGET_ARM)
+ return CC_Zmode;
+
+ /* FALLTHROUGH */
+
+ case LTU:
+ case LEU:
+ case GTU:
+ case GEU:
+ /* DImode unsigned comparisons can be implemented by cmp +
+ cmpeq without a scratch register. Not worth doing in
+ Thumb-2. */
+ if (TARGET_ARM)
+ return CC_CZmode;
+
+ /* FALLTHROUGH */
+
+ case LT:
+ case LE:
+ case GT:
+ case GE:
+ /* DImode signed and unsigned comparisons can be implemented
+ by cmp + sbcs with a scratch register, but that does not
+ set the Z flag - we must reverse GT/LE/GTU/LEU. */
+ gcc_assert (op != EQ && op != NE);
+ return CC_NCVmode;
+
+ default:
+ gcc_unreachable ();
+ }
+ }
+
return CCmode;
}
@@ -9922,10 +10040,39 @@ arm_select_cc_mode (enum rtx_code op, rt
rtx
arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
{
- enum machine_mode mode = SELECT_CC_MODE (code, x, y);
- rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
+ enum machine_mode mode;
+ rtx cc_reg;
+ int dimode_comparison = GET_MODE (x) == DImode || GET_MODE (y) == DImode;
- emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
+ /* We might have X as a constant, Y as a register because of the predicates
+ used for cmpdi. If so, force X to a register here. */
+ if (dimode_comparison && !REG_P (x))
+ x = force_reg (DImode, x);
+
+ mode = SELECT_CC_MODE (code, x, y);
+ cc_reg = gen_rtx_REG (mode, CC_REGNUM);
+
+ if (dimode_comparison
+ && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)
+ && mode != CC_CZmode)
+ {
+ rtx clobber, set;
+
+ /* To compare two non-zero values for equality, XOR them and
+ then compare against zero. Not used for ARM mode; there
+ CC_CZmode is cheaper. */
+ if (mode == CC_Zmode && y != const0_rtx)
+ {
+ x = expand_binop (DImode, xor_optab, x, y, NULL_RTX, 0, OPTAB_WIDEN);
+ y = const0_rtx;
+ }
+ /* A scratch register is required. */
+ clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode));
+ set = gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_COMPARE (mode, x, y));
+ emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
+ }
+ else
+ emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
return cc_reg;
}
@@ -11254,6 +11401,34 @@ arm_const_double_by_parts (rtx val)
return false;
}
+/* Return true if it is possible to inline both the high and low parts
+ of a 64-bit constant into 32-bit data processing instructions. */
+bool
+arm_const_double_by_immediates (rtx val)
+{
+ enum machine_mode mode = GET_MODE (val);
+ rtx part;
+
+ if (mode == VOIDmode)
+ mode = DImode;
+
+ part = gen_highpart_mode (SImode, mode, val);
+
+ gcc_assert (GET_CODE (part) == CONST_INT);
+
+ if (!const_ok_for_arm (INTVAL (part)))
+ return false;
+
+ part = gen_lowpart (SImode, val);
+
+ gcc_assert (GET_CODE (part) == CONST_INT);
+
+ if (!const_ok_for_arm (INTVAL (part)))
+ return false;
+
+ return true;
+}
+
/* Scan INSN and note any of its operands that need fixing.
If DO_PUSHES is false we do not actually push any of the fixups
needed. The function returns TRUE if any fixups were needed/pushed.
@@ -15150,8 +15325,18 @@ arm_print_operand (FILE *stream, rtx x,
the value being loaded is big-wordian or little-wordian. The
order of the two register loads can matter however, if the address
of the memory location is actually held in one of the registers
- being overwritten by the load. */
+ being overwritten by the load.
+
+ The 'Q' and 'R' constraints are also available for 64-bit
+ constants. */
case 'Q':
+ if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+ {
+ rtx part = gen_lowpart (SImode, x);
+ fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
+ return;
+ }
+
if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
{
output_operand_lossage ("invalid operand for code '%c'", code);
@@ -15162,6 +15347,18 @@ arm_print_operand (FILE *stream, rtx x,
return;
case 'R':
+ if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+ {
+ enum machine_mode mode = GET_MODE (x);
+ rtx part;
+
+ if (mode == VOIDmode)
+ mode = DImode;
+ part = gen_highpart_mode (SImode, mode, x);
+ fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, INTVAL (part));
+ return;
+ }
+
if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
{
output_operand_lossage ("invalid operand for code '%c'", code);
@@ -15854,6 +16051,28 @@ get_arm_condition_code (rtx comparison)
default: gcc_unreachable ();
}
+ case CC_CZmode:
+ switch (comp_code)
+ {
+ case NE: return ARM_NE;
+ case EQ: return ARM_EQ;
+ case GEU: return ARM_CS;
+ case GTU: return ARM_HI;
+ case LEU: return ARM_LS;
+ case LTU: return ARM_CC;
+ default: gcc_unreachable ();
+ }
+
+ case CC_NCVmode:
+ switch (comp_code)
+ {
+ case GE: return ARM_GE;
+ case LT: return ARM_LT;
+ case GEU: return ARM_CS;
+ case LTU: return ARM_CC;
+ default: gcc_unreachable ();
+ }
+
case CCmode:
switch (comp_code)
{
Index: gcc-4.5.3/gcc/config/arm/arm.h
===================================================================
--- gcc-4.5.3.orig/gcc/config/arm/arm.h
+++ gcc-4.5.3/gcc/config/arm/arm.h
@@ -2253,19 +2253,7 @@ extern int making_const_table;
: reverse_condition (code))
#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
- do \
- { \
- if (GET_CODE (OP1) == CONST_INT \
- && ! (const_ok_for_arm (INTVAL (OP1)) \
- || (const_ok_for_arm (- INTVAL (OP1))))) \
- { \
- rtx const_op = OP1; \
- CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \
- &const_op); \
- OP1 = const_op; \
- } \
- } \
- while (0)
+ (CODE) = arm_canonicalize_comparison (CODE, &(OP0), &(OP1))
/* The arm5 clz instruction returns 32. */
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
Index: gcc-4.5.3/gcc/config/arm/arm.md
===================================================================
--- gcc-4.5.3.orig/gcc/config/arm/arm.md
+++ gcc-4.5.3/gcc/config/arm/arm.md
@@ -6718,17 +6718,45 @@
operands[3])); DONE;"
)
-;; this uses the Cirrus DI compare instruction
(define_expand "cbranchdi4"
[(set (pc) (if_then_else
(match_operator 0 "arm_comparison_operator"
- [(match_operand:DI 1 "cirrus_fp_register" "")
- (match_operand:DI 2 "cirrus_fp_register" "")])
+ [(match_operand:DI 1 "cmpdi_operand" "")
+ (match_operand:DI 2 "cmpdi_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
- operands[3])); DONE;"
+ "TARGET_32BIT"
+ "{
+ rtx swap = NULL_RTX;
+ enum rtx_code code = GET_CODE (operands[0]);
+
+ /* We should not have two constants. */
+ gcc_assert (GET_MODE (operands[1]) == DImode
+ || GET_MODE (operands[2]) == DImode);
+
+ /* Flip unimplemented DImode comparisons to a form that
+ arm_gen_compare_reg can handle. */
+ switch (code)
+ {
+ case GT:
+ swap = gen_rtx_LT (VOIDmode, operands[2], operands[1]); break;
+ case LE:
+ swap = gen_rtx_GE (VOIDmode, operands[2], operands[1]); break;
+ case GTU:
+ swap = gen_rtx_LTU (VOIDmode, operands[2], operands[1]); break;
+ case LEU:
+ swap = gen_rtx_GEU (VOIDmode, operands[2], operands[1]); break;
+ default:
+ break;
+ }
+ if (swap)
+ emit_jump_insn (gen_cbranch_cc (swap, operands[2], operands[1],
+ operands[3]));
+ else
+ emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
+ }"
)
(define_insn "*cbranchsi4_insn"
@@ -7880,6 +7908,52 @@
(const_string "alu_shift_reg")))]
)
+;; DImode comparisons. The generic code generates branches that
+;; if-conversion can not reduce to a conditional compare, so we do
+;; that directly.
+
+(define_insn "*arm_cmpdi_insn"
+ [(set (reg:CC_NCV CC_REGNUM)
+ (compare:CC_NCV (match_operand:DI 0 "s_register_operand" "r")
+ (match_operand:DI 1 "arm_di_operand" "rDi")))
+ (clobber (match_scratch:SI 2 "=r"))]
+ "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)"
+ "cmp\\t%Q0, %Q1\;sbcs\\t%2, %R0, %R1"
+ [(set_attr "conds" "set")
+ (set_attr "length" "8")]
+)
+
+(define_insn "*arm_cmpdi_unsigned"
+ [(set (reg:CC_CZ CC_REGNUM)
+ (compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r")
+ (match_operand:DI 1 "arm_di_operand" "rDi")))]
+ "TARGET_ARM"
+ "cmp%?\\t%R0, %R1\;cmpeq\\t%Q0, %Q1"
+ [(set_attr "conds" "set")
+ (set_attr "length" "8")]
+)
+
+(define_insn "*arm_cmpdi_zero"
+ [(set (reg:CC_Z CC_REGNUM)
+ (compare:CC_Z (match_operand:DI 0 "s_register_operand" "r")
+ (const_int 0)))
+ (clobber (match_scratch:SI 1 "=r"))]
+ "TARGET_32BIT"
+ "orr%.\\t%1, %Q0, %R0"
+ [(set_attr "conds" "set")]
+)
+
+(define_insn "*thumb_cmpdi_zero"
+ [(set (reg:CC_Z CC_REGNUM)
+ (compare:CC_Z (match_operand:DI 0 "s_register_operand" "l")
+ (const_int 0)))
+ (clobber (match_scratch:SI 1 "=l"))]
+ "TARGET_THUMB1"
+ "orr\\t%1, %Q0, %R0"
+ [(set_attr "conds" "set")
+ (set_attr "length" "2")]
+)
+
;; Cirrus SF compare instruction
(define_insn "*cirrus_cmpsf"
[(set (reg:CCFP CC_REGNUM)
@@ -8183,17 +8257,44 @@
operands[2], operands[3])); DONE;"
)
-;; this uses the Cirrus DI compare instruction
(define_expand "cstoredi4"
[(set (match_operand:SI 0 "s_register_operand" "")
(match_operator:SI 1 "arm_comparison_operator"
- [(match_operand:DI 2 "cirrus_fp_register" "")
- (match_operand:DI 3 "cirrus_fp_register" "")]))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
- "emit_insn (gen_cstore_cc (operands[0], operands[1],
- operands[2], operands[3])); DONE;"
-)
+ [(match_operand:DI 2 "cmpdi_operand" "")
+ (match_operand:DI 3 "cmpdi_operand" "")]))]
+ "TARGET_32BIT"
+ "{
+ rtx swap = NULL_RTX;
+ enum rtx_code code = GET_CODE (operands[1]);
+ /* We should not have two constants. */
+ gcc_assert (GET_MODE (operands[2]) == DImode
+ || GET_MODE (operands[3]) == DImode);
+
+ /* Flip unimplemented DImode comparisons to a form that
+ arm_gen_compare_reg can handle. */
+ switch (code)
+ {
+ case GT:
+ swap = gen_rtx_LT (VOIDmode, operands[3], operands[2]); break;
+ case LE:
+ swap = gen_rtx_GE (VOIDmode, operands[3], operands[2]); break;
+ case GTU:
+ swap = gen_rtx_LTU (VOIDmode, operands[3], operands[2]); break;
+ case LEU:
+ swap = gen_rtx_GEU (VOIDmode, operands[3], operands[2]); break;
+ default:
+ break;
+ }
+ if (swap)
+ emit_insn (gen_cstore_cc (operands[0], swap, operands[3],
+ operands[2]));
+ else
+ emit_insn (gen_cstore_cc (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
+ }"
+)
(define_expand "cstoresi_eq0_thumb1"
[(parallel
Index: gcc-4.5.3/gcc/config/arm/constraints.md
===================================================================
--- gcc-4.5.3.orig/gcc/config/arm/constraints.md
+++ gcc-4.5.3/gcc/config/arm/constraints.md
@@ -29,7 +29,7 @@
;; in Thumb-1 state: I, J, K, L, M, N, O
;; The following multi-letter normal constraints have been used:
-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy
+;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
;; in Thumb-1 state: Pa, Pb
;; in Thumb-2 state: Ps, Pt
@@ -191,6 +191,13 @@
(match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
&& !(optimize_size || arm_ld_sched)")))
+(define_constraint "Di"
+ "@internal
+ In ARM/Thumb-2 state a const_int or const_double where both the high
+ and low SImode words can be generated as immediates in 32-bit instructions."
+ (and (match_code "const_double,const_int")
+ (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
+
(define_constraint "Dn"
"@internal
In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
Index: gcc-4.5.3/gcc/config/arm/predicates.md
===================================================================
--- gcc-4.5.3.orig/gcc/config/arm/predicates.md
+++ gcc-4.5.3/gcc/config/arm/predicates.md
@@ -101,6 +101,12 @@
(and (match_code "const_int")
(match_test "const_ok_for_arm (INTVAL (op))")))
+;; A constant value which fits into two instructions, each taking
+;; an arithmetic constant operand for one of the words.
+(define_predicate "arm_immediate_di_operand"
+ (and (match_code "const_int,const_double")
+ (match_test "arm_const_double_by_immediates (op)")))
+
(define_predicate "arm_neg_immediate_operand"
(and (match_code "const_int")
(match_test "const_ok_for_arm (-INTVAL (op))")))
@@ -130,6 +136,10 @@
(ior (match_operand 0 "arm_rhs_operand")
(match_operand 0 "arm_not_immediate_operand")))
+(define_predicate "arm_di_operand"
+ (ior (match_operand 0 "s_register_operand")
+ (match_operand 0 "arm_immediate_di_operand")))
+
;; True if the operand is a memory reference which contains an
;; offsettable address.
(define_predicate "offsettable_memory_operand"
@@ -538,3 +548,12 @@
(and (match_code "const_int")
(match_test "INTVAL (op) >= 0 && INTVAL (op) <= 15")))
+;; Predicates for named expanders that overlap multiple ISAs.
+
+(define_predicate "cmpdi_operand"
+ (if_then_else (match_test "TARGET_HARD_FLOAT && TARGET_MAVERICK")
+ (and (match_test "TARGET_ARM")
+ (match_operand 0 "cirrus_fp_register"))
+ (and (match_test "TARGET_32BIT")
+ (match_operand 0 "arm_di_operand"))))
+
Index: gcc-4.5.3/gcc/testsuite/gcc.c-torture/execute/20100416-1.c
===================================================================
--- /dev/null
+++ gcc-4.5.3/gcc/testsuite/gcc.c-torture/execute/20100416-1.c
@@ -0,0 +1,40 @@
+void abort(void);
+
+int
+movegt(int x, int y, long long a)
+{
+ int i;
+ int ret = 0;
+ for (i = 0; i < y; i++)
+ {
+ if (a >= (long long) 0xf000000000000000LL)
+ ret = x;
+ else
+ ret = y;
+ }
+ return ret;
+}
+
+struct test
+{
+ long long val;
+ int ret;
+} tests[] = {
+ { 0xf000000000000000LL, -1 },
+ { 0xefffffffffffffffLL, 1 },
+ { 0xf000000000000001LL, -1 },
+ { 0x0000000000000000LL, -1 },
+ { 0x8000000000000000LL, 1 },
+};
+
+int
+main()
+{
+ int i;
+ for (i = 0; i < sizeof (tests) / sizeof (tests[0]); i++)
+ {
+ if (movegt (-1, 1, tests[i].val) != tests[i].ret)
+ abort ();
+ }
+ return 0;
+}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99302.patch
-244
View File
@@ -1,244 +0,0 @@
2010-07-09 Sandra Loosemore <sandra@codesourcery.com>
Backport from mainline (originally on Sourcery G++ 4.4):
2010-07-02 Julian Brown <julian@codesourcery.com>
Sandra Loosemore <sandra@codesourcery.com>
PR target/43703
gcc/
* config/arm/vec-common.md (add<mode>3, sub<mode>3, smin<mode>3)
(smax<mode>3): Disable for NEON float modes when
flag_unsafe_math_optimizations is false.
* config/arm/neon.md (*add<mode>3_neon, *sub<mode>3_neon)
(*mul<mode>3_neon)
(mul<mode>3add<mode>_neon, mul<mode>3neg<mode>add<mode>_neon)
(reduc_splus_<mode>, reduc_smin_<mode>, reduc_smax_<mode>): Disable
for NEON float modes when flag_unsafe_math_optimizations is false.
(quad_halves_<code>v4sf): Only enable if flag_unsafe_math_optimizations
is true.
* doc/invoke.texi (ARM Options): Add note about floating point
vectorization requiring -funsafe-math-optimizations.
gcc/testsuite/
* gcc.dg/vect/vect.exp: Add -ffast-math for NEON.
* gcc.dg/vect/vect-reduc-6.c: Add XFAIL for NEON.
2010-07-08 Sandra Loosemore <sandra@codesourcery.com>
Backport from upstream (originally from Sourcery G++ 4.4):
=== modified file 'gcc/config/arm/neon.md'
--- old/gcc/config/arm/neon.md 2010-07-29 15:59:12 +0000
+++ new/gcc/config/arm/neon.md 2010-07-29 17:03:20 +0000
@@ -819,7 +819,7 @@
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(plus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
(match_operand:VDQ 2 "s_register_operand" "w")))]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
@@ -853,7 +853,7 @@
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(minus:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
(match_operand:VDQ 2 "s_register_operand" "w")))]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
@@ -888,7 +888,7 @@
[(set (match_operand:VDQ 0 "s_register_operand" "=w")
(mult:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
(match_operand:VDQ 2 "s_register_operand" "w")))]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vmul.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
@@ -910,7 +910,7 @@
(plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
(match_operand:VDQ 3 "s_register_operand" "w"))
(match_operand:VDQ 1 "s_register_operand" "0")))]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
[(set (attr "neon_type")
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
@@ -932,7 +932,7 @@
(minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0")
(mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
(match_operand:VDQ 3 "s_register_operand" "w"))))]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
[(set (attr "neon_type")
(if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
@@ -1361,7 +1361,7 @@
(parallel [(const_int 0) (const_int 1)]))
(vec_select:V2SF (match_dup 1)
(parallel [(const_int 2) (const_int 3)]))))]
- "TARGET_NEON"
+ "TARGET_NEON && flag_unsafe_math_optimizations"
"<VQH_mnem>.f32\t%P0, %e1, %f1"
[(set_attr "vqh_mnem" "<VQH_mnem>")
(set (attr "neon_type")
@@ -1496,7 +1496,7 @@
(define_expand "reduc_splus_<mode>"
[(match_operand:VD 0 "s_register_operand" "")
(match_operand:VD 1 "s_register_operand" "")]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
&gen_neon_vpadd_internal<mode>);
@@ -1506,7 +1506,7 @@
(define_expand "reduc_splus_<mode>"
[(match_operand:VQ 0 "s_register_operand" "")
(match_operand:VQ 1 "s_register_operand" "")]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
rtx step1 = gen_reg_rtx (<V_HALF>mode);
rtx res_d = gen_reg_rtx (<V_HALF>mode);
@@ -1541,7 +1541,7 @@
(define_expand "reduc_smin_<mode>"
[(match_operand:VD 0 "s_register_operand" "")
(match_operand:VD 1 "s_register_operand" "")]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
&gen_neon_vpsmin<mode>);
@@ -1551,7 +1551,7 @@
(define_expand "reduc_smin_<mode>"
[(match_operand:VQ 0 "s_register_operand" "")
(match_operand:VQ 1 "s_register_operand" "")]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
rtx step1 = gen_reg_rtx (<V_HALF>mode);
rtx res_d = gen_reg_rtx (<V_HALF>mode);
@@ -1566,7 +1566,7 @@
(define_expand "reduc_smax_<mode>"
[(match_operand:VD 0 "s_register_operand" "")
(match_operand:VD 1 "s_register_operand" "")]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
neon_pairwise_reduce (operands[0], operands[1], <MODE>mode,
&gen_neon_vpsmax<mode>);
@@ -1576,7 +1576,7 @@
(define_expand "reduc_smax_<mode>"
[(match_operand:VQ 0 "s_register_operand" "")
(match_operand:VQ 1 "s_register_operand" "")]
- "TARGET_NEON"
+ "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
rtx step1 = gen_reg_rtx (<V_HALF>mode);
rtx res_d = gen_reg_rtx (<V_HALF>mode);
=== modified file 'gcc/config/arm/vec-common.md'
--- old/gcc/config/arm/vec-common.md 2009-11-11 14:23:03 +0000
+++ new/gcc/config/arm/vec-common.md 2010-07-29 17:03:20 +0000
@@ -57,7 +57,8 @@
[(set (match_operand:VALL 0 "s_register_operand" "")
(plus:VALL (match_operand:VALL 1 "s_register_operand" "")
(match_operand:VALL 2 "s_register_operand" "")))]
- "TARGET_NEON
+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
+ || flag_unsafe_math_optimizations))
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
{
})
@@ -66,7 +67,8 @@
[(set (match_operand:VALL 0 "s_register_operand" "")
(minus:VALL (match_operand:VALL 1 "s_register_operand" "")
(match_operand:VALL 2 "s_register_operand" "")))]
- "TARGET_NEON
+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
+ || flag_unsafe_math_optimizations))
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
{
})
@@ -75,7 +77,9 @@
[(set (match_operand:VALLW 0 "s_register_operand" "")
(mult:VALLW (match_operand:VALLW 1 "s_register_operand" "")
(match_operand:VALLW 2 "s_register_operand" "")))]
- "TARGET_NEON || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
+ || flag_unsafe_math_optimizations))
+ || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)"
{
})
@@ -83,7 +87,8 @@
[(set (match_operand:VALLW 0 "s_register_operand" "")
(smin:VALLW (match_operand:VALLW 1 "s_register_operand" "")
(match_operand:VALLW 2 "s_register_operand" "")))]
- "TARGET_NEON
+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
+ || flag_unsafe_math_optimizations))
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
{
})
@@ -101,7 +106,8 @@
[(set (match_operand:VALLW 0 "s_register_operand" "")
(smax:VALLW (match_operand:VALLW 1 "s_register_operand" "")
(match_operand:VALLW 2 "s_register_operand" "")))]
- "TARGET_NEON
+ "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode)
+ || flag_unsafe_math_optimizations))
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
{
})
=== modified file 'gcc/doc/invoke.texi'
--- old/gcc/doc/invoke.texi 2010-07-29 15:53:39 +0000
+++ new/gcc/doc/invoke.texi 2010-07-29 17:03:20 +0000
@@ -9874,6 +9874,14 @@
If @option{-msoft-float} is specified this specifies the format of
floating point values.
+If the selected floating-point hardware includes the NEON extension
+(e.g. @option{-mfpu}=@samp{neon}), note that floating-point
+operations will not be used by GCC's auto-vectorization pass unless
+@option{-funsafe-math-optimizations} is also specified. This is
+because NEON hardware does not fully implement the IEEE 754 standard for
+floating-point arithmetic (in particular denormal values are treated as
+zero), so the use of NEON instructions may lead to a loss of precision.
+
@item -mfp16-format=@var{name}
@opindex mfp16-format
Specify the format of the @code{__fp16} half-precision floating-point type.
=== modified file 'gcc/testsuite/gcc.dg/vect/vect-reduc-6.c'
--- old/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c 2007-09-04 12:05:19 +0000
+++ new/gcc/testsuite/gcc.dg/vect/vect-reduc-6.c 2010-07-29 17:03:20 +0000
@@ -49,5 +49,6 @@
}
/* need -ffast-math to vectorizer these loops. */
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */
+/* ARM NEON passes -ffast-math to these tests, so expect this to fail. */
+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail arm_neon_ok } } } */
/* { dg-final { cleanup-tree-dump "vect" } } */
=== modified file 'gcc/testsuite/gcc.dg/vect/vect.exp'
--- old/gcc/testsuite/gcc.dg/vect/vect.exp 2010-07-29 15:38:15 +0000
+++ new/gcc/testsuite/gcc.dg/vect/vect.exp 2010-07-29 17:03:20 +0000
@@ -102,6 +102,10 @@
set dg-do-what-default run
} elseif [is-effective-target arm_neon_ok] {
eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
+ # NEON does not support denormals, so is not used for vectorization by
+ # default to avoid loss of precision. We must pass -ffast-math to test
+ # vectorization of float operations.
+ lappend DEFAULT_VECTCFLAGS "-ffast-math"
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99303.patch
-131
View File
@@ -1,131 +0,0 @@
Merge from Sourcery G++ 4.4:
2009-05-21 Sandra Loosemore <sandra@codesourcery.com>
Merge from Sourcery G++ 4.3:
2009-04-04 Sandra Loosemore <sandra@codesourcery.com>
Issue #5104
PR tree-optimization/39604
gcc/testsuite
* g++.dg/tree-ssa/sink-1.C: New.
gcc/
* tree_ssa-sink.c (sink_code_in_bb): Do not sink statements out
of a lexical block containing variable definitions.
2010-07-09 Sandra Loosemore <sandra@codesourcery.com>
Backport from mainline (originally on Sourcery G++ 4.4):
2010-07-02 Julian Brown <julian@codesourcery.com>
=== added file 'gcc/testsuite/g++.dg/tree-ssa/sink-1.C'
--- old/gcc/testsuite/g++.dg/tree-ssa/sink-1.C 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/g++.dg/tree-ssa/sink-1.C 2010-07-30 12:14:18 +0000
@@ -0,0 +1,50 @@
+/* { dg-do run } */
+/* { dg-options "-O1" } */
+
+class A {
+ public:
+ A() {}
+ virtual ~A() {}
+ void * dostuff();
+
+ virtual int dovirtual() = 0;
+};
+
+
+class B : public A {
+ public:
+ B() {}
+ int dovirtual() { return 0;}
+ virtual ~B() {};
+};
+
+class C : public B {
+ public:
+ C() {}
+ virtual ~C() {};
+};
+
+void* A::dostuff()
+{
+ return (void*)dovirtual();
+}
+
+/* tree-ssa-sink was sinking the inlined destructor for STUFF out of
+ the first inner block and into the second one, where it was ending up
+ after the inlined constructor for STUFF2. This is bad because
+ cfgexpand aliases STUFF and STUFF2 to the same storage at -O1
+ (i.e., without -fstrict-aliasing), with the result that STUFF2's
+ vtable was getting trashed. */
+
+int main() {
+ {
+ B stuff;
+ stuff.dostuff();
+ }
+ {
+ C stuff2;
+ stuff2.dostuff();
+ }
+ return 0;
+}
+
=== modified file 'gcc/tree-ssa-sink.c'
--- old/gcc/tree-ssa-sink.c 2009-11-28 16:21:00 +0000
+++ new/gcc/tree-ssa-sink.c 2010-07-30 12:14:18 +0000
@@ -470,6 +470,47 @@
last = false;
continue;
}
+
+ /* We cannot move statements that contain references to block-scope
+ variables out of that block, as this may lead to incorrect aliasing
+ when we lay out the stack frame in cfgexpand.c.
+ In lieu of more sophisticated analysis, be very conservative here
+ and prohibit moving any statement that references memory out of a
+ block with variables. */
+ if (gimple_references_memory_p (stmt))
+ {
+ tree fromblock = gimple_block (stmt);
+ while (fromblock
+ && fromblock != current_function_decl
+ && !BLOCK_VARS (fromblock))
+ fromblock = BLOCK_SUPERCONTEXT (fromblock);
+ if (fromblock && fromblock != current_function_decl)
+ {
+ gimple tostmt;
+ tree toblock;
+
+ if (gsi_end_p (togsi))
+ tostmt = gimple_seq_last_stmt (gsi_seq (togsi));
+ else
+ tostmt = gsi_stmt (togsi);
+ if (tostmt)
+ toblock = gimple_block (tostmt);
+ else
+ toblock = NULL;
+ while (toblock
+ && toblock != current_function_decl
+ && toblock != fromblock)
+ toblock = BLOCK_SUPERCONTEXT (toblock);
+ if (!toblock || toblock != fromblock)
+ {
+ if (!gsi_end_p (gsi))
+ gsi_prev (&gsi);
+ last = false;
+ continue;
+ }
+ }
+ }
+
if (dump_file)
{
fprintf (dump_file, "Sinking ");
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99304.patch
-81
View File
@@ -1,81 +0,0 @@
2010-07-10 Yao Qi <yao@codesourcery.com>
Merge from Sourcery G++ 4.4:
2009-05-28 Julian Brown <julian@codesourcery.com>
Merged from Sourcery G++ 4.3:
libgcc/
* config.host (arm*-*-linux*, arm*-*-uclinux*, arm*-*-eabi*)
(arm*-*-symbianelf): Add arm/t-divmod-ef to tmake_file.
* Makefile.in (LIB2_DIVMOD_EXCEPTION_FLAGS): Set to previous
default if not set by a target-specific Makefile fragment.
(lib2-divmod-o, lib2-divmod-s-o): Use above.
* config/arm/t-divmod-ef: New.
2010-07-09 Sandra Loosemore <sandra@codesourcery.com>
Merge from Sourcery G++ 4.4:
=== modified file 'libgcc/Makefile.in'
--- old/libgcc/Makefile.in 2010-03-30 12:08:52 +0000
+++ new/libgcc/Makefile.in 2010-07-30 12:21:02 +0000
@@ -400,18 +400,24 @@
endif
endif
+ifeq ($(LIB2_DIVMOD_EXCEPTION_FLAGS),)
+# Provide default flags for compiling divmod functions, if they haven't been
+# set already by a target-specific Makefile fragment.
+LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions -fnon-call-exceptions
+endif
+
# Build LIB2_DIVMOD_FUNCS.
lib2-divmod-o = $(patsubst %,%$(objext),$(LIB2_DIVMOD_FUNCS))
$(lib2-divmod-o): %$(objext): $(gcc_srcdir)/libgcc2.c
$(gcc_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \
- -fexceptions -fnon-call-exceptions $(vis_hide)
+ $(LIB2_DIVMOD_EXCEPTION_FLAGS) $(vis_hide)
libgcc-objects += $(lib2-divmod-o)
ifeq ($(enable_shared),yes)
lib2-divmod-s-o = $(patsubst %,%_s$(objext),$(LIB2_DIVMOD_FUNCS))
$(lib2-divmod-s-o): %_s$(objext): $(gcc_srcdir)/libgcc2.c
$(gcc_s_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \
- -fexceptions -fnon-call-exceptions
+ $(LIB2_DIVMOD_EXCEPTION_FLAGS)
libgcc-s-objects += $(lib2-divmod-s-o)
endif
=== modified file 'libgcc/config.host'
--- old/libgcc/config.host 2010-04-02 02:02:18 +0000
+++ new/libgcc/config.host 2010-07-30 12:21:02 +0000
@@ -208,12 +208,15 @@
arm*-*-netbsd*)
;;
arm*-*-linux*) # ARM GNU/Linux with ELF
+ tmake_file="${tmake_file} arm/t-divmod-ef"
;;
arm*-*-uclinux*) # ARM ucLinux
+ tmake_file="${tmake_file} arm/t-divmod-ef"
;;
arm*-*-ecos-elf)
;;
arm*-*-eabi* | arm*-*-symbianelf* )
+ tmake_file="${tmake_file} arm/t-divmod-ef"
;;
arm*-*-rtems*)
;;
=== added directory 'libgcc/config/arm'
=== added file 'libgcc/config/arm/t-divmod-ef'
--- old/libgcc/config/arm/t-divmod-ef 1970-01-01 00:00:00 +0000
+++ new/libgcc/config/arm/t-divmod-ef 2010-07-30 12:21:02 +0000
@@ -0,0 +1,4 @@
+# On ARM, specifying -fnon-call-exceptions will needlessly pull in
+# the unwinder in simple programs which use 64-bit division. Omitting
+# the option is safe.
+LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99305.patch
-52
View File
@@ -1,52 +0,0 @@
2009-09-02 Daniel Jacobowitz <dan@codesourcery.com>
libgcc/
* shared-object.mk (c_flags-$(base)$(objext)): New.
($(base)$(objext)): Use above.
($(base)_s$(objext)): Likewise.
* static-object.mk (c_flags-$(base)$(objext)): New.
($(base)$(objext)): Use above.
2010-07-10 Yao Qi <yao@codesourcery.com>
Merge from Sourcery G++ 4.4:
2009-05-28 Julian Brown <julian@codesourcery.com>
Merged from Sourcery G++ 4.3:
=== modified file 'libgcc/shared-object.mk'
--- old/libgcc/shared-object.mk 2008-07-03 18:22:00 +0000
+++ new/libgcc/shared-object.mk 2010-07-30 13:11:02 +0000
@@ -8,11 +8,13 @@
ifeq ($(suffix $o),.c)
+c_flags-$(base)$(objext) := $(c_flags)
$(base)$(objext): $o
- $(gcc_compile) $(c_flags) -c $< $(vis_hide)
+ $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide)
+c_flags-$(base)_s$(objext) := $(c_flags)
$(base)_s$(objext): $o
- $(gcc_s_compile) $(c_flags) -c $<
+ $(gcc_s_compile) $(c_flags-$@) -c $<
else
=== modified file 'libgcc/static-object.mk'
--- old/libgcc/static-object.mk 2007-01-04 04:22:37 +0000
+++ new/libgcc/static-object.mk 2010-07-30 13:11:02 +0000
@@ -8,8 +8,9 @@
ifeq ($(suffix $o),.c)
+c_flags-$(base)$(objext) := $(c_flags)
$(base)$(objext): $o
- $(gcc_compile) $(c_flags) -c $< $(vis_hide)
+ $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide)
else
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99306.patch
-1401
View File
File diff suppressed because it is too large Load Diff
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99307.patch
-138
View File
@@ -1,138 +0,0 @@
2010-07-12 Yao Qi <yao@codesourcery.com>
Merge from Sourcery G++ 4.4:
2009-10-06 Paul Brook <paul@codesourcery.com>
Issue #3869
gcc/
* target.h (gcc_target): Add warn_func_result.
* target-def.h (TARGET_WARN_FUNC_RESULT): Define and use.
* tree-cfg.h (execute_warn_function_return): Use
targetm.warn_func_result.
* config/arm/arm.c (TARGET_WARN_FUNC_RESULT): Define.
(arm_warn_func_result): New function.
gcc/testuite/
* gcc.target/arm/naked-3.c: New test.
2010-07-10 Sandra Loosemore <sandra@codesourcery.com>
Backport from mainline:
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-07-29 16:58:56 +0000
+++ new/gcc/config/arm/arm.c 2010-07-30 13:58:02 +0000
@@ -214,6 +214,7 @@
static int arm_issue_rate (void);
static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
static bool arm_allocate_stack_slots_for_args (void);
+static bool arm_warn_func_result (void);
static const char *arm_invalid_parameter_type (const_tree t);
static const char *arm_invalid_return_type (const_tree t);
static tree arm_promoted_type (const_tree t);
@@ -378,6 +379,9 @@
#undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
#define TARGET_TRAMPOLINE_ADJUST_ADDRESS arm_trampoline_adjust_address
+#undef TARGET_WARN_FUNC_RESULT
+#define TARGET_WARN_FUNC_RESULT arm_warn_func_result
+
#undef TARGET_DEFAULT_SHORT_ENUMS
#define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
@@ -2008,6 +2012,14 @@
return !IS_NAKED (arm_current_func_type ());
}
+static bool
+arm_warn_func_result (void)
+{
+ /* Naked functions are implemented entirely in assembly, including the
+ return sequence, so suppress warnings about this. */
+ return !IS_NAKED (arm_current_func_type ());
+}
+
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts.
=== modified file 'gcc/target-def.h'
--- old/gcc/target-def.h 2010-03-24 20:44:48 +0000
+++ new/gcc/target-def.h 2010-07-30 13:58:02 +0000
@@ -212,6 +212,10 @@
#define TARGET_EXTRA_LIVE_ON_ENTRY hook_void_bitmap
#endif
+#ifndef TARGET_WARN_FUNC_RESULT
+#define TARGET_WARN_FUNC_RESULT hook_bool_void_true
+#endif
+
#ifndef TARGET_ASM_FILE_START_APP_OFF
#define TARGET_ASM_FILE_START_APP_OFF false
#endif
@@ -1020,6 +1024,7 @@
TARGET_EMUTLS, \
TARGET_OPTION_HOOKS, \
TARGET_EXTRA_LIVE_ON_ENTRY, \
+ TARGET_WARN_FUNC_RESULT, \
TARGET_UNWIND_TABLES_DEFAULT, \
TARGET_HAVE_NAMED_SECTIONS, \
TARGET_HAVE_SWITCHABLE_BSS_SECTIONS, \
=== modified file 'gcc/target.h'
--- old/gcc/target.h 2010-03-27 10:27:39 +0000
+++ new/gcc/target.h 2010-07-30 13:58:02 +0000
@@ -1171,6 +1171,10 @@
bits in the bitmap passed in. */
void (*live_on_entry) (bitmap);
+ /* Return false if warnings about missing return statements or suspect
+ noreturn attributes should be suppressed for the current function. */
+ bool (*warn_func_result) (void);
+
/* True if unwinding tables should be generated by default. */
bool unwind_tables_default;
=== added file 'gcc/testsuite/gcc.target/arm/naked-3.c'
--- old/gcc/testsuite/gcc.target/arm/naked-3.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/naked-3.c 2010-07-30 13:58:02 +0000
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -Wall" } */
+/* Check that we do not get warnings about missing return statements
+ or bogus looking noreturn functions. */
+int __attribute__((naked))
+foo(void)
+{
+ __asm__ volatile ("mov r0, #1\r\nbx lr\n");
+}
+
+int __attribute__((naked,noreturn))
+bar(void)
+{
+ __asm__ volatile ("frob r0\n");
+}
=== modified file 'gcc/tree-cfg.c'
--- old/gcc/tree-cfg.c 2010-03-16 12:31:38 +0000
+++ new/gcc/tree-cfg.c 2010-07-30 13:58:02 +0000
@@ -47,6 +47,7 @@
#include "value-prof.h"
#include "pointer-set.h"
#include "tree-inline.h"
+#include "target.h"
/* This file contains functions for building the Control Flow Graph (CFG)
for a function tree. */
@@ -7092,6 +7093,9 @@
edge e;
edge_iterator ei;
+ if (!targetm.warn_func_result())
+ return 0;
+
/* If we have a path to EXIT, then we do return. */
if (TREE_THIS_VOLATILE (cfun->decl)
&& EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0)
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99308.patch
-112
View File
@@ -1,112 +0,0 @@
2010-07-15 Jie Zhang <jie@codesourcery.com>
Backport from mainline (originally from Sourcery G++ 4.4):
gcc/cp/
2010-04-07 Jie Zhang <jie@codesourcery.com>
PR c++/42556
* typeck2.c (split_nonconstant_init_1): Drop empty CONSTRUCTOR
when all of its elements are non-constant and have been split out.
gcc/testsuite/
2010-04-07 Jie Zhang <jie@codesourcery.com>
PR c++/42556
* g++.dg/init/pr42556.C: New test.
2010-07-12 Yao Qi <yao@codesourcery.com>
Merge from Sourcery G++ 4.4:
=== modified file 'gcc/cp/typeck2.c'
--- old/gcc/cp/typeck2.c 2010-02-23 18:32:20 +0000
+++ new/gcc/cp/typeck2.c 2010-07-30 14:05:57 +0000
@@ -549,13 +549,15 @@
expression to which INIT should be assigned. INIT is a CONSTRUCTOR. */
static void
-split_nonconstant_init_1 (tree dest, tree init)
+split_nonconstant_init_1 (tree dest, tree *initp)
{
unsigned HOST_WIDE_INT idx;
+ tree init = *initp;
tree field_index, value;
tree type = TREE_TYPE (dest);
tree inner_type = NULL;
bool array_type_p = false;
+ HOST_WIDE_INT num_type_elements, num_initialized_elements;
switch (TREE_CODE (type))
{
@@ -567,6 +569,7 @@
case RECORD_TYPE:
case UNION_TYPE:
case QUAL_UNION_TYPE:
+ num_initialized_elements = 0;
FOR_EACH_CONSTRUCTOR_ELT (CONSTRUCTOR_ELTS (init), idx,
field_index, value)
{
@@ -589,12 +592,13 @@
sub = build3 (COMPONENT_REF, inner_type, dest, field_index,
NULL_TREE);
- split_nonconstant_init_1 (sub, value);
+ split_nonconstant_init_1 (sub, &value);
}
else if (!initializer_constant_valid_p (value, inner_type))
{
tree code;
tree sub;
+ HOST_WIDE_INT inner_elements;
/* FIXME: Ordered removal is O(1) so the whole function is
worst-case quadratic. This could be fixed using an aside
@@ -617,9 +621,22 @@
code = build2 (INIT_EXPR, inner_type, sub, value);
code = build_stmt (input_location, EXPR_STMT, code);
add_stmt (code);
+
+ inner_elements = count_type_elements (inner_type, true);
+ if (inner_elements < 0)
+ num_initialized_elements = -1;
+ else if (num_initialized_elements >= 0)
+ num_initialized_elements += inner_elements;
continue;
}
}
+
+ num_type_elements = count_type_elements (type, true);
+ /* If all elements of the initializer are non-constant and
+ have been split out, we don't need the empty CONSTRUCTOR. */
+ if (num_type_elements > 0
+ && num_type_elements == num_initialized_elements)
+ *initp = NULL;
break;
case VECTOR_TYPE:
@@ -655,7 +672,7 @@
if (TREE_CODE (init) == CONSTRUCTOR)
{
code = push_stmt_list ();
- split_nonconstant_init_1 (dest, init);
+ split_nonconstant_init_1 (dest, &init);
code = pop_stmt_list (code);
DECL_INITIAL (dest) = init;
TREE_READONLY (dest) = 0;
=== added file 'gcc/testsuite/g++.dg/init/pr42556.C'
--- old/gcc/testsuite/g++.dg/init/pr42556.C 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/g++.dg/init/pr42556.C 2010-07-30 14:05:57 +0000
@@ -0,0 +1,10 @@
+// { dg-do compile }
+// { dg-options "-fdump-tree-gimple" }
+
+void foo (int a, int b, int c, int d)
+{
+ int v[4] = {a, b, c, d};
+}
+
+// { dg-final { scan-tree-dump-not "v = {}" "gimple" } }
+// { dg-final { cleanup-tree-dump "gimple" } }
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99310.patch
-36
View File
@@ -1,36 +0,0 @@
Backport from mainline (originally from Sourcery G++ 4.4):
gcc/
2010-07-07 Jie Zhang <jie@codesourcery.com>
* genautomata.c (output_automata_list_min_issue_delay_code):
Correctly decompress min_issue_delay.
2010-07-15 Jie Zhang <jie@codesourcery.com>
Issue #8980
Backport from mainline (originally from Sourcery G++ 4.4):
=== modified file 'gcc/genautomata.c'
--- old/gcc/genautomata.c 2009-11-25 10:55:54 +0000
+++ new/gcc/genautomata.c 2010-07-30 14:21:58 +0000
@@ -7865,12 +7865,15 @@
{
fprintf (output_file, ") / %d];\n",
automaton->min_issue_delay_table_compression_factor);
- fprintf (output_file, " %s = (%s >> (8 - (",
+ fprintf (output_file, " %s = (%s >> (8 - ((",
TEMPORARY_VARIABLE_NAME, TEMPORARY_VARIABLE_NAME);
output_translate_vect_name (output_file, automaton);
+ fprintf (output_file, " [%s] + ", INTERNAL_INSN_CODE_NAME);
+ fprintf (output_file, "%s->", CHIP_PARAMETER_NAME);
+ output_chip_member_name (output_file, automaton);
+ fprintf (output_file, " * %d)", automaton->insn_equiv_classes_num);
fprintf
- (output_file, " [%s] %% %d + 1) * %d)) & %d;\n",
- INTERNAL_INSN_CODE_NAME,
+ (output_file, " %% %d + 1) * %d)) & %d;\n",
automaton->min_issue_delay_table_compression_factor,
8 / automaton->min_issue_delay_table_compression_factor,
(1 << (8 / automaton->min_issue_delay_table_compression_factor))
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99312.patch
-714
View File
@@ -1,714 +0,0 @@
2010-07-15 Sandra Loosemore <sandra@codesourcery.com>
Backport from mainline:
2010-06-09 Sandra Loosemore <sandra@codesourcery.com>
gcc/
* tree-ssa-loop-ivopts.c (adjust_setup_cost): New function.
(get_computation_cost_at): Use it.
(determine_use_iv_cost_condition): Likewise.
(determine_iv_cost): Likewise.
2010-07-05 Sandra Loosemore <sandra@codesourcery.com>
PR middle-end/42505
gcc/
* tree-ssa-loop-ivopts.c (determine_set_costs): Delete obsolete
comments about cost model.
(try_add_cand_for): Add second strategy for choosing initial set
based on original IVs, controlled by ORIGINALP argument.
(get_initial_solution): Add ORIGINALP argument.
(find_optimal_iv_set_1): New function, split from find_optimal_iv_set.
(find_optimal_iv_set): Try two different strategies for choosing
the IV set, and return the one with lower cost.
gcc/testsuite/
* gcc.target/arm/pr42505.c: New test case.
2010-07-10 Sandra Loosemore <sandra@codesourcery.com>
PR middle-end/42505
gcc/
* tree-inline.c (estimate_num_insns): Refactor builtin complexity
lookup code into....
* builtins.c (is_simple_builtin, is_inexpensive_builtin): ...these
new functions.
* tree.h (is_simple_builtin, is_inexpensive_builtin): Declare.
* cfgloopanal.c (target_clobbered_regs): Define.
(init_set_costs): Initialize target_clobbered_regs.
(estimate_reg_pressure_cost): Add call_p argument. When true,
adjust the number of available registers to exclude the
call-clobbered registers.
* cfgloop.h (target_clobbered_regs): Declare.
(estimate_reg_pressure_cost): Adjust declaration.
* tree-ssa-loop-ivopts.c (struct ivopts_data): Add body_includes_call.
(ivopts_global_cost_for_size): Pass it to estimate_reg_pressure_cost.
(determine_set_costs): Dump target_clobbered_regs.
(loop_body_includes_call): New function.
(tree_ssa_iv_optimize_loop): Use it to initialize new field.
* loop-invariant.c (gain_for_invariant): Adjust arguments to pass
call_p flag through.
(best_gain_for_invariant): Likewise.
(find_invariants_to_move): Likewise.
(move_single_loop_invariants): Likewise, using already-computed
has_call field.
2010-07-15 Jie Zhang <jie@codesourcery.com>
Issue #8497, #8893
=== modified file 'gcc/builtins.c'
--- old/gcc/builtins.c 2010-04-13 12:47:11 +0000
+++ new/gcc/builtins.c 2010-08-02 13:51:23 +0000
@@ -13624,3 +13624,123 @@
break;
}
}
+
+/* Return true if DECL is a builtin that expands to a constant or similarly
+ simple code. */
+bool
+is_simple_builtin (tree decl)
+{
+ if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL)
+ switch (DECL_FUNCTION_CODE (decl))
+ {
+ /* Builtins that expand to constants. */
+ case BUILT_IN_CONSTANT_P:
+ case BUILT_IN_EXPECT:
+ case BUILT_IN_OBJECT_SIZE:
+ case BUILT_IN_UNREACHABLE:
+ /* Simple register moves or loads from stack. */
+ case BUILT_IN_RETURN_ADDRESS:
+ case BUILT_IN_EXTRACT_RETURN_ADDR:
+ case BUILT_IN_FROB_RETURN_ADDR:
+ case BUILT_IN_RETURN:
+ case BUILT_IN_AGGREGATE_INCOMING_ADDRESS:
+ case BUILT_IN_FRAME_ADDRESS:
+ case BUILT_IN_VA_END:
+ case BUILT_IN_STACK_SAVE:
+ case BUILT_IN_STACK_RESTORE:
+ /* Exception state returns or moves registers around. */
+ case BUILT_IN_EH_FILTER:
+ case BUILT_IN_EH_POINTER:
+ case BUILT_IN_EH_COPY_VALUES:
+ return true;
+
+ default:
+ return false;
+ }
+
+ return false;
+}
+
+/* Return true if DECL is a builtin that is not expensive, i.e., they are
+ most probably expanded inline into reasonably simple code. This is a
+ superset of is_simple_builtin. */
+bool
+is_inexpensive_builtin (tree decl)
+{
+ if (!decl)
+ return false;
+ else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD)
+ return true;
+ else if (DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL)
+ switch (DECL_FUNCTION_CODE (decl))
+ {
+ case BUILT_IN_ABS:
+ case BUILT_IN_ALLOCA:
+ case BUILT_IN_BSWAP32:
+ case BUILT_IN_BSWAP64:
+ case BUILT_IN_CLZ:
+ case BUILT_IN_CLZIMAX:
+ case BUILT_IN_CLZL:
+ case BUILT_IN_CLZLL:
+ case BUILT_IN_CTZ:
+ case BUILT_IN_CTZIMAX:
+ case BUILT_IN_CTZL:
+ case BUILT_IN_CTZLL:
+ case BUILT_IN_FFS:
+ case BUILT_IN_FFSIMAX:
+ case BUILT_IN_FFSL:
+ case BUILT_IN_FFSLL:
+ case BUILT_IN_IMAXABS:
+ case BUILT_IN_FINITE:
+ case BUILT_IN_FINITEF:
+ case BUILT_IN_FINITEL:
+ case BUILT_IN_FINITED32:
+ case BUILT_IN_FINITED64:
+ case BUILT_IN_FINITED128:
+ case BUILT_IN_FPCLASSIFY:
+ case BUILT_IN_ISFINITE:
+ case BUILT_IN_ISINF_SIGN:
+ case BUILT_IN_ISINF:
+ case BUILT_IN_ISINFF:
+ case BUILT_IN_ISINFL:
+ case BUILT_IN_ISINFD32:
+ case BUILT_IN_ISINFD64:
+ case BUILT_IN_ISINFD128:
+ case BUILT_IN_ISNAN:
+ case BUILT_IN_ISNANF:
+ case BUILT_IN_ISNANL:
+ case BUILT_IN_ISNAND32:
+ case BUILT_IN_ISNAND64:
+ case BUILT_IN_ISNAND128:
+ case BUILT_IN_ISNORMAL:
+ case BUILT_IN_ISGREATER:
+ case BUILT_IN_ISGREATEREQUAL:
+ case BUILT_IN_ISLESS:
+ case BUILT_IN_ISLESSEQUAL:
+ case BUILT_IN_ISLESSGREATER:
+ case BUILT_IN_ISUNORDERED:
+ case BUILT_IN_VA_ARG_PACK:
+ case BUILT_IN_VA_ARG_PACK_LEN:
+ case BUILT_IN_VA_COPY:
+ case BUILT_IN_TRAP:
+ case BUILT_IN_SAVEREGS:
+ case BUILT_IN_POPCOUNTL:
+ case BUILT_IN_POPCOUNTLL:
+ case BUILT_IN_POPCOUNTIMAX:
+ case BUILT_IN_POPCOUNT:
+ case BUILT_IN_PARITYL:
+ case BUILT_IN_PARITYLL:
+ case BUILT_IN_PARITYIMAX:
+ case BUILT_IN_PARITY:
+ case BUILT_IN_LABS:
+ case BUILT_IN_LLABS:
+ case BUILT_IN_PREFETCH:
+ return true;
+
+ default:
+ return is_simple_builtin (decl);
+ }
+
+ return false;
+}
+
=== modified file 'gcc/cfgloop.h'
--- old/gcc/cfgloop.h 2009-11-25 10:55:54 +0000
+++ new/gcc/cfgloop.h 2010-08-02 13:51:23 +0000
@@ -622,13 +622,14 @@
/* The properties of the target. */
extern unsigned target_avail_regs;
+extern unsigned target_clobbered_regs;
extern unsigned target_res_regs;
extern unsigned target_reg_cost [2];
extern unsigned target_spill_cost [2];
/* Register pressure estimation for induction variable optimizations & loop
invariant motion. */
-extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool);
+extern unsigned estimate_reg_pressure_cost (unsigned, unsigned, bool, bool);
extern void init_set_costs (void);
/* Loop optimizer initialization. */
=== modified file 'gcc/cfgloopanal.c'
--- old/gcc/cfgloopanal.c 2009-09-30 08:57:56 +0000
+++ new/gcc/cfgloopanal.c 2010-08-02 13:51:23 +0000
@@ -320,6 +320,8 @@
/* The properties of the target. */
unsigned target_avail_regs; /* Number of available registers. */
+unsigned target_clobbered_regs; /* Number of available registers that are
+ call-clobbered. */
unsigned target_res_regs; /* Number of registers reserved for temporary
expressions. */
unsigned target_reg_cost[2]; /* The cost for register when there still
@@ -342,10 +344,15 @@
unsigned i;
target_avail_regs = 0;
+ target_clobbered_regs = 0;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (TEST_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], i)
&& !fixed_regs[i])
- target_avail_regs++;
+ {
+ target_avail_regs++;
+ if (call_used_regs[i])
+ target_clobbered_regs++;
+ }
target_res_regs = 3;
@@ -379,20 +386,29 @@
/* Estimates cost of increased register pressure caused by making N_NEW new
registers live around the loop. N_OLD is the number of registers live
- around the loop. */
+ around the loop. If CALL_P is true, also take into account that
+ call-used registers may be clobbered in the loop body, reducing the
+ number of available registers before we spill. */
unsigned
-estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed)
+estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed,
+ bool call_p)
{
unsigned cost;
unsigned regs_needed = n_new + n_old;
+ unsigned available_regs = target_avail_regs;
+
+ /* If there is a call in the loop body, the call-clobbered registers
+ are not available for loop invariants. */
+ if (call_p)
+ available_regs = available_regs - target_clobbered_regs;
/* If we have enough registers, we should use them and not restrict
the transformations unnecessarily. */
- if (regs_needed + target_res_regs <= target_avail_regs)
+ if (regs_needed + target_res_regs <= available_regs)
return 0;
- if (regs_needed <= target_avail_regs)
+ if (regs_needed <= available_regs)
/* If we are close to running out of registers, try to preserve
them. */
cost = target_reg_cost [speed] * n_new;
=== modified file 'gcc/loop-invariant.c'
--- old/gcc/loop-invariant.c 2010-04-02 18:54:46 +0000
+++ new/gcc/loop-invariant.c 2010-08-02 13:51:23 +0000
@@ -1173,11 +1173,13 @@
/* Calculates gain for eliminating invariant INV. REGS_USED is the number
of registers used in the loop, NEW_REGS is the number of new variables
already added due to the invariant motion. The number of registers needed
- for it is stored in *REGS_NEEDED. */
+ for it is stored in *REGS_NEEDED. SPEED and CALL_P are flags passed
+ through to estimate_reg_pressure_cost. */
static int
gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
- unsigned *new_regs, unsigned regs_used, bool speed)
+ unsigned *new_regs, unsigned regs_used,
+ bool speed, bool call_p)
{
int comp_cost, size_cost;
@@ -1188,9 +1190,9 @@
if (! flag_ira_loop_pressure)
{
size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0],
- regs_used, speed)
+ regs_used, speed, call_p)
- estimate_reg_pressure_cost (new_regs[0],
- regs_used, speed));
+ regs_used, speed, call_p));
}
else
{
@@ -1245,7 +1247,8 @@
static int
best_gain_for_invariant (struct invariant **best, unsigned *regs_needed,
- unsigned *new_regs, unsigned regs_used, bool speed)
+ unsigned *new_regs, unsigned regs_used,
+ bool speed, bool call_p)
{
struct invariant *inv;
int i, gain = 0, again;
@@ -1261,7 +1264,7 @@
continue;
again = gain_for_invariant (inv, aregs_needed, new_regs, regs_used,
- speed);
+ speed, call_p);
if (again > gain)
{
gain = again;
@@ -1314,7 +1317,7 @@
/* Determines which invariants to move. */
static void
-find_invariants_to_move (bool speed)
+find_invariants_to_move (bool speed, bool call_p)
{
int gain;
unsigned i, regs_used, regs_needed[N_REG_CLASSES], new_regs[N_REG_CLASSES];
@@ -1353,7 +1356,8 @@
new_regs[ira_reg_class_cover[i]] = 0;
}
while ((gain = best_gain_for_invariant (&inv, regs_needed,
- new_regs, regs_used, speed)) > 0)
+ new_regs, regs_used,
+ speed, call_p)) > 0)
{
set_move_mark (inv->invno, gain);
if (! flag_ira_loop_pressure)
@@ -1554,7 +1558,8 @@
init_inv_motion_data ();
find_invariants (loop);
- find_invariants_to_move (optimize_loop_for_speed_p (loop));
+ find_invariants_to_move (optimize_loop_for_speed_p (loop),
+ LOOP_DATA (loop)->has_call);
move_invariants (loop);
free_inv_motion_data ();
=== added file 'gcc/testsuite/gcc.target/arm/pr42505.c'
--- old/gcc/testsuite/gcc.target/arm/pr42505.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/pr42505.c 2010-08-02 13:51:23 +0000
@@ -0,0 +1,23 @@
+/* { dg-options "-mthumb -Os -march=armv5te" } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */
+
+struct A {
+ int f1;
+ int f2;
+};
+
+int func(int c);
+
+/* This function should not need to spill anything to the stack. */
+int test(struct A* src, struct A* dst, int count)
+{
+ while (count--) {
+ if (!func(src->f2)) {
+ return 0;
+ }
+ *dst++ = *src++;
+ }
+
+ return 1;
+}
=== modified file 'gcc/tree-inline.c'
--- old/gcc/tree-inline.c 2010-03-18 20:07:13 +0000
+++ new/gcc/tree-inline.c 2010-08-02 13:51:23 +0000
@@ -3246,34 +3246,13 @@
if (POINTER_TYPE_P (funtype))
funtype = TREE_TYPE (funtype);
- if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_MD)
+ if (is_simple_builtin (decl))
+ return 0;
+ else if (is_inexpensive_builtin (decl))
cost = weights->target_builtin_call_cost;
else
cost = weights->call_cost;
- if (decl && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL)
- switch (DECL_FUNCTION_CODE (decl))
- {
- case BUILT_IN_CONSTANT_P:
- return 0;
- case BUILT_IN_EXPECT:
- return 0;
-
- /* Prefetch instruction is not expensive. */
- case BUILT_IN_PREFETCH:
- cost = weights->target_builtin_call_cost;
- break;
-
- /* Exception state returns or moves registers around. */
- case BUILT_IN_EH_FILTER:
- case BUILT_IN_EH_POINTER:
- case BUILT_IN_EH_COPY_VALUES:
- return 0;
-
- default:
- break;
- }
-
if (decl)
funtype = TREE_TYPE (decl);
=== modified file 'gcc/tree-ssa-loop-ivopts.c'
--- old/gcc/tree-ssa-loop-ivopts.c 2010-04-01 15:18:07 +0000
+++ new/gcc/tree-ssa-loop-ivopts.c 2010-08-02 13:51:23 +0000
@@ -257,6 +257,9 @@
/* Are we optimizing for speed? */
bool speed;
+
+ /* Whether the loop body includes any function calls. */
+ bool body_includes_call;
};
/* An assignment of iv candidates to uses. */
@@ -2926,6 +2929,20 @@
return get_computation_at (loop, use, cand, use->stmt);
}
+/* Adjust the cost COST for being in loop setup rather than loop body.
+ If we're optimizing for space, the loop setup overhead is constant;
+ if we're optimizing for speed, amortize it over the per-iteration cost. */
+static unsigned
+adjust_setup_cost (struct ivopts_data *data, unsigned cost)
+{
+ if (cost == INFTY)
+ return cost;
+ else if (optimize_loop_for_speed_p (data->current_loop))
+ return cost / AVG_LOOP_NITER (data->current_loop);
+ else
+ return cost;
+}
+
/* Returns cost of addition in MODE. */
static unsigned
@@ -3838,8 +3855,8 @@
/* Symbol + offset should be compile-time computable so consider that they
are added once to the variable, if present. */
if (var_present && (symbol_present || offset))
- cost.cost += add_cost (TYPE_MODE (ctype), speed)
- / AVG_LOOP_NITER (data->current_loop);
+ cost.cost += adjust_setup_cost (data,
+ add_cost (TYPE_MODE (ctype), speed));
/* Having offset does not affect runtime cost in case it is added to
symbol, but it increases complexity. */
@@ -4104,7 +4121,7 @@
elim_cost = force_var_cost (data, bound, &depends_on_elim);
/* The bound is a loop invariant, so it will be only computed
once. */
- elim_cost.cost /= AVG_LOOP_NITER (data->current_loop);
+ elim_cost.cost = adjust_setup_cost (data, elim_cost.cost);
}
else
elim_cost = infinite_cost;
@@ -4351,7 +4368,7 @@
cost_base = force_var_cost (data, base, NULL);
cost_step = add_cost (TYPE_MODE (TREE_TYPE (base)), data->speed);
- cost = cost_step + cost_base.cost / AVG_LOOP_NITER (current_loop);
+ cost = cost_step + adjust_setup_cost (data, cost_base.cost);
/* Prefer the original ivs unless we may gain something by replacing it.
The reason is to make debugging simpler; so this is not relevant for
@@ -4404,7 +4421,8 @@
{
/* We add size to the cost, so that we prefer eliminating ivs
if possible. */
- return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed);
+ return size + estimate_reg_pressure_cost (size, data->regs_used, data->speed,
+ data->body_includes_call);
}
/* For each size of the induction variable set determine the penalty. */
@@ -4419,30 +4437,11 @@
struct loop *loop = data->current_loop;
bitmap_iterator bi;
- /* We use the following model (definitely improvable, especially the
- cost function -- TODO):
-
- We estimate the number of registers available (using MD data), name it A.
-
- We estimate the number of registers used by the loop, name it U. This
- number is obtained as the number of loop phi nodes (not counting virtual
- registers and bivs) + the number of variables from outside of the loop.
-
- We set a reserve R (free regs that are used for temporary computations,
- etc.). For now the reserve is a constant 3.
-
- Let I be the number of induction variables.
-
- -- if U + I + R <= A, the cost is I * SMALL_COST (just not to encourage
- make a lot of ivs without a reason).
- -- if A - R < U + I <= A, the cost is I * PRES_COST
- -- if U + I > A, the cost is I * PRES_COST and
- number of uses * SPILL_COST * (U + I - A) / (U + I) is added. */
-
if (dump_file && (dump_flags & TDF_DETAILS))
{
fprintf (dump_file, "Global costs:\n");
fprintf (dump_file, " target_avail_regs %d\n", target_avail_regs);
+ fprintf (dump_file, " target_clobbered_regs %d\n", target_clobbered_regs);
fprintf (dump_file, " target_reg_cost %d\n", target_reg_cost[data->speed]);
fprintf (dump_file, " target_spill_cost %d\n", target_spill_cost[data->speed]);
}
@@ -5062,11 +5061,13 @@
}
/* Tries to extend the sets IVS in the best possible way in order
- to express the USE. */
+ to express the USE. If ORIGINALP is true, prefer candidates from
+ the original set of IVs, otherwise favor important candidates not
+ based on any memory object. */
static bool
try_add_cand_for (struct ivopts_data *data, struct iv_ca *ivs,
- struct iv_use *use)
+ struct iv_use *use, bool originalp)
{
comp_cost best_cost, act_cost;
unsigned i;
@@ -5085,7 +5086,8 @@
iv_ca_set_no_cp (data, ivs, use);
}
- /* First try important candidates not based on any memory object. Only if
+ /* If ORIGINALP is true, try to find the original IV for the use. Otherwise
+ first try important candidates not based on any memory object. Only if
this fails, try the specific ones. Rationale -- in loops with many
variables the best choice often is to use just one generic biv. If we
added here many ivs specific to the uses, the optimization algorithm later
@@ -5097,7 +5099,10 @@
{
cand = iv_cand (data, i);
- if (cand->iv->base_object != NULL_TREE)
+ if (originalp && cand->pos !=IP_ORIGINAL)
+ continue;
+
+ if (!originalp && cand->iv->base_object != NULL_TREE)
continue;
if (iv_ca_cand_used_p (ivs, cand))
@@ -5133,8 +5138,13 @@
continue;
/* Already tried this. */
- if (cand->important && cand->iv->base_object == NULL_TREE)
- continue;
+ if (cand->important)
+ {
+ if (originalp && cand->pos == IP_ORIGINAL)
+ continue;
+ if (!originalp && cand->iv->base_object == NULL_TREE)
+ continue;
+ }
if (iv_ca_cand_used_p (ivs, cand))
continue;
@@ -5168,13 +5178,13 @@
/* Finds an initial assignment of candidates to uses. */
static struct iv_ca *
-get_initial_solution (struct ivopts_data *data)
+get_initial_solution (struct ivopts_data *data, bool originalp)
{
struct iv_ca *ivs = iv_ca_new (data);
unsigned i;
for (i = 0; i < n_iv_uses (data); i++)
- if (!try_add_cand_for (data, ivs, iv_use (data, i)))
+ if (!try_add_cand_for (data, ivs, iv_use (data, i), originalp))
{
iv_ca_free (&ivs);
return NULL;
@@ -5246,14 +5256,12 @@
solution and remove the unused ivs while this improves the cost. */
static struct iv_ca *
-find_optimal_iv_set (struct ivopts_data *data)
+find_optimal_iv_set_1 (struct ivopts_data *data, bool originalp)
{
- unsigned i;
struct iv_ca *set;
- struct iv_use *use;
/* Get the initial solution. */
- set = get_initial_solution (data);
+ set = get_initial_solution (data, originalp);
if (!set)
{
if (dump_file && (dump_flags & TDF_DETAILS))
@@ -5276,11 +5284,46 @@
}
}
+ return set;
+}
+
+static struct iv_ca *
+find_optimal_iv_set (struct ivopts_data *data)
+{
+ unsigned i;
+ struct iv_ca *set, *origset;
+ struct iv_use *use;
+ comp_cost cost, origcost;
+
+ /* Determine the cost based on a strategy that starts with original IVs,
+ and try again using a strategy that prefers candidates not based
+ on any IVs. */
+ origset = find_optimal_iv_set_1 (data, true);
+ set = find_optimal_iv_set_1 (data, false);
+
+ if (!origset && !set)
+ return NULL;
+
+ origcost = origset ? iv_ca_cost (origset) : infinite_cost;
+ cost = set ? iv_ca_cost (set) : infinite_cost;
+
if (dump_file && (dump_flags & TDF_DETAILS))
{
- comp_cost cost = iv_ca_cost (set);
- fprintf (dump_file, "Final cost %d (complexity %d)\n\n", cost.cost, cost.complexity);
- }
+ fprintf (dump_file, "Original cost %d (complexity %d)\n\n",
+ origcost.cost, origcost.complexity);
+ fprintf (dump_file, "Final cost %d (complexity %d)\n\n",
+ cost.cost, cost.complexity);
+ }
+
+ /* Choose the one with the best cost. */
+ if (compare_costs (origcost, cost) <= 0)
+ {
+ if (set)
+ iv_ca_free (&set);
+ set = origset;
+ }
+ else if (origset)
+ iv_ca_free (&origset);
for (i = 0; i < n_iv_uses (data); i++)
{
@@ -5768,6 +5811,25 @@
VEC_free (iv_cand_p, heap, data->iv_candidates);
}
+/* Returns true if the loop body BODY includes any function calls. */
+
+static bool
+loop_body_includes_call (basic_block *body, unsigned num_nodes)
+{
+ gimple_stmt_iterator gsi;
+ unsigned i;
+
+ for (i = 0; i < num_nodes; i++)
+ for (gsi = gsi_start_bb (body[i]); !gsi_end_p (gsi); gsi_next (&gsi))
+ {
+ gimple stmt = gsi_stmt (gsi);
+ if (is_gimple_call (stmt)
+ && !is_inexpensive_builtin (gimple_call_fndecl (stmt)))
+ return true;
+ }
+ return false;
+}
+
/* Optimizes the LOOP. Returns true if anything changed. */
static bool
@@ -5799,6 +5861,7 @@
}
body = get_loop_body (loop);
+ data->body_includes_call = loop_body_includes_call (body, loop->num_nodes);
renumber_gimple_stmt_uids_in_blocks (body, loop->num_nodes);
free (body);
=== modified file 'gcc/tree.h'
--- old/gcc/tree.h 2010-04-02 18:54:46 +0000
+++ new/gcc/tree.h 2010-08-02 13:51:23 +0000
@@ -4962,6 +4962,8 @@
extern bool merge_ranges (int *, tree *, tree *, int, tree, tree, int,
tree, tree);
extern void set_builtin_user_assembler_name (tree decl, const char *asmspec);
+extern bool is_simple_builtin (tree);
+extern bool is_inexpensive_builtin (tree);
/* In convert.c */
extern tree strip_float_extensions (tree);
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99313.patch
-37
View File
@@ -1,37 +0,0 @@
2010-07-15 Yao Qi <yao@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-02-25 Maxim Kuvyrkov <maxim@codesourcery.com>
gcc/
* tree.c (initializer_zerop): Handle STRING_CST.
2010-07-15 Sandra Loosemore <sandra@codesourcery.com>
Backport from mainline:
=== modified file 'gcc/tree.c'
--- old/gcc/tree.c 2010-04-01 15:18:07 +0000
+++ new/gcc/tree.c 2010-08-02 16:32:37 +0000
@@ -9335,6 +9335,19 @@
return true;
}
+ case STRING_CST:
+ {
+ int i;
+
+ /* We need to loop through all elements to handle cases like
+ "\0" and "\0foobar". */
+ for (i = 0; i < TREE_STRING_LENGTH (init); ++i)
+ if (TREE_STRING_POINTER (init)[i] != '\0')
+ return false;
+
+ return true;
+ }
+
default:
return false;
}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99314.patch
-433
View File
@@ -1,433 +0,0 @@
2010-07-16 Jie Zhang <jie@codesourcery.com>
Issue #7688
Backport from mainline:
gcc/
2010-07-12 Jie Zhang <jie@codesourcery.com>
* postreload.c (reg_symbol_ref[]): New.
(move2add_use_add2_insn): New.
(move2add_use_add3_insn): New.
(reload_cse_move2add): Handle SYMBOL + OFFSET case.
(move2add_note_store): Likewise.
2010-07-15 Yao Qi <yao@codesourcery.com>
Merge from Sourcery G++ 4.4:
=== modified file 'gcc/postreload.c'
--- old/gcc/postreload.c 2010-03-16 10:50:42 +0000
+++ new/gcc/postreload.c 2010-08-02 16:55:34 +0000
@@ -1160,17 +1160,19 @@
information about register contents we have would be costly, so we
use move2add_last_label_luid to note where the label is and then
later disable any optimization that would cross it.
- reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
- reg_set_luid[n] is greater than move2add_last_label_luid. */
+ reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
+ are only valid if reg_set_luid[n] is greater than
+ move2add_last_label_luid. */
static int reg_set_luid[FIRST_PSEUDO_REGISTER];
/* If reg_base_reg[n] is negative, register n has been set to
- reg_offset[n] in mode reg_mode[n] .
+ reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
If reg_base_reg[n] is non-negative, register n has been set to the
sum of reg_offset[n] and the value of register reg_base_reg[n]
before reg_set_luid[n], calculated in mode reg_mode[n] . */
static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
static int reg_base_reg[FIRST_PSEUDO_REGISTER];
+static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER];
static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
/* move2add_luid is linearly increased while scanning the instructions
@@ -1190,6 +1192,151 @@
&& TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
GET_MODE_BITSIZE (INMODE))))
+/* This function is called with INSN that sets REG to (SYM + OFF),
+ while REG is known to already have value (SYM + offset).
+ This function tries to change INSN into an add instruction
+ (set (REG) (plus (REG) (OFF - offset))) using the known value.
+ It also updates the information about REG's known value. */
+
+static void
+move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx insn)
+{
+ rtx pat = PATTERN (insn);
+ rtx src = SET_SRC (pat);
+ int regno = REGNO (reg);
+ rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno],
+ GET_MODE (reg));
+ bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+
+ /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
+ use (set (reg) (reg)) instead.
+ We don't delete this insn, nor do we convert it into a
+ note, to avoid losing register notes or the return
+ value flag. jump2 already knows how to get rid of
+ no-op moves. */
+ if (new_src == const0_rtx)
+ {
+ /* If the constants are different, this is a
+ truncation, that, if turned into (set (reg)
+ (reg)), would be discarded. Maybe we should
+ try a truncMN pattern? */
+ if (INTVAL (off) == reg_offset [regno])
+ validate_change (insn, &SET_SRC (pat), reg, 0);
+ }
+ else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
+ && have_add2_insn (reg, new_src))
+ {
+ rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
+ validate_change (insn, &SET_SRC (pat), tem, 0);
+ }
+ else if (sym == NULL_RTX && GET_MODE (reg) != BImode)
+ {
+ enum machine_mode narrow_mode;
+ for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
+ narrow_mode != VOIDmode
+ && narrow_mode != GET_MODE (reg);
+ narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
+ {
+ if (have_insn_for (STRICT_LOW_PART, narrow_mode)
+ && ((reg_offset[regno]
+ & ~GET_MODE_MASK (narrow_mode))
+ == (INTVAL (off)
+ & ~GET_MODE_MASK (narrow_mode))))
+ {
+ rtx narrow_reg = gen_rtx_REG (narrow_mode,
+ REGNO (reg));
+ rtx narrow_src = gen_int_mode (INTVAL (off),
+ narrow_mode);
+ rtx new_set =
+ gen_rtx_SET (VOIDmode,
+ gen_rtx_STRICT_LOW_PART (VOIDmode,
+ narrow_reg),
+ narrow_src);
+ if (validate_change (insn, &PATTERN (insn),
+ new_set, 0))
+ break;
+ }
+ }
+ }
+ reg_set_luid[regno] = move2add_luid;
+ reg_base_reg[regno] = -1;
+ reg_mode[regno] = GET_MODE (reg);
+ reg_symbol_ref[regno] = sym;
+ reg_offset[regno] = INTVAL (off);
+}
+
+
+/* This function is called with INSN that sets REG to (SYM + OFF),
+ but REG doesn't have known value (SYM + offset). This function
+ tries to find another register which is known to already have
+ value (SYM + offset) and change INSN into an add instruction
+ (set (REG) (plus (the found register) (OFF - offset))) if such
+ a register is found. It also updates the information about
+ REG's known value. */
+
+static void
+move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx insn)
+{
+ rtx pat = PATTERN (insn);
+ rtx src = SET_SRC (pat);
+ int regno = REGNO (reg);
+ int min_cost = INT_MAX;
+ int min_regno;
+ bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
+ int i;
+
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ if (reg_set_luid[i] > move2add_last_label_luid
+ && reg_mode[i] == GET_MODE (reg)
+ && reg_base_reg[i] < 0
+ && reg_symbol_ref[i] != NULL_RTX
+ && rtx_equal_p (sym, reg_symbol_ref[i]))
+ {
+ rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i],
+ GET_MODE (reg));
+ /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
+ use (set (reg) (reg)) instead.
+ We don't delete this insn, nor do we convert it into a
+ note, to avoid losing register notes or the return
+ value flag. jump2 already knows how to get rid of
+ no-op moves. */
+ if (new_src == const0_rtx)
+ {
+ min_cost = 0;
+ min_regno = i;
+ break;
+ }
+ else
+ {
+ int cost = rtx_cost (new_src, PLUS, speed);
+ if (cost < min_cost)
+ {
+ min_cost = cost;
+ min_regno = i;
+ }
+ }
+ }
+
+ if (min_cost < rtx_cost (src, SET, speed))
+ {
+ rtx tem;
+
+ tem = gen_rtx_REG (GET_MODE (reg), min_regno);
+ if (i != min_regno)
+ {
+ rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno],
+ GET_MODE (reg));
+ tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src);
+ }
+ validate_change (insn, &SET_SRC (pat), tem, 0);
+ }
+ reg_set_luid[regno] = move2add_luid;
+ reg_base_reg[regno] = -1;
+ reg_mode[regno] = GET_MODE (reg);
+ reg_symbol_ref[regno] = sym;
+ reg_offset[regno] = INTVAL (off);
+}
+
static void
reload_cse_move2add (rtx first)
{
@@ -1197,7 +1344,13 @@
rtx insn;
for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
- reg_set_luid[i] = 0;
+ {
+ reg_set_luid[i] = 0;
+ reg_offset[i] = 0;
+ reg_base_reg[i] = 0;
+ reg_symbol_ref[i] = NULL_RTX;
+ reg_mode[i] = VOIDmode;
+ }
move2add_last_label_luid = 0;
move2add_luid = 2;
@@ -1245,65 +1398,11 @@
(set (STRICT_LOW_PART (REGX)) (CONST_INT B))
*/
- if (CONST_INT_P (src) && reg_base_reg[regno] < 0)
+ if (CONST_INT_P (src)
+ && reg_base_reg[regno] < 0
+ && reg_symbol_ref[regno] == NULL_RTX)
{
- rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno],
- GET_MODE (reg));
- bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
-
- /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
- use (set (reg) (reg)) instead.
- We don't delete this insn, nor do we convert it into a
- note, to avoid losing register notes or the return
- value flag. jump2 already knows how to get rid of
- no-op moves. */
- if (new_src == const0_rtx)
- {
- /* If the constants are different, this is a
- truncation, that, if turned into (set (reg)
- (reg)), would be discarded. Maybe we should
- try a truncMN pattern? */
- if (INTVAL (src) == reg_offset [regno])
- validate_change (insn, &SET_SRC (pat), reg, 0);
- }
- else if (rtx_cost (new_src, PLUS, speed) < rtx_cost (src, SET, speed)
- && have_add2_insn (reg, new_src))
- {
- rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src);
- validate_change (insn, &SET_SRC (pat), tem, 0);
- }
- else if (GET_MODE (reg) != BImode)
- {
- enum machine_mode narrow_mode;
- for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
- narrow_mode != VOIDmode
- && narrow_mode != GET_MODE (reg);
- narrow_mode = GET_MODE_WIDER_MODE (narrow_mode))
- {
- if (have_insn_for (STRICT_LOW_PART, narrow_mode)
- && ((reg_offset[regno]
- & ~GET_MODE_MASK (narrow_mode))
- == (INTVAL (src)
- & ~GET_MODE_MASK (narrow_mode))))
- {
- rtx narrow_reg = gen_rtx_REG (narrow_mode,
- REGNO (reg));
- rtx narrow_src = gen_int_mode (INTVAL (src),
- narrow_mode);
- rtx new_set =
- gen_rtx_SET (VOIDmode,
- gen_rtx_STRICT_LOW_PART (VOIDmode,
- narrow_reg),
- narrow_src);
- if (validate_change (insn, &PATTERN (insn),
- new_set, 0))
- break;
- }
- }
- }
- reg_set_luid[regno] = move2add_luid;
- reg_mode[regno] = GET_MODE (reg);
- reg_offset[regno] = INTVAL (src);
+ move2add_use_add2_insn (reg, NULL_RTX, src, insn);
continue;
}
@@ -1373,6 +1472,51 @@
}
}
}
+
+ /* Try to transform
+ (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
+ ...
+ (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
+ to
+ (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
+ ...
+ (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
+ if ((GET_CODE (src) == SYMBOL_REF
+ || (GET_CODE (src) == CONST
+ && GET_CODE (XEXP (src, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
+ && CONST_INT_P (XEXP (XEXP (src, 0), 1))))
+ && dbg_cnt (cse2_move2add))
+ {
+ rtx sym, off;
+
+ if (GET_CODE (src) == SYMBOL_REF)
+ {
+ sym = src;
+ off = const0_rtx;
+ }
+ else
+ {
+ sym = XEXP (XEXP (src, 0), 0);
+ off = XEXP (XEXP (src, 0), 1);
+ }
+
+ /* If the reg already contains the value which is sum of
+ sym and some constant value, we can use an add2 insn. */
+ if (reg_set_luid[regno] > move2add_last_label_luid
+ && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])
+ && reg_base_reg[regno] < 0
+ && reg_symbol_ref[regno] != NULL_RTX
+ && rtx_equal_p (sym, reg_symbol_ref[regno]))
+ move2add_use_add2_insn (reg, sym, off, insn);
+
+ /* Otherwise, we have to find a register whose value is sum
+ of sym and some constant value. */
+ else
+ move2add_use_add3_insn (reg, sym, off, insn);
+
+ continue;
+ }
}
for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
@@ -1386,7 +1530,7 @@
reg_set_luid[regno] = 0;
}
}
- note_stores (PATTERN (insn), move2add_note_store, NULL);
+ note_stores (PATTERN (insn), move2add_note_store, insn);
/* If INSN is a conditional branch, we try to extract an
implicit set out of it. */
@@ -1408,7 +1552,7 @@
{
rtx implicit_set =
gen_rtx_SET (VOIDmode, XEXP (cnd, 0), XEXP (cnd, 1));
- move2add_note_store (SET_DEST (implicit_set), implicit_set, 0);
+ move2add_note_store (SET_DEST (implicit_set), implicit_set, insn);
}
}
@@ -1426,13 +1570,15 @@
}
}
-/* SET is a SET or CLOBBER that sets DST.
+/* SET is a SET or CLOBBER that sets DST. DATA is the insn which
+ contains SET.
Update reg_set_luid, reg_offset and reg_base_reg accordingly.
Called from reload_cse_move2add via note_stores. */
static void
-move2add_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
+move2add_note_store (rtx dst, const_rtx set, void *data)
{
+ rtx insn = (rtx) data;
unsigned int regno = 0;
unsigned int nregs = 0;
unsigned int i;
@@ -1466,6 +1612,38 @@
nregs = hard_regno_nregs[regno][mode];
if (SCALAR_INT_MODE_P (GET_MODE (dst))
+ && nregs == 1 && GET_CODE (set) == SET)
+ {
+ rtx note, sym = NULL_RTX;
+ HOST_WIDE_INT off;
+
+ note = find_reg_equal_equiv_note (insn);
+ if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
+ {
+ sym = XEXP (note, 0);
+ off = 0;
+ }
+ else if (note && GET_CODE (XEXP (note, 0)) == CONST
+ && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
+ && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
+ {
+ sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
+ off = INTVAL (XEXP (XEXP (XEXP (note, 0), 0), 1));
+ }
+
+ if (sym != NULL_RTX)
+ {
+ reg_base_reg[regno] = -1;
+ reg_symbol_ref[regno] = sym;
+ reg_offset[regno] = off;
+ reg_mode[regno] = mode;
+ reg_set_luid[regno] = move2add_luid;
+ return;
+ }
+ }
+
+ if (SCALAR_INT_MODE_P (GET_MODE (dst))
&& nregs == 1 && GET_CODE (set) == SET
&& GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
&& GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
@@ -1525,6 +1703,7 @@
case CONST_INT:
/* Start tracking the register as a constant. */
reg_base_reg[regno] = -1;
+ reg_symbol_ref[regno] = NULL_RTX;
reg_offset[regno] = INTVAL (SET_SRC (set));
/* We assign the same luid to all registers set to constants. */
reg_set_luid[regno] = move2add_last_label_luid + 1;
@@ -1545,6 +1724,7 @@
if (reg_set_luid[base_regno] <= move2add_last_label_luid)
{
reg_base_reg[base_regno] = base_regno;
+ reg_symbol_ref[base_regno] = NULL_RTX;
reg_offset[base_regno] = 0;
reg_set_luid[base_regno] = move2add_luid;
reg_mode[base_regno] = mode;
@@ -1558,6 +1738,7 @@
/* Copy base information from our base register. */
reg_set_luid[regno] = reg_set_luid[base_regno];
reg_base_reg[regno] = reg_base_reg[base_regno];
+ reg_symbol_ref[regno] = reg_symbol_ref[base_regno];
/* Compute the sum of the offsets or constants. */
reg_offset[regno] = trunc_int_for_mode (offset
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99315.patch
-57
View File
@@ -1,57 +0,0 @@
2010-08-03 Chung-Lin Tang <cltang@codesourcery.com>
Backport from mainline:
gcc/
2010-07-28 Chung-Lin Tang <cltang@codesourcery.com>
* config/arm/arm.c (arm_pcs_default): Remove static.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_PCS or
__ARM_PCS_VFP to indicate soft/hard-float calling convention.
(arm_pcs_default): Declare.
2010-07-16 Jie Zhang <jie@codesourcery.com>
Issue #7688
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-02 13:42:24 +0000
+++ new/gcc/config/arm/arm.c 2010-08-03 13:55:46 +0000
@@ -704,7 +704,7 @@
/* The maximum number of insns to be used when loading a constant. */
static int arm_constant_limit = 3;
-static enum arm_pcs arm_pcs_default;
+enum arm_pcs arm_pcs_default;
/* For an explanation of these variables, see final_prescan_insn below. */
int arm_ccfsm_state;
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2010-07-29 16:58:56 +0000
+++ new/gcc/config/arm/arm.h 2010-08-03 10:40:56 +0000
@@ -94,7 +94,13 @@
if (arm_arch_iwmmxt) \
builtin_define ("__IWMMXT__"); \
if (TARGET_AAPCS_BASED) \
- builtin_define ("__ARM_EABI__"); \
+ { \
+ if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \
+ builtin_define ("__ARM_PCS_VFP"); \
+ else if (arm_pcs_default == ARM_PCS_AAPCS) \
+ builtin_define ("__ARM_PCS"); \
+ builtin_define ("__ARM_EABI__"); \
+ } \
} while (0)
/* The various ARM cores. */
@@ -1648,6 +1654,9 @@
ARM_PCS_UNKNOWN
};
+/* Default procedure calling standard of current compilation unit. */
+extern enum arm_pcs arm_pcs_default;
+
/* A C type for declaring a variable that is used as the first argument of
`FUNCTION_ARG' and other related values. */
typedef struct
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99316.patch
-76
View File
@@ -1,76 +0,0 @@
2010-07-20 Yao Qi <yao@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-06-07 Kazu Hirata <kazu@codesourcery.com>
Issue #8535
Backport from mainline:
gcc/
2010-06-07 Kazu Hirata <kazu@codesourcery.com>
PR rtl-optimization/44404
* auto-inc-dec.c (find_inc): Use reg_overlap_mentioned_p instead
of count_occurrences to see if it's safe to modify mem_insn.insn.
gcc/testsuite/
2010-06-07 Kazu Hirata <kazu@codesourcery.com>
PR rtl-optimization/44404
* gcc.dg/pr44404.c: New.
2010-08-03 Chung-Lin Tang <cltang@codesourcery.com>
Backport from mainline:
=== modified file 'gcc/auto-inc-dec.c'
--- old/gcc/auto-inc-dec.c 2010-04-02 18:54:46 +0000
+++ new/gcc/auto-inc-dec.c 2010-08-05 11:30:21 +0000
@@ -1068,7 +1068,7 @@
/* For the post_add to work, the result_reg of the inc must not be
used in the mem insn since this will become the new index
register. */
- if (count_occurrences (PATTERN (mem_insn.insn), inc_insn.reg_res, 1) != 0)
+ if (reg_overlap_mentioned_p (inc_insn.reg_res, PATTERN (mem_insn.insn)))
{
if (dump_file)
fprintf (dump_file, "base reg replacement failure.\n");
=== added file 'gcc/testsuite/gcc.dg/pr44404.c'
--- old/gcc/testsuite/gcc.dg/pr44404.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.dg/pr44404.c 2010-08-05 11:30:21 +0000
@@ -0,0 +1,35 @@
+/* PR rtl-optimization/44404
+ foo() used to be miscompiled on ARM due to a bug in auto-inc-dec.c,
+ which resulted in "strb r1, [r1], #-36". */
+
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-unroll-loops" } */
+
+extern char *strcpy (char *, const char *);
+extern int strcmp (const char*, const char*);
+extern void abort (void);
+
+char buf[128];
+
+void __attribute__((noinline))
+bar (int a, const char *p)
+{
+ if (strcmp (p, "0123456789abcdefghijklmnopqrstuvwxyz") != 0)
+ abort ();
+}
+
+void __attribute__((noinline))
+foo (int a)
+{
+ if (a)
+ bar (0, buf);
+ strcpy (buf, "0123456789abcdefghijklmnopqrstuvwxyz");
+ bar (0, buf);
+}
+
+int
+main (void)
+{
+ foo (0);
+ return 0;
+}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99318.patch
-118
View File
@@ -1,118 +0,0 @@
2010-07-24 Jie Zhang <jie@codesourcery.com>
Issue #9079
Backport from mainline:
gcc/
2010-07-23 Jie Zhang <jie@codesourcery.com>
PR target/44290
* attribs.c (decl_attributes): Insert "noinline" and "noclone"
if "naked".
* tree-sra.c (ipa_sra_preliminary_function_checks): Return
false if ! tree_versionable_function_p.
gcc/testsuite/
2010-07-23 Jie Zhang <jie@codesourcery.com>
PR target/44290
* gcc.dg/pr44290-1.c: New test.
* gcc.dg/pr44290-2.c: New test.
2010-07-22 Maxim Kuvyrkov <maxim@codesourcery.com>
Backport from FSF GCC 4.5 branch to fix PR45015:
=== modified file 'gcc/attribs.c'
--- old/gcc/attribs.c 2010-04-02 18:54:46 +0000
+++ new/gcc/attribs.c 2010-08-05 11:39:36 +0000
@@ -278,6 +278,19 @@
TREE_VALUE (cur_attr) = chainon (opts, TREE_VALUE (cur_attr));
}
+ /* A "naked" function attribute implies "noinline" and "noclone" for
+ those targets that support it. */
+ if (TREE_CODE (*node) == FUNCTION_DECL
+ && lookup_attribute_spec (get_identifier ("naked"))
+ && lookup_attribute ("naked", attributes) != NULL)
+ {
+ if (lookup_attribute ("noinline", attributes) == NULL)
+ attributes = tree_cons (get_identifier ("noinline"), NULL, attributes);
+
+ if (lookup_attribute ("noclone", attributes) == NULL)
+ attributes = tree_cons (get_identifier ("noclone"), NULL, attributes);
+ }
+
targetm.insert_attributes (*node, &attributes);
for (a = attributes; a; a = TREE_CHAIN (a))
=== added file 'gcc/testsuite/gcc.dg/pr44290-1.c'
--- old/gcc/testsuite/gcc.dg/pr44290-1.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.dg/pr44290-1.c 2010-08-05 11:39:36 +0000
@@ -0,0 +1,18 @@
+/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+static void __attribute__((naked))
+foo(void *from, void *to)
+{
+ asm volatile("dummy"::"r"(from), "r"(to));
+}
+
+unsigned int fie[2];
+
+void fum(void *to)
+{
+ foo(fie, to);
+}
+
+/* { dg-final { scan-tree-dump "foo \\\(void \\\* from, void \\\* to\\\)" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
=== added file 'gcc/testsuite/gcc.dg/pr44290-2.c'
--- old/gcc/testsuite/gcc.dg/pr44290-2.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.dg/pr44290-2.c 2010-08-05 11:39:36 +0000
@@ -0,0 +1,24 @@
+/* { dg-do compile { target arm*-*-* avr-*-* mcore-*-* rx-*-* spu-*-* } } */
+/* { dg-options "-O2 -fdump-tree-optimized" } */
+
+static unsigned long __attribute__((naked))
+foo (unsigned long base)
+{
+ asm volatile ("dummy");
+}
+unsigned long
+bar (void)
+{
+ static int start, set;
+
+ if (!set)
+ {
+ set = 1;
+ start = foo (0);
+ }
+
+ return foo (start);
+}
+
+/* { dg-final { scan-tree-dump "foo \\\(long unsigned int base\\\)" "optimized" } } */
+/* { dg-final { cleanup-tree-dump "optimized" } } */
=== modified file 'gcc/tree-sra.c'
--- old/gcc/tree-sra.c 2010-03-17 12:02:35 +0000
+++ new/gcc/tree-sra.c 2010-08-05 11:39:36 +0000
@@ -4096,6 +4096,13 @@
static bool
ipa_sra_preliminary_function_checks (struct cgraph_node *node)
{
+ if (!tree_versionable_function_p (current_function_decl))
+ {
+ if (dump_file)
+ fprintf (dump_file, "Function isn't allowed to be versioned.\n");
+ return false;
+ }
+
if (!cgraph_node_can_be_local_p (node))
{
if (dump_file)
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99319.patch
-197
View File
@@ -1,197 +0,0 @@
2010-07-24 Sandra Loosemore <sandra@codesourcery.com>
Backport from mainline:
2010-04-10 Wei Guozhi <carrot@google.com>
PR target/42601
gcc/
* config/arm/arm.c (arm_pic_static_addr): New function.
(legitimize_pic_address): Call arm_pic_static_addr when it detects
a static symbol.
(arm_output_addr_const_extra): Output expression for new pattern.
* config/arm/arm.md (UNSPEC_SYMBOL_OFFSET): New unspec symbol.
2010-07-22 Sandra Loosemore <sandra@codesourcery.com>
PR tree-optimization/39839
gcc/testsuite/
* gcc.target/arm/pr39839.c: New test case.
2010-07-24 Jie Zhang <jie@codesourcery.com>
Issue #9079
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-03 13:55:46 +0000
+++ new/gcc/config/arm/arm.c 2010-08-05 12:06:40 +0000
@@ -225,6 +225,7 @@
static void arm_asm_trampoline_template (FILE *);
static void arm_trampoline_init (rtx, tree, rtx);
static rtx arm_trampoline_adjust_address (rtx);
+static rtx arm_pic_static_addr (rtx orig, rtx reg);
/* Table of machine attributes. */
@@ -4986,29 +4987,16 @@
{
rtx pic_ref, address;
rtx insn;
- int subregs = 0;
-
- /* If this function doesn't have a pic register, create one now. */
- require_pic_register ();
if (reg == 0)
{
gcc_assert (can_create_pseudo_p ());
reg = gen_reg_rtx (Pmode);
-
- subregs = 1;
+ address = gen_reg_rtx (Pmode);
}
-
- if (subregs)
- address = gen_reg_rtx (Pmode);
else
address = reg;
- if (TARGET_32BIT)
- emit_insn (gen_pic_load_addr_32bit (address, orig));
- else /* TARGET_THUMB1 */
- emit_insn (gen_pic_load_addr_thumb1 (address, orig));
-
/* VxWorks does not impose a fixed gap between segments; the run-time
gap can be different from the object-file gap. We therefore can't
use GOTOFF unless we are absolutely sure that the symbol is in the
@@ -5020,16 +5008,23 @@
SYMBOL_REF_LOCAL_P (orig)))
&& NEED_GOT_RELOC
&& !TARGET_VXWORKS_RTP)
- pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
+ insn = arm_pic_static_addr (orig, reg);
else
{
+ /* If this function doesn't have a pic register, create one now. */
+ require_pic_register ();
+
+ if (TARGET_32BIT)
+ emit_insn (gen_pic_load_addr_32bit (address, orig));
+ else /* TARGET_THUMB1 */
+ emit_insn (gen_pic_load_addr_thumb1 (address, orig));
+
pic_ref = gen_const_mem (Pmode,
gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
address));
+ insn = emit_move_insn (reg, pic_ref);
}
- insn = emit_move_insn (reg, pic_ref);
-
/* Put a REG_EQUAL note on this insn, so that it can be optimized
by loop. */
set_unique_reg_note (insn, REG_EQUAL, orig);
@@ -5236,6 +5231,43 @@
emit_use (pic_reg);
}
+/* Generate code to load the address of a static var when flag_pic is set. */
+static rtx
+arm_pic_static_addr (rtx orig, rtx reg)
+{
+ rtx l1, labelno, offset_rtx, insn;
+
+ gcc_assert (flag_pic);
+
+ /* We use an UNSPEC rather than a LABEL_REF because this label
+ never appears in the code stream. */
+ labelno = GEN_INT (pic_labelno++);
+ l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
+ l1 = gen_rtx_CONST (VOIDmode, l1);
+
+ /* On the ARM the PC register contains 'dot + 8' at the time of the
+ addition, on the Thumb it is 'dot + 4'. */
+ offset_rtx = plus_constant (l1, TARGET_ARM ? 8 : 4);
+ offset_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, orig, offset_rtx),
+ UNSPEC_SYMBOL_OFFSET);
+ offset_rtx = gen_rtx_CONST (Pmode, offset_rtx);
+
+ if (TARGET_32BIT)
+ {
+ emit_insn (gen_pic_load_addr_32bit (reg, offset_rtx));
+ if (TARGET_ARM)
+ insn = emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
+ else
+ insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
+ }
+ else /* TARGET_THUMB1 */
+ {
+ emit_insn (gen_pic_load_addr_thumb1 (reg, offset_rtx));
+ insn = emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
+ }
+
+ return insn;
+}
/* Return nonzero if X is valid as an ARM state addressing register. */
static int
@@ -21461,6 +21493,16 @@
fputc (')', fp);
return TRUE;
}
+ else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_SYMBOL_OFFSET)
+ {
+ output_addr_const (fp, XVECEXP (x, 0, 0));
+ if (GOT_PCREL)
+ fputs ("+.", fp);
+ fputs ("-(", fp);
+ output_addr_const (fp, XVECEXP (x, 0, 1));
+ fputc (')', fp);
+ return TRUE;
+ }
else if (GET_CODE (x) == CONST_VECTOR)
return arm_emit_vector_const (fp, x);
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2010-07-30 14:17:05 +0000
+++ new/gcc/config/arm/arm.md 2010-08-05 12:06:40 +0000
@@ -101,6 +101,8 @@
; a given symbolic address.
(UNSPEC_THUMB1_CASESI 25) ; A Thumb1 compressed dispatch-table call.
(UNSPEC_RBIT 26) ; rbit operation.
+ (UNSPEC_SYMBOL_OFFSET 27) ; The offset of the start of the symbol from
+ ; another symbolic address.
]
)
=== added file 'gcc/testsuite/gcc.target/arm/pr39839.c'
--- old/gcc/testsuite/gcc.target/arm/pr39839.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/pr39839.c 2010-08-05 12:06:40 +0000
@@ -0,0 +1,24 @@
+/* { dg-options "-mthumb -Os -march=armv5te -mthumb-interwork -fpic" } */
+/* { dg-require-effective-target arm_thumb1_ok } */
+/* { dg-final { scan-assembler-not "str\[\\t \]*r.,\[\\t \]*.sp," } } */
+
+struct S
+{
+ int count;
+ char *addr;
+};
+
+void func(const char*, const char*, int, const char*);
+
+/* This function should not need to spill to the stack. */
+void test(struct S *p)
+{
+ int off = p->count;
+ while (p->count >= 0)
+ {
+ const char *s = "xyz";
+ if (*p->addr) s = "pqr";
+ func("abcde", p->addr + off, off, s);
+ p->count--;
+ }
+}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99320.patch
-138
View File
@@ -1,138 +0,0 @@
2010-08-05 Andrew Stubbs <ams@codesourcery.com>
gcc/testsuite/
* gcc.dg/vect/vect-shift-2.c: Revert all previous changes.
* gcc.dg/vect/vect-shift-4.c: New file.
2010-07-20 Yao Qi <yao@codesourcery.com>
Merge from Sourcery G++ 4.4:
2009-06-16 Daniel Jacobowitz <dan@codesourcery.com>
Merge from Sourcery G++ 4.3:
2008-12-03 Daniel Jacobowitz <dan@codesourcery.com>
gcc/testsuite/
* gcc.dg/vect/vect-shift-2.c, gcc.dg/vect/vect-shift-3.c: New.
* lib/target-supports.exp (check_effective_target_vect_shift_char): New
function.
2010-07-24 Sandra Loosemore <sandra@codesourcery.com>
Backport from mainline:
=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-3.c'
--- old/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.dg/vect/vect-shift-3.c 2010-08-05 14:13:43 +0000
@@ -0,0 +1,37 @@
+/* { dg-require-effective-target vect_shift } */
+/* { dg-require-effective-target vect_int } */
+
+#include "tree-vect.h"
+
+#define N 32
+
+unsigned short dst[N] __attribute__((aligned(N)));
+unsigned short src[N] __attribute__((aligned(N)));
+
+__attribute__ ((noinline))
+void array_shift(void)
+{
+ int i;
+ for (i = 0; i < N; i++)
+ dst[i] = src[i] >> 3;
+}
+
+int main()
+{
+ volatile int i;
+ check_vect ();
+
+ for (i = 0; i < N; i++)
+ src[i] = i << 3;
+
+ array_shift ();
+
+ for (i = 0; i < N; i++)
+ if (dst[i] != i)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
=== added file 'gcc/testsuite/gcc.dg/vect/vect-shift-4.c'
--- old/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.dg/vect/vect-shift-4.c 2010-08-05 14:13:43 +0000
@@ -0,0 +1,37 @@
+/* { dg-require-effective-target vect_shift_char } */
+/* { dg-require-effective-target vect_int } */
+
+#include "tree-vect.h"
+
+#define N 32
+
+unsigned char dst[N] __attribute__((aligned(N)));
+unsigned char src[N] __attribute__((aligned(N)));
+
+__attribute__ ((noinline))
+void array_shift(void)
+{
+ int i;
+ for (i = 0; i < N; i++)
+ dst[i] = src[i] >> 3;
+}
+
+int main()
+{
+ volatile int i;
+ check_vect ();
+
+ for (i = 0; i < N; i++)
+ src[i] = i << 3;
+
+ array_shift ();
+
+ for (i = 0; i < N; i++)
+ if (dst[i] != i)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */
=== modified file 'gcc/testsuite/lib/target-supports.exp'
--- old/gcc/testsuite/lib/target-supports.exp 2010-07-29 15:38:15 +0000
+++ new/gcc/testsuite/lib/target-supports.exp 2010-08-05 14:13:43 +0000
@@ -2001,6 +2001,26 @@
return $et_vect_shift_saved
}
+# Return 1 if the target supports hardware vector shift operation for char.
+
+proc check_effective_target_vect_shift_char { } {
+ global et_vect_shift_char_saved
+
+ if [info exists et_vect_shift_char_saved] {
+ verbose "check_effective_target_vect_shift_char: using cached result" 2
+ } else {
+ set et_vect_shift_char_saved 0
+ if { ([istarget powerpc*-*-*]
+ && ![istarget powerpc-*-linux*paired*])
+ || [check_effective_target_arm32] } {
+ set et_vect_shift_char_saved 1
+ }
+ }
+
+ verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2
+ return $et_vect_shift_char_saved
+}
+
# Return 1 if the target supports hardware vectors of long, 0 otherwise.
#
# This can change for different subtargets so do not cache the result.
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99321.patch
-28
View File
@@ -1,28 +0,0 @@
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2007-07-05 Mark Shinwell <shinwell@codesourcery.com>
gcc/
* config/arm/arm.h (BRANCH_COST): Set to 1 when optimizing for size
on Thumb-2.
2010-08-05 Andrew Stubbs <ams@codesourcery.com>
gcc/testsuite/
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2010-08-03 10:40:56 +0000
+++ new/gcc/config/arm/arm.h 2010-08-05 14:29:52 +0000
@@ -2210,7 +2210,8 @@
/* Try to generate sequences that don't involve branches, we can then use
conditional instructions */
#define BRANCH_COST(speed_p, predictable_p) \
- (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
+ (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \
+ : (optimize > 0 ? 2 : 0))
/* Position Independent Code. */
/* We decide which register to use based on the compilation options and
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99322.patch
-53
View File
@@ -1,53 +0,0 @@
2007-06-06 Joseph Myers <joseph@codesourcery.com>
gcc/
* config/arm/arm.h (VALID_IWMMXT_REG_MODE): Allow SImode.
(ARM_LEGITIMIZE_RELOAD_ADDRESS): Reduce range allowed for SImode
offsets with iWMMXt.
* config/arm/arm.c (arm_hard_regno_mode_ok): Update for change to
VALID_IWMMXT_REG_MODE.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2007-07-05 Mark Shinwell <shinwell@codesourcery.com>
gcc/
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-05 12:06:40 +0000
+++ new/gcc/config/arm/arm.c 2010-08-05 14:33:31 +0000
@@ -16538,7 +16538,7 @@
return mode == SImode;
if (IS_IWMMXT_REGNUM (regno))
- return VALID_IWMMXT_REG_MODE (mode);
+ return VALID_IWMMXT_REG_MODE (mode) && mode != SImode;
}
/* We allow almost any value to be stored in the general registers.
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2010-08-05 14:29:52 +0000
+++ new/gcc/config/arm/arm.h 2010-08-05 14:33:31 +0000
@@ -1077,7 +1077,7 @@
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
#define VALID_IWMMXT_REG_MODE(MODE) \
- (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
+ (arm_vector_mode_supported_p (MODE) || (MODE) == DImode || (MODE) == SImode)
/* Modes valid for Neon D registers. */
#define VALID_NEON_DREG_MODE(MODE) \
@@ -1364,6 +1364,9 @@
else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
/* Need to be careful, -256 is not a valid offset. */ \
low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
+ else if (TARGET_REALLY_IWMMXT && MODE == SImode) \
+ /* Need to be careful, -1024 is not a valid offset. */ \
+ low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
else if (MODE == SImode \
|| (MODE == SFmode && TARGET_SOFT_FLOAT) \
|| ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99323.patch
-688
View File
@@ -1,688 +0,0 @@
Vladimir Prus <vladimir@codesourcery.com>
Julian Brown <julian@codesourcery.com>
gcc/
* config/arm/arm.c (arm_override_options): Warn if mlow-irq-latency is
specified in Thumb mode.
(load_multiple_sequence): Return 0 if low irq latency is requested.
(store_multiple_sequence): Likewise.
(arm_gen_load_multiple): Load registers one-by-one if low irq latency
is requested.
(arm_gen_store_multiple): Likewise.
(vfp_output_fldmd): When low_irq_latency is non zero, pop each
register separately.
(vfp_emit_fstmd): When low_irq_latency is non zero, save each register
separately.
(arm_get_vfp_saved_size): Adjust saved register size calculation for
the above changes.
(print_pop_reg_by_ldr): New.
(arm_output_epilogue): Use print_pop_reg_by_ldr when low irq latency
is requested.
(emit_multi_reg_push): Push registers separately if low irq latency
is requested.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set __low_irq_latency__.
(low_irq_latency): Define.
(USE_RETURN_INSN): Don't use return insn when low irq latency is
requested.
* config/arm/lib1funcs.asm (do_pop, do_push): Define as variadic
macros. When __low_irq_latency__ is defined, push and pop registers
individually.
(div0): Use correct punctuation.
* config/arm/ieee754-df.S: Adjust syntax of using do_push.
* config/arm/ieee754-sf.S: Likewise.
* config/arm/bpabi.S: Likewise.
* config/arm/arm.opt (mlow-irq-latency): New option.
* config/arm/predicates.md (load_multiple_operation): Return false is
low irq latency is requested.
(store_multiple_operation): Likewise.
* config/arm/arm.md (movmemqi): Don't use it if low irq latency is
requested.
* doc/invoke.texi (-mlow-irq-latency): Add documentation.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2007-06-06 Joseph Myers <joseph@codesourcery.com>
gcc/
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-05 14:33:31 +0000
+++ new/gcc/config/arm/arm.c 2010-08-05 15:20:54 +0000
@@ -1884,6 +1884,13 @@
/* Register global variables with the garbage collector. */
arm_add_gc_roots ();
+
+ if (low_irq_latency && TARGET_THUMB)
+ {
+ warning (0,
+ "-mlow-irq-latency has no effect when compiling for Thumb");
+ low_irq_latency = 0;
+ }
}
static void
@@ -9053,6 +9060,9 @@
int base_reg = -1;
int i;
+ if (low_irq_latency)
+ return 0;
+
/* Can only handle 2, 3, or 4 insns at present,
though could be easily extended if required. */
gcc_assert (nops >= 2 && nops <= 4);
@@ -9282,6 +9292,9 @@
int base_reg = -1;
int i;
+ if (low_irq_latency)
+ return 0;
+
/* Can only handle 2, 3, or 4 insns at present, though could be easily
extended if required. */
gcc_assert (nops >= 2 && nops <= 4);
@@ -9489,7 +9502,7 @@
As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
for counts of 3 or 4 regs. */
- if (arm_tune_xscale && count <= 2 && ! optimize_size)
+ if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
{
rtx seq;
@@ -9552,7 +9565,7 @@
/* See arm_gen_load_multiple for discussion of
the pros/cons of ldm/stm usage for XScale. */
- if (arm_tune_xscale && count <= 2 && ! optimize_size)
+ if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
{
rtx seq;
@@ -11795,6 +11808,21 @@
vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
{
int i;
+ int offset;
+
+ if (low_irq_latency)
+ {
+ /* Output a sequence of FLDD instructions. */
+ offset = 0;
+ for (i = reg; i < reg + count; ++i, offset += 8)
+ {
+ fputc ('\t', stream);
+ asm_fprintf (stream, "fldd\td%d, [%r,#%d]\n", i, base, offset);
+ }
+ asm_fprintf (stream, "\tadd\tsp, sp, #%d\n", count * 8);
+ return;
+ }
+
/* Workaround ARM10 VFPr1 bug. */
if (count == 2 && !arm_arch6)
@@ -11865,6 +11893,56 @@
rtx tmp, reg;
int i;
+ if (low_irq_latency)
+ {
+ int saved_size;
+ rtx sp_insn;
+
+ if (!count)
+ return 0;
+
+ saved_size = count * GET_MODE_SIZE (DFmode);
+
+ /* Since fstd does not have postdecrement addressing mode,
+ we first decrement stack pointer and then use base+offset
+ stores for VFP registers. The ARM EABI unwind information
+ can't easily describe base+offset loads, so we attach
+ a note for the effects of the whole block in the first insn,
+ and avoid marking the subsequent instructions
+ with RTX_FRAME_RELATED_P. */
+ sp_insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
+ GEN_INT (-saved_size));
+ sp_insn = emit_insn (sp_insn);
+ RTX_FRAME_RELATED_P (sp_insn) = 1;
+
+ dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
+ XVECEXP (dwarf, 0, 0) =
+ gen_rtx_SET (VOIDmode, stack_pointer_rtx,
+ plus_constant (stack_pointer_rtx, -saved_size));
+
+ /* push double VFP registers to stack */
+ for (i = 0; i < count; ++i )
+ {
+ rtx reg;
+ rtx mem;
+ rtx addr;
+ rtx insn;
+ reg = gen_rtx_REG (DFmode, base_reg + 2*i);
+ addr = (i == 0) ? stack_pointer_rtx
+ : gen_rtx_PLUS (SImode, stack_pointer_rtx,
+ GEN_INT (i * GET_MODE_SIZE (DFmode)));
+ mem = gen_frame_mem (DFmode, addr);
+ insn = emit_move_insn (mem, reg);
+ XVECEXP (dwarf, 0, i+1) =
+ gen_rtx_SET (VOIDmode, mem, reg);
+ }
+
+ REG_NOTES (sp_insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
+ REG_NOTES (sp_insn));
+
+ return saved_size;
+ }
+
/* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
register pairs are stored by a store multiple insn. We avoid this
by pushing an extra pair. */
@@ -13307,7 +13385,7 @@
if (count > 0)
{
/* Workaround ARM10 VFPr1 bug. */
- if (count == 2 && !arm_arch6)
+ if (count == 2 && !arm_arch6 && !low_irq_latency)
count++;
saved += count * 8;
}
@@ -13645,6 +13723,41 @@
}
+/* Generate to STREAM a code sequence that pops registers identified
+ in REGS_MASK from SP. SP is incremented as the result.
+*/
+static void
+print_pop_reg_by_ldr (FILE *stream, int regs_mask, int rfe)
+{
+ int reg;
+
+ gcc_assert (! (regs_mask & (1 << SP_REGNUM)));
+
+ for (reg = 0; reg < PC_REGNUM; ++reg)
+ if (regs_mask & (1 << reg))
+ asm_fprintf (stream, "\tldr\t%r, [%r], #4\n",
+ reg, SP_REGNUM);
+
+ if (regs_mask & (1 << PC_REGNUM))
+ {
+ if (rfe)
+ /* When returning from exception, we need to
+ copy SPSR to CPSR. There are two ways to do
+ that: the ldm instruction with "^" suffix,
+ and movs instruction. The latter would
+ require that we load from stack to some
+ scratch register, and then move to PC.
+ Therefore, we'd need extra instruction and
+ have to make sure we actually have a spare
+ register. Using ldm with a single register
+ is simler. */
+ asm_fprintf (stream, "\tldm\tsp!, {pc}^\n");
+ else
+ asm_fprintf (stream, "\tldr\t%r, [%r], #4\n",
+ PC_REGNUM, SP_REGNUM);
+ }
+}
+
const char *
arm_output_epilogue (rtx sibling)
{
@@ -14018,22 +14131,19 @@
to load use the LDR instruction - it is faster. For Thumb-2
always use pop and the assembler will pick the best instruction.*/
if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
- && !IS_INTERRUPT(func_type))
+ && !IS_INTERRUPT (func_type))
{
asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
}
else if (saved_regs_mask)
{
- if (saved_regs_mask & (1 << SP_REGNUM))
- /* Note - write back to the stack register is not enabled
- (i.e. "ldmfd sp!..."). We know that the stack pointer is
- in the list of registers and if we add writeback the
- instruction becomes UNPREDICTABLE. */
- print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
- rfe);
- else if (TARGET_ARM)
- print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
- rfe);
+ gcc_assert ( ! (saved_regs_mask & (1 << SP_REGNUM)));
+ if (TARGET_ARM)
+ if (low_irq_latency)
+ print_pop_reg_by_ldr (f, saved_regs_mask, rfe);
+ else
+ print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
+ rfe);
else
print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
}
@@ -14154,6 +14264,32 @@
gcc_assert (num_regs && num_regs <= 16);
+ if (low_irq_latency)
+ {
+ rtx insn = 0;
+
+ /* Emit a series of ldr instructions rather rather than a single ldm. */
+ /* TODO: Use ldrd where possible. */
+ gcc_assert (! (mask & (1 << SP_REGNUM)));
+
+ for (i = LAST_ARM_REGNUM; i >= 0; --i)
+ {
+ if (mask & (1 << i))
+
+ {
+ rtx reg, where, mem;
+
+ reg = gen_rtx_REG (SImode, i);
+ where = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
+ mem = gen_rtx_MEM (SImode, where);
+ insn = emit_move_insn (mem, reg);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
+ }
+
+ return insn;
+ }
+
/* We don't record the PC in the dwarf frame information. */
num_dwarf_regs = num_regs;
if (mask & (1 << PC_REGNUM))
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2010-08-05 14:33:31 +0000
+++ new/gcc/config/arm/arm.h 2010-08-05 15:20:54 +0000
@@ -101,6 +101,8 @@
builtin_define ("__ARM_PCS"); \
builtin_define ("__ARM_EABI__"); \
} \
+ if (low_irq_latency) \
+ builtin_define ("__low_irq_latency__"); \
} while (0)
/* The various ARM cores. */
@@ -449,6 +451,10 @@
/* Nonzero if chip supports integer division instruction. */
extern int arm_arch_hwdiv;
+/* Nonzero if we should minimize interrupt latency of the
+ generated code. */
+extern int low_irq_latency;
+
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APCS_FRAME)
#endif
@@ -1823,9 +1829,10 @@
/* Determine if the epilogue should be output as RTL.
You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
/* This is disabled for Thumb-2 because it will confuse the
- conditional insn counter. */
+ conditional insn counter.
+ Do not use a return insn if we're avoiding ldm/stm instructions. */
#define USE_RETURN_INSN(ISCOND) \
- (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0)
+ ((TARGET_ARM && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0)
/* Definitions for register eliminations.
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2010-08-05 12:06:40 +0000
+++ new/gcc/config/arm/arm.md 2010-08-05 15:20:54 +0000
@@ -6587,7 +6587,7 @@
(match_operand:BLK 1 "general_operand" "")
(match_operand:SI 2 "const_int_operand" "")
(match_operand:SI 3 "const_int_operand" "")]
- "TARGET_EITHER"
+ "TARGET_EITHER && !low_irq_latency"
"
if (TARGET_32BIT)
{
=== modified file 'gcc/config/arm/arm.opt'
--- old/gcc/config/arm/arm.opt 2009-06-18 11:24:10 +0000
+++ new/gcc/config/arm/arm.opt 2010-08-05 15:20:54 +0000
@@ -161,6 +161,10 @@
Target Report Mask(NEON_VECTORIZE_QUAD)
Use Neon quad-word (rather than double-word) registers for vectorization
+mlow-irq-latency
+Target Report Var(low_irq_latency)
+Try to reduce interrupt latency of the generated code
+
mword-relocations
Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
Only generate absolute relocations on word sized values.
=== modified file 'gcc/config/arm/bpabi.S'
--- old/gcc/config/arm/bpabi.S 2009-12-17 15:37:23 +0000
+++ new/gcc/config/arm/bpabi.S 2010-08-05 15:20:54 +0000
@@ -116,16 +116,17 @@
test_div_by_zero signed
sub sp, sp, #8
-#if defined(__thumb2__)
+/* Low latency and Thumb-2 do_push implementations can't push sp directly. */
+#if defined(__thumb2__) || defined(__irq_low_latency__)
mov ip, sp
- push {ip, lr}
+ do_push (ip, lr)
#else
- do_push {sp, lr}
+ stmfd sp!, {sp, lr}
#endif
bl SYM(__gnu_ldivmod_helper) __PLT__
ldr lr, [sp, #4]
add sp, sp, #8
- do_pop {r2, r3}
+ do_pop (r2, r3)
RET
#endif /* L_aeabi_ldivmod */
@@ -136,16 +137,17 @@
test_div_by_zero unsigned
sub sp, sp, #8
-#if defined(__thumb2__)
+/* Low latency and Thumb-2 do_push implementations can't push sp directly. */
+#if defined(__thumb2__) || defined(__irq_low_latency__)
mov ip, sp
- push {ip, lr}
+ do_push (ip, lr)
#else
- do_push {sp, lr}
+ stmfd sp!, {sp, lr}
#endif
bl SYM(__gnu_uldivmod_helper) __PLT__
ldr lr, [sp, #4]
add sp, sp, #8
- do_pop {r2, r3}
+ do_pop (r2, r3)
RET
#endif /* L_aeabi_divmod */
=== modified file 'gcc/config/arm/ieee754-df.S'
--- old/gcc/config/arm/ieee754-df.S 2009-06-05 12:52:36 +0000
+++ new/gcc/config/arm/ieee754-df.S 2010-08-05 15:20:54 +0000
@@ -83,7 +83,7 @@
ARM_FUNC_START adddf3
ARM_FUNC_ALIAS aeabi_dadd adddf3
-1: do_push {r4, r5, lr}
+1: do_push (r4, r5, lr)
@ Look for zeroes, equal values, INF, or NAN.
shift1 lsl, r4, xh, #1
@@ -427,7 +427,7 @@
do_it eq, t
moveq r1, #0
RETc(eq)
- do_push {r4, r5, lr}
+ do_push (r4, r5, lr)
mov r4, #0x400 @ initial exponent
add r4, r4, #(52-1 - 1)
mov r5, #0 @ sign bit is 0
@@ -447,7 +447,7 @@
do_it eq, t
moveq r1, #0
RETc(eq)
- do_push {r4, r5, lr}
+ do_push (r4, r5, lr)
mov r4, #0x400 @ initial exponent
add r4, r4, #(52-1 - 1)
ands r5, r0, #0x80000000 @ sign bit in r5
@@ -481,7 +481,7 @@
RETc(eq) @ we are done already.
@ value was denormalized. We can normalize it now.
- do_push {r4, r5, lr}
+ do_push (r4, r5, lr)
mov r4, #0x380 @ setup corresponding exponent
and r5, xh, #0x80000000 @ move sign bit in r5
bic xh, xh, #0x80000000
@@ -508,9 +508,9 @@
@ compatibility.
adr ip, LSYM(f0_ret)
@ Push pc as well so that RETLDM works correctly.
- do_push {r4, r5, ip, lr, pc}
+ do_push (r4, r5, ip, lr, pc)
#else
- do_push {r4, r5, lr}
+ do_push (r4, r5, lr)
#endif
mov r5, #0
@@ -534,9 +534,9 @@
@ compatibility.
adr ip, LSYM(f0_ret)
@ Push pc as well so that RETLDM works correctly.
- do_push {r4, r5, ip, lr, pc}
+ do_push (r4, r5, ip, lr, pc)
#else
- do_push {r4, r5, lr}
+ do_push (r4, r5, lr)
#endif
ands r5, ah, #0x80000000 @ sign bit in r5
@@ -585,7 +585,7 @@
@ Legacy code expects the result to be returned in f0. Copy it
@ there as well.
LSYM(f0_ret):
- do_push {r0, r1}
+ do_push (r0, r1)
ldfd f0, [sp], #8
RETLDM
@@ -602,7 +602,7 @@
ARM_FUNC_START muldf3
ARM_FUNC_ALIAS aeabi_dmul muldf3
- do_push {r4, r5, r6, lr}
+ do_push (r4, r5, r6, lr)
@ Mask out exponents, trap any zero/denormal/INF/NAN.
mov ip, #0xff
@@ -910,7 +910,7 @@
ARM_FUNC_START divdf3
ARM_FUNC_ALIAS aeabi_ddiv divdf3
- do_push {r4, r5, r6, lr}
+ do_push (r4, r5, r6, lr)
@ Mask out exponents, trap any zero/denormal/INF/NAN.
mov ip, #0xff
@@ -1195,7 +1195,7 @@
@ The status-returning routines are required to preserve all
@ registers except ip, lr, and cpsr.
-6: do_push {r0, lr}
+6: do_push (r0, lr)
ARM_CALL cmpdf2
@ Set the Z flag correctly, and the C flag unconditionally.
cmp r0, #0
=== modified file 'gcc/config/arm/ieee754-sf.S'
--- old/gcc/config/arm/ieee754-sf.S 2009-06-05 12:52:36 +0000
+++ new/gcc/config/arm/ieee754-sf.S 2010-08-05 15:20:54 +0000
@@ -481,7 +481,7 @@
and r3, ip, #0x80000000
@ Well, no way to make it shorter without the umull instruction.
- do_push {r3, r4, r5}
+ do_push (r3, r4, r5)
mov r4, r0, lsr #16
mov r5, r1, lsr #16
bic r0, r0, r4, lsl #16
@@ -492,7 +492,7 @@
mla r0, r4, r1, r0
adds r3, r3, r0, lsl #16
adc r1, ip, r0, lsr #16
- do_pop {r0, r4, r5}
+ do_pop (r0, r4, r5)
#else
@@ -882,7 +882,7 @@
@ The status-returning routines are required to preserve all
@ registers except ip, lr, and cpsr.
-6: do_push {r0, r1, r2, r3, lr}
+6: do_push (r0, r1, r2, r3, lr)
ARM_CALL cmpsf2
@ Set the Z flag correctly, and the C flag unconditionally.
cmp r0, #0
=== modified file 'gcc/config/arm/lib1funcs.asm'
--- old/gcc/config/arm/lib1funcs.asm 2010-04-02 18:54:46 +0000
+++ new/gcc/config/arm/lib1funcs.asm 2010-08-05 15:20:54 +0000
@@ -254,8 +254,8 @@
.macro shift1 op, arg0, arg1, arg2
\op \arg0, \arg1, \arg2
.endm
-#define do_push push
-#define do_pop pop
+#define do_push(...) push {__VA_ARGS__}
+#define do_pop(...) pop {__VA_ARGS__}
#define COND(op1, op2, cond) op1 ## op2 ## cond
/* Perform an arithmetic operation with a variable shift operand. This
requires two instructions and a scratch register on Thumb-2. */
@@ -269,8 +269,42 @@
.macro shift1 op, arg0, arg1, arg2
mov \arg0, \arg1, \op \arg2
.endm
-#define do_push stmfd sp!,
-#define do_pop ldmfd sp!,
+#if defined(__low_irq_latency__)
+#define do_push(...) \
+ _buildN1(do_push, _buildC1(__VA_ARGS__))( __VA_ARGS__)
+#define _buildN1(BASE, X) _buildN2(BASE, X)
+#define _buildN2(BASE, X) BASE##X
+#define _buildC1(...) _buildC2(__VA_ARGS__,9,8,7,6,5,4,3,2,1)
+#define _buildC2(a1,a2,a3,a4,a5,a6,a7,a8,a9,c,...) c
+
+#define do_push1(r1) str r1, [sp, #-4]!
+#define do_push2(r1, r2) str r2, [sp, #-4]! ; str r1, [sp, #-4]!
+#define do_push3(r1, r2, r3) str r3, [sp, #-4]! ; str r2, [sp, #-4]!; str r1, [sp, #-4]!
+#define do_push4(r1, r2, r3, r4) \
+ do_push3 (r2, r3, r4);\
+ do_push1 (r1)
+#define do_push5(r1, r2, r3, r4, r5) \
+ do_push4 (r2, r3, r4, r5);\
+ do_push1 (r1)
+
+#define do_pop(...) \
+_buildN1(do_pop, _buildC1(__VA_ARGS__))( __VA_ARGS__)
+
+#define do_pop1(r1) ldr r1, [sp], #4
+#define do_pop2(r1, r2) ldr r1, [sp], #4 ; ldr r2, [sp], #4
+#define do_pop3(r1, r2, r3) ldr r1, [sp], #4 ; str r2, [sp], #4; str r3, [sp], #4
+#define do_pop4(r1, r2, r3, r4) \
+ do_pop1 (r1);\
+ do_pup3 (r2, r3, r4)
+#define do_pop5(r1, r2, r3, r4, r5) \
+ do_pop1 (r1);\
+ do_pop4 (r2, r3, r4, r5)
+#else
+#define do_push(...) stmfd sp!, { __VA_ARGS__}
+#define do_pop(...) ldmfd sp!, {__VA_ARGS__}
+#endif
+
+
#define COND(op1, op2, cond) op1 ## cond ## op2
.macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp
\name \dest, \src1, \src2, \shiftop \shiftreg
@@ -1260,7 +1294,7 @@
ARM_FUNC_START div0
#endif
- do_push {r1, lr}
+ do_push (r1, lr)
mov r0, #SIGFPE
bl SYM(raise) __PLT__
RETLDM r1
@@ -1277,7 +1311,7 @@
#if defined __ARM_EABI__ && defined __linux__
@ EABI GNU/Linux call to cacheflush syscall.
ARM_FUNC_START clear_cache
- do_push {r7}
+ do_push (r7)
#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__)
movw r7, #2
movt r7, #0xf
@@ -1287,7 +1321,7 @@
#endif
mov r2, #0
swi 0
- do_pop {r7}
+ do_pop (r7)
RET
FUNC_END clear_cache
#else
@@ -1490,7 +1524,7 @@
push {r4, lr}
# else
ARM_FUNC_START clzdi2
- do_push {r4, lr}
+ do_push (r4, lr)
# endif
cmp xxh, #0
bne 1f
=== modified file 'gcc/config/arm/predicates.md'
--- old/gcc/config/arm/predicates.md 2010-07-30 14:17:05 +0000
+++ new/gcc/config/arm/predicates.md 2010-08-05 15:20:54 +0000
@@ -328,6 +328,9 @@
HOST_WIDE_INT i = 1, base = 0;
rtx elt;
+ if (low_irq_latency)
+ return false;
+
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET)
return false;
@@ -385,6 +388,9 @@
HOST_WIDE_INT i = 1, base = 0;
rtx elt;
+ if (low_irq_latency)
+ return false;
+
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET)
return false;
=== modified file 'gcc/doc/invoke.texi'
--- old/gcc/doc/invoke.texi 2010-07-29 17:03:20 +0000
+++ new/gcc/doc/invoke.texi 2010-08-05 15:20:54 +0000
@@ -469,6 +469,7 @@
-mtpcs-frame -mtpcs-leaf-frame @gol
-mcaller-super-interworking -mcallee-super-interworking @gol
-mtp=@var{name} @gol
+-mlow-irq-latency @gol
-mword-relocations @gol
-mfix-cortex-m3-ldrd}
@@ -9489,6 +9490,12 @@
@code{,}, @code{!}, @code{|}, and @code{*} as needed.
+@item -mlow-irq-latency
+@opindex mlow-irq-latency
+Avoid instructions with high interrupt latency when generating
+code. This can increase code size and reduce performance.
+The option is off by default.
+
@end table
The conditional text @code{X} in a %@{@code{S}:@code{X}@} or similar
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99324.patch
-109
View File
@@ -1,109 +0,0 @@
Julian Brown <julian@codesourcery.com>
Mark Shinwell <mark@codesourcery.com>
gcc/
* regrename.c (addresses.h): Move include of addresses.h after
include of flags.h.
* recog.c: Likewise.
* regcprop.c: Likewise.
* config/arm/arm.h (CLASS_LIKELY_SPILLED_P): Check against
LO_REGS only for Thumb-1.
(MODE_BASE_REG_CLASS): Restrict base registers to those which can
be used in short instructions when optimising for size on Thumb-2.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
Vladimir Prus <vladimir@codesourcery.com>
Julian Brown <julian@codesourcery.com>
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2010-08-05 15:20:54 +0000
+++ new/gcc/config/arm/arm.h 2010-08-05 15:28:47 +0000
@@ -1254,11 +1254,14 @@
|| reg_classes_intersect_p (VFP_REGS, (CLASS)) \
: 0)
-/* We need to define this for LO_REGS on thumb. Otherwise we can end up
- using r0-r4 for function arguments, r7 for the stack frame and don't
- have enough left over to do doubleword arithmetic. */
+/* We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
+ using r0-r4 for function arguments, r7 for the stack frame and don't have
+ enough left over to do doubleword arithmetic. For Thumb-2 all the
+ potentially problematic instructions accept high registers so this is not
+ necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
+ that require many low registers. */
#define CLASS_LIKELY_SPILLED_P(CLASS) \
- ((TARGET_THUMB && (CLASS) == LO_REGS) \
+ ((TARGET_THUMB1 && (CLASS) == LO_REGS) \
|| (CLASS) == CC_REG)
/* The class value for index registers, and the one for base regs. */
@@ -1269,7 +1272,7 @@
when addressing quantities in QI or HI mode; if we don't know the
mode, then we must be conservative. */
#define MODE_BASE_REG_CLASS(MODE) \
- (TARGET_32BIT ? CORE_REGS : \
+ (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \
(((MODE) == SImode) ? BASE_REGS : LO_REGS))
/* For Thumb we can not support SP+reg addressing, so we return LO_REGS
=== modified file 'gcc/recog.c'
--- old/gcc/recog.c 2010-04-02 18:54:46 +0000
+++ new/gcc/recog.c 2010-08-05 15:28:47 +0000
@@ -31,10 +31,10 @@
#include "hard-reg-set.h"
#include "recog.h"
#include "regs.h"
-#include "addresses.h"
#include "expr.h"
#include "function.h"
#include "flags.h"
+#include "addresses.h"
#include "real.h"
#include "toplev.h"
#include "basic-block.h"
=== modified file 'gcc/regcprop.c'
--- old/gcc/regcprop.c 2010-02-26 11:01:28 +0000
+++ new/gcc/regcprop.c 2010-08-05 15:28:47 +0000
@@ -26,7 +26,6 @@
#include "tm_p.h"
#include "insn-config.h"
#include "regs.h"
-#include "addresses.h"
#include "hard-reg-set.h"
#include "basic-block.h"
#include "reload.h"
@@ -34,6 +33,7 @@
#include "function.h"
#include "recog.h"
#include "flags.h"
+#include "addresses.h"
#include "toplev.h"
#include "obstack.h"
#include "timevar.h"
=== modified file 'gcc/regrename.c'
--- old/gcc/regrename.c 2010-04-02 18:54:46 +0000
+++ new/gcc/regrename.c 2010-08-05 15:28:47 +0000
@@ -26,7 +26,6 @@
#include "tm_p.h"
#include "insn-config.h"
#include "regs.h"
-#include "addresses.h"
#include "hard-reg-set.h"
#include "basic-block.h"
#include "reload.h"
@@ -34,6 +33,7 @@
#include "function.h"
#include "recog.h"
#include "flags.h"
+#include "addresses.h"
#include "toplev.h"
#include "obstack.h"
#include "timevar.h"
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99325.patch
-174
View File
@@ -1,174 +0,0 @@
http://gcc.gnu.org/ml/gcc-patches/2006-04/msg00811.html
Kazu Hirata <kazu@codesourcery.com>
gcc/testsuite/
* gcc.target/arm/vfp-ldmdbd.c, gcc.target/arm/vfp-ldmdbs.c,
gcc.target/arm/vfp-ldmiad.c, gcc.target/arm/vfp-ldmias.c,
gcc.target/arm/vfp-stmdbd.c, gcc.target/arm/vfp-stmdbs.c,
gcc.target/arm/vfp-stmiad.c, gcc.target/arm/vfp-stmias.c: New.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
Julian Brown <julian@codesourcery.com>
Mark Shinwell <mark@codesourcery.com>
=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c'
--- old/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c 2010-08-05 15:37:24 +0000
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void bar (double);
+
+void
+foo (double *p, double a, int n)
+{
+ do
+ bar (*--p + a);
+ while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmdbd" } } */
=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c'
--- old/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c 2010-08-05 15:37:24 +0000
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void baz (float);
+
+void
+foo (float *p, float a, int n)
+{
+ do
+ bar (*--p + a);
+ while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmdbs" } } */
=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmiad.c'
--- old/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c 2010-08-05 15:37:24 +0000
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void bar (double);
+
+void
+foo (double *p, double a, int n)
+{
+ do
+ bar (*p++ + a);
+ while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmiad" } } */
=== added file 'gcc/testsuite/gcc.target/arm/vfp-ldmias.c'
--- old/gcc/testsuite/gcc.target/arm/vfp-ldmias.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/vfp-ldmias.c 2010-08-05 15:37:24 +0000
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+extern void baz (float);
+
+void
+foo (float *p, float a, int n)
+{
+ do
+ bar (*p++ + a);
+ while (n--);
+}
+
+/* { dg-final { scan-assembler "fldmias" } } */
=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmdbd.c'
--- old/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c 2010-08-05 15:37:24 +0000
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (double *p, double a, double b, int n)
+{
+ double c = a + b;
+ do
+ *--p = c;
+ while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmdbd" } } */
=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmdbs.c'
--- old/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c 2010-08-05 15:37:24 +0000
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (float *p, float a, float b, int n)
+{
+ float c = a + b;
+ do
+ *--p = c;
+ while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmdbs" } } */
=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmiad.c'
--- old/gcc/testsuite/gcc.target/arm/vfp-stmiad.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/vfp-stmiad.c 2010-08-05 15:37:24 +0000
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (double *p, double a, double b, int n)
+{
+ double c = a + b;
+ do
+ *p++ = c;
+ while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmiad" } } */
=== added file 'gcc/testsuite/gcc.target/arm/vfp-stmias.c'
--- old/gcc/testsuite/gcc.target/arm/vfp-stmias.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/vfp-stmias.c 2010-08-05 15:37:24 +0000
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_vfp_ok } */
+/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
+
+void
+foo (float *p, float a, float b, int n)
+{
+ float c = a + b;
+ do
+ *p++ = c;
+ while (n--);
+}
+
+/* { dg-final { scan-assembler "fstmias" } } */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99326.patch
-86
View File
@@ -1,86 +0,0 @@
http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html
* g++.dg/other/armv7m-1.C: New.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
http://gcc.gnu.org/ml/gcc-patches/2006-04/msg00811.html
=== added file 'gcc/testsuite/g++.dg/other/armv7m-1.C'
--- old/gcc/testsuite/g++.dg/other/armv7m-1.C 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/g++.dg/other/armv7m-1.C 2010-08-05 16:23:43 +0000
@@ -0,0 +1,69 @@
+/* { dg-do run { target arm*-*-* } } */
+/* Test Armv7m interrupt routines. */
+#include <stdlib.h>
+
+#ifdef __ARM_ARCH_7M__
+void __attribute__((interrupt))
+foo(void)
+{
+ long long n;
+ long p;
+ asm volatile ("" : "=r" (p) : "0" (&n));
+ if (p & 4)
+ abort ();
+ return;
+}
+
+void __attribute__((interrupt))
+bar(void)
+{
+ throw 42;
+}
+
+int main()
+{
+ int a;
+ int before;
+ int after;
+ volatile register int sp asm("sp");
+
+ asm volatile ("mov %0, sp\n"
+ "blx %2\n"
+ "mov %1, sp\n"
+ : "=&r" (before), "=r" (after) : "r" (foo)
+ : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr");
+ if (before != after)
+ abort();
+ asm volatile ("mov %0, sp\n"
+ "sub sp, sp, #4\n"
+ "blx %2\n"
+ "add sp, sp, #4\n"
+ "mov %1, sp\n"
+ : "=&r" (before), "=r" (after) : "r" (foo)
+ : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr");
+ if (before != after)
+ abort();
+ before = sp;
+ try
+ {
+ bar();
+ }
+ catch (int i)
+ {
+ if (i != 42)
+ abort();
+ }
+ catch (...)
+ {
+ abort();
+ }
+ if (before != sp)
+ abort();
+ exit(0);
+}
+#else
+int main()
+{
+ exit (0);
+}
+#endif
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99327.patch
-132
View File
@@ -1,132 +0,0 @@
Backport from FSF mainline:
Mark Shinwell <shinwell@codesourcery.com>
Julian Brown <julian@codesourcery.com>
gcc/
* config/arm/thumb2.md (thumb2_movsi_insn): Split ldr and str
alternatives according to use of high and low regs.
* config/arm/vfp.md (thumb2_movsi_vfp): Likewise.
* config/arm/arm.h (CONDITIONAL_REGISTER_USAGE): Use high regs when
optimizing for size on Thumb-2.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
http://gcc.gnu.org/ml/gcc-patches/2006-03/msg00038.html
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2010-08-05 15:28:47 +0000
+++ new/gcc/config/arm/arm.h 2010-08-05 16:34:46 +0000
@@ -783,12 +783,11 @@
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
\
- if (TARGET_THUMB && optimize_size) \
- { \
- /* When optimizing for size, it's better not to use \
- the HI regs, because of the overhead of stacking \
- them. */ \
- /* ??? Is this still true for thumb2? */ \
+ if (TARGET_THUMB1 && optimize_size) \
+ { \
+ /* When optimizing for size on Thumb-1, it's better not \
+ to use the HI regs, because of the overhead of \
+ stacking them. */ \
for (regno = FIRST_HI_REGNUM; \
regno <= LAST_HI_REGNUM; ++regno) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
=== modified file 'gcc/config/arm/thumb2.md'
--- old/gcc/config/arm/thumb2.md 2010-04-02 07:32:00 +0000
+++ new/gcc/config/arm/thumb2.md 2010-08-05 16:34:46 +0000
@@ -223,9 +223,14 @@
(set_attr "neg_pool_range" "*,*,*,0,*")]
)
+;; We have two alternatives here for memory loads (and similarly for stores)
+;; to reflect the fact that the permissible constant pool ranges differ
+;; between ldr instructions taking low regs and ldr instructions taking high
+;; regs. The high register alternatives are not taken into account when
+;; choosing register preferences in order to reflect their expense.
(define_insn "*thumb2_movsi_insn"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
- (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,rk"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l, *hk,m,*m")
+ (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))]
"TARGET_THUMB2 && ! TARGET_IWMMXT
&& !(TARGET_HARD_FLOAT && TARGET_VFP)
&& ( register_operand (operands[0], SImode)
@@ -236,11 +241,13 @@
mvn%?\\t%0, #%B1
movw%?\\t%0, %1
ldr%?\\t%0, %1
+ ldr%?\\t%0, %1
+ str%?\\t%1, %0
str%?\\t%1, %0"
- [(set_attr "type" "*,*,*,*,load1,store1")
+ [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
(set_attr "predicable" "yes")
- (set_attr "pool_range" "*,*,*,*,4096,*")
- (set_attr "neg_pool_range" "*,*,*,*,0,*")]
+ (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
+ (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
)
(define_insn "tls_load_dot_plus_four"
=== modified file 'gcc/config/arm/vfp.md'
--- old/gcc/config/arm/vfp.md 2010-07-30 14:17:05 +0000
+++ new/gcc/config/arm/vfp.md 2010-08-05 16:34:46 +0000
@@ -86,9 +86,11 @@
(set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
)
+;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
+;; high/low register alternatives for loads and stores here.
(define_insn "*thumb2_movsi_vfp"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
- (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l,*hk,m,*m,*t,r, *t,*t, *Uv")
+ (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,*mi,l,*hk,r,*t,*t,*Uvi,*t"))]
"TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
&& ( s_register_operand (operands[0], SImode)
|| s_register_operand (operands[1], SImode))"
@@ -102,25 +104,27 @@
case 3:
return \"movw%?\\t%0, %1\";
case 4:
+ case 5:
return \"ldr%?\\t%0, %1\";
- case 5:
+ case 6:
+ case 7:
return \"str%?\\t%1, %0\";
- case 6:
+ case 8:
return \"fmsr%?\\t%0, %1\\t%@ int\";
- case 7:
+ case 9:
return \"fmrs%?\\t%0, %1\\t%@ int\";
- case 8:
+ case 10:
return \"fcpys%?\\t%0, %1\\t%@ int\";
- case 9: case 10:
+ case 11: case 12:
return output_move_vfp (operands);
default:
gcc_unreachable ();
}
"
[(set_attr "predicable" "yes")
- (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
- (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
- (set_attr "neg_pool_range" "*,*,*,*, 0,*,*,*,*,1008,*")]
+ (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
+ (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
+ (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
)
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99332.patch
-68
View File
@@ -1,68 +0,0 @@
2010-08-06 Yao Qi <yao@codesourcery.com>
LP: #612011
gcc/
* config/arm/arm.c (output_move_double): Fix typo generating
instructions ('ldr'->'str').
gcc/testsuite/
* gcc.target/arm/pr45094.c: New test.
2010-08-02 Ulrich Weigand <uweigand@de.ibm.com>
LP: #604874
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-10 13:31:21 +0000
+++ new/gcc/config/arm/arm.c 2010-08-10 14:03:02 +0000
@@ -12506,13 +12506,13 @@
{
if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
{
- output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
- output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops);
+ output_asm_insn ("str%?\t%0, [%1, %2]!", otherops);
+ output_asm_insn ("str%?\t%H0, [%1, #4]", otherops);
}
else
{
- output_asm_insn ("ldr%?\t%H0, [%1, #4]", otherops);
- output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
+ output_asm_insn ("str%?\t%H0, [%1, #4]", otherops);
+ output_asm_insn ("str%?\t%0, [%1], %2", otherops);
}
}
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
=== added file 'gcc/testsuite/gcc.target/arm/pr45094.c'
--- old/gcc/testsuite/gcc.target/arm/pr45094.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/pr45094.c 2010-08-06 05:10:03 +0000
@@ -0,0 +1,27 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_hw } */
+/* { dg-options "-O2 -mcpu=cortex-a8" } */
+/* { dg-add-options arm_neon } */
+
+#include <stdlib.h>
+
+long long buffer[32];
+
+void __attribute__((noinline)) f(long long *p, int n)
+{
+ while (--n >= 0)
+ {
+ *p = 1;
+ p += 32;
+ }
+}
+
+int main(void)
+{
+ f(buffer, 1);
+
+ if (!buffer[0])
+ abort();
+
+ return 0;
+}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99335.patch
-138
View File
@@ -1,138 +0,0 @@
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
Mark Shinwell <shinwell@codesourcery.com>
gcc/
* config/arm/vfp.md (*arm_movsi_vfp, *thumb2_movsi_vfp)
(*arm_movdi_vfp, *thumb2_movdi_vfp, *movsf_vfp, *thumb2_movsf_vfp)
(*movdf_vfp, *thumb2_movdf_vfp, *movsfcc_vfp, *thumb2_movsfcc_vfp)
(*movdfcc_vfp, *thumb2_movdfcc_vfp): Add neon_type.
* config/arm/arm.md (neon_type): Update comment.
2010-08-10 Andrew Stubbs <ams@codesourcery.com>
gcc/
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2010-08-10 13:31:21 +0000
+++ new/gcc/config/arm/arm.md 2010-08-12 11:29:02 +0000
@@ -255,8 +255,6 @@
(define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
;; Classification of NEON instructions for scheduling purposes.
-;; Do not set this attribute and the "type" attribute together in
-;; any one instruction pattern.
(define_attr "neon_type"
"neon_int_1,\
neon_int_2,\
=== modified file 'gcc/config/arm/vfp.md'
--- old/gcc/config/arm/vfp.md 2010-08-10 13:31:21 +0000
+++ new/gcc/config/arm/vfp.md 2010-08-12 11:29:02 +0000
@@ -82,6 +82,7 @@
"
[(set_attr "predicable" "yes")
(set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
+ (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
(set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
)
@@ -123,6 +124,7 @@
"
[(set_attr "predicable" "yes")
(set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
+ (set_attr "neon_type" "*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
(set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
)
@@ -160,6 +162,7 @@
}
"
[(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
+ (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
(set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
(eq_attr "alternative" "5")
(if_then_else
@@ -198,6 +201,7 @@
}
"
[(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
+ (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
(set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
(eq_attr "alternative" "5")
(if_then_else
@@ -352,6 +356,7 @@
[(set_attr "predicable" "yes")
(set_attr "type"
"r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
+ (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
(set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
)
@@ -388,6 +393,7 @@
[(set_attr "predicable" "yes")
(set_attr "type"
"r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*")
+ (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
(set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
(set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
)
@@ -430,6 +436,7 @@
"
[(set_attr "type"
"r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
+ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
(set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
@@ -474,6 +481,7 @@
"
[(set_attr "type"
"r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
+ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
(set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
@@ -509,7 +517,8 @@
fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
[(set_attr "conds" "use")
(set_attr "length" "4,4,8,4,4,8,4,4,8")
- (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
+ (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
+ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
)
(define_insn "*thumb2_movsfcc_vfp"
@@ -532,7 +541,8 @@
ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
[(set_attr "conds" "use")
(set_attr "length" "6,6,10,6,6,10,6,6,10")
- (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
+ (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
+ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
)
(define_insn "*movdfcc_vfp"
@@ -555,7 +565,8 @@
fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
[(set_attr "conds" "use")
(set_attr "length" "4,4,8,4,4,8,4,4,8")
- (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
+ (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
+ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
)
(define_insn "*thumb2_movdfcc_vfp"
@@ -578,7 +589,8 @@
ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
[(set_attr "conds" "use")
(set_attr "length" "6,6,10,6,6,10,6,6,10")
- (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
+ (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
+ (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
)
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99336.patch
-95
View File
@@ -1,95 +0,0 @@
gcc/
* config/arm/arm.c (arm_override_options): Override alignments if
tuning for Cortex-A8.
(create_fix_barrier, arm_reorg): If aligning to jumps or loops,
make labels have a size.
* config/arm/arm.md (VUNSPEC_ALIGN16, VUNSPEC_ALIGN32): New constants.
(align_16, align_32): New patterns.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
Mark Shinwell <shinwell@codesourcery.com>
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-10 14:03:02 +0000
+++ new/gcc/config/arm/arm.c 2010-08-12 11:33:54 +0000
@@ -1449,6 +1449,16 @@
chosen. */
gcc_assert (arm_tune != arm_none);
+ if (arm_tune == cortexa8 && optimize >= 3)
+ {
+ /* These alignments were experimentally determined to improve SPECint
+ performance on SPECCPU 2000. */
+ if (align_functions <= 0)
+ align_functions = 16;
+ if (align_jumps <= 0)
+ align_jumps = 16;
+ }
+
tune_flags = all_cores[(int)arm_tune].flags;
if (target_fp16_format_name)
@@ -11263,7 +11273,10 @@
gcc_assert (GET_CODE (from) != BARRIER);
/* Count the length of this insn. */
- count += get_attr_length (from);
+ if (LABEL_P (from) && (align_jumps > 0 || align_loops > 0))
+ count += MAX (align_jumps, align_loops);
+ else
+ count += get_attr_length (from);
/* If there is a jump table, add its length. */
tmp = is_jump_table (from);
@@ -11603,6 +11616,8 @@
insn = table;
}
}
+ else if (LABEL_P (insn) && (align_jumps > 0 || align_loops > 0))
+ address += MAX (align_jumps, align_loops);
}
fix = minipool_fix_head;
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2010-08-12 11:29:02 +0000
+++ new/gcc/config/arm/arm.md 2010-08-12 11:33:54 +0000
@@ -135,6 +135,8 @@
(VUNSPEC_WCMP_EQ 12) ; Used by the iWMMXt WCMPEQ instructions
(VUNSPEC_WCMP_GTU 13) ; Used by the iWMMXt WCMPGTU instructions
(VUNSPEC_WCMP_GT 14) ; Used by the iwMMXT WCMPGT instructions
+ (VUNSPEC_ALIGN16 15) ; Used to force 16-byte alignment.
+ (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment.
(VUNSPEC_EH_RETURN 20); Use to override the return address for exception
; handling.
]
@@ -11042,6 +11044,24 @@
"
)
+(define_insn "align_16"
+ [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN16)]
+ "TARGET_EITHER"
+ "*
+ assemble_align (128);
+ return \"\";
+ "
+)
+
+(define_insn "align_32"
+ [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN32)]
+ "TARGET_EITHER"
+ "*
+ assemble_align (256);
+ return \"\";
+ "
+)
+
(define_insn "consttable_end"
[(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
"TARGET_EITHER"
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99337.patch
-36
View File
@@ -1,36 +0,0 @@
2008-09-08 Daniel Jacobowitz <dan@codesourcery.com>
gcc/
* config/arm/unwind-arm.c (__gnu_unwind_pr_common): Correct test
for barrier handlers.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
gcc/
* config/arm/arm.c (arm_override_options): Override alignments if
tuning for Cortex-A8.
=== modified file 'gcc/config/arm/unwind-arm.c'
--- old/gcc/config/arm/unwind-arm.c 2009-10-30 14:55:10 +0000
+++ new/gcc/config/arm/unwind-arm.c 2010-08-12 12:39:35 +0000
@@ -1196,8 +1196,6 @@
ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1];
if (data[0] & uint32_highbit)
- phase2_call_unexpected_after_unwind = 1;
- else
{
data += rtti_count + 1;
/* Setup for entry to the handler. */
@@ -1207,6 +1205,8 @@
_Unwind_SetGR (context, 0, (_uw) ucbp);
return _URC_INSTALL_CONTEXT;
}
+ else
+ phase2_call_unexpected_after_unwind = 1;
}
if (data[0] & uint32_highbit)
data++;
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99338.patch
-111
View File
@@ -1,111 +0,0 @@
2009-06-23 Kazu Hirata <kazu@codesourcery.com>
Issue #4613
gcc/
* config/arm/arm.c (arm_rtx_costs_1): Teach that the cost of MLS
is the same as its underlying multiplication.
* config/arm/arm.md (two splitters): New.
* config/arm/predicates.md (binary_operator): New.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2008-09-08 Daniel Jacobowitz <dan@codesourcery.com>
gcc/
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-12 11:33:54 +0000
+++ new/gcc/config/arm/arm.c 2010-08-12 13:35:39 +0000
@@ -6604,6 +6604,19 @@
return true;
}
+ /* MLS is just as expensive as its underlying multiplication.
+ Exclude a shift by a constant, which is expressed as a
+ multiplication. */
+ if (TARGET_32BIT && arm_arch_thumb2
+ && GET_CODE (XEXP (x, 1)) == MULT
+ && ! (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
+ && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
+ (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
+ {
+ /* The cost comes from the cost of the multiply. */
+ return false;
+ }
+
/* Fall through */
case PLUS:
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2010-08-12 11:33:54 +0000
+++ new/gcc/config/arm/arm.md 2010-08-12 13:35:39 +0000
@@ -1355,6 +1355,49 @@
(set_attr "predicable" "yes")]
)
+; The combiner cannot combine the first and last insns in the
+; following sequence because of the intervening insn, so help the
+; combiner with this splitter. The combiner does attempt to split
+; this particular combination but does not know this exact split.
+; Note that the combiner puts the constant at the outermost operation
+; as a part of canonicalization.
+;
+; mul r3, r2, r1
+; <add/sub> r3, r3, <constant>
+; add r3, r3, r4
+
+(define_split
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (match_operator:SI 1 "plusminus_operator"
+ [(plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "")
+ (match_operand:SI 3 "s_register_operand" ""))
+ (match_operand:SI 4 "s_register_operand" ""))
+ (match_operand:SI 5 "arm_immediate_operand" "")]))]
+ "TARGET_32BIT"
+ [(set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 2) (match_dup 3))
+ (match_dup 4)))
+ (set (match_dup 0)
+ (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))]
+ "")
+
+; Likewise for MLS. MLS is available only on select architectures.
+
+(define_split
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (match_operator:SI 1 "plusminus_operator"
+ [(minus:SI (match_operand:SI 2 "s_register_operand" "")
+ (mult:SI (match_operand:SI 3 "s_register_operand" "")
+ (match_operand:SI 4 "s_register_operand" "")))
+ (match_operand:SI 5 "arm_immediate_operand" "")]))]
+ "TARGET_32BIT && arm_arch_thumb2"
+ [(set (match_dup 0)
+ (minus:SI (match_dup 2)
+ (mult:SI (match_dup 3) (match_dup 4))))
+ (set (match_dup 0)
+ (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))]
+ "")
+
(define_insn "*mulsi3addsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
=== modified file 'gcc/config/arm/predicates.md'
--- old/gcc/config/arm/predicates.md 2010-08-10 13:31:21 +0000
+++ new/gcc/config/arm/predicates.md 2010-08-12 13:35:39 +0000
@@ -197,6 +197,11 @@
(and (match_code "plus,minus,ior,xor,and")
(match_test "mode == GET_MODE (op)")))
+;; True for plus/minus operators
+(define_special_predicate "plusminus_operator"
+ (and (match_code "plus,minus")
+ (match_test "mode == GET_MODE (op)")))
+
;; True for logical binary operators.
(define_special_predicate "logical_binary_operator"
(and (match_code "ior,xor,and")
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99339.patch
-236
View File
@@ -1,236 +0,0 @@
Backport from FSF mainline:
gcc/
* gengtype-lex.l: Add HARD_REG_SET.
* expr.c (expand_expr_real_1): Record writes to hard registers.
* function.h (rtl_data): Add asm_clobbers.
* ira.c (compute_regs_asm_clobbered): Use crtl->asm_clobbers.
(ira_setup_eliminable_regset): Remove regs_asm_clobbered.
Use crtl->asm_clobbers.
gcc/testsuite/
* gcc.target/arm/frame-pointer-1.c: New test.
* gcc.target/i386/pr9771-1.c: Move code out of main to allow frame
pointer elimination.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2009-06-23 Kazu Hirata <kazu@codesourcery.com>
=== modified file 'gcc/expr.c'
--- old/gcc/expr.c 2010-05-31 14:45:06 +0000
+++ new/gcc/expr.c 2010-08-12 13:51:16 +0000
@@ -8458,6 +8458,19 @@
expand_decl_rtl:
gcc_assert (decl_rtl);
decl_rtl = copy_rtx (decl_rtl);
+ /* Record writes to register variables. */
+ if (modifier == EXPAND_WRITE && REG_P (decl_rtl)
+ && REGNO (decl_rtl) < FIRST_PSEUDO_REGISTER)
+ {
+ int i = REGNO (decl_rtl);
+ int nregs = hard_regno_nregs[i][GET_MODE (decl_rtl)];
+ while (nregs)
+ {
+ SET_HARD_REG_BIT (crtl->asm_clobbers, i);
+ i++;
+ nregs--;
+ }
+ }
/* Ensure variable marked as used even if it doesn't go through
a parser. If it hasn't be used yet, write out an external
=== modified file 'gcc/function.h'
--- old/gcc/function.h 2009-11-25 10:55:54 +0000
+++ new/gcc/function.h 2010-08-12 13:51:16 +0000
@@ -25,6 +25,7 @@
#include "tree.h"
#include "hashtab.h"
#include "vecprim.h"
+#include "hard-reg-set.h"
/* Stack of pending (incomplete) sequences saved by `start_sequence'.
Each element describes one pending sequence.
@@ -433,6 +434,12 @@
TREE_NOTHROW (current_function_decl) it is set even for overwritable
function where currently compiled version of it is nothrow. */
bool nothrow;
+
+ /* Like regs_ever_live, but 1 if a reg is set or clobbered from an
+ asm. Unlike regs_ever_live, elements of this array corresponding
+ to eliminable regs (like the frame pointer) are set if an asm
+ sets them. */
+ HARD_REG_SET asm_clobbers;
};
#define return_label (crtl->x_return_label)
=== modified file 'gcc/gengtype-lex.l'
--- old/gcc/gengtype-lex.l 2009-11-21 10:24:25 +0000
+++ new/gcc/gengtype-lex.l 2010-08-12 13:51:16 +0000
@@ -49,7 +49,7 @@
ID [[:alpha:]_][[:alnum:]_]*
WS [[:space:]]+
HWS [ \t\r\v\f]*
-IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t
+IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t|HARD_REG_SET
ITYPE {IWORD}({WS}{IWORD})*
EOID [^[:alnum:]_]
=== modified file 'gcc/ira.c'
--- old/gcc/ira.c 2010-03-31 01:44:10 +0000
+++ new/gcc/ira.c 2010-08-12 13:51:16 +0000
@@ -1385,14 +1385,12 @@
return for_each_rtx (&insn, insn_contains_asm_1, NULL);
}
-/* Set up regs_asm_clobbered. */
+/* Add register clobbers from asm statements. */
static void
-compute_regs_asm_clobbered (char *regs_asm_clobbered)
+compute_regs_asm_clobbered (void)
{
basic_block bb;
- memset (regs_asm_clobbered, 0, sizeof (char) * FIRST_PSEUDO_REGISTER);
-
FOR_EACH_BB (bb)
{
rtx insn;
@@ -1413,7 +1411,7 @@
+ hard_regno_nregs[dregno][mode] - 1;
for (i = dregno; i <= end; ++i)
- regs_asm_clobbered[i] = 1;
+ SET_HARD_REG_BIT(crtl->asm_clobbers, i);
}
}
}
@@ -1425,12 +1423,6 @@
void
ira_setup_eliminable_regset (void)
{
- /* Like regs_ever_live, but 1 if a reg is set or clobbered from an
- asm. Unlike regs_ever_live, elements of this array corresponding
- to eliminable regs (like the frame pointer) are set if an asm
- sets them. */
- char *regs_asm_clobbered
- = (char *) alloca (FIRST_PSEUDO_REGISTER * sizeof (char));
#ifdef ELIMINABLE_REGS
int i;
static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS;
@@ -1454,7 +1446,8 @@
COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs);
CLEAR_HARD_REG_SET (eliminable_regset);
- compute_regs_asm_clobbered (regs_asm_clobbered);
+ compute_regs_asm_clobbered ();
+
/* Build the regset of all eliminable registers and show we can't
use those that we already know won't be eliminated. */
#ifdef ELIMINABLE_REGS
@@ -1464,7 +1457,7 @@
= (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to)
|| (eliminables[i].to == STACK_POINTER_REGNUM && need_fp));
- if (! regs_asm_clobbered[eliminables[i].from])
+ if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from))
{
SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from);
@@ -1478,7 +1471,7 @@
df_set_regs_ever_live (eliminables[i].from, true);
}
#if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
- if (! regs_asm_clobbered[HARD_FRAME_POINTER_REGNUM])
+ if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM))
{
SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM);
if (need_fp)
@@ -1492,7 +1485,7 @@
#endif
#else
- if (! regs_asm_clobbered[FRAME_POINTER_REGNUM])
+ if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM))
{
SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM);
if (need_fp)
=== added file 'gcc/testsuite/gcc.target/arm/frame-pointer-1.c'
--- old/gcc/testsuite/gcc.target/arm/frame-pointer-1.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/frame-pointer-1.c 2010-08-12 13:51:16 +0000
@@ -0,0 +1,42 @@
+/* Check local register variables using a register conventionally
+ used as the frame pointer aren't clobbered under high register pressure. */
+/* { dg-do run } */
+/* { dg-options "-Os -mthumb -fomit-frame-pointer" } */
+
+#include <stdlib.h>
+
+int global=5;
+
+void __attribute__((noinline)) foo(int p1, int p2, int p3, int p4)
+{
+ if (global != 5 || p1 != 1 || p2 != 2 || p3 != 3 || p4 != 4)
+ abort();
+}
+
+int __attribute__((noinline)) test(int a, int b, int c, int d)
+{
+ register unsigned long r __asm__("r7") = 0xdeadbeef;
+ int e;
+
+ /* ABCD are live after the call which should be enough
+ to cause r7 to be used if it weren't for the register variable. */
+ foo(a,b,c,d);
+
+ e = 0;
+ __asm__ __volatile__ ("mov %0, %2"
+ : "=r" (e)
+ : "0" (e), "r" (r));
+
+ global = a+b+c+d;
+
+ return e;
+}
+
+int main()
+{
+ if (test(1, 2, 3, 4) != 0xdeadbeef)
+ abort();
+ if (global != 10)
+ abort();
+ return 0;
+}
=== modified file 'gcc/testsuite/gcc.target/i386/pr9771-1.c'
--- old/gcc/testsuite/gcc.target/i386/pr9771-1.c 2007-08-22 08:59:14 +0000
+++ new/gcc/testsuite/gcc.target/i386/pr9771-1.c 2010-08-12 13:51:16 +0000
@@ -28,7 +28,10 @@
*adr = save;
}
-int main()
+/* This must not be inlined becuase main() requires the frame pointer
+ for stack alignment. */
+void test(void) __attribute__((noinline));
+void test(void)
{
B = &x;
@@ -42,3 +45,9 @@
exit(0);
}
+int main()
+{
+ test();
+ return 0;
+
+}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99340.patch
-43
View File
@@ -1,43 +0,0 @@
Merge from Sourcery G++ 4.4:
2009-08-26 Kazu Hirata <kazu@codesourcery.com>
Issue #6089
gcc/
* config/arm/arm.c (arm_rtx_costs_1): Don't special case for
Thumb-2 in the MINUS case.
2010-07-26 Julian Brown <julian@codesourcery.com>
Backport from FSF mainline:
gcc/
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-12 13:35:39 +0000
+++ new/gcc/config/arm/arm.c 2010-08-12 14:08:29 +0000
@@ -6494,23 +6494,6 @@
return true;
case MINUS:
- if (TARGET_THUMB2)
- {
- if (GET_MODE_CLASS (mode) == MODE_FLOAT)
- {
- if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
- *total = COSTS_N_INSNS (1);
- else
- *total = COSTS_N_INSNS (20);
- }
- else
- *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
- /* Thumb2 does not have RSB, so all arguments must be
- registers (subtracting a constant is canonicalized as
- addition of the negated constant). */
- return false;
- }
-
if (mode == DImode)
{
*total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99341.patch
-28
View File
@@ -1,28 +0,0 @@
2009-08-26 Julian Brown <julian@codesourcery.com>
gcc/config/arm/
* uclinux-eabi.h (LINK_GCC_C_SEQUENCE_SPEC): Override definition
for uclinux.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2009-08-26 Kazu Hirata <kazu@codesourcery.com>
=== modified file 'gcc/config/arm/uclinux-eabi.h'
--- old/gcc/config/arm/uclinux-eabi.h 2009-02-20 15:20:38 +0000
+++ new/gcc/config/arm/uclinux-eabi.h 2010-08-12 15:23:21 +0000
@@ -50,6 +50,10 @@
#undef ARM_DEFAULT_ABI
#define ARM_DEFAULT_ABI ARM_ABI_AAPCS_LINUX
+#undef LINK_GCC_C_SEQUENCE_SPEC
+#define LINK_GCC_C_SEQUENCE_SPEC \
+ "--start-group %G %L --end-group"
+
/* Clear the instruction cache from `beg' to `end'. This makes an
inline system call to SYS_cacheflush. */
#undef CLEAR_INSN_CACHE
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99342.patch
-76
View File
@@ -1,76 +0,0 @@
2010-05-25 Julian Brown <julian@codesourcery.com>
gcc/
* config/arm/arm.c (arm_tune_cortex_a5): New.
(arm_override_options): Set above. Set max_insns_skipped to 1 for
Cortex-A5.
* config/arm/arm.h (arm_tune_cortex_a5): Add declaration.
(BRANCH_COST): Set to zero for Cortex-A5 unless optimising for
size.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2009-08-26 Julian Brown <julian@codesourcery.com>
gcc/config/arm/
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-12 14:08:29 +0000
+++ new/gcc/config/arm/arm.c 2010-08-12 16:18:41 +0000
@@ -671,6 +671,9 @@
This typically means an ARM6 or ARM7 with MMU or MPU. */
int arm_tune_wbuf = 0;
+/* Nonzero if tuning for Cortex-A5. */
+int arm_tune_cortex_a5 = 0;
+
/* Nonzero if tuning for Cortex-A9. */
int arm_tune_cortex_a9 = 0;
@@ -1582,6 +1585,7 @@
arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
+ arm_tune_cortex_a5 = (arm_tune == cortexa5) != 0;
arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
/* If we are not using the default (ARM mode) section anchor offset
@@ -1880,6 +1884,11 @@
that is worth skipping is shorter. */
if (arm_tune_strongarm)
max_insns_skipped = 3;
+
+ /* Branches can be dual-issued on Cortex-A5, so conditional execution is
+ less appealing. */
+ if (arm_tune_cortex_a5)
+ max_insns_skipped = 1;
}
/* Hot/Cold partitioning is not currently supported, since we can't
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2010-08-05 16:34:46 +0000
+++ new/gcc/config/arm/arm.h 2010-08-12 16:18:41 +0000
@@ -435,6 +435,9 @@
/* Nonzero if tuning for stores via the write buffer. */
extern int arm_tune_wbuf;
+/* Nonzero if tuning for Cortex-A5. */
+extern int arm_tune_cortex_a5;
+
/* Nonzero if tuning for Cortex-A9. */
extern int arm_tune_cortex_a9;
@@ -2222,7 +2225,8 @@
/* Try to generate sequences that don't involve branches, we can then use
conditional instructions */
#define BRANCH_COST(speed_p, predictable_p) \
- (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \
+ (TARGET_32BIT ? ((arm_tune_cortex_a5 && !optimize_size) ? 0 \
+ : (TARGET_THUMB2 && optimize_size ? 1 : 4)) \
: (optimize > 0 ? 2 : 0))
/* Position Independent Code. */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99343.patch
-132
View File
@@ -1,132 +0,0 @@
Backport from FSF mainline:
gcc/
* config/arm/thumb2.md (*thumb2_addsi3_compare0): New.
(*thumb2_addsi3_compare0_scratch): New.
* config/arm/constraints.md (Pv): New.
* config/arm/arm.md (*addsi3_compare0): Remove FIXME comment. Use
for ARM mode only.
(*addsi3_compare0_scratch): Likewise.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-05-25 Julian Brown <julian@codesourcery.com>
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2010-08-12 13:35:39 +0000
+++ new/gcc/config/arm/arm.md 2010-08-12 16:47:21 +0000
@@ -701,7 +701,6 @@
""
)
-;; ??? Make Thumb-2 variants which prefer low regs
(define_insn "*addsi3_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
@@ -710,7 +709,7 @@
(const_int 0)))
(set (match_operand:SI 0 "s_register_operand" "=r,r")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_32BIT"
+ "TARGET_ARM"
"@
add%.\\t%0, %1, %2
sub%.\\t%0, %1, #%n2"
@@ -723,7 +722,7 @@
(plus:SI (match_operand:SI 0 "s_register_operand" "r, r")
(match_operand:SI 1 "arm_add_operand" "rI,L"))
(const_int 0)))]
- "TARGET_32BIT"
+ "TARGET_ARM"
"@
cmn%?\\t%0, %1
cmp%?\\t%0, #%n1"
=== modified file 'gcc/config/arm/constraints.md'
--- old/gcc/config/arm/constraints.md 2010-07-29 16:58:56 +0000
+++ new/gcc/config/arm/constraints.md 2010-08-12 16:47:21 +0000
@@ -31,7 +31,7 @@
;; The following multi-letter normal constraints have been used:
;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
;; in Thumb-1 state: Pa, Pb
-;; in Thumb-2 state: Ps, Pt
+;; in Thumb-2 state: Ps, Pt, Pv
;; The following memory constraints have been used:
;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
@@ -158,6 +158,11 @@
(and (match_code "const_int")
(match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
+(define_constraint "Pv"
+ "@internal In Thumb-2 state a constant in the range -255 to 0"
+ (and (match_code "const_int")
+ (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
+
(define_constraint "G"
"In ARM/Thumb-2 state a valid FPA immediate constant."
(and (match_code "const_double")
=== modified file 'gcc/config/arm/thumb2.md'
--- old/gcc/config/arm/thumb2.md 2010-08-05 16:34:46 +0000
+++ new/gcc/config/arm/thumb2.md 2010-08-12 16:47:21 +0000
@@ -1241,6 +1241,56 @@
(set_attr "length" "2")]
)
+(define_insn "*thumb2_addsi3_compare0"
+ [(set (reg:CC_NOOV CC_REGNUM)
+ (compare:CC_NOOV
+ (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
+ (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_THUMB2"
+ "*
+ HOST_WIDE_INT val;
+
+ if (GET_CODE (operands[2]) == CONST_INT)
+ val = INTVAL (operands[2]);
+ else
+ val = 0;
+
+ if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
+ return \"subs\\t%0, %1, #%n2\";
+ else
+ return \"adds\\t%0, %1, %2\";
+ "
+ [(set_attr "conds" "set")
+ (set_attr "length" "2,2,4")]
+)
+
+(define_insn "*thumb2_addsi3_compare0_scratch"
+ [(set (reg:CC_NOOV CC_REGNUM)
+ (compare:CC_NOOV
+ (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
+ (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
+ (const_int 0)))]
+ "TARGET_THUMB2"
+ "*
+ HOST_WIDE_INT val;
+
+ if (GET_CODE (operands[1]) == CONST_INT)
+ val = INTVAL (operands[1]);
+ else
+ val = 0;
+
+ if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
+ return \"cmp\\t%0, #%n1\";
+ else
+ return \"cmn\\t%0, %1\";
+ "
+ [(set_attr "conds" "set")
+ (set_attr "length" "2,4")]
+)
+
;; 16-bit encodings of "muls" and "mul<c>". We only use these when
;; optimizing for size since "muls" is slow on all known
;; implementations and since "mul<c>" will be generated by
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99344.patch
-30
View File
@@ -1,30 +0,0 @@
2010-02-03 Daniel Gutson <dgutson@codesourcery.com>
Issue #6472
gcc/
* config/arm/lib1funcs.asm (__ARM_ARCH__): __ARM_ARCH_7EM__
added to the preprocessor condition.
2010-07-26 Julian Brown <julian@codesourcery.com>
Backport from FSF mainline:
gcc/
* config/arm/thumb2.md (*thumb2_addsi3_compare0): New.
(*thumb2_addsi3_compare0_scratch): New.
=== modified file 'gcc/config/arm/lib1funcs.asm'
--- old/gcc/config/arm/lib1funcs.asm 2010-08-05 15:20:54 +0000
+++ new/gcc/config/arm/lib1funcs.asm 2010-08-12 16:49:44 +0000
@@ -104,7 +104,8 @@
#endif
#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
- || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__)
+ || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
+ || defined(__ARM_ARCH_7EM__)
# define __ARM_ARCH__ 7
#endif
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99345.patch
-30
View File
@@ -1,30 +0,0 @@
Merge from Sourcery G++ 4.4:
2010-02-04 Daniel Jacobowitz <dan@codesourcery.com>
Issue #7197 - backtrace() through throw()
libstdc++-v3/
* libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): For
ARM EABI, skip handlers for _US_VIRTUAL_UNWIND_FRAME
| _US_FORCE_UNWIND.
2010-07-26 Julian Brown <julian@codesourcery.com>
Backport from FSF mainline:
2010-02-03 Daniel Gutson <dgutson@codesourcery.com>
=== modified file 'libstdc++-v3/libsupc++/eh_personality.cc'
--- old/libstdc++-v3/libsupc++/eh_personality.cc 2010-02-17 05:43:24 +0000
+++ new/libstdc++-v3/libsupc++/eh_personality.cc 2010-08-12 16:53:10 +0000
@@ -383,6 +383,8 @@
switch (state & _US_ACTION_MASK)
{
case _US_VIRTUAL_UNWIND_FRAME:
+ if (state & _US_FORCE_UNWIND)
+ CONTINUE_UNWINDING;
actions = _UA_SEARCH_PHASE;
break;
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99346.patch
-170
View File
@@ -1,170 +0,0 @@
Backport from FSF mainline:
Julian Brown <julian@codesourcery.com>
Mark Mitchell <mark@codesourcery.com>
gcc/
* config/arm/arm.c (arm_function_ok_for_sibcall): Only forbid
sibling calls for Thumb-1.
* config/arm/arm.h (USE_RETURN_INSN): Enable for Thumb-2.
* config/arm/arm.md (*call_symbol, *call_value_symbol): Use for
Thumb-2.
(*call_insn, *call_value_insn): Don't use for Thumb-2.
(sibcall, sibcall_value, *sibcall_insn, *sibcall_value_insn): Use
for Thumb-2.
(return): New expander.
(*arm_return): New name for ARM return insn.
* config/arm/thumb2.md (*thumb2_return): New insn pattern.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-02-04 Daniel Jacobowitz <dan@codesourcery.com>
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-12 16:18:41 +0000
+++ new/gcc/config/arm/arm.c 2010-08-13 10:30:35 +0000
@@ -4886,8 +4886,8 @@
return false;
/* Never tailcall something for which we have no decl, or if we
- are in Thumb mode. */
- if (decl == NULL || TARGET_THUMB)
+ are generating code for Thumb-1. */
+ if (decl == NULL || TARGET_THUMB1)
return false;
/* The PIC register is live on entry to VxWorks PLT entries, so we
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2010-08-12 16:18:41 +0000
+++ new/gcc/config/arm/arm.h 2010-08-13 10:30:35 +0000
@@ -1833,11 +1833,8 @@
/* Determine if the epilogue should be output as RTL.
You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
-/* This is disabled for Thumb-2 because it will confuse the
- conditional insn counter.
- Do not use a return insn if we're avoiding ldm/stm instructions. */
#define USE_RETURN_INSN(ISCOND) \
- ((TARGET_ARM && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0)
+ ((TARGET_32BIT && !low_irq_latency) ? use_return_insn (ISCOND, NULL) : 0)
/* Definitions for register eliminations.
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2010-08-12 16:47:21 +0000
+++ new/gcc/config/arm/arm.md 2010-08-13 10:30:35 +0000
@@ -8798,7 +8798,7 @@
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
(clobber (reg:SI LR_REGNUM))]
- "TARGET_ARM
+ "TARGET_32BIT
&& (GET_CODE (operands[0]) == SYMBOL_REF)
&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
"*
@@ -8814,7 +8814,7 @@
(match_operand:SI 2 "" "")))
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNUM))]
- "TARGET_ARM
+ "TARGET_32BIT
&& (GET_CODE (operands[1]) == SYMBOL_REF)
&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
"*
@@ -8829,7 +8829,7 @@
(match_operand:SI 1 "" ""))
(use (match_operand 2 "" ""))
(clobber (reg:SI LR_REGNUM))]
- "TARGET_THUMB
+ "TARGET_THUMB1
&& GET_CODE (operands[0]) == SYMBOL_REF
&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
"bl\\t%a0"
@@ -8843,7 +8843,7 @@
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNUM))]
- "TARGET_THUMB
+ "TARGET_THUMB1
&& GET_CODE (operands[1]) == SYMBOL_REF
&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
"bl\\t%a1"
@@ -8857,7 +8857,7 @@
(match_operand 1 "general_operand" ""))
(return)
(use (match_operand 2 "" ""))])]
- "TARGET_ARM"
+ "TARGET_32BIT"
"
{
if (operands[2] == NULL_RTX)
@@ -8871,7 +8871,7 @@
(match_operand 2 "general_operand" "")))
(return)
(use (match_operand 3 "" ""))])]
- "TARGET_ARM"
+ "TARGET_32BIT"
"
{
if (operands[3] == NULL_RTX)
@@ -8884,7 +8884,7 @@
(match_operand 1 "" ""))
(return)
(use (match_operand 2 "" ""))]
- "TARGET_ARM && GET_CODE (operands[0]) == SYMBOL_REF"
+ "TARGET_32BIT && GET_CODE (operands[0]) == SYMBOL_REF"
"*
return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\";
"
@@ -8897,15 +8897,20 @@
(match_operand 2 "" "")))
(return)
(use (match_operand 3 "" ""))]
- "TARGET_ARM && GET_CODE (operands[1]) == SYMBOL_REF"
+ "TARGET_32BIT && GET_CODE (operands[1]) == SYMBOL_REF"
"*
return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\";
"
[(set_attr "type" "call")]
)
+(define_expand "return"
+ [(return)]
+ "TARGET_32BIT && USE_RETURN_INSN (FALSE)"
+ "")
+
;; Often the return insn will be the same as loading from memory, so set attr
-(define_insn "return"
+(define_insn "*arm_return"
[(return)]
"TARGET_ARM && USE_RETURN_INSN (FALSE)"
"*
=== modified file 'gcc/config/arm/thumb2.md'
--- old/gcc/config/arm/thumb2.md 2010-08-12 16:47:21 +0000
+++ new/gcc/config/arm/thumb2.md 2010-08-13 10:30:35 +0000
@@ -1054,6 +1054,19 @@
(set_attr "length" "20")]
)
+;; Note: this is not predicable, to avoid issues with linker-generated
+;; interworking stubs.
+(define_insn "*thumb2_return"
+ [(return)]
+ "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
+ "*
+ {
+ return output_return_instruction (const_true_rtx, TRUE, FALSE);
+ }"
+ [(set_attr "type" "load1")
+ (set_attr "length" "12")]
+)
+
(define_insn_and_split "thumb2_eh_return"
[(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
VUNSPEC_EH_RETURN)
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99348.patch
-37
View File
@@ -1,37 +0,0 @@
2010-02-23 Julian Brown <julian@codesourcery.com>
gcc/
* calls.c (precompute_register_parameters): Avoid generating a
register move if optimizing for size.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-02-15 Julian Brown <julian@codesourcery.com>
Issue #7486
=== modified file 'gcc/calls.c'
--- old/gcc/calls.c 2010-04-02 18:54:46 +0000
+++ new/gcc/calls.c 2010-08-13 10:50:45 +0000
@@ -703,7 +703,9 @@
For small register classes, also do this if this call uses
register parameters. This is to avoid reload conflicts while
- loading the parameters registers. */
+ loading the parameters registers.
+
+ Avoid creating the extra move if optimizing for size. */
else if ((! (REG_P (args[i].value)
|| (GET_CODE (args[i].value) == SUBREG
@@ -711,6 +713,7 @@
&& args[i].mode != BLKmode
&& rtx_cost (args[i].value, SET, optimize_insn_for_speed_p ())
> COSTS_N_INSNS (1)
+ && !optimize_size
&& ((SMALL_REGISTER_CLASSES && *reg_parm_seen)
|| optimize))
args[i].value = copy_to_mode_reg (args[i].mode, args[i].value);
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99349.patch
-401
View File
@@ -1,401 +0,0 @@
* config/arm/arm.c (thumb2_size_rtx_costs): New.
(arm_rtx_costs): Call above for Thumb-2.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-02-23 Julian Brown <julian@codesourcery.com>
gcc/
* calls.c (precompute_register_parameters): Avoid generating a
register move if optimizing for size.
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-13 10:43:42 +0000
+++ new/gcc/config/arm/arm.c 2010-08-13 10:55:28 +0000
@@ -141,6 +141,7 @@
static bool arm_have_conditional_execution (void);
static bool arm_rtx_costs_1 (rtx, enum rtx_code, int*, bool);
static bool arm_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
+static bool thumb2_size_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *);
static bool arm_slowmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
static bool arm_fastmul_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool);
@@ -7316,14 +7317,372 @@
}
}
+static bool
+thumb2_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+ int *total)
+{
+ /* Attempt to give a lower cost to RTXs which can optimistically be
+ represented as short insns, assuming that the right conditions will hold
+ later (e.g. low registers will be chosen if a short insn requires them).
+
+ Note that we don't make wide insns cost twice as much as narrow insns,
+ because we can't prove that a particular RTX will actually use a narrow
+ insn, because not enough information is available (e.g., we don't know
+ which hard registers pseudos will be assigned). Consider these to be
+ "expected" sizes/weightings.
+
+ (COSTS_NARROW_INSNS has the same weight as COSTS_N_INSNS.) */
+
+#define COSTS_NARROW_INSNS(N) ((N) * 4)
+#define COSTS_WIDE_INSNS(N) ((N) * 6)
+#define THUMB2_LIBCALL_COST COSTS_WIDE_INSNS (2)
+ enum machine_mode mode = GET_MODE (x);
+
+ switch (code)
+ {
+ case MEM:
+ if (REG_P (XEXP (x, 0)))
+ {
+ /* Hopefully this will use a narrow ldm/stm insn. */
+ *total = COSTS_NARROW_INSNS (1);
+ return true;
+ }
+ else if ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
+ || reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0))
+ || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0)))
+ {
+ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode));
+ return true;
+ }
+ else if (GET_CODE (XEXP (x, 0)) == PLUS)
+ {
+ rtx plus = XEXP (x, 0);
+
+ if (GET_CODE (XEXP (plus, 1)) == CONST_INT)
+ {
+ HOST_WIDE_INT cst = INTVAL (XEXP (plus, 1));
+
+ if (cst >= 0 && cst < 256)
+ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode));
+ else
+ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
+
+ *total += rtx_cost (XEXP (plus, 0), code, false);
+
+ return true;
+ }
+ }
+
+ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode));
+ return false;
+
+ case DIV:
+ case MOD:
+ case UDIV:
+ case UMOD:
+ if (arm_arch_hwdiv)
+ *total = COSTS_WIDE_INSNS (1);
+ else
+ *total = THUMB2_LIBCALL_COST;
+ return false;
+
+ case ROTATE:
+ if (mode == SImode && REG_P (XEXP (x, 1)))
+ {
+ *total = COSTS_WIDE_INSNS (1) + COSTS_NARROW_INSNS (1)
+ + rtx_cost (XEXP (x, 0), code, false);
+ return true;
+ }
+ /* Fall through */
+
+ case ASHIFT:
+ case LSHIFTRT:
+ case ASHIFTRT:
+ if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ {
+ *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false);
+ return true;
+ }
+ else if (mode == SImode)
+ {
+ *total = COSTS_NARROW_INSNS (1);
+ return false;
+ }
+
+ /* Needs a libcall. */
+ *total = THUMB2_LIBCALL_COST;
+ return false;
+
+ case ROTATERT:
+ if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ {
+ *total = COSTS_WIDE_INSNS (3) + rtx_cost (XEXP (x, 0), code, false);
+ return true;
+ }
+ else if (mode == SImode)
+ {
+ if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ *total = COSTS_WIDE_INSNS (1) + rtx_cost (XEXP (x, 0), code, false);
+ else
+ *total = COSTS_NARROW_INSNS (1)
+ + rtx_cost (XEXP (x, 0), code, false);
+ return true;
+ }
+
+ /* Needs a libcall. */
+ *total = THUMB2_LIBCALL_COST;
+ return false;
+
+ case MINUS:
+ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+ && (mode == SFmode || !TARGET_VFP_SINGLE))
+ {
+ *total = COSTS_WIDE_INSNS (1);
+ return false;
+ }
+
+ if (mode == SImode)
+ {
+ enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
+ enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
+
+ if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
+ || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
+ || subcode1 == ROTATE || subcode1 == ROTATERT
+ || subcode1 == ASHIFT || subcode1 == LSHIFTRT
+ || subcode1 == ASHIFTRT)
+ {
+ /* It's just the cost of the two operands. */
+ *total = 0;
+ return false;
+ }
+
+ if (subcode1 == CONST_INT)
+ {
+ HOST_WIDE_INT cst = INTVAL (XEXP (x, 1));
+
+ if (cst >= 0 && cst < 256)
+ *total = COSTS_NARROW_INSNS (1);
+ else
+ *total = COSTS_WIDE_INSNS (1);
+
+ *total += rtx_cost (XEXP (x, 0), code, false);
+
+ return true;
+ }
+
+ *total = COSTS_NARROW_INSNS (1);
+ return false;
+ }
+
+ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
+ return false;
+
+ case PLUS:
+ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+ && (mode == SFmode || !TARGET_VFP_SINGLE))
+ {
+ *total = COSTS_WIDE_INSNS (1);
+ return false;
+ }
+
+ /* Fall through */
+ case AND: case XOR: case IOR:
+ if (mode == SImode)
+ {
+ enum rtx_code subcode = GET_CODE (XEXP (x, 0));
+
+ if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
+ || subcode == LSHIFTRT || subcode == ASHIFTRT
+ || (code == AND && subcode == NOT))
+ {
+ /* It's just the cost of the two operands. */
+ *total = 0;
+ return false;
+ }
+
+ if (code == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ {
+ HOST_WIDE_INT cst = INTVAL (XEXP (x, 1));
+
+ if ((reg_mentioned_p (virtual_stack_vars_rtx, XEXP (x, 0))
+ || reg_mentioned_p (stack_pointer_rtx, XEXP (x, 0)))
+ && cst > -512 && cst < 1024)
+ /* Only approximately correct, depending on destination
+ register. */
+ *total = COSTS_NARROW_INSNS (1);
+ else if (cst > -256 && cst < 256)
+ *total = COSTS_NARROW_INSNS (1);
+ else
+ *total = COSTS_WIDE_INSNS (1);
+
+ *total += rtx_cost (XEXP (x, 0), code, false);
+
+ return true;
+ }
+
+ if (subcode == MULT
+ && power_of_two_operand (XEXP (XEXP (x, 0), 1), mode))
+ {
+ *total = COSTS_WIDE_INSNS (1)
+ + rtx_cost (XEXP (x, 1), code, false);
+ return true;
+ }
+ }
+
+ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode));
+ return false;
+
+ case MULT:
+ if (mode == SImode && GET_CODE (XEXP (x, 1)) != CONST_INT)
+ {
+ /* Might be using muls. */
+ *total = COSTS_NARROW_INSNS (1);
+ return false;
+ }
+ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
+ return false;
+
+ case NEG:
+ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+ && (mode == SFmode || !TARGET_VFP_SINGLE))
+ {
+ *total = COSTS_WIDE_INSNS (1);
+ return false;
+ }
+
+ /* Fall through */
+ case NOT:
+ if (mode == SImode)
+ {
+ *total = COSTS_NARROW_INSNS (1);
+ return false;
+ }
+ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
+ return false;
+
+ case IF_THEN_ELSE:
+ *total = COSTS_NARROW_INSNS (1);
+ return false;
+
+ case COMPARE:
+ if (cc_register (XEXP (x, 0), VOIDmode))
+ *total = 0;
+ else
+ *total = COSTS_NARROW_INSNS (1);
+ return false;
+
+ case ABS:
+ if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
+ && (mode == SFmode || !TARGET_VFP_SINGLE))
+ *total = COSTS_WIDE_INSNS (1);
+ else
+ *total = COSTS_NARROW_INSNS (ARM_NUM_REGS (mode)) * 2;
+ return false;
+
+ case SIGN_EXTEND:
+ if (GET_MODE_SIZE (mode) <= 4)
+ *total = GET_CODE (XEXP (x, 0)) == MEM ? 0 : COSTS_NARROW_INSNS (1);
+ else
+ *total = COSTS_NARROW_INSNS (1)
+ + COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
+ return false;
+
+ case ZERO_EXTEND:
+ if (GET_MODE_SIZE (mode) > 4)
+ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode) - 1);
+ else if (GET_CODE (XEXP (x, 0)) == MEM)
+ *total = 0;
+ else
+ *total = COSTS_NARROW_INSNS (1);
+ return false;
+
+ case CONST_INT:
+ {
+ HOST_WIDE_INT cst = INTVAL (x);
+
+ switch (outer_code)
+ {
+ case PLUS:
+ if (cst > -256 && cst < 256)
+ *total = 0;
+ else
+ /* See note about optabs below. */
+ *total = COSTS_N_INSNS (1);
+ return true;
+
+ case MINUS:
+ case COMPARE:
+ if (cst >= 0 && cst < 256)
+ *total = 0;
+ else
+ /* See note about optabs below. */
+ *total = COSTS_N_INSNS (1);
+ return true;
+
+ case ASHIFT:
+ case ASHIFTRT:
+ case LSHIFTRT:
+ *total = 0;
+ return true;
+
+ default:
+ /* Constants are compared explicitly against COSTS_N_INSNS (1) in
+ optabs.c, creating an alternative, larger code sequence for more
+ expensive constants). So, it doesn't pay to make some constants
+ cost more than this. */
+ *total = COSTS_N_INSNS (1);
+ }
+ return true;
+ }
+
+ case CONST:
+ case LABEL_REF:
+ case SYMBOL_REF:
+ *total = COSTS_WIDE_INSNS (2);
+ return true;
+
+ case CONST_DOUBLE:
+ *total = COSTS_WIDE_INSNS (4);
+ return true;
+
+ case HIGH:
+ case LO_SUM:
+ /* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
+ cost of these slightly. */
+ *total = COSTS_WIDE_INSNS (1) + 1;
+ return true;
+
+ default:
+ if (mode != VOIDmode)
+ *total = COSTS_WIDE_INSNS (ARM_NUM_REGS (mode));
+ else
+ /* A guess (inherited from arm_size_rtx_costs). */
+ *total = COSTS_WIDE_INSNS (4);
+ return false;
+ }
+
+ return true;
+#undef THUMB2_LIBCALL_COST
+#undef COSTS_WIDE_INSNS
+#undef COSTS_NARROW_INSNS
+}
+
/* RTX costs when optimizing for size. */
static bool
arm_rtx_costs (rtx x, int code, int outer_code, int *total,
bool speed)
{
if (!speed)
- return arm_size_rtx_costs (x, (enum rtx_code) code,
- (enum rtx_code) outer_code, total);
+ {
+ if (TARGET_THUMB2)
+ return thumb2_size_rtx_costs (x, (enum rtx_code) code,
+ (enum rtx_code) outer_code, total);
+ else
+ return arm_size_rtx_costs (x, (enum rtx_code) code,
+ (enum rtx_code) outer_code, total);
+ }
else
return all_cores[(int)arm_tune].rtx_costs (x, (enum rtx_code) code,
(enum rtx_code) outer_code,
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99350.patch
-184
View File
@@ -1,184 +0,0 @@
Jie Zhang <jie@codesourcery.com>
Issue #7122
gcc/
* config/arm/vfp.md (movdf_vfp): Add load double 0.0 case.
(thumb2_movdf_vfp): Likewise. Require that one of the operands be a
register.
* config/arm/constraints.md (D0): New constraint.
gcc/testsuite/
* gcc.target/arm/neon-load-df0.c: New test.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-02-23 Julian Brown <julian@codesourcery.com>
gcc/
=== modified file 'gcc/config/arm/constraints.md'
--- old/gcc/config/arm/constraints.md 2010-08-12 16:47:21 +0000
+++ new/gcc/config/arm/constraints.md 2010-08-13 10:59:06 +0000
@@ -29,7 +29,7 @@
;; in Thumb-1 state: I, J, K, L, M, N, O
;; The following multi-letter normal constraints have been used:
-;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy, Di
+;; in ARM/Thumb-2 state: D0, Da, Db, Dc, Di, Dn, Dl, DL, Dv, Dy
;; in Thumb-1 state: Pa, Pb
;; in Thumb-2 state: Ps, Pt, Pv
@@ -173,6 +173,13 @@
(and (match_code "const_double")
(match_test "TARGET_32BIT && neg_const_double_rtx_ok_for_fpa (op)")))
+(define_constraint "D0"
+ "@internal
+ In ARM/Thumb-2 state a 0.0 floating point constant which can
+ be loaded with a Neon vmov immediate instruction."
+ (and (match_code "const_double")
+ (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
+
(define_constraint "Da"
"@internal
In ARM/Thumb-2 state a const_int, const_double or const_vector that can
=== modified file 'gcc/config/arm/vfp.md'
--- old/gcc/config/arm/vfp.md 2010-08-12 11:29:02 +0000
+++ new/gcc/config/arm/vfp.md 2010-08-13 10:59:06 +0000
@@ -402,8 +402,8 @@
;; DFmode moves
(define_insn "*movdf_vfp"
- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
+ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w, r, m,w ,Uv,w,r")
+ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,D0,mF,r,UvF,w, w,r"))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
&& ( register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
@@ -418,16 +418,18 @@
case 2:
gcc_assert (TARGET_VFP_DOUBLE);
return \"fconstd%?\\t%P0, #%G1\";
- case 3: case 4:
+ case 3:
+ return \"vmov.i32\\t%P0, #0\";
+ case 4: case 5:
return output_move_double (operands);
- case 5: case 6:
+ case 6: case 7:
return output_move_vfp (operands);
- case 7:
+ case 8:
if (TARGET_VFP_SINGLE)
return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
else
return \"fcpyd%?\\t%P0, %P1\";
- case 8:
+ case 9:
return \"#\";
default:
gcc_unreachable ();
@@ -435,10 +437,10 @@
}
"
[(set_attr "type"
- "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
- (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
- (eq_attr "alternative" "7")
+ "r_2_f,f_2_r,fconstd,*,f_loadd,f_stored,load2,store2,ffarithd,*")
+ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,neon_vmov,*,*,*,*,neon_vmov,*")
+ (set (attr "length") (cond [(eq_attr "alternative" "4,5,9") (const_int 8)
+ (eq_attr "alternative" "8")
(if_then_else
(eq (symbol_ref "TARGET_VFP_SINGLE")
(const_int 1))
@@ -446,14 +448,16 @@
(const_int 4))]
(const_int 4)))
(set_attr "predicable" "yes")
- (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
- (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
+ (set_attr "pool_range" "*,*,*,*,1020,*,1020,*,*,*")
+ (set_attr "neg_pool_range" "*,*,*,*,1008,*,1008,*,*,*")]
)
(define_insn "*thumb2_movdf_vfp"
- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
- (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
- "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
+ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,w,r, m,w ,Uv,w,r")
+ (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,D0,mF,r,UvF,w, w,r"))]
+ "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
+ && ( register_operand (operands[0], DFmode)
+ || register_operand (operands[1], DFmode))"
"*
{
switch (which_alternative)
@@ -465,11 +469,13 @@
case 2:
gcc_assert (TARGET_VFP_DOUBLE);
return \"fconstd%?\\t%P0, #%G1\";
- case 3: case 4: case 8:
+ case 3:
+ return \"vmov.i32\\t%P0, #0\";
+ case 4: case 5: case 9:
return output_move_double (operands);
- case 5: case 6:
+ case 6: case 7:
return output_move_vfp (operands);
- case 7:
+ case 8:
if (TARGET_VFP_SINGLE)
return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
else
@@ -480,18 +486,18 @@
}
"
[(set_attr "type"
- "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
- (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
- (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
- (eq_attr "alternative" "7")
+ "r_2_f,f_2_r,fconstd,*,load2,store2,f_load,f_store,ffarithd,*")
+ (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,neon_vmov,*,*,*,*,neon_vmov,*")
+ (set (attr "length") (cond [(eq_attr "alternative" "4,5,9") (const_int 8)
+ (eq_attr "alternative" "8")
(if_then_else
(eq (symbol_ref "TARGET_VFP_SINGLE")
(const_int 1))
(const_int 8)
(const_int 4))]
(const_int 4)))
- (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
- (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
+ (set_attr "pool_range" "*,*,*,*,4096,*,1020,*,*,*")
+ (set_attr "neg_pool_range" "*,*,*,*,0,*,1008,*,*,*")]
)
=== added file 'gcc/testsuite/gcc.target/arm/neon-load-df0.c'
--- old/gcc/testsuite/gcc.target/arm/neon-load-df0.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-load-df0.c 2010-08-13 10:59:06 +0000
@@ -0,0 +1,14 @@
+/* Test the optimization of loading 0.0 for ARM Neon. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+double x;
+void bar ()
+{
+ x = 0.0;
+}
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[dD\]\[0-9\]+, #0\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99351.patch
-548
View File
@@ -1,548 +0,0 @@
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
Jie Zhang <jie@codesourcery.com>
Issue #7122
gcc/
* config/arm/arm.c (arm_rtx_costs_1): Adjust cost for
CONST_VECTOR.
(arm_size_rtx_costs): Likewise.
(thumb2_size_rtx_costs): Likewise.
(neon_valid_immediate): Add a case for double 0.0.
gcc/testsuite/
* gcc.target/arm/neon-vdup-1.c: New test case.
* gcc.target/arm/neon-vdup-2.c: New test case.
* gcc.target/arm/neon-vdup-3.c: New test case.
* gcc.target/arm/neon-vdup-4.c: New test case.
* gcc.target/arm/neon-vdup-5.c: New test case.
* gcc.target/arm/neon-vdup-6.c: New test case.
* gcc.target/arm/neon-vdup-7.c: New test case.
* gcc.target/arm/neon-vdup-8.c: New test case.
* gcc.target/arm/neon-vdup-9.c: New test case.
* gcc.target/arm/neon-vdup-10.c: New test case.
* gcc.target/arm/neon-vdup-11.c: New test case.
* gcc.target/arm/neon-vdup-12.c: New test case.
* gcc.target/arm/neon-vdup-13.c: New test case.
* gcc.target/arm/neon-vdup-14.c: New test case.
* gcc.target/arm/neon-vdup-15.c: New test case.
* gcc.target/arm/neon-vdup-16.c: New test case.
* gcc.target/arm/neon-vdup-17.c: New test case.
* gcc.target/arm/neon-vdup-18.c: New test case.
* gcc.target/arm/neon-vdup-19.c: New test case.
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-13 10:55:28 +0000
+++ new/gcc/config/arm/arm.c 2010-08-13 11:02:47 +0000
@@ -7061,6 +7061,17 @@
*total = COSTS_N_INSNS (4);
return true;
+ case CONST_VECTOR:
+ if (TARGET_NEON
+ && TARGET_HARD_FLOAT
+ && outer == SET
+ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
+ && neon_immediate_valid_for_move (x, mode, NULL, NULL))
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (4);
+ return true;
+
default:
*total = COSTS_N_INSNS (4);
return false;
@@ -7301,6 +7312,17 @@
*total = COSTS_N_INSNS (4);
return true;
+ case CONST_VECTOR:
+ if (TARGET_NEON
+ && TARGET_HARD_FLOAT
+ && outer_code == SET
+ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
+ && neon_immediate_valid_for_move (x, mode, NULL, NULL))
+ *total = COSTS_N_INSNS (1);
+ else
+ *total = COSTS_N_INSNS (4);
+ return true;
+
case HIGH:
case LO_SUM:
/* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
@@ -7647,6 +7669,17 @@
*total = COSTS_WIDE_INSNS (4);
return true;
+ case CONST_VECTOR:
+ if (TARGET_NEON
+ && TARGET_HARD_FLOAT
+ && outer_code == SET
+ && (VALID_NEON_DREG_MODE (mode) || VALID_NEON_QREG_MODE (mode))
+ && neon_immediate_valid_for_move (x, mode, NULL, NULL))
+ *total = COSTS_WIDE_INSNS (1);
+ else
+ *total = COSTS_WIDE_INSNS (4);
+ return true;
+
case HIGH:
case LO_SUM:
/* We prefer constant pool entries to MOVW/MOVT pairs, so bump the
@@ -8315,11 +8348,14 @@
vmov i64 17 aaaaaaaa bbbbbbbb cccccccc dddddddd
eeeeeeee ffffffff gggggggg hhhhhhhh
vmov f32 18 aBbbbbbc defgh000 00000000 00000000
+ vmov f32 19 00000000 00000000 00000000 00000000
For case 18, B = !b. Representable values are exactly those accepted by
vfp3_const_double_index, but are output as floating-point numbers rather
than indices.
+ For case 19, we will change it to vmov.i32 when assembling.
+
Variants 0-5 (inclusive) may also be used as immediates for the second
operand of VORR/VBIC instructions.
@@ -8362,7 +8398,7 @@
rtx el0 = CONST_VECTOR_ELT (op, 0);
REAL_VALUE_TYPE r0;
- if (!vfp3_const_double_rtx (el0))
+ if (!vfp3_const_double_rtx (el0) && el0 != CONST0_RTX (GET_MODE (el0)))
return -1;
REAL_VALUE_FROM_CONST_DOUBLE (r0, el0);
@@ -8384,7 +8420,10 @@
if (elementwidth)
*elementwidth = 0;
- return 18;
+ if (el0 == CONST0_RTX (GET_MODE (el0)))
+ return 19;
+ else
+ return 18;
}
/* Splat vector constant out into a byte vector. */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-1.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-1.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-1.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+float32x4_t out_float32x4_t;
+void test_vdupq_nf32 (void)
+{
+ out_float32x4_t = vdupq_n_f32 (0.0);
+}
+
+/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #0\.0\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-10.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-10.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-10.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (~0x12000000);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #3992977407\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-11.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-11.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-11.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x8_t out_uint16x8_t;
+void test_vdupq_nu16 (void)
+{
+ out_uint16x8_t = vdupq_n_u16 (0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-12.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-12.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-12.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x8_t out_uint16x8_t;
+void test_vdupq_nu16 (void)
+{
+ out_uint16x8_t = vdupq_n_u16 (0x1200);
+}
+
+/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-13.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-13.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-13.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x8_t out_uint16x8_t;
+void test_vdupq_nu16 (void)
+{
+ out_uint16x8_t = vdupq_n_u16 (~0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #65517\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-14.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-14.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-14.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u16' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint16x8_t out_uint16x8_t;
+void test_vdupq_nu16 (void)
+{
+ out_uint16x8_t = vdupq_n_u16 (~0x1200);
+}
+
+/* { dg-final { scan-assembler "vmov\.i16\[ \]+\[qQ\]\[0-9\]+, #60927\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-15.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-15.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-15.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u8' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint8x16_t out_uint8x16_t;
+void test_vdupq_nu8 (void)
+{
+ out_uint8x16_t = vdupq_n_u8 (0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i8\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-16.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-16.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-16.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (0x12ff);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4863\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-17.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-17.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-17.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (0x12ffff);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1245183\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-18.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-18.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-18.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (~0x12ff);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962432\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-19.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-19.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-19.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (~0x12ffff);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293722112\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-2.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-2.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-2.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_f32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+float32x4_t out_float32x4_t;
+void test_vdupq_nf32 (void)
+{
+ out_float32x4_t = vdupq_n_f32 (0.125);
+}
+
+/* { dg-final { scan-assembler "vmov\.f32\[ \]+\[qQ\]\[0-9\]+, #1\.25e-1\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-3.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-3.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-3.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #18\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-4.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-4.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-4.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (0x1200);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4608\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-5.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-5.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-5.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (0x120000);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #1179648\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-6.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-6.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-6.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (0x12000000);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #301989888\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-7.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-7.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-7.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (~0x12);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294967277\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-8.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-8.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-8.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (~0x1200);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4294962687\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
=== added file 'gcc/testsuite/gcc.target/arm/neon-vdup-9.c'
--- old/gcc/testsuite/gcc.target/arm/neon-vdup-9.c 1970-01-01 00:00:00 +0000
+++ new/gcc/testsuite/gcc.target/arm/neon-vdup-9.c 2010-08-13 11:02:47 +0000
@@ -0,0 +1,17 @@
+/* Test the optimization of `vdupq_n_u32' ARM Neon intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+
+#include <arm_neon.h>
+
+uint32x4_t out_uint32x4_t;
+void test_vdupq_nu32 (void)
+{
+ out_uint32x4_t = vdupq_n_u32 (~0x120000);
+}
+
+/* { dg-final { scan-assembler "vmov\.i32\[ \]+\[qQ\]\[0-9\]+, #4293787647\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99352.patch
-118
View File
@@ -1,118 +0,0 @@
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-04-07 Thomas Schwinge <thomas@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Issue #6715
PR debug/40521
gcc/
* dwarf2out.c (NEED_UNWIND_TABLES): Define.
(dwarf2out_do_frame, dwarf2out_do_cfi_asm, dwarf2out_begin_prologue)
(dwarf2out_frame_finish, dwarf2out_assembly_start): Use it.
(dwarf2out_assembly_start): Correct logic for TARGET_UNWIND_INFO.
* config/arm/arm.h (DWARF2_UNWIND_INFO): Remove definition.
* config/arm/bpabi.h (DWARF2_UNWIND_INFO): Define to zero.
=== modified file 'gcc/config/arm/arm.h'
--- old/gcc/config/arm/arm.h 2010-08-13 10:30:35 +0000
+++ new/gcc/config/arm/arm.h 2010-08-13 11:11:15 +0000
@@ -932,9 +932,6 @@
#define MUST_USE_SJLJ_EXCEPTIONS 1
#endif
-/* We can generate DWARF2 Unwind info, even though we don't use it. */
-#define DWARF2_UNWIND_INFO 1
-
/* Use r0 and r1 to pass exception handling information. */
#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
=== modified file 'gcc/config/arm/bpabi.h'
--- old/gcc/config/arm/bpabi.h 2009-11-20 17:37:30 +0000
+++ new/gcc/config/arm/bpabi.h 2010-08-13 11:11:15 +0000
@@ -26,6 +26,7 @@
#define TARGET_BPABI (TARGET_AAPCS_BASED)
/* BPABI targets use EABI frame unwinding tables. */
+#define DWARF2_UNWIND_INFO 0
#define TARGET_UNWIND_INFO 1
/* Section 4.1 of the AAPCS requires the use of VFP format. */
=== modified file 'gcc/dwarf2out.c'
--- old/gcc/dwarf2out.c 2010-07-01 11:31:19 +0000
+++ new/gcc/dwarf2out.c 2010-08-13 11:11:15 +0000
@@ -124,6 +124,9 @@
# endif
#endif
+#define NEED_UNWIND_TABLES \
+ (flag_unwind_tables || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS))
+
/* Map register numbers held in the call frame info that gcc has
collected using DWARF_FRAME_REGNUM to those that should be output in
.debug_frame and .eh_frame. */
@@ -147,9 +150,7 @@
|| write_symbols == VMS_AND_DWARF2_DEBUG
|| DWARF2_FRAME_INFO || saved_do_cfi_asm
#ifdef DWARF2_UNWIND_INFO
- || (DWARF2_UNWIND_INFO
- && (flag_unwind_tables
- || (flag_exceptions && ! USING_SJLJ_EXCEPTIONS)))
+ || (DWARF2_UNWIND_INFO && NEED_UNWIND_TABLES)
#endif
);
}
@@ -185,7 +186,7 @@
#ifdef TARGET_UNWIND_INFO
return false;
#else
- if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions))
+ if (!NEED_UNWIND_TABLES)
return false;
#endif
}
@@ -3906,8 +3907,7 @@
/* ??? current_function_func_begin_label is also used by except.c
for call-site information. We must emit this label if it might
be used. */
- if ((! flag_exceptions || USING_SJLJ_EXCEPTIONS)
- && ! dwarf2out_do_frame ())
+ if (! NEED_UNWIND_TABLES && ! dwarf2out_do_frame ())
return;
#else
if (! dwarf2out_do_frame ())
@@ -4067,7 +4067,7 @@
#ifndef TARGET_UNWIND_INFO
/* Output another copy for the unwinder. */
- if (! USING_SJLJ_EXCEPTIONS && (flag_unwind_tables || flag_exceptions))
+ if (NEED_UNWIND_TABLES)
output_call_frame_info (1);
#endif
}
@@ -20732,10 +20732,15 @@
{
if (HAVE_GAS_CFI_SECTIONS_DIRECTIVE && dwarf2out_do_cfi_asm ())
{
-#ifndef TARGET_UNWIND_INFO
- if (USING_SJLJ_EXCEPTIONS || (!flag_unwind_tables && !flag_exceptions))
-#endif
+#ifdef TARGET_UNWIND_INFO
+ /* We're only ever interested in .debug_frame. */
+ fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n");
+#else
+ /* GAS defaults to emitting .eh_frame only, and .debug_frame is not
+ wanted in case that the former one is present. */
+ if (! NEED_UNWIND_TABLES)
fprintf (asm_out_file, "\t.cfi_sections\t.debug_frame\n");
+#endif
}
}
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99353.patch
-298
View File
@@ -1,298 +0,0 @@
2010-04-08 Bernd Schmidt <bernds@codesourcery.com>
Issue #6952
gcc/
* ira-costs.c (record_reg_classes): Ignore alternatives that are
not enabled.
* config/arm/vfp.md (arm_movdi_vfp): Enable only when not tuning
for Cortex-A8.
(arm_movdi_vfp_cortexa8): New pattern.
* config/arm/neon.md (adddi3_neon, subdi3_neon, anddi3_neon,
iordi3_neon, xordi3_neon): Add alternatives to discourage Neon
instructions when tuning for Cortex-A8. Set attribute "alt_tune".
* config/arm/arm.md (define_attr "alt_tune", define_attr "enabled"):
New.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-04-07 Thomas Schwinge <thomas@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2010-08-13 10:30:35 +0000
+++ new/gcc/config/arm/arm.md 2010-08-13 11:40:17 +0000
@@ -432,6 +432,20 @@
(const_string "yes")
(const_string "no"))))
+; Specifies which machine an alternative is tuned for. Used to compute
+; attribute ENABLED.
+(define_attr "alt_tune" "all,onlya8,nota8" (const_string "all"))
+
+(define_attr "enabled" ""
+ (cond [(and (eq_attr "alt_tune" "onlya8")
+ (not (eq_attr "tune" "cortexa8")))
+ (const_int 0)
+
+ (and (eq_attr "alt_tune" "nota8")
+ (eq_attr "tune" "cortexa8"))
+ (const_int 0)]
+ (const_int 1)))
+
(include "arm-generic.md")
(include "arm926ejs.md")
(include "arm1020e.md")
=== modified file 'gcc/config/arm/neon.md'
--- old/gcc/config/arm/neon.md 2010-08-10 13:31:21 +0000
+++ new/gcc/config/arm/neon.md 2010-08-13 11:40:17 +0000
@@ -827,23 +827,25 @@
)
(define_insn "adddi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
- (plus:DI (match_operand:DI 1 "s_register_operand" "%w,0,0")
- (match_operand:DI 2 "s_register_operand" "w,r,0")))
+ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r")
+ (plus:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0")
+ (match_operand:DI 2 "s_register_operand" "w,w,r,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_NEON"
{
switch (which_alternative)
{
- case 0: return "vadd.i64\t%P0, %P1, %P2";
- case 1: return "#";
+ case 0: /* fall through */
+ case 1: return "vadd.i64\t%P0, %P1, %P2";
case 2: return "#";
+ case 3: return "#";
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1,*,*")
- (set_attr "conds" "*,clob,clob")
- (set_attr "length" "*,8,8")]
+ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
+ (set_attr "conds" "*,*,clob,clob")
+ (set_attr "length" "*,*,8,8")
+ (set_attr "alt_tune" "nota8,onlya8,*,*")]
)
(define_insn "*sub<mode>3_neon"
@@ -861,24 +863,26 @@
)
(define_insn "subdi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?&r")
- (minus:DI (match_operand:DI 1 "s_register_operand" "w,0,r,0")
- (match_operand:DI 2 "s_register_operand" "w,r,0,0")))
+ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r,?&r")
+ (minus:DI (match_operand:DI 1 "s_register_operand" "w,w,0,r,0")
+ (match_operand:DI 2 "s_register_operand" "w,w,r,0,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_NEON"
{
switch (which_alternative)
{
- case 0: return "vsub.i64\t%P0, %P1, %P2";
- case 1: /* fall through */
- case 2: /* fall through */
- case 3: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2";
+ case 0: /* fall through */
+ case 1: return "vsub.i64\t%P0, %P1, %P2";
+ case 2: /* fall through */
+ case 3: /* fall through */
+ case 4: return "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2";
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_2,*,*,*")
- (set_attr "conds" "*,clob,clob,clob")
- (set_attr "length" "*,8,8,8")]
+ [(set_attr "neon_type" "neon_int_2,neon_int_2,*,*,*")
+ (set_attr "conds" "*,*,clob,clob,clob")
+ (set_attr "length" "*,*,8,8,8")
+ (set_attr "alt_tune" "nota8,onlya8,*,*,*")]
)
(define_insn "*mul<mode>3_neon"
@@ -964,23 +968,26 @@
)
(define_insn "iordi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r")
- (ior:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r")
- (match_operand:DI 2 "neon_logic_op2" "w,Dl,r,r")))]
+ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r")
+ (ior:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r")
+ (match_operand:DI 2 "neon_logic_op2" "w,w,Dl,Dl,r,r")))]
"TARGET_NEON"
{
switch (which_alternative)
{
- case 0: return "vorr\t%P0, %P1, %P2";
- case 1: return neon_output_logic_immediate ("vorr", &operands[2],
+ case 0: /* fall through */
+ case 1: return "vorr\t%P0, %P1, %P2";
+ case 2: /* fall through */
+ case 3: return neon_output_logic_immediate ("vorr", &operands[2],
DImode, 0, VALID_NEON_QREG_MODE (DImode));
- case 2: return "#";
- case 3: return "#";
+ case 4: return "#";
+ case 5: return "#";
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
- (set_attr "length" "*,*,8,8")]
+ [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*")
+ (set_attr "length" "*,*,*,*,8,8")
+ (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")]
)
;; The concrete forms of the Neon immediate-logic instructions are vbic and
@@ -1006,23 +1013,26 @@
)
(define_insn "anddi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "=w,w,?&r,?&r")
- (and:DI (match_operand:DI 1 "s_register_operand" "%w,0,0,r")
- (match_operand:DI 2 "neon_inv_logic_op2" "w,DL,r,r")))]
+ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,w,?w,?&r,?&r")
+ (and:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,0,0,r")
+ (match_operand:DI 2 "neon_inv_logic_op2" "w,w,DL,DL,r,r")))]
"TARGET_NEON"
{
switch (which_alternative)
{
- case 0: return "vand\t%P0, %P1, %P2";
- case 1: return neon_output_logic_immediate ("vand", &operands[2],
+ case 0: /* fall through */
+ case 1: return "vand\t%P0, %P1, %P2";
+ case 2: /* fall through */
+ case 3: return neon_output_logic_immediate ("vand", &operands[2],
DImode, 1, VALID_NEON_QREG_MODE (DImode));
- case 2: return "#";
- case 3: return "#";
+ case 4: return "#";
+ case 5: return "#";
default: gcc_unreachable ();
}
}
- [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
- (set_attr "length" "*,*,8,8")]
+ [(set_attr "neon_type" "neon_int_1,neon_int_1,neon_int_1,neon_int_1,*,*")
+ (set_attr "length" "*,*,*,*,8,8")
+ (set_attr "alt_tune" "nota8,onlya8,nota8,onlya8,*,*")]
)
(define_insn "orn<mode>3_neon"
@@ -1080,16 +1090,18 @@
)
(define_insn "xordi3_neon"
- [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r")
- (xor:DI (match_operand:DI 1 "s_register_operand" "%w,0,r")
- (match_operand:DI 2 "s_register_operand" "w,r,r")))]
+ [(set (match_operand:DI 0 "s_register_operand" "=w,?w,?&r,?&r")
+ (xor:DI (match_operand:DI 1 "s_register_operand" "%w,w,0,r")
+ (match_operand:DI 2 "s_register_operand" "w,w,r,r")))]
"TARGET_NEON"
"@
veor\t%P0, %P1, %P2
+ veor\t%P0, %P1, %P2
#
#"
- [(set_attr "neon_type" "neon_int_1,*,*")
- (set_attr "length" "*,8,8")]
+ [(set_attr "neon_type" "neon_int_1,neon_int_1,*,*")
+ (set_attr "length" "*,*,8,8")
+ (set_attr "alt_tune" "nota8,onlya8,*,*")]
)
(define_insn "one_cmpl<mode>2"
=== modified file 'gcc/config/arm/vfp.md'
--- old/gcc/config/arm/vfp.md 2010-08-13 10:59:06 +0000
+++ new/gcc/config/arm/vfp.md 2010-08-13 11:40:17 +0000
@@ -133,9 +133,51 @@
;; DImode moves
(define_insn "*arm_movdi_vfp"
- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,r,w,w, Uv")
- (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
+ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,w,r,w,w, Uv")
+ (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune != cortexa8
+ && ( register_operand (operands[0], DImode)
+ || register_operand (operands[1], DImode))"
+ "*
+ switch (which_alternative)
+ {
+ case 0:
+ return \"#\";
+ case 1:
+ case 2:
+ return output_move_double (operands);
+ case 3:
+ return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
+ case 4:
+ return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
+ case 5:
+ if (TARGET_VFP_SINGLE)
+ return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
+ else
+ return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
+ case 6: case 7:
+ return output_move_vfp (operands);
+ default:
+ gcc_unreachable ();
+ }
+ "
+ [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
+ (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
+ (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
+ (eq_attr "alternative" "5")
+ (if_then_else
+ (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
+ (const_int 8)
+ (const_int 4))]
+ (const_int 4)))
+ (set_attr "pool_range" "*,1020,*,*,*,*,1020,*")
+ (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
+)
+
+(define_insn "*arm_movdi_vfp_cortexa8"
+ [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r,m,w,!r,w,w, Uv")
+ (match_operand:DI 1 "di_operand" "rIK,mi,r,r,w,w,Uvi,w"))]
+ "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP && arm_tune == cortexa8
&& ( register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
"*
=== modified file 'gcc/ira-costs.c'
--- old/gcc/ira-costs.c 2009-11-25 10:55:54 +0000
+++ new/gcc/ira-costs.c 2010-08-13 11:40:17 +0000
@@ -224,6 +224,14 @@
int alt_fail = 0;
int alt_cost = 0, op_cost_add;
+ if (!recog_data.alternative_enabled_p[alt])
+ {
+ for (i = 0; i < recog_data.n_operands; i++)
+ constraints[i] = skip_alternative (constraints[i]);
+
+ continue;
+ }
+
for (i = 0; i < n_ops; i++)
{
unsigned char c;
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99354.patch
-384
View File
@@ -1,384 +0,0 @@
Richard Earnshaw <rearnsha@arm.com>
gcc/
* doc/tm.texi (OVERLAPPING_REGISTER_NAMES): Document new macro.
* output.h (decode_reg_name_and_count): Declare.
* varasm.c (decode_reg_name_and_count): New function.
(decode_reg_name): Reimplement using decode_reg_name_and_count.
* reginfo.c (fix_register): Use decode_reg_name_and_count and
iterate over all regs used.
* stmt.c (expand_asm_operands): Likewise.
* config/arm/aout.h (OVERLAPPING_REGISTER_NAMES): Define.
(ADDITIONAL_REGISTER_NAMES): Remove aliases that overlap
multiple machine registers.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-04-08 Bernd Schmidt <bernds@codesourcery.com>
Issue #6952
=== modified file 'gcc/config/arm/aout.h'
--- old/gcc/config/arm/aout.h 2009-06-21 19:48:15 +0000
+++ new/gcc/config/arm/aout.h 2010-08-13 11:53:46 +0000
@@ -163,31 +163,45 @@
{"mvdx12", 39}, \
{"mvdx13", 40}, \
{"mvdx14", 41}, \
- {"mvdx15", 42}, \
- {"d0", 63}, {"q0", 63}, \
- {"d1", 65}, \
- {"d2", 67}, {"q1", 67}, \
- {"d3", 69}, \
- {"d4", 71}, {"q2", 71}, \
- {"d5", 73}, \
- {"d6", 75}, {"q3", 75}, \
- {"d7", 77}, \
- {"d8", 79}, {"q4", 79}, \
- {"d9", 81}, \
- {"d10", 83}, {"q5", 83}, \
- {"d11", 85}, \
- {"d12", 87}, {"q6", 87}, \
- {"d13", 89}, \
- {"d14", 91}, {"q7", 91}, \
- {"d15", 93}, \
- {"q8", 95}, \
- {"q9", 99}, \
- {"q10", 103}, \
- {"q11", 107}, \
- {"q12", 111}, \
- {"q13", 115}, \
- {"q14", 119}, \
- {"q15", 123} \
+ {"mvdx15", 42} \
+}
+#endif
+
+#ifndef OVERLAPPING_REGISTER_NAMES
+#define OVERLAPPING_REGISTER_NAMES \
+{ \
+ {"d0", 63, 2}, \
+ {"d1", 65, 2}, \
+ {"d2", 67, 2}, \
+ {"d3", 69, 2}, \
+ {"d4", 71, 2}, \
+ {"d5", 73, 2}, \
+ {"d6", 75, 2}, \
+ {"d7", 77, 2}, \
+ {"d8", 79, 2}, \
+ {"d9", 81, 2}, \
+ {"d10", 83, 2}, \
+ {"d11", 85, 2}, \
+ {"d12", 87, 2}, \
+ {"d13", 89, 2}, \
+ {"d14", 91, 2}, \
+ {"d15", 93, 2}, \
+ {"q0", 63, 4}, \
+ {"q1", 67, 4}, \
+ {"q2", 71, 4}, \
+ {"q3", 75, 4}, \
+ {"q4", 79, 4}, \
+ {"q5", 83, 4}, \
+ {"q6", 87, 4}, \
+ {"q7", 91, 4}, \
+ {"q8", 95, 4}, \
+ {"q9", 99, 4}, \
+ {"q10", 103, 4}, \
+ {"q11", 107, 4}, \
+ {"q12", 111, 4}, \
+ {"q13", 115, 4}, \
+ {"q14", 119, 4}, \
+ {"q15", 123, 4} \
}
#endif
=== modified file 'gcc/doc/tm.texi'
--- old/gcc/doc/tm.texi 2010-06-24 20:06:37 +0000
+++ new/gcc/doc/tm.texi 2010-08-13 11:53:46 +0000
@@ -8339,6 +8339,22 @@
to registers using alternate names.
@end defmac
+@defmac OVERLAPPING_REGISTER_NAMES
+If defined, a C initializer for an array of structures containing a
+name, a register number and a count of the number of consecutive
+machine registers the name overlaps. This macro defines additional
+names for hard registers, thus allowing the @code{asm} option in
+declarations to refer to registers using alternate names. Unlike
+@code{ADDITIONAL_REGISTER_NAMES}, this macro should be used when the
+register name implies multiple underlying registers.
+
+This macro should be used when it is important that a clobber in an
+@code{asm} statement clobbers all the underlying values implied by the
+register name. For example, on ARM, clobbering the double-precision
+VFP register ``d0'' implies clobbering both single-precision registers
+``s0'' and ``s1''.
+@end defmac
+
@defmac ASM_OUTPUT_OPCODE (@var{stream}, @var{ptr})
Define this macro if you are using an unusual assembler that
requires different names for the machine instructions.
=== modified file 'gcc/output.h'
--- old/gcc/output.h 2009-10-26 21:57:10 +0000
+++ new/gcc/output.h 2010-08-13 11:53:46 +0000
@@ -173,6 +173,11 @@
Prefixes such as % are optional. */
extern int decode_reg_name (const char *);
+/* Similar to decode_reg_name, but takes an extra parameter that is a
+ pointer to the number of (internal) registers described by the
+ external name. */
+extern int decode_reg_name_and_count (const char *, int *);
+
extern void assemble_alias (tree, tree);
extern void default_assemble_visibility (tree, int);
=== modified file 'gcc/reginfo.c'
--- old/gcc/reginfo.c 2010-04-19 09:04:43 +0000
+++ new/gcc/reginfo.c 2010-08-13 11:53:46 +0000
@@ -799,36 +799,41 @@
fix_register (const char *name, int fixed, int call_used)
{
int i;
+ int reg, nregs;
/* Decode the name and update the primary form of
the register info. */
- if ((i = decode_reg_name (name)) >= 0)
+ if ((reg = decode_reg_name_and_count (name, &nregs)) >= 0)
{
- if ((i == STACK_POINTER_REGNUM
+ gcc_assert (nregs >= 1);
+ for (i = reg; i < reg + nregs; i++)
+ {
+ if ((i == STACK_POINTER_REGNUM
#ifdef HARD_FRAME_POINTER_REGNUM
- || i == HARD_FRAME_POINTER_REGNUM
+ || i == HARD_FRAME_POINTER_REGNUM
#else
- || i == FRAME_POINTER_REGNUM
+ || i == FRAME_POINTER_REGNUM
#endif
- )
- && (fixed == 0 || call_used == 0))
- {
- static const char * const what_option[2][2] = {
- { "call-saved", "call-used" },
- { "no-such-option", "fixed" }};
+ )
+ && (fixed == 0 || call_used == 0))
+ {
+ static const char * const what_option[2][2] = {
+ { "call-saved", "call-used" },
+ { "no-such-option", "fixed" }};
- error ("can't use '%s' as a %s register", name,
- what_option[fixed][call_used]);
- }
- else
- {
- fixed_regs[i] = fixed;
- call_used_regs[i] = call_used;
+ error ("can't use '%s' as a %s register", name,
+ what_option[fixed][call_used]);
+ }
+ else
+ {
+ fixed_regs[i] = fixed;
+ call_used_regs[i] = call_used;
#ifdef CALL_REALLY_USED_REGISTERS
- if (fixed == 0)
- call_really_used_regs[i] = call_used;
+ if (fixed == 0)
+ call_really_used_regs[i] = call_used;
#endif
+ }
}
}
else
=== modified file 'gcc/stmt.c'
--- old/gcc/stmt.c 2010-02-19 09:53:51 +0000
+++ new/gcc/stmt.c 2010-08-13 11:53:46 +0000
@@ -684,13 +684,14 @@
for (tail = clobbers; tail; tail = TREE_CHAIN (tail))
{
const char *regname;
+ int nregs;
if (TREE_VALUE (tail) == error_mark_node)
return;
regname = TREE_STRING_POINTER (TREE_VALUE (tail));
- i = decode_reg_name (regname);
- if (i >= 0 || i == -4)
+ i = decode_reg_name_and_count (regname, &nregs);
+ if (i == -4)
++nclobbers;
else if (i == -2)
error ("unknown register name %qs in %<asm%>", regname);
@@ -698,14 +699,21 @@
/* Mark clobbered registers. */
if (i >= 0)
{
- /* Clobbering the PIC register is an error. */
- if (i == (int) PIC_OFFSET_TABLE_REGNUM)
+ int reg;
+
+ for (reg = i; reg < i + nregs; reg++)
{
- error ("PIC register %qs clobbered in %<asm%>", regname);
- return;
+ ++nclobbers;
+
+ /* Clobbering the PIC register is an error. */
+ if (reg == (int) PIC_OFFSET_TABLE_REGNUM)
+ {
+ error ("PIC register clobbered by %qs in %<asm%>", regname);
+ return;
+ }
+
+ SET_HARD_REG_BIT (clobbered_regs, reg);
}
-
- SET_HARD_REG_BIT (clobbered_regs, i);
}
}
@@ -1026,7 +1034,8 @@
for (tail = clobbers; tail; tail = TREE_CHAIN (tail))
{
const char *regname = TREE_STRING_POINTER (TREE_VALUE (tail));
- int j = decode_reg_name (regname);
+ int reg, nregs;
+ int j = decode_reg_name_and_count (regname, &nregs);
rtx clobbered_reg;
if (j < 0)
@@ -1048,30 +1057,39 @@
continue;
}
- /* Use QImode since that's guaranteed to clobber just one reg. */
- clobbered_reg = gen_rtx_REG (QImode, j);
-
- /* Do sanity check for overlap between clobbers and respectively
- input and outputs that hasn't been handled. Such overlap
- should have been detected and reported above. */
- if (!clobber_conflict_found)
+ for (reg = j; reg < j + nregs; reg++)
{
- int opno;
-
- /* We test the old body (obody) contents to avoid tripping
- over the under-construction body. */
- for (opno = 0; opno < noutputs; opno++)
- if (reg_overlap_mentioned_p (clobbered_reg, output_rtx[opno]))
- internal_error ("asm clobber conflict with output operand");
-
- for (opno = 0; opno < ninputs - ninout; opno++)
- if (reg_overlap_mentioned_p (clobbered_reg,
- ASM_OPERANDS_INPUT (obody, opno)))
- internal_error ("asm clobber conflict with input operand");
+ /* Use QImode since that's guaranteed to clobber just
+ * one reg. */
+ clobbered_reg = gen_rtx_REG (QImode, reg);
+
+ /* Do sanity check for overlap between clobbers and
+ respectively input and outputs that hasn't been
+ handled. Such overlap should have been detected and
+ reported above. */
+ if (!clobber_conflict_found)
+ {
+ int opno;
+
+ /* We test the old body (obody) contents to avoid
+ tripping over the under-construction body. */
+ for (opno = 0; opno < noutputs; opno++)
+ if (reg_overlap_mentioned_p (clobbered_reg,
+ output_rtx[opno]))
+ internal_error
+ ("asm clobber conflict with output operand");
+
+ for (opno = 0; opno < ninputs - ninout; opno++)
+ if (reg_overlap_mentioned_p (clobbered_reg,
+ ASM_OPERANDS_INPUT (obody,
+ opno)))
+ internal_error
+ ("asm clobber conflict with input operand");
+ }
+
+ XVECEXP (body, 0, i++)
+ = gen_rtx_CLOBBER (VOIDmode, clobbered_reg);
}
-
- XVECEXP (body, 0, i++)
- = gen_rtx_CLOBBER (VOIDmode, clobbered_reg);
}
if (nlabels > 0)
=== modified file 'gcc/varasm.c'
--- old/gcc/varasm.c 2010-03-27 11:56:30 +0000
+++ new/gcc/varasm.c 2010-08-13 11:53:46 +0000
@@ -1043,8 +1043,11 @@
Prefixes such as % are optional. */
int
-decode_reg_name (const char *asmspec)
+decode_reg_name_and_count (const char *asmspec, int *pnregs)
{
+ /* Presume just one register is clobbered. */
+ *pnregs = 1;
+
if (asmspec != 0)
{
int i;
@@ -1070,6 +1073,25 @@
&& ! strcmp (asmspec, strip_reg_name (reg_names[i])))
return i;
+#ifdef OVERLAPPING_REGISTER_NAMES
+ {
+ static const struct
+ {
+ const char *const name;
+ const int number;
+ const int nregs;
+ } table[] = OVERLAPPING_REGISTER_NAMES;
+
+ for (i = 0; i < (int) ARRAY_SIZE (table); i++)
+ if (table[i].name[0]
+ && ! strcmp (asmspec, table[i].name))
+ {
+ *pnregs = table[i].nregs;
+ return table[i].number;
+ }
+ }
+#endif /* OVERLAPPING_REGISTER_NAMES */
+
#ifdef ADDITIONAL_REGISTER_NAMES
{
static const struct { const char *const name; const int number; } table[]
@@ -1093,6 +1115,14 @@
return -1;
}
+
+int
+decode_reg_name (const char *name)
+{
+ int count;
+ return decode_reg_name_and_count (name, &count);
+}
+
/* Return true if DECL's initializer is suitable for a BSS section. */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99355.patch
-181
View File
@@ -1,181 +0,0 @@
2010-04-12 Andrew Stubbs <ams@codesourcery.com>
Issue #7178
gcc/
* config/arm/arm.c (arm_init_libfuncs): Change __gnu_f2h_ieee to
__aeabi_f2h, __gnu_f2h_alternative to __aeabi_f2h_alt, __gnu_h2f_ieee
to __aeabi_h2f, and __gnu_h2f_alternative to __aeabi_h2f_alt.
* config/arm/fp16.c (__gnu_f2h_internal): Change return type to
unsigned int. Change 'sign' variable likewise.
(__gnu_h2f_internal): Set to static inline.
Change return type to unsigned int. Change 'sign' variable likewise.
(ALIAS): New define.
(__gnu_f2h_ieee): Change unsigned short to unsigned int.
(__gnu_h2f_ieee): Likewise.
(__gnu_f2h_alternative): Likewise.
(__gnu_h2f_alternative): Likewise.
(__aeabi_f2h, __aeabi_h2f): New aliases.
(__aeabi_f2h_alt, __aeabi_h2f_alt): Likewise.
* config/arm/sfp-machine.h (__extendhfsf2): Set to __aeabi_h2f.
(__truncsfhf2): Set to __aeabi_f2h.
gcc/testsuite/
* g++.dg/ext/arm-fp16/arm-fp16-ops-5.C: Check for __aeabi_h2f
and __aeabi_f2h.
* g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Likewise.
* gcc.dg/torture/arm-fp16-ops-5.c: Likewise.
* gcc.dg/torture/arm-fp16-ops-6.c: Likewise.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
Richard Earnshaw <rearnsha@arm.com>
gcc/
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-13 11:02:47 +0000
+++ new/gcc/config/arm/arm.c 2010-08-13 14:08:20 +0000
@@ -1054,12 +1054,12 @@
/* Conversions. */
set_conv_libfunc (trunc_optab, HFmode, SFmode,
(arm_fp16_format == ARM_FP16_FORMAT_IEEE
- ? "__gnu_f2h_ieee"
- : "__gnu_f2h_alternative"));
+ ? "__aeabi_f2h"
+ : "__aeabi_f2h_alt"));
set_conv_libfunc (sext_optab, SFmode, HFmode,
(arm_fp16_format == ARM_FP16_FORMAT_IEEE
- ? "__gnu_h2f_ieee"
- : "__gnu_h2f_alternative"));
+ ? "__aeabi_h2f"
+ : "__aeabi_h2f_alt"));
/* Arithmetic. */
set_optab_libfunc (add_optab, HFmode, NULL);
=== modified file 'gcc/config/arm/fp16.c'
--- old/gcc/config/arm/fp16.c 2009-06-18 11:26:37 +0000
+++ new/gcc/config/arm/fp16.c 2010-08-13 14:08:20 +0000
@@ -22,10 +22,10 @@
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
-static inline unsigned short
+static inline unsigned int
__gnu_f2h_internal(unsigned int a, int ieee)
{
- unsigned short sign = (a >> 16) & 0x8000;
+ unsigned int sign = (a >> 16) & 0x8000;
int aexp = (a >> 23) & 0xff;
unsigned int mantissa = a & 0x007fffff;
unsigned int mask;
@@ -95,10 +95,10 @@
return sign | (((aexp + 14) << 10) + (mantissa >> 13));
}
-unsigned int
-__gnu_h2f_internal(unsigned short a, int ieee)
+static inline unsigned int
+__gnu_h2f_internal(unsigned int a, int ieee)
{
- unsigned int sign = (unsigned int)(a & 0x8000) << 16;
+ unsigned int sign = (a & 0x00008000) << 16;
int aexp = (a >> 10) & 0x1f;
unsigned int mantissa = a & 0x3ff;
@@ -120,26 +120,33 @@
return sign | (((aexp + 0x70) << 23) + (mantissa << 13));
}
-unsigned short
+#define ALIAS(src, dst) \
+ typeof (src) dst __attribute__ ((alias (#src)));
+
+unsigned int
__gnu_f2h_ieee(unsigned int a)
{
return __gnu_f2h_internal(a, 1);
}
+ALIAS (__gnu_f2h_ieee, __aeabi_f2h)
unsigned int
-__gnu_h2f_ieee(unsigned short a)
+__gnu_h2f_ieee(unsigned int a)
{
return __gnu_h2f_internal(a, 1);
}
+ALIAS (__gnu_h2f_ieee, __aeabi_h2f)
-unsigned short
+unsigned int
__gnu_f2h_alternative(unsigned int x)
{
return __gnu_f2h_internal(x, 0);
}
+ALIAS (__gnu_f2h_alternative, __aeabi_f2h_alt)
unsigned int
-__gnu_h2f_alternative(unsigned short a)
+__gnu_h2f_alternative(unsigned int a)
{
return __gnu_h2f_internal(a, 0);
}
+ALIAS (__gnu_h2f_alternative, __aeabi_h2f_alt)
=== modified file 'gcc/config/arm/sfp-machine.h'
--- old/gcc/config/arm/sfp-machine.h 2009-06-18 11:26:37 +0000
+++ new/gcc/config/arm/sfp-machine.h 2010-08-13 14:08:20 +0000
@@ -99,7 +99,7 @@
#define __fixdfdi __aeabi_d2lz
#define __fixunsdfdi __aeabi_d2ulz
#define __floatdidf __aeabi_l2d
-#define __extendhfsf2 __gnu_h2f_ieee
-#define __truncsfhf2 __gnu_f2h_ieee
+#define __extendhfsf2 __aeabi_h2f
+#define __truncsfhf2 __aeabi_f2h
#endif /* __ARM_EABI__ */
=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C'
--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C 2010-07-29 15:38:15 +0000
+++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C 2010-08-13 14:08:20 +0000
@@ -13,3 +13,5 @@
/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
/* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
/* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
+/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */
+/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */
=== modified file 'gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C'
--- old/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C 2010-07-29 15:38:15 +0000
+++ new/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C 2010-08-13 14:08:20 +0000
@@ -13,3 +13,5 @@
/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
/* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
/* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
+/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */
+/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */
=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c'
--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c 2010-07-29 15:38:15 +0000
+++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c 2010-08-13 14:08:20 +0000
@@ -13,3 +13,5 @@
/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
/* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
/* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
+/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */
+/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */
=== modified file 'gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c'
--- old/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c 2010-07-29 15:38:15 +0000
+++ new/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c 2010-08-13 14:08:20 +0000
@@ -13,3 +13,5 @@
/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
/* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
/* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
+/* { dg-final { scan-assembler-not "\tbl\t__aeabi_h2f" } } */
+/* { dg-final { scan-assembler-not "\tbl\t__aeabi_f2h" } } */
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99356.patch
-376
View File
@@ -1,376 +0,0 @@
2010-04-11 Julian Brown <julian@codesourcery.com>
Issue #7326
gcc/
* config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5.
* config/arm/arm.md (generic_sched): No for Cortex-A5.
(generic_vfp): Likewise.
(cortex-a5.md): Include.
* config/arm/cortex-a5.md: New.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-04-12 Andrew Stubbs <ams@codesourcery.com>
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2010-08-13 14:08:20 +0000
+++ new/gcc/config/arm/arm.c 2010-08-13 15:15:12 +0000
@@ -22262,6 +22262,7 @@
{
case cortexr4:
case cortexr4f:
+ case cortexa5:
case cortexa8:
case cortexa9:
return 2;
=== modified file 'gcc/config/arm/arm.md'
--- old/gcc/config/arm/arm.md 2010-08-13 11:40:17 +0000
+++ new/gcc/config/arm/arm.md 2010-08-13 15:15:12 +0000
@@ -419,7 +419,7 @@
(define_attr "generic_sched" "yes,no"
(const (if_then_else
- (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9")
+ (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9")
(eq_attr "tune_cortexr4" "yes"))
(const_string "no")
(const_string "yes"))))
@@ -427,7 +427,7 @@
(define_attr "generic_vfp" "yes,no"
(const (if_then_else
(and (eq_attr "fpu" "vfp")
- (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9")
+ (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9")
(eq_attr "tune_cortexr4" "no"))
(const_string "yes")
(const_string "no"))))
@@ -451,6 +451,7 @@
(include "arm1020e.md")
(include "arm1026ejs.md")
(include "arm1136jfs.md")
+(include "cortex-a5.md")
(include "cortex-a8.md")
(include "cortex-a9.md")
(include "cortex-r4.md")
=== added file 'gcc/config/arm/cortex-a5.md'
--- old/gcc/config/arm/cortex-a5.md 1970-01-01 00:00:00 +0000
+++ new/gcc/config/arm/cortex-a5.md 2010-08-13 15:15:12 +0000
@@ -0,0 +1,310 @@
+;; ARM Cortex-A5 pipeline description
+;; Copyright (C) 2010 Free Software Foundation, Inc.
+;; Contributed by CodeSourcery.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but
+;; WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+;; General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "cortex_a5")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Functional units.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; The integer (ALU) pipeline. There are five DPU pipeline stages. However the
+;; decode/issue stages operate the same for all instructions, so do not model
+;; them. We only need to model the first execute stage because instructions
+;; always advance one stage per cycle in order. Only branch instructions may
+;; dual-issue, so a single unit covers all of the LS, ALU, MAC and FPU
+;; pipelines.
+
+(define_cpu_unit "cortex_a5_ex1" "cortex_a5")
+
+;; The branch pipeline. Branches can dual-issue with other instructions
+;; (except when those instructions take multiple cycles to issue).
+
+(define_cpu_unit "cortex_a5_branch" "cortex_a5")
+
+;; Pseudo-unit for blocking the multiply pipeline when a double-precision
+;; multiply is in progress.
+
+(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5")
+
+;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
+;; of the add pipeline by fmac instructions, etc.
+
+(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5")
+
+;; Floating-point div/sqrt (long latency, out-of-order completion).
+
+(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; ALU instructions.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define_insn_reservation "cortex_a5_alu" 2
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "alu"))
+ "cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_alu_shift" 2
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "alu_shift,alu_shift_reg"))
+ "cortex_a5_ex1")
+
+;; Forwarding path for unshifted operands.
+
+(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
+ "cortex_a5_alu")
+
+(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
+ "cortex_a5_alu_shift"
+ "arm_no_early_alu_shift_dep")
+
+;; The multiplier pipeline can forward results from wr stage only (so I don't
+;; think there's any need to specify bypasses).
+
+(define_insn_reservation "cortex_a5_mul" 2
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "mult"))
+ "cortex_a5_ex1")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Load/store instructions.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; Address-generation happens in the issue stage, which is one stage behind
+;; the ex1 stage (the first stage we care about for scheduling purposes). The
+;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
+
+;; FIXME: These might not be entirely accurate for load2, load3, load4. I think
+;; they make sense since there's a 32-bit interface between the DPU and the DCU,
+;; so we can't load more than that per cycle. The store2, store3, store4
+;; reservations are similarly guessed.
+
+(define_insn_reservation "cortex_a5_load1" 2
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "load_byte,load1"))
+ "cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_store1" 0
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "store1"))
+ "cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_load2" 3
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "load2"))
+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_store2" 0
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "store2"))
+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_load3" 4
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "load3"))
+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
+ cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_store3" 0
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "store3"))
+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
+ cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_load4" 5
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "load3"))
+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
+ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_store4" 0
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "store3"))
+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
+ cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Branches.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; Direct branches are the only instructions we can dual-issue (also IT and
+;; nop, but those aren't very interesting for scheduling). (The latency here
+;; is meant to represent when the branch actually takes place, but may not be
+;; entirely correct.)
+
+(define_insn_reservation "cortex_a5_branch" 3
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "branch,call"))
+ "cortex_a5_branch")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Floating-point arithmetic.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define_insn_reservation "cortex_a5_fpalu" 4
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
+ fcmps, fcmpd"))
+ "cortex_a5_ex1+cortex_a5_fpadd_pipe")
+
+;; For fconsts and fconstd, 8-bit immediate data is passed directly from
+;; f1 to f3 (which I think reduces the latency by one cycle).
+
+(define_insn_reservation "cortex_a5_fconst" 3
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "fconsts,fconstd"))
+ "cortex_a5_ex1+cortex_a5_fpadd_pipe")
+
+;; We should try not to attempt to issue a single-precision multiplication in
+;; the middle of a double-precision multiplication operation (the usage of
+;; cortex_a5_fpmul_pipe).
+
+(define_insn_reservation "cortex_a5_fpmuls" 4
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "fmuls"))
+ "cortex_a5_ex1+cortex_a5_fpmul_pipe")
+
+;; For single-precision multiply-accumulate, the add (accumulate) is issued
+;; whilst the multiply is in F4. The multiply result can then be forwarded
+;; from F5 to F1. The issue unit is only used once (when we first start
+;; processing the instruction), but the usage of the FP add pipeline could
+;; block other instructions attempting to use it simultaneously. We try to
+;; avoid that using cortex_a5_fpadd_pipe.
+
+(define_insn_reservation "cortex_a5_fpmacs" 8
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "fmacs"))
+ "cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
+
+;; Non-multiply instructions can issue in the middle two instructions of a
+;; double-precision multiply. Note that it isn't entirely clear when a branch
+;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
+;; that for now though.
+
+(define_insn_reservation "cortex_a5_fpmuld" 7
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "fmuld"))
+ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
+ cortex_a5_ex1+cortex_a5_fpmul_pipe")
+
+(define_insn_reservation "cortex_a5_fpmacd" 11
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "fmacd"))
+ "cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
+ cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Floating-point divide/square root instructions.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; ??? Not sure if the 14 cycles taken for single-precision divide to complete
+;; includes the time taken for the special instruction used to collect the
+;; result to travel down the multiply pipeline, or not. Assuming so. (If
+;; that's wrong, the latency should be increased by a few cycles.)
+
+;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
+;; multiply pipeline to collect the divide/square-root result.
+
+(define_insn_reservation "cortex_a5_fdivs" 14
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "fdivs"))
+ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
+
+;; ??? Similarly for fdivd.
+
+(define_insn_reservation "cortex_a5_fdivd" 29
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "fdivd"))
+ "cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; VFP to/from core transfers.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; FP loads take data from wr/rot/f3. Might need to define bypasses to model
+;; this?
+
+;; Core-to-VFP transfers use the multiply pipeline.
+;; Not sure about this at all... I think we need some bypasses too.
+
+(define_insn_reservation "cortex_a5_r2f" 4
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "r_2_f"))
+ "cortex_a5_ex1")
+
+;; Not sure about this either. 6.8.7 says "Additionally, the store pipe used
+;; for store and FP->core register transfers can forward into the F2 and F3
+;; stages."
+;; This doesn't correspond to what we have though.
+
+(define_insn_reservation "cortex_a5_f2r" 2
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "f_2_r"))
+ "cortex_a5_ex1")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; VFP flag transfer.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+;; ??? The flag forwarding described in section 6.8.11 of the Cortex-A5 DPU
+;; specification (from fmstat to the ex2 stage of the second instruction) is
+;; not modeled at present.
+
+(define_insn_reservation "cortex_a5_f_flags" 4
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "f_flag"))
+ "cortex_a5_ex1")
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; VFP load/store.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(define_insn_reservation "cortex_a5_f_loads" 4
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "f_loads"))
+ "cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_f_loadd" 5
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "f_load,f_loadd"))
+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_f_stores" 0
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "f_stores"))
+ "cortex_a5_ex1")
+
+(define_insn_reservation "cortex_a5_f_stored" 0
+ (and (eq_attr "tune" "cortexa5")
+ (eq_attr "type" "f_store,f_stored"))
+ "cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
+
+;; Load-to-use for floating-point values has a penalty of one cycle, i.e. a
+;; latency of two (6.8.3).
+
+(define_bypass 2 "cortex_a5_f_loads"
+ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
+ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
+ cortex_a5_f2r")
+
+(define_bypass 3 "cortex_a5_f_loadd"
+ "cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
+ cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
+ cortex_a5_f2r")
toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99357.patch
-27
View File
@@ -1,27 +0,0 @@
2010-06-12 Jie Zhang <jie@codesourcery.com>
gcc/
* config/arm/vfp.md (arm_movsi_vfp): Set neon_type correctly
for neon_ldr and neon_str instructions.
2010-07-26 Julian Brown <julian@codesourcery.com>
Merge from Sourcery G++ 4.4:
2010-04-11 Julian Brown <julian@codesourcery.com>
Issue #7326
=== modified file 'gcc/config/arm/vfp.md'
--- old/gcc/config/arm/vfp.md 2010-08-13 11:40:17 +0000
+++ new/gcc/config/arm/vfp.md 2010-08-13 15:28:31 +0000
@@ -82,7 +82,7 @@
"
[(set_attr "predicable" "yes")
(set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
- (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
+ (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,neon_ldr,neon_str")
(set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
(set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
)

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