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gcc-4.5: Upgrade to latest gcc-4_5-branch and linaro 4.5

Browse Source 
Additionally fix ppc build break caused by linaro android config
patches.

Angstrom console-image built clean from scratch for arm ppc mips x86 x86_64

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
This commit is contained in:
Khem Raj
2011-06-18 00:37:23 +00:00
committed by Koen Kooi
parent c85efd2281
commit 7d954ed266
12 changed files with 7213 additions and 217 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
meta-oe/recipes-devtools/gcc/gcc-4.5.inc
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@@ -14,14 +14,21 @@ LIC_FILES_CHKSUM = "file://COPYING;md5=59530bdf33659b29e73d4adb9f9f6552 \
PV = "4.5"
INC_PR = "r36"
# BINV should point to minor release
BINV = "${PV}.3"
INC_PR = "r37"
SRC_URI[md5sum] = "8e0b5c12212e185f3e4383106bfa9cc6"
SRC_URI[sha256sum] = "0a8847af44a9b33813b199997a73139517c96adfd519eaf24c79d4d9d09f65de"
# BINV should be incremented after updating to a revision
# after a minor gcc release (e.g. 4.5.1 or 4.5.2) has been made
# the value will be minor-release+1 e.g. if minor release was
# 4.5.1 then the value below will be 2 which will mean 4.5.2
# which will be next minor release and so on.
SRC_URI = "${GNU_MIRROR}/gcc/gcc-${BINV}/gcc-${BINV}.tar.bz2 \
BINV = "${PV}.4"
SRCREV = 175127
BRANCH = "gcc-4_5-branch"
PR_append = "+svnr${SRCPV}"
SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH};proto=http \
file://gcc-4.3.1-ARCH_FLAGS_FOR_TARGET.patch \
file://100-uclibc-conf.patch \
file://gcc-uclibc-locale-ctype_touplow_t.patch \
@@ -177,6 +184,15 @@ SRC_URI = "${GNU_MIRROR}/gcc/gcc-${BINV}/gcc-${BINV}.tar.bz2 \
file://linaro/gcc-4.5-linaro-r99495.patch \
file://linaro/gcc-4.5-linaro-r99498.patch \
file://linaro/gcc-4.5-linaro-r99502.patch \
file://linaro/gcc-4.5-linaro-r99503.patch \
file://linaro/gcc-4.5-linaro-r99504.patch \
file://linaro/gcc-4.5-linaro-r99506.patch \
file://linaro/gcc-4.5-linaro-r99507.patch \
file://linaro/gcc-4.5-linaro-r99510.patch \
file://linaro/gcc-4.5-linaro-r99511.patch \
file://linaro/gcc-4.5-linaro-r99514.patch \
file://linaro/gcc-4.5-linaro-r99516.patch \
\
file://more-epilogues.patch \
file://gcc-scalar-widening-pr45847.patch \
file://gcc-arm-volatile-bitfield-fix.patch \
@@ -198,13 +214,15 @@ SRC_URI = "${GNU_MIRROR}/gcc/gcc-${BINV}/gcc-${BINV}.tar.bz2 \
file://COLLECT_GCC_OPTIONS.patch \
file://gcc-poison-dir-extend.patch \
file://gcc-poison-parameters.patch \
file://gcc-ppc-config-fix.patch \
file://gcc-ppc-include-config-linux.h.patch \
"
# Language Overrides
FORTRAN = ""
JAVA = ""
S = "${WORKDIR}/gcc-${BINV}"
S = "${WORKDIR}/${BRANCH}"
#EXTRA_OECONF_BASE = " --enable-cheaders=c_std \
# --enable-libssp \

227
meta-oe/recipes-devtools/gcc/gcc-4.5/gcc-ppc-config-fix.patch Normal file
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@@ -0,0 +1,227 @@
commit de784bee66a1ec1d0dad00d9eedbe9b1667dd883
Author: jsm28 <jsm28@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Mon Dec 20 15:29:31 2010 +0000
* config/rs6000/freebsd.h (SVR4_ASM_SPEC): Don't define.
(DBX_REGISTER_NUMBER): Define.
* config/rs6000/lynx.h (DBX_REGISTER_NUMBER): Define.
* config/rs6000/netbsd.h (DBX_REGISTER_NUMBER): Define.
* config/rs6000/sysv4.h (SIZE_TYPE): Define.
(ASM_SPEC): Define without using SVR4_ASM_SPEC.
(DBX_REGISTER_NUMBER): Undefine.
* config.gcc (powerpc-*-eabispe*, powerpc-*-eabisimaltivec*,
powerpc-*-eabisim*, powerpc-*-elf*, powerpc-*-eabialtivec*,
powerpc-xilinx-eabi*, powerpc-*-eabi*, powerpc-*-rtems*,
powerpc-*-linux* | powerpc64-*-linux*, powerpc64-*-gnu*,
powerpc-*-gnu-gnualtivec*, powerpc-*-gnu*,
powerpc-wrs-vxworks|powerpc-wrs-vxworksae, powerpcle-*-elf*,
powerpcle-*-eabisim*, powerpcle-*-eabi*): Don't use svr4.h.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@168085 138bc75d-0d04-0410-961f-82ee72b054a4
Index: gcc-4.5.3/gcc/config.gcc
===================================================================
--- gcc-4.5.3.orig/gcc/config.gcc 2011-06-15 21:18:55.000000000 -0700
+++ gcc-4.5.3/gcc/config.gcc 2011-06-16 15:01:07.945285352 -0700
@@ -1989,53 +1989,53 @@
extra_options="${extra_options} rs6000/sysv4.opt"
;;
powerpc-*-eabispe*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabispe.h"
+ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabispe.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-spe rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-eabisimaltivec*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h rs6000/eabialtivec.h"
+ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h rs6000/eabialtivec.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-eabisim*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-elf*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
;;
powerpc-*-eabialtivec*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h"
+ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcendian rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-xilinx-eabi*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/singlefp.h rs6000/xfpu.h rs6000/xilinx.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm rs6000/t-xilinx"
use_gcc_stdint=wrap
;;
powerpc-*-eabi*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
use_gcc_stdint=wrap
;;
powerpc-*-rtems*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h"
+ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-rtems t-rtems rs6000/t-ppccomm"
;;
powerpc-*-linux* | powerpc64-*-linux*)
- tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h"
+ tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h rs6000/sysv4.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="t-dfprules rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm"
maybe_biarch=yes
@@ -2079,12 +2079,12 @@
fi
;;
powerpc64-*-gnu*)
- tm_file="${tm_file} elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/default64.h rs6000/linux64.h rs6000/gnu.h glibc-stdint.h"
+ tm_file="${tm_file} elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/default64.h rs6000/linux64.h rs6000/gnu.h glibc-stdint.h"
extra_options="${extra_options} rs6000/sysv4.opt rs6000/linux64.opt"
tmake_file="t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu"
;;
powerpc-*-gnu-gnualtivec*)
- tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h glibc-stdint.h"
+ tm_file="${cpu_type}/${cpu_type}.h elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h glibc-stdint.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcos t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu rs6000/t-ppccomm"
if test x$enable_threads = xyes; then
@@ -2092,7 +2092,7 @@
fi
;;
powerpc-*-gnu*)
- tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/gnu.h glibc-stdint.h"
+ tm_file="${cpu_type}/${cpu_type}.h elfos.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/gnu.h glibc-stdint.h"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcos t-slibgcc-elf-ver t-slibgcc-libgcc t-gnu rs6000/t-ppccomm"
extra_options="${extra_options} rs6000/sysv4.opt"
if test x$enable_threads = xyes; then
@@ -2100,7 +2100,7 @@
fi
;;
powerpc-wrs-vxworks|powerpc-wrs-vxworksae)
- tm_file="${tm_file} elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h"
+ tm_file="${tm_file} elfos.h freebsd-spec.h rs6000/sysv4.h"
tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppccomm rs6000/t-vxworks"
extra_options="${extra_options} rs6000/sysv4.opt"
extra_headers=ppc-asm.h
@@ -2126,18 +2126,18 @@
gas=yes
;;
powerpcle-*-elf*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
extra_options="${extra_options} rs6000/sysv4.opt"
;;
powerpcle-*-eabisim*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h rs6000/eabisim.h"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
extra_options="${extra_options} rs6000/sysv4.opt"
use_gcc_stdint=wrap
;;
powerpcle-*-eabi*)
- tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h"
+ tm_file="${tm_file} dbxelf.h elfos.h usegas.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/sysv4le.h rs6000/eabi.h rs6000/e500.h"
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
extra_options="${extra_options} rs6000/sysv4.opt"
use_gcc_stdint=wrap
Index: gcc-4.5.3/gcc/config/rs6000/freebsd.h
===================================================================
--- gcc-4.5.3.orig/gcc/config/rs6000/freebsd.h 2009-08-10 11:23:57.000000000 -0700
+++ gcc-4.5.3/gcc/config/rs6000/freebsd.h 2011-06-16 15:02:02.775285339 -0700
@@ -69,6 +69,4 @@
/* Override rs6000.h definition. */
#undef ASM_APP_OFF
#define ASM_APP_OFF "#NO_APP\n"
-/* Define SVR4_ASM_SPEC, we use GAS by default. See svr4.h for details. */
-#define SVR4_ASM_SPEC \
- "%{v:-V} %{Wa,*:%*}"
+#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
Index: gcc-4.5.3/gcc/config/rs6000/lynx.h
===================================================================
--- gcc-4.5.3.orig/gcc/config/rs6000/lynx.h 2007-08-02 03:49:31.000000000 -0700
+++ gcc-4.5.3/gcc/config/rs6000/lynx.h 2011-06-16 15:01:07.945285352 -0700
@@ -1,5 +1,5 @@
/* Definitions for Rs6000 running LynxOS.
- Copyright (C) 1995, 1996, 2000, 2002, 2003, 2004, 2005, 2007
+ Copyright (C) 1995, 1996, 2000, 2002, 2003, 2004, 2005, 2007, 2010
Free Software Foundation, Inc.
Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com)
Rewritten by Adam Nemet, LynuxWorks Inc.
@@ -105,6 +105,8 @@
#undef HAVE_AS_TLS
#define HAVE_AS_TLS 0
+#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
+
#ifdef CRT_BEGIN
/* This function is part of crtbegin*.o which is at the beginning of
the link and is called from .fini which is usually toward the end
Index: gcc-4.5.3/gcc/config/rs6000/netbsd.h
===================================================================
--- gcc-4.5.3.orig/gcc/config/rs6000/netbsd.h 2009-02-20 07:20:38.000000000 -0800
+++ gcc-4.5.3/gcc/config/rs6000/netbsd.h 2011-06-16 15:01:07.945285352 -0700
@@ -1,6 +1,6 @@
/* Definitions of target machine for GNU compiler,
for PowerPC NetBSD systems.
- Copyright 2002, 2003, 2007, 2008 Free Software Foundation, Inc.
+ Copyright 2002, 2003, 2007, 2008, 2010 Free Software Foundation, Inc.
Contributed by Wasabi Systems, Inc.
This file is part of GCC.
@@ -89,3 +89,5 @@
#undef TARGET_VERSION
#define TARGET_VERSION fprintf (stderr, " (NetBSD/powerpc ELF)");
+
+#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)
Index: gcc-4.5.3/gcc/config/rs6000/sysv4.h
===================================================================
--- gcc-4.5.3.orig/gcc/config/rs6000/sysv4.h 2011-06-15 21:18:57.000000000 -0700
+++ gcc-4.5.3/gcc/config/rs6000/sysv4.h 2011-06-16 15:01:07.945285352 -0700
@@ -293,6 +293,10 @@
#define RESTORE_FP_PREFIX "_restfpr_"
#define RESTORE_FP_SUFFIX ""
+/* Type used for size_t, as a string used in a declaration. */
+#undef SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
/* Type used for ptrdiff_t, as a string used in a declaration. */
#define PTRDIFF_TYPE "int"
@@ -588,9 +592,8 @@
/* Override svr4.h definition. */
#undef ASM_SPEC
#define ASM_SPEC "%(asm_cpu) \
-%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}" \
-SVR4_ASM_SPEC \
-"%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \
+%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}} \
+%{mrelocatable} %{mrelocatable-lib} %{fpic|fpie|fPIC|fPIE:-K PIC} \
%{memb|msdata=eabi: -memb} \
%{mlittle|mlittle-endian:-mlittle; \
mbig|mbig-endian :-mbig; \
@@ -1127,3 +1130,5 @@
/* This target uses the sysv4.opt file. */
#define TARGET_USES_SYSV4_OPT 1
+
+#undef DBX_REGISTER_NUMBER

73
meta-oe/recipes-devtools/gcc/gcc-4.5/gcc-ppc-include-config-linux.h.patch Normal file
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@@ -0,0 +1,73 @@
The patch is a solution for https://bugs.launchpad.net/ubuntu/+source/gcc-4.5/+bug/768921
-Khem
Index: gcc-4_5-branch/gcc/config.gcc
===================================================================
--- gcc-4_5-branch.orig/gcc/config.gcc 2011-06-16 21:23:22.000000000 -0700
+++ gcc-4_5-branch/gcc/config.gcc 2011-06-16 21:51:20.845279713 -0700
@@ -2035,7 +2035,7 @@
tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-rtems t-rtems rs6000/t-ppccomm"
;;
powerpc-*-linux* | powerpc64-*-linux*)
- tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h rs6000/sysv4.h"
+ tm_file="${tm_file} dbxelf.h elfos.h linux.h freebsd-spec.h rs6000/sysv4.h"
extra_options="${extra_options} rs6000/sysv4.opt"
tmake_file="t-dfprules rs6000/t-fprules rs6000/t-ppcos ${tmake_file} rs6000/t-ppccomm"
maybe_biarch=yes
Index: gcc-4_5-branch/gcc/config/rs6000/sysv4.h
===================================================================
--- gcc-4_5-branch.orig/gcc/config/rs6000/sysv4.h 2011-06-16 21:23:22.000000000 -0700
+++ gcc-4_5-branch/gcc/config/rs6000/sysv4.h 2011-06-16 22:08:49.425279473 -0700
@@ -620,6 +620,7 @@
#define CC1_SECURE_PLT_DEFAULT_SPEC ""
#endif
+#undef CC1_SPEC
/* Pass -G xxx to the compiler and set correct endian mode. */
#define CC1_SPEC "%{G*} %(cc1_cpu) \
%{mlittle|mlittle-endian: %(cc1_endian_little); \
@@ -903,22 +904,13 @@
#define LINK_START_LINUX_SPEC ""
#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
-#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
-#if DEFAULT_LIBC == LIBC_UCLIBC
-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
-#elif DEFAULT_LIBC == LIBC_GLIBC
-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
-#else
-#error "Unsupported DEFAULT_LIBC"
-#endif
-#define LINUX_DYNAMIC_LINKER \
- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
#define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \
%{rdynamic:-export-dynamic} \
%{!dynamic-linker:-dynamic-linker " LINUX_DYNAMIC_LINKER "}}}"
#if defined(HAVE_LD_EH_FRAME_HDR)
+# undef LINK_EH_SPEC
# define LINK_EH_SPEC "--no-add-needed %{!static:--eh-frame-hdr} "
#endif
@@ -1113,6 +1105,7 @@
be stacked, so that invocations of #pragma pack(pop)' will return
to the previous value. */
+#undef HANDLE_PRAGMA_PACK_PUSH_POP
#define HANDLE_PRAGMA_PACK_PUSH_POP 1
/* Select a format to encode pointers in exception handling data. CODE
Index: gcc-4_5-branch/gcc/config/freebsd-spec.h
===================================================================
--- gcc-4_5-branch.orig/gcc/config/freebsd-spec.h 2011-06-16 17:59:03.000000000 -0700
+++ gcc-4_5-branch/gcc/config/freebsd-spec.h 2011-06-16 22:11:34.145279435 -0700
@@ -154,6 +154,7 @@
#endif
#if defined(HAVE_LD_EH_FRAME_HDR)
+#undef LINK_EH_SPEC
#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
#endif

278
meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99475.patch
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@@ -98,8 +98,8 @@
=== added file 'gcc/config/arm/arm-ldmstm.ml'
Index: gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml
===================================================================
--- /dev/null
+++ gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml 2011-06-16 18:46:26.355282255 -0700
@@ -0,0 +1,333 @@
+(* Auto-generate ARM ldm/stm patterns
+ Copyright (C) 2010 Free Software Foundation, Inc.
@@ -436,9 +436,9 @@ Index: gcc-4_5-branch/gcc/config/arm/arm-ldmstm.ml
+ patterns ();
Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
===================================================================
--- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h
+++ gcc-4_5-branch/gcc/config/arm/arm-protos.h
@@ -100,14 +100,11 @@ extern int symbol_mentioned_p (rtx);
--- gcc-4_5-branch.orig/gcc/config/arm/arm-protos.h 2011-06-16 18:46:18.000000000 -0700
+++ gcc-4_5-branch/gcc/config/arm/arm-protos.h 2011-06-16 18:46:26.355282255 -0700
@@ -99,14 +99,11 @@
extern int label_mentioned_p (rtx);
extern RTX_CODE minmax_code (rtx);
extern int adjacent_mem_locations (rtx, rtx);
@@ -460,9 +460,9 @@ Index: gcc-4_5-branch/gcc/config/arm/arm-protos.h
extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx,
Index: gcc-4_5-branch/gcc/config/arm/arm.c
===================================================================
--- gcc-4_5-branch.orig/gcc/config/arm/arm.c
+++ gcc-4_5-branch/gcc/config/arm/arm.c
@@ -753,6 +753,12 @@ static const char * const arm_condition_
--- gcc-4_5-branch.orig/gcc/config/arm/arm.c 2011-06-16 18:46:23.000000000 -0700
+++ gcc-4_5-branch/gcc/config/arm/arm.c 2011-06-16 18:46:26.365282255 -0700
@@ -753,6 +753,12 @@
"hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
};
@@ -475,7 +475,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
#define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
#define streq(string1, string2) (strcmp (string1, string2) == 0)
@@ -9680,24 +9686,125 @@ adjacent_mem_locations (rtx a, rtx b)
@@ -9668,24 +9674,125 @@
return 0;
}
@@ -612,7 +612,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
/* Loop over the operands and check that the memory references are
suitable (i.e. immediate offsets from the same base register). At
@@ -9735,32 +9842,30 @@ load_multiple_sequence (rtx *operands, i
@@ -9723,32 +9830,30 @@
if (i == 0)
{
base_reg = REGNO (reg);
@@ -659,7 +659,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
}
else
/* Not a suitable memory address. */
@@ -9769,167 +9874,90 @@ load_multiple_sequence (rtx *operands, i
@@ -9757,167 +9862,90 @@
/* All the useful information has now been extracted from the
operands into unsorted_regs and unsorted_offsets; additionally,
@@ -888,7 +888,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
/* Loop over the operands and check that the memory references are
suitable (i.e. immediate offsets from the same base register). At
@@ -9964,32 +9992,32 @@ store_multiple_sequence (rtx *operands,
@@ -9952,32 +9980,32 @@
&& (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
== CONST_INT)))
{
@@ -937,7 +937,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
}
else
/* Not a suitable memory address. */
@@ -9998,111 +10026,65 @@ store_multiple_sequence (rtx *operands,
@@ -9986,111 +10014,65 @@
/* All the useful information has now been extracted from the
operands into unsorted_regs and unsorted_offsets; additionally,
@@ -1087,7 +1087,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
/* XScale has load-store double instructions, but they have stricter
alignment requirements than load-store multiple, so we cannot
@@ -10139,18 +10121,10 @@ arm_gen_load_multiple (int base_regno, i
@@ -10127,18 +10109,10 @@
start_sequence ();
for (i = 0; i < count; i++)
@@ -1109,7 +1109,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
seq = get_insns ();
end_sequence ();
@@ -10159,41 +10133,40 @@ arm_gen_load_multiple (int base_regno, i
@@ -10147,41 +10121,40 @@
}
result = gen_rtx_PARALLEL (VOIDmode,
@@ -1170,7 +1170,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
the pros/cons of ldm/stm usage for XScale. */
if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
{
@@ -10202,18 +10175,10 @@ arm_gen_store_multiple (int base_regno,
@@ -10190,18 +10163,10 @@
start_sequence ();
for (i = 0; i < count; i++)
@@ -1192,7 +1192,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
seq = get_insns ();
end_sequence ();
@@ -10222,29 +10187,319 @@ arm_gen_store_multiple (int base_regno,
@@ -10210,29 +10175,319 @@
}
result = gen_rtx_PARALLEL (VOIDmode,
@@ -1522,7 +1522,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
}
int
@@ -10280,20 +10535,21 @@ arm_gen_movmemqi (rtx *operands)
@@ -10268,20 +10523,21 @@
for (i = 0; in_words_to_go >= 2; i+=4)
{
if (in_words_to_go > 4)
@@ -1554,9 +1554,9 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.c
dstbase, &dstoffset));
Index: gcc-4_5-branch/gcc/config/arm/arm.h
===================================================================
--- gcc-4_5-branch.orig/gcc/config/arm/arm.h
+++ gcc-4_5-branch/gcc/config/arm/arm.h
@@ -1143,6 +1143,9 @@ extern int arm_structure_size_boundary;
--- gcc-4_5-branch.orig/gcc/config/arm/arm.h 2011-06-16 18:46:20.000000000 -0700
+++ gcc-4_5-branch/gcc/config/arm/arm.h 2011-06-16 18:46:26.375282255 -0700
@@ -1143,6 +1143,9 @@
((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \
|| (MODE) == CImode || (MODE) == XImode)
@@ -1566,7 +1566,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.h
/* The order in which register should be allocated. It is good to use ip
since no saving is required (though calls clobber it) and it never contains
function parameters. It is quite good to use lr since other calls may
@@ -2823,4 +2826,8 @@ enum arm_builtins
@@ -2821,4 +2824,8 @@
#define NEED_INDICATE_EXEC_STACK 0
#endif
@@ -1577,8 +1577,8 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.h
#endif /* ! GCC_ARM_H */
Index: gcc-4_5-branch/gcc/config/arm/arm.md
===================================================================
--- gcc-4_5-branch.orig/gcc/config/arm/arm.md
+++ gcc-4_5-branch/gcc/config/arm/arm.md
--- gcc-4_5-branch.orig/gcc/config/arm/arm.md 2011-06-16 18:46:23.000000000 -0700
+++ gcc-4_5-branch/gcc/config/arm/arm.md 2011-06-16 18:46:26.375282255 -0700
@@ -6282,7 +6282,7 @@
;; load- and store-multiple insns
@@ -1847,7 +1847,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.md
;; Move a block of memory if it is word aligned and MORE than 2 words long.
;; We could let this apply for blocks of less than this, but it clobbers so
@@ -9031,8 +8804,8 @@
@@ -9025,8 +8798,8 @@
if (REGNO (reg) == R0_REGNUM)
{
/* On thumb we have to use a write-back instruction. */
@@ -1858,7 +1858,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.md
size = TARGET_ARM ? 16 : 0;
}
else
@@ -9078,8 +8851,8 @@
@@ -9072,8 +8845,8 @@
if (REGNO (reg) == R0_REGNUM)
{
/* On thumb we have to use a write-back instruction. */
@@ -1869,7 +1869,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.md
size = TARGET_ARM ? 16 : 0;
}
else
@@ -10672,87 +10445,6 @@
@@ -10666,87 +10439,6 @@
""
)
@@ -1957,7 +1957,7 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.md
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(and:SI (ge:SI (match_operand:SI 1 "s_register_operand" "")
@@ -11554,6 +11246,8 @@
@@ -11549,6 +11241,8 @@
"
)
@@ -1968,8 +1968,8 @@ Index: gcc-4_5-branch/gcc/config/arm/arm.md
;; Load the Maverick co-processor patterns
Index: gcc-4_5-branch/gcc/config/arm/ldmstm.md
===================================================================
--- /dev/null
+++ gcc-4_5-branch/gcc/config/arm/ldmstm.md
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ gcc-4_5-branch/gcc/config/arm/ldmstm.md 2011-06-16 18:46:26.375282255 -0700
@@ -0,0 +1,1191 @@
+/* ARM ldm/stm instruction patterns. This file was automatically generated
+ using arm-ldmstm.ml. Please do not edit manually.
@@ -3164,8 +3164,8 @@ Index: gcc-4_5-branch/gcc/config/arm/ldmstm.md
+
Index: gcc-4_5-branch/gcc/config/arm/predicates.md
===================================================================
--- gcc-4_5-branch.orig/gcc/config/arm/predicates.md
+++ gcc-4_5-branch/gcc/config/arm/predicates.md
--- gcc-4_5-branch.orig/gcc/config/arm/predicates.md 2011-06-16 18:46:18.000000000 -0700
+++ gcc-4_5-branch/gcc/config/arm/predicates.md 2011-06-16 18:46:26.375282255 -0700
@@ -211,6 +211,11 @@
(and (match_code "ior,xor,and")
(match_test "mode == GET_MODE (op)")))
@@ -3314,9 +3314,9 @@ Index: gcc-4_5-branch/gcc/config/arm/predicates.md
return true;
Index: gcc-4_5-branch/gcc/config/i386/i386.md
===================================================================
--- gcc-4_5-branch.orig/gcc/config/i386/i386.md
+++ gcc-4_5-branch/gcc/config/i386/i386.md
@@ -4934,6 +4934,7 @@
--- gcc-4_5-branch.orig/gcc/config/i386/i386.md 2011-06-16 18:46:21.000000000 -0700
+++ gcc-4_5-branch/gcc/config/i386/i386.md 2011-06-16 18:46:26.385282255 -0700
@@ -4960,6 +4960,7 @@
(set (match_operand:SSEMODEI24 2 "register_operand" "")
(fix:SSEMODEI24 (match_dup 0)))]
"TARGET_SHORTEN_X87_SSE
@@ -3324,7 +3324,7 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
"")
@@ -20036,15 +20037,14 @@
@@ -20057,15 +20058,14 @@
;; leal (%edx,%eax,4), %eax
(define_peephole2
@@ -3345,7 +3345,7 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
(clobber (reg:CC FLAGS_REG))])]
"INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3
/* Validate MODE for lea. */
@@ -20053,31 +20053,27 @@
@@ -20074,31 +20074,27 @@
|| GET_MODE (operands[0]) == HImode))
|| GET_MODE (operands[0]) == SImode
|| (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
@@ -3389,87 +3389,11 @@ Index: gcc-4_5-branch/gcc/config/i386/i386.md
operands[0] = dest;
})
Index: gcc-4_5-branch/gcc/df-problems.c
===================================================================
--- gcc-4_5-branch.orig/gcc/df-problems.c
+++ gcc-4_5-branch/gcc/df-problems.c
@@ -3748,9 +3748,22 @@ df_simulate_find_defs (rtx insn, bitmap
for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
{
df_ref def = *def_rec;
- /* If the def is to only part of the reg, it does
- not kill the other defs that reach here. */
- if (!(DF_REF_FLAGS (def) & (DF_REF_PARTIAL | DF_REF_CONDITIONAL)))
+ bitmap_set_bit (defs, DF_REF_REGNO (def));
+ }
+}
+
+/* Find the set of real DEFs, which are not clobbers, for INSN. */
+
+void
+df_simulate_find_noclobber_defs (rtx insn, bitmap defs)
+{
+ df_ref *def_rec;
+ unsigned int uid = INSN_UID (insn);
+
+ for (def_rec = DF_INSN_UID_DEFS (uid); *def_rec; def_rec++)
+ {
+ df_ref def = *def_rec;
+ if (!(DF_REF_FLAGS (def) & (DF_REF_MUST_CLOBBER | DF_REF_MAY_CLOBBER)))
bitmap_set_bit (defs, DF_REF_REGNO (def));
}
}
@@ -3921,7 +3934,7 @@ df_simulate_initialize_forwards (basic_b
{
df_ref def = *def_rec;
if (DF_REF_FLAGS (def) & DF_REF_AT_TOP)
- bitmap_clear_bit (live, DF_REF_REGNO (def));
+ bitmap_set_bit (live, DF_REF_REGNO (def));
}
}
@@ -3942,7 +3955,7 @@ df_simulate_one_insn_forwards (basic_blo
while here the scan is performed forwards! So, first assume that the
def is live, and if this is not true REG_UNUSED notes will rectify the
situation. */
- df_simulate_find_defs (insn, live);
+ df_simulate_find_noclobber_defs (insn, live);
/* Clear all of the registers that go dead. */
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
Index: gcc-4_5-branch/gcc/df.h
===================================================================
--- gcc-4_5-branch.orig/gcc/df.h
+++ gcc-4_5-branch/gcc/df.h
@@ -978,6 +978,7 @@ extern void df_note_add_problem (void);
extern void df_md_add_problem (void);
extern void df_md_simulate_artificial_defs_at_top (basic_block, bitmap);
extern void df_md_simulate_one_insn (basic_block, rtx, bitmap);
+extern void df_simulate_find_noclobber_defs (rtx, bitmap);
extern void df_simulate_find_defs (rtx, bitmap);
extern void df_simulate_defs (rtx, bitmap);
extern void df_simulate_uses (rtx, bitmap);
Index: gcc-4_5-branch/gcc/fwprop.c
===================================================================
--- gcc-4_5-branch.orig/gcc/fwprop.c
+++ gcc-4_5-branch/gcc/fwprop.c
@@ -228,7 +228,10 @@ single_def_use_enter_block (struct dom_w
process_uses (df_get_artificial_uses (bb_index), DF_REF_AT_TOP);
process_defs (df_get_artificial_defs (bb_index), DF_REF_AT_TOP);
- df_simulate_initialize_forwards (bb, local_lr);
+
+ /* We don't call df_simulate_initialize_forwards, as it may overestimate
+ the live registers if there are unused artificial defs. We prefer
+ liveness to be underestimated. */
FOR_BB_INSNS (bb, insn)
if (INSN_P (insn))
Index: gcc-4_5-branch/gcc/genoutput.c
===================================================================
--- gcc-4_5-branch.orig/gcc/genoutput.c
+++ gcc-4_5-branch/gcc/genoutput.c
@@ -266,6 +266,8 @@ output_operand_data (void)
--- gcc-4_5-branch.orig/gcc/genoutput.c 2011-06-16 17:59:04.000000000 -0700
+++ gcc-4_5-branch/gcc/genoutput.c 2011-06-16 18:46:26.385282255 -0700
@@ -266,6 +266,8 @@
printf (" %d,\n", d->strict_low);
@@ -3480,9 +3404,9 @@ Index: gcc-4_5-branch/gcc/genoutput.c
printf(" },\n");
Index: gcc-4_5-branch/gcc/genrecog.c
===================================================================
--- gcc-4_5-branch.orig/gcc/genrecog.c
+++ gcc-4_5-branch/gcc/genrecog.c
@@ -1782,20 +1782,11 @@ change_state (const char *oldpos, const
--- gcc-4_5-branch.orig/gcc/genrecog.c 2011-06-16 17:59:04.000000000 -0700
+++ gcc-4_5-branch/gcc/genrecog.c 2011-06-16 18:46:26.395282255 -0700
@@ -1782,20 +1782,11 @@
int odepth = strlen (oldpos);
int ndepth = strlen (newpos);
int depth;
@@ -3503,77 +3427,11 @@ Index: gcc-4_5-branch/gcc/genrecog.c
/* Go down to desired level. */
while (depth < ndepth)
{
Index: gcc-4_5-branch/gcc/ifcvt.c
===================================================================
--- gcc-4_5-branch.orig/gcc/ifcvt.c
+++ gcc-4_5-branch/gcc/ifcvt.c
@@ -4011,6 +4011,7 @@ dead_or_predicable (basic_block test_bb,
basic_block new_dest = dest_edge->dest;
rtx head, end, jump, earliest = NULL_RTX, old_dest;
bitmap merge_set = NULL;
+ bitmap merge_set_noclobber = NULL;
/* Number of pending changes. */
int n_validated_changes = 0;
rtx new_dest_label;
@@ -4169,6 +4170,7 @@ dead_or_predicable (basic_block test_bb,
end of the block. */
merge_set = BITMAP_ALLOC (&reg_obstack);
+ merge_set_noclobber = BITMAP_ALLOC (&reg_obstack);
/* If we allocated new pseudos (e.g. in the conditional move
expander called from noce_emit_cmove), we must resize the
@@ -4187,6 +4189,7 @@ dead_or_predicable (basic_block test_bb,
df_ref def = *def_rec;
bitmap_set_bit (merge_set, DF_REF_REGNO (def));
}
+ df_simulate_find_noclobber_defs (insn, merge_set_noclobber);
}
}
@@ -4197,7 +4200,7 @@ dead_or_predicable (basic_block test_bb,
unsigned i;
bitmap_iterator bi;
- EXECUTE_IF_SET_IN_BITMAP (merge_set, 0, i, bi)
+ EXECUTE_IF_SET_IN_BITMAP (merge_set_noclobber, 0, i, bi)
{
if (i < FIRST_PSEUDO_REGISTER
&& ! fixed_regs[i]
@@ -4233,7 +4236,7 @@ dead_or_predicable (basic_block test_bb,
TEST_SET & DF_LIVE_IN (merge_bb)
are empty. */
- if (bitmap_intersect_p (merge_set, test_set)
+ if (bitmap_intersect_p (merge_set_noclobber, test_set)
|| bitmap_intersect_p (merge_set, test_live)
|| bitmap_intersect_p (test_set, df_get_live_in (merge_bb)))
intersect = true;
@@ -4320,6 +4323,7 @@ dead_or_predicable (basic_block test_bb,
remove_reg_equal_equiv_notes_for_regno (i);
BITMAP_FREE (merge_set);
+ BITMAP_FREE (merge_set_noclobber);
}
reorder_insns (head, end, PREV_INSN (earliest));
@@ -4340,7 +4344,10 @@ dead_or_predicable (basic_block test_bb,
cancel_changes (0);
fail:
if (merge_set)
- BITMAP_FREE (merge_set);
+ {
+ BITMAP_FREE (merge_set);
+ BITMAP_FREE (merge_set_noclobber);
+ }
return FALSE;
}
Index: gcc-4_5-branch/gcc/recog.c
===================================================================
--- gcc-4_5-branch.orig/gcc/recog.c
+++ gcc-4_5-branch/gcc/recog.c
@@ -2082,6 +2082,7 @@ extract_insn (rtx insn)
--- gcc-4_5-branch.orig/gcc/recog.c 2011-06-16 18:46:02.000000000 -0700
+++ gcc-4_5-branch/gcc/recog.c 2011-06-16 18:46:26.395282255 -0700
@@ -2082,6 +2082,7 @@
recog_data.operand_loc,
recog_data.constraints,
recog_data.operand_mode, NULL);
@@ -3581,7 +3439,7 @@ Index: gcc-4_5-branch/gcc/recog.c
if (noperands > 0)
{
const char *p = recog_data.constraints[0];
@@ -2111,6 +2112,7 @@ extract_insn (rtx insn)
@@ -2111,6 +2112,7 @@
for (i = 0; i < noperands; i++)
{
recog_data.constraints[i] = insn_data[icode].operand[i].constraint;
@@ -3589,7 +3447,7 @@ Index: gcc-4_5-branch/gcc/recog.c
recog_data.operand_mode[i] = insn_data[icode].operand[i].mode;
/* VOIDmode match_operands gets mode from their real operand. */
if (recog_data.operand_mode[i] == VOIDmode)
@@ -2909,6 +2911,10 @@ struct peep2_insn_data
@@ -2909,6 +2911,10 @@
static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1];
static int peep2_current;
@@ -3600,7 +3458,7 @@ Index: gcc-4_5-branch/gcc/recog.c
/* The number of instructions available to match a peep2. */
int peep2_current_count;
@@ -2917,6 +2923,16 @@ int peep2_current_count;
@@ -2917,6 +2923,16 @@
DF_LIVE_OUT for the block. */
#define PEEP2_EOB pc_rtx
@@ -3617,7 +3475,7 @@ Index: gcc-4_5-branch/gcc/recog.c
/* Return the Nth non-note insn after `current', or return NULL_RTX if it
does not exist. Used by the recognizer to find the next insn to match
in a multi-insn pattern. */
@@ -2926,9 +2942,7 @@ peep2_next_insn (int n)
@@ -2926,9 +2942,7 @@
{
gcc_assert (n <= peep2_current_count);
@@ -3628,7 +3486,7 @@ Index: gcc-4_5-branch/gcc/recog.c
return peep2_insn_data[n].insn;
}
@@ -2941,9 +2955,7 @@ peep2_regno_dead_p (int ofs, int regno)
@@ -2941,9 +2955,7 @@
{
gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
@@ -3639,7 +3497,7 @@ Index: gcc-4_5-branch/gcc/recog.c
gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
@@ -2959,9 +2971,7 @@ peep2_reg_dead_p (int ofs, rtx reg)
@@ -2959,9 +2971,7 @@
gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1);
@@ -3650,7 +3508,7 @@ Index: gcc-4_5-branch/gcc/recog.c
gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX);
@@ -2996,12 +3006,8 @@ peep2_find_free_register (int from, int
@@ -2996,12 +3006,8 @@
gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1);
gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1);
@@ -3665,7 +3523,7 @@ Index: gcc-4_5-branch/gcc/recog.c
gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before);
@@ -3010,8 +3016,7 @@ peep2_find_free_register (int from, int
@@ -3010,8 +3016,7 @@
{
HARD_REG_SET this_live;
@@ -3675,7 +3533,7 @@ Index: gcc-4_5-branch/gcc/recog.c
gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
IOR_HARD_REG_SET (live, this_live);
@@ -3104,19 +3109,234 @@ peep2_reinit_state (regset live)
@@ -3104,19 +3109,234 @@
COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live);
}
@@ -3913,7 +3771,7 @@ Index: gcc-4_5-branch/gcc/recog.c
df_analyze ();
/* Initialize the regsets we're going to use. */
@@ -3126,214 +3346,59 @@ peephole2_optimize (void)
@@ -3126,214 +3346,59 @@
FOR_EACH_BB_REVERSE (bb)
{
@@ -3950,7 +3808,9 @@ Index: gcc-4_5-branch/gcc/recog.c
- peep2_insn_data[peep2_current].insn = insn;
- df_simulate_one_insn_backwards (bb, insn, live);
- COPY_REG_SET (peep2_insn_data[peep2_current].live_before, live);
-
+ rtx attempt, head;
+ int match_len;
- if (RTX_FRAME_RELATED_P (insn))
- {
- /* If an insn has RTX_FRAME_RELATED_P set, peephole
@@ -3972,9 +3832,7 @@ Index: gcc-4_5-branch/gcc/recog.c
- {
- int j;
- rtx old_insn, new_insn, note;
+ rtx attempt, head;
+ int match_len;
-
- j = i + peep2_current;
- if (j >= MAX_INSNS_PER_PEEP2 + 1)
- j -= MAX_INSNS_PER_PEEP2 + 1;
@@ -4170,7 +4028,7 @@ Index: gcc-4_5-branch/gcc/recog.c
}
}
@@ -3341,7 +3406,7 @@ peephole2_optimize (void)
@@ -3341,7 +3406,7 @@
for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i)
BITMAP_FREE (peep2_insn_data[i].live_before);
BITMAP_FREE (live);
@@ -4181,9 +4039,9 @@ Index: gcc-4_5-branch/gcc/recog.c
#endif /* HAVE_peephole2 */
Index: gcc-4_5-branch/gcc/recog.h
===================================================================
--- gcc-4_5-branch.orig/gcc/recog.h
+++ gcc-4_5-branch/gcc/recog.h
@@ -194,6 +194,9 @@ struct recog_data
--- gcc-4_5-branch.orig/gcc/recog.h 2011-06-16 17:59:04.000000000 -0700
+++ gcc-4_5-branch/gcc/recog.h 2011-06-16 18:46:26.405282255 -0700
@@ -194,6 +194,9 @@
/* Gives the constraint string for operand N. */
const char *constraints[MAX_RECOG_OPERANDS];
@@ -4193,7 +4051,7 @@ Index: gcc-4_5-branch/gcc/recog.h
/* Gives the mode of operand N. */
enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
@@ -260,6 +263,8 @@ struct insn_operand_data
@@ -260,6 +263,8 @@
const char strict_low;
@@ -4204,9 +4062,9 @@ Index: gcc-4_5-branch/gcc/recog.h
Index: gcc-4_5-branch/gcc/reload.c
===================================================================
--- gcc-4_5-branch.orig/gcc/reload.c
+++ gcc-4_5-branch/gcc/reload.c
@@ -3631,7 +3631,7 @@ find_reloads (rtx insn, int replace, int
--- gcc-4_5-branch.orig/gcc/reload.c 2011-06-16 17:59:04.000000000 -0700
+++ gcc-4_5-branch/gcc/reload.c 2011-06-16 18:46:26.405282255 -0700
@@ -3631,7 +3631,7 @@
|| modified[j] != RELOAD_WRITE)
&& j != i
/* Ignore things like match_operator operands. */

6070
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26
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@@ -0,0 +1,26 @@
Remove the following
2011-04-20 Richard Sandiford <richard.sandiford@linaro.org>
gcc/testsuite/
From Richard Earnshaw <rearnsha@arm.com>
PR target/46329
* gcc.target/arm/pr46329.c: New test.
=== removed file 'gcc/testsuite/gcc.target/arm/pr46329.c'
--- old/gcc/testsuite/gcc.target/arm/pr46329.c 2011-05-03 12:49:58 +0000
+++ new/gcc/testsuite/gcc.target/arm/pr46329.c 1970-01-01 00:00:00 +0000
@@ -1,11 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-O2" } */
-/* { dg-add-options arm_neon } */
-
-int __attribute__ ((vector_size (32))) x;
-void
-foo (void)
-{
- x <<= x;
-}

21
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@@ -0,0 +1,21 @@
2011-05-06 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
From Sergey Grechanik <mouseentity@ispras.ru>, approved for mainline
* config/arm/arm.c (coproc_secondary_reload_class): Return NO_REGS
for constant vectors.
=== modified file 'gcc/config/arm/arm.c'
--- old/gcc/config/arm/arm.c 2011-04-20 10:10:50 +0000
+++ new/gcc/config/arm/arm.c 2011-05-04 15:13:02 +0000
@@ -9353,7 +9353,7 @@
/* The neon move patterns handle all legitimate vector and struct
addresses. */
if (TARGET_NEON
- && MEM_P (x)
+ && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
&& (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
|| VALID_NEON_STRUCT_MODE (mode)))

20
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@@ -0,0 +1,20 @@
2011-05-03 Tom de Vries <tom@codesourcery.com>
gcc/
* stmt.c (set_jump_prob): Make robust against *inv_scale == 0.
=== modified file 'gcc/stmt.c'
--- old/gcc/stmt.c 2011-02-07 13:23:30 +0000
+++ new/gcc/stmt.c 2011-05-06 19:17:34 +0000
@@ -2312,7 +2312,9 @@
set_jump_prob (rtx jump, int prob, int *inv_scale)
{
/* j[i] = p[i] * scale / REG_BR_PROB_BASE. */
- int jump_prob = prob * REG_BR_PROB_BASE / *inv_scale;
+ int jump_prob = (*inv_scale > 0
+ ? prob * REG_BR_PROB_BASE / *inv_scale
+ : REG_BR_PROB_BASE / 2);
/* f[i] = REG_BR_PROB_BASE - j[i]. */
int fallthrough_prob = REG_BR_PROB_BASE - jump_prob;

24
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@@ -0,0 +1,24 @@
2011-05-13 Michael Hope <michael.hope@linaro.org>
gcc/
Backport from mainline:
2011-05-05 Michael Hope <michael.hope@linaro.org>
PR pch/45979
* config/host-linux.c (TRY_EMPTY_VM_SPACE): Define for
__ARM_EABI__ hosts.
=== modified file 'gcc/config/host-linux.c'
--- old/gcc/config/host-linux.c 2009-02-20 15:20:38 +0000
+++ new/gcc/config/host-linux.c 2011-05-06 20:16:10 +0000
@@ -86,6 +86,8 @@
# define TRY_EMPTY_VM_SPACE 0x60000000
#elif defined(__mc68000__)
# define TRY_EMPTY_VM_SPACE 0x40000000
+#elif defined(__ARM_EABI__)
+# define TRY_EMPTY_VM_SPACE 0x60000000
#else
# define TRY_EMPTY_VM_SPACE 0
#endif

582
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@@ -0,0 +1,582 @@
2011-05-13 Revital Eres <revital.eres@linaro.org>
gcc/
* loop-doloop.c (doloop_condition_get): Support new form of
doloop pattern and use prev_nondebug_insn instead of PREV_INSN.
* config/arm/thumb2.md (*thumb2_addsi3_compare0): Remove "*".
(doloop_end): New.
* config/arm/arm.md (*addsi3_compare0): Remove "*".
* params.def (sms-min-sc): New param flag.
* doc/invoke.texi (sms-min-sc): Document it.
* ddg.c (create_ddg_dep_from_intra_loop_link): If a true dep edge
enters the branch create an anti edge in the opposite direction
to prevent the creation of reg-moves.
(get_node_of_insn_uid, check_closing_branch_deps): Delete
functions.
(create_ddg): Restore previous definition and implementation.
* ddg.h (create_ddg): Restore previous definition.
* modulo-sched.c: Adjust comment to reflect the fact we are
scheduling closing branch.
(PS_STAGE_COUNT): Rename to CALC_STAGE_COUNT and redefine.
(stage_count): New field in struct partial_schedule.
(calculate_stage_count): New function.
(normalize_sched_times): Rename to reset_sched_times and handle
incrementing the sched time of the nodes by a constant value
passed as parameter.
(duplicate_insns_of_cycles): Skip closing branch.
(sms_schedule_by_order): Schedule closing branch.
(ps_insn_find_column): Handle closing branch.
(sms_schedule): Call reset_sched_times and adjust the code to
support scheduling of the closing branch. Use sms-min-sc.
Support new form of doloop pattern.
(ps_insert_empty_row): Update calls to normalize_sched_times
and rotate_partial_schedule functions.
(mark_doloop_insns): Remove.
=== modified file 'gcc/ddg.c'
--- old/gcc/ddg.c 2011-03-24 07:45:38 +0000
+++ new/gcc/ddg.c 2011-05-11 08:00:14 +0000
@@ -60,8 +60,6 @@
static ddg_edge_ptr create_ddg_edge (ddg_node_ptr, ddg_node_ptr, dep_type,
dep_data_type, int, int);
static void add_edge_to_ddg (ddg_ptr g, ddg_edge_ptr);
-static ddg_node_ptr get_node_of_insn_uid (ddg_ptr, int);
-
/* Auxiliary variable for mem_read_insn_p/mem_write_insn_p. */
static bool mem_ref_p;
@@ -199,6 +197,11 @@
}
}
+ /* If a true dep edge enters the branch create an anti edge in the
+ opposite direction to prevent the creation of reg-moves. */
+ if ((DEP_TYPE (link) == REG_DEP_TRUE) && JUMP_P (dest_node->insn))
+ create_ddg_dep_no_link (g, dest_node, src_node, ANTI_DEP, REG_DEP, 1);
+
latency = dep_cost (link);
e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance);
add_edge_to_ddg (g, e);
@@ -452,65 +455,12 @@
sched_free_deps (head, tail, false);
}
-/* Given DOLOOP_INSNS which holds the instructions that
- belong to the do-loop part; mark closing_branch_deps field in ddg G
- as TRUE if the do-loop part's instructions are dependent on the other
- loop instructions. Otherwise mark it as FALSE. */
-static void
-check_closing_branch_deps (ddg_ptr g, sbitmap doloop_insns)
-{
- sbitmap_iterator sbi;
- unsigned int u = 0;
-
- EXECUTE_IF_SET_IN_SBITMAP (doloop_insns, 0, u, sbi)
- {
- ddg_edge_ptr e;
- ddg_node_ptr u_node = get_node_of_insn_uid (g, u);
-
- gcc_assert (u_node);
-
- for (e = u_node->in; e != 0; e = e->next_in)
- {
- ddg_node_ptr v_node = e->src;
-
- if (((unsigned int) INSN_UID (v_node->insn) == u)
- || DEBUG_INSN_P (v_node->insn))
- continue;
-
- /* Ignore dependencies between memory writes and the
- jump. */
- if (JUMP_P (u_node->insn)
- && e->type == OUTPUT_DEP
- && mem_write_insn_p (v_node->insn))
- continue;
- if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn)))
- {
- g->closing_branch_deps = 1;
- return;
- }
- }
- for (e = u_node->out; e != 0; e = e->next_out)
- {
- ddg_node_ptr v_node = e->dest;
-
- if (((unsigned int) INSN_UID (v_node->insn) == u)
- || DEBUG_INSN_P (v_node->insn))
- continue;
- if (!TEST_BIT (doloop_insns, INSN_UID (v_node->insn)))
- {
- g->closing_branch_deps = 1;
- return;
- }
- }
- }
- g->closing_branch_deps = 0;
-}
/* Given a basic block, create its DDG and return a pointer to a variable
of ddg type that represents it.
Initialize the ddg structure fields to the appropriate values. */
ddg_ptr
-create_ddg (basic_block bb, sbitmap doloop_insns)
+create_ddg (basic_block bb, int closing_branch_deps)
{
ddg_ptr g;
rtx insn, first_note;
@@ -520,6 +470,7 @@
g = (ddg_ptr) xcalloc (1, sizeof (struct ddg));
g->bb = bb;
+ g->closing_branch_deps = closing_branch_deps;
/* Count the number of insns in the BB. */
for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb));
@@ -592,11 +543,6 @@
/* Build the data dependency graph. */
build_intra_loop_deps (g);
build_inter_loop_deps (g);
-
- /* Check whether the do-loop part is decoupled from the other loop
- instructions. */
- check_closing_branch_deps (g, doloop_insns);
-
return g;
}
@@ -890,18 +836,6 @@
return NULL;
}
-/* Given the uid of an instruction UID return the node that represents it. */
-static ddg_node_ptr
-get_node_of_insn_uid (ddg_ptr g, int uid)
-{
- int i;
-
- for (i = 0; i < g->num_nodes; i++)
- if (uid == INSN_UID (g->nodes[i].insn))
- return &g->nodes[i];
- return NULL;
-}
-
/* Given a set OPS of nodes in the DDG, find the set of their successors
which are not in OPS, and set their bits in SUCC. Bits corresponding to
OPS are cleared from SUCC. Leaves the other bits in SUCC unchanged. */
=== modified file 'gcc/ddg.h'
--- old/gcc/ddg.h 2011-03-24 07:45:38 +0000
+++ new/gcc/ddg.h 2011-05-11 08:00:14 +0000
@@ -167,7 +167,7 @@
};
-ddg_ptr create_ddg (basic_block, sbitmap);
+ddg_ptr create_ddg (basic_block, int closing_branch_deps);
void free_ddg (ddg_ptr);
void print_ddg (FILE *, ddg_ptr);
=== modified file 'gcc/doc/invoke.texi'
--- old/gcc/doc/invoke.texi 2011-04-17 23:04:58 +0000
+++ new/gcc/doc/invoke.texi 2011-05-11 08:00:14 +0000
@@ -8430,6 +8430,10 @@
The maximum number of best instructions in the ready list that are considered
for renaming in the selective scheduler. The default value is 2.
+@item sms-min-sc
+The minimum value of stage count that swing modulo scheduler will
+generate. The default value is 2.
+
@item max-last-value-rtl
The maximum size measured as number of RTLs that can be recorded in an expression
in combiner for a pseudo register as last known value of that register. The default
=== modified file 'gcc/modulo-sched.c'
--- old/gcc/modulo-sched.c 2011-03-24 07:45:38 +0000
+++ new/gcc/modulo-sched.c 2011-05-11 08:00:14 +0000
@@ -84,14 +84,13 @@
II cycles (i.e. use register copies to prevent a def from overwriting
itself before reaching the use).
- SMS works with countable loops (1) whose control part can be easily
- decoupled from the rest of the loop and (2) whose loop count can
- be easily adjusted. This is because we peel a constant number of
- iterations into a prologue and epilogue for which we want to avoid
- emitting the control part, and a kernel which is to iterate that
- constant number of iterations less than the original loop. So the
- control part should be a set of insns clearly identified and having
- its own iv, not otherwise used in the loop (at-least for now), which
+ SMS works with countable loops whose loop count can be easily
+ adjusted. This is because we peel a constant number of iterations
+ into a prologue and epilogue for which we want to avoid emitting
+ the control part, and a kernel which is to iterate that constant
+ number of iterations less than the original loop. So the control
+ part should be a set of insns clearly identified and having its
+ own iv, not otherwise used in the loop (at-least for now), which
initializes a register before the loop to the number of iterations.
Currently SMS relies on the do-loop pattern to recognize such loops,
where (1) the control part comprises of all insns defining and/or
@@ -116,7 +115,7 @@
/* The number of different iterations the nodes in ps span, assuming
the stage boundaries are placed efficiently. */
-#define CALC_STAGE_COUNT(min_cycle,max_cycle,ii) ((max_cycle - min_cycle \
+#define CALC_STAGE_COUNT(max_cycle,min_cycle,ii) ((max_cycle - min_cycle \
+ 1 + ii - 1) / ii)
/* The stage count of ps. */
#define PS_STAGE_COUNT(ps) (((partial_schedule_ptr)(ps))->stage_count)
@@ -200,7 +199,6 @@
static void duplicate_insns_of_cycles (partial_schedule_ptr,
int, int, int, rtx);
static int calculate_stage_count (partial_schedule_ptr ps);
-
#define SCHED_ASAP(x) (((node_sched_params_ptr)(x)->aux.info)->asap)
#define SCHED_TIME(x) (((node_sched_params_ptr)(x)->aux.info)->time)
#define SCHED_FIRST_REG_MOVE(x) \
@@ -318,7 +316,7 @@
: prev_nondebug_insn (tail));
for (insn = head; insn != first_insn_not_to_check; insn = NEXT_INSN (insn))
- if (reg_mentioned_p (reg, insn) && NONDEBUG_INSN_P (insn))
+ if (reg_mentioned_p (reg, insn) && !DEBUG_INSN_P (insn))
{
if (dump_file)
{
@@ -337,24 +335,6 @@
#endif
}
-/* Mark in DOLOOP_INSNS the instructions that belong to the do-loop part.
- Use TAIL to recognize that part. */
-static void
-mark_doloop_insns (sbitmap doloop_insns, rtx tail)
-{
- rtx first_insn_not_to_check, insn;
-
- /* This is the first instruction which belongs the doloop part. */
- first_insn_not_to_check = (GET_CODE (PATTERN (tail)) == PARALLEL ? tail
- : prev_nondebug_insn (tail));
-
- sbitmap_zero (doloop_insns);
- for (insn = first_insn_not_to_check; insn != NEXT_INSN (tail);
- insn = NEXT_INSN (insn))
- if (NONDEBUG_INSN_P (insn))
- SET_BIT (doloop_insns, INSN_UID (insn));
-}
-
/* Check if COUNT_REG is set to a constant in the PRE_HEADER block, so
that the number of iterations is a compile-time constant. If so,
return the rtx that sets COUNT_REG to a constant, and set COUNT to
@@ -607,44 +587,42 @@
ddg_node_ptr u = crr_insn->node;
int normalized_time = SCHED_TIME (u) - amount;
int new_min_cycle = PS_MIN_CYCLE (ps) - amount;
- /* The first cycle in row zero after the rotation. */
- int new_first_cycle_in_row_zero =
- new_min_cycle + ii - SMODULO (new_min_cycle, ii);
+ int sc_until_cycle_zero, stage;
- if (dump_file)
- fprintf (dump_file, "crr_insn->node=%d, crr_insn->cycle=%d,\
- min_cycle=%d\n", crr_insn->node->cuid, SCHED_TIME
- (u), ps->min_cycle);
+ if (dump_file)
+ {
+ /* Print the scheduling times after the rotation. */
+ fprintf (dump_file, "crr_insn->node=%d (insn id %d), "
+ "crr_insn->cycle=%d, min_cycle=%d", crr_insn->node->cuid,
+ INSN_UID (crr_insn->node->insn), SCHED_TIME (u),
+ normalized_time);
+ if (JUMP_P (crr_insn->node->insn))
+ fprintf (dump_file, " (branch)");
+ fprintf (dump_file, "\n");
+ }
+
gcc_assert (SCHED_TIME (u) >= ps->min_cycle);
gcc_assert (SCHED_TIME (u) <= ps->max_cycle);
SCHED_TIME (u) = normalized_time;
- crr_insn->cycle = normalized_time;
SCHED_ROW (u) = SMODULO (normalized_time, ii);
-
- /* If min_cycle is in row zero after the rotation then
- the stage count can be calculated by dividing the cycle
- with ii. Otherwise, the calculation is done by dividing the
- SMSed kernel into two intervals:
-
- 1) min_cycle <= interval 0 < first_cycle_in_row_zero
- 2) first_cycle_in_row_zero <= interval 1 < max_cycle
-
- Cycles in interval 0 are in stage 0. The stage of cycles
- in interval 1 should be added by 1 to take interval 0 into
- account. */
- if (SMODULO (new_min_cycle, ii) == 0)
- SCHED_STAGE (u) = normalized_time / ii;
- else
- {
- if (crr_insn->cycle < new_first_cycle_in_row_zero)
- SCHED_STAGE (u) = 0;
- else
- SCHED_STAGE (u) =
- ((SCHED_TIME (u) - new_first_cycle_in_row_zero) / ii) + 1;
+
+ /* The calculation of stage count is done adding the number
+ of stages before cycle zero and after cycle zero. */
+ sc_until_cycle_zero = CALC_STAGE_COUNT (-1, new_min_cycle, ii);
+
+ if (SCHED_TIME (u) < 0)
+ {
+ stage = CALC_STAGE_COUNT (-1, SCHED_TIME (u), ii);
+ SCHED_STAGE (u) = sc_until_cycle_zero - stage;
+ }
+ else
+ {
+ stage = CALC_STAGE_COUNT (SCHED_TIME (u), 0, ii);
+ SCHED_STAGE (u) = sc_until_cycle_zero + stage - 1;
}
}
}
-
+
/* Set SCHED_COLUMN of each node according to its position in PS. */
static void
set_columns_for_ps (partial_schedule_ptr ps)
@@ -694,8 +672,8 @@
/* Do not duplicate any insn which refers to count_reg as it
belongs to the control part.
- If closing_branch_deps is true the closing branch is scheduled
- as well and thus should be ignored.
+ The closing branch is scheduled as well and thus should
+ be ignored.
TODO: This should be done by analyzing the control part of
the loop. */
if (reg_mentioned_p (count_reg, u_node->insn)
@@ -945,8 +923,7 @@
basic_block condition_bb = NULL;
edge latch_edge;
gcov_type trip_count = 0;
- sbitmap doloop_insns;
-
+
loop_optimizer_init (LOOPS_HAVE_PREHEADERS
| LOOPS_HAVE_RECORDED_EXITS);
if (number_of_loops () <= 1)
@@ -971,7 +948,6 @@
setup_sched_infos ();
haifa_sched_init ();
- doloop_insns = sbitmap_alloc (get_max_uid () + 1);
/* Allocate memory to hold the DDG array one entry for each loop.
We use loop->num as index into this array. */
g_arr = XCNEWVEC (ddg_ptr, number_of_loops ());
@@ -1104,16 +1080,18 @@
continue;
}
- mark_doloop_insns (doloop_insns, tail);
- if (! (g = create_ddg (bb, doloop_insns)))
+
+ /* Always schedule the closing branch with the rest of the
+ instructions. The branch is rotated to be in row ii-1 at the
+ end of the scheduling procedure to make sure it's the last
+ instruction in the iteration. */
+ if (! (g = create_ddg (bb, 1)))
{
if (dump_file)
fprintf (dump_file, "SMS create_ddg failed\n");
continue;
}
- if (dump_file)
- fprintf (dump_file, "SMS closing_branch_deps: %d\n",
- g->closing_branch_deps);
+
g_arr[loop->num] = g;
if (dump_file)
fprintf (dump_file, "...OK\n");
@@ -1215,16 +1193,17 @@
ps = sms_schedule_by_order (g, mii, maxii, node_order);
- if (ps)
- {
- stage_count = calculate_stage_count (ps);
- gcc_assert(stage_count >= 1);
- PS_STAGE_COUNT(ps) = stage_count;
- }
-
- /* Stage count of 1 means that there is no interleaving between
- iterations, let the scheduling passes do the job. */
- if (stage_count <= 1
+ if (ps)
+ {
+ stage_count = calculate_stage_count (ps);
+ gcc_assert(stage_count >= 1);
+ PS_STAGE_COUNT(ps) = stage_count;
+ }
+
+ /* The default value of PARAM_SMS_MIN_SC is 2 as stage count of
+ 1 means that there is no interleaving between iterations thus
+ we let the scheduling passes do the job in this case. */
+ if (stage_count < (unsigned) PARAM_VALUE (PARAM_SMS_MIN_SC)
|| (count_init && (loop_count <= stage_count))
|| (flag_branch_probabilities && (trip_count <= stage_count)))
{
@@ -1242,21 +1221,12 @@
else
{
struct undo_replace_buff_elem *reg_move_replaces;
- int amount;
-
- /* Set the stage boundaries. If the DDG is built with closing_branch_deps,
- the closing_branch was scheduled and should appear in the last (ii-1)
- row. Otherwise, we are free to schedule the branch, and we let nodes
- that were scheduled at the first PS_MIN_CYCLE cycle appear in the first
- row; this should reduce stage_count to minimum.
- TODO: Revisit the issue of scheduling the insns of the
- control part relative to the branch when the control part
- has more than one insn. */
- amount = (g->closing_branch_deps)? SCHED_TIME (g->closing_branch) + 1:
- PS_MIN_CYCLE (ps);
+ int amount = SCHED_TIME (g->closing_branch) + 1;
+
+ /* Set the stage boundaries. The closing_branch was scheduled
+ and should appear in the last (ii-1) row. */
reset_sched_times (ps, amount);
rotate_partial_schedule (ps, amount);
-
set_columns_for_ps (ps);
canon_loop (loop);
@@ -1267,13 +1237,8 @@
"SMS succeeded %d %d (with ii, sc)\n", ps->ii,
stage_count);
print_partial_schedule (ps, dump_file);
- if (!g->closing_branch_deps)
- fprintf (dump_file,
- "SMS Branch (%d) will later be scheduled at \
- cycle %d.\n",
- g->closing_branch->cuid, PS_MIN_CYCLE (ps) - 1);
- }
-
+ }
+
/* case the BCT count is not known , Do loop-versioning */
if (count_reg && ! count_init)
{
@@ -1318,7 +1283,6 @@
}
free (g_arr);
- sbitmap_free (doloop_insns);
/* Release scheduler data, needed until now because of DFA. */
haifa_sched_finish ();
@@ -1826,13 +1790,6 @@
RESET_BIT (tobe_scheduled, u);
continue;
}
- /* Closing branch handled later unless closing_branch_deps
- is true. */
- if (JUMP_P (insn) && !g->closing_branch_deps)
- {
- RESET_BIT (tobe_scheduled, u);
- continue;
- }
if (TEST_BIT (sched_nodes, u))
continue;
@@ -2675,9 +2632,9 @@
last_in_row = next_ps_i;
}
- /* If closing_branch_deps is true we are scheduling the closing
- branch as well. Make sure there is no dependent instruction after
- it as the branch should be the last instruction. */
+ /* The closing branch is scheduled as well. Make sure there is no
+ dependent instruction after it as the branch should be the last
+ instruction in the row. */
if (JUMP_P (ps_i->node->insn))
{
if (first_must_follow)
@@ -2918,51 +2875,21 @@
return ps_i;
}
-/* Calculate the stage count of the partial schedule PS. */
+/* Calculate the stage count of the partial schedule PS. The calculation
+ takes into account the rotation to bring the closing branch to row
+ ii-1. */
int
calculate_stage_count (partial_schedule_ptr ps)
{
- int stage_count;
-
- /* If closing_branch_deps is false then the stage
- boundaries are placed efficiently, meaning that min_cycle will be
- placed at row 0. Otherwise, the closing branch will be placed in
- row ii-1. For the later case we assume the final SMSed kernel can
- be divided into two intervals. This assumption is used for the
- stage count calculation:
-
- 1) min_cycle <= interval 0 < first_cycle_in_row_zero
- 2) first_cycle_in_row_zero <= interval 1 < max_cycle
- */
- stage_count =
- CALC_STAGE_COUNT (PS_MIN_CYCLE (ps), PS_MAX_CYCLE (ps), ps->ii);
- if (ps->g->closing_branch_deps)
- {
- int new_min_cycle;
- int new_min_cycle_row;
- int rotation_amount = SCHED_TIME (ps->g->closing_branch) + 1;
-
- /* This is the new value of min_cycle after the final rotation to
- bring closing branch into row ii-1. */
- new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
- /* This is the row which the the new min_cycle will be placed in. */
- new_min_cycle_row = SMODULO (new_min_cycle, ps->ii);
- /* If the row of min_cycle is zero then interval 0 is empty.
- Otherwise, we need to calculate interval 1 and add it by one
- to take interval 0 into account. */
- if (new_min_cycle_row != 0)
- {
- int new_max_cycle, first_cycle_in_row_zero;
-
- new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
- first_cycle_in_row_zero =
- new_min_cycle + ps->ii - new_min_cycle_row;
-
- stage_count =
- CALC_STAGE_COUNT (first_cycle_in_row_zero, new_max_cycle,
- ps->ii) + 1;
- }
- }
+ int rotation_amount = (SCHED_TIME (ps->g->closing_branch)) + 1;
+ int new_min_cycle = PS_MIN_CYCLE (ps) - rotation_amount;
+ int new_max_cycle = PS_MAX_CYCLE (ps) - rotation_amount;
+ int stage_count = CALC_STAGE_COUNT (-1, new_min_cycle, ps->ii);
+
+ /* The calculation of stage count is done adding the number of stages
+ before cycle zero and after cycle zero. */
+ stage_count += CALC_STAGE_COUNT (new_max_cycle, 0, ps->ii);
+
return stage_count;
}
=== modified file 'gcc/params.def'
--- old/gcc/params.def 2011-02-01 14:20:13 +0000
+++ new/gcc/params.def 2011-05-11 08:00:14 +0000
@@ -324,6 +324,11 @@
"sms-max-ii-factor",
"A factor for tuning the upper bound that swing modulo scheduler uses for scheduling a loop",
100, 0, 0)
+/* The minimum value of stage count that swing modulo scheduler will generate. */
+DEFPARAM(PARAM_SMS_MIN_SC,
+ "sms-min-sc",
+ "The minimum value of stage count that swing modulo scheduler will generate.",
+ 2, 1, 1)
DEFPARAM(PARAM_SMS_DFA_HISTORY,
"sms-dfa-history",
"The number of cycles the swing modulo scheduler considers when checking conflicts using DFA",

32
meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99514.patch Normal file
View File

@@ -0,0 +1,32 @@
2011-05-19 Revital Eres <revital.eres@linaro.org>
gcc/
* ddg.c (free_ddg_all_sccs): Free sccs field in struct
ddg_all_sccs.
* modulo-sched.c (sms_schedule): Avoid unfreed
memory when SMS fails.
=== modified file 'gcc/ddg.c'
--- old/gcc/ddg.c 2011-05-11 08:00:14 +0000
+++ new/gcc/ddg.c 2011-05-13 16:16:22 +0000
@@ -978,6 +978,7 @@
for (i = 0; i < all_sccs->num_sccs; i++)
free_scc (all_sccs->sccs[i]);
+ free (all_sccs->sccs);
free (all_sccs);
}
=== modified file 'gcc/modulo-sched.c'
--- old/gcc/modulo-sched.c 2011-05-11 08:00:14 +0000
+++ new/gcc/modulo-sched.c 2011-05-13 16:16:22 +0000
@@ -1216,7 +1216,6 @@
fprintf (dump_file, HOST_WIDEST_INT_PRINT_DEC, trip_count);
fprintf (dump_file, ")\n");
}
- continue;
}
else
{

45
meta-oe/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99516.patch Normal file
View File

@@ -0,0 +1,45 @@
2011-06-09 Chung-Lin Tang <cltang@codesourcery.com>
LP:748138
gcc/
* cfgrtl.c (try_redirect_by_replacing_jump): Treat EXIT_BLOCK_PTR case
separately before call to redirect_jump(). Add assertion.
(patch_jump_insn): Same.
=== modified file 'gcc/cfgrtl.c'
--- old/gcc/cfgrtl.c 2011-02-08 10:51:58 +0000
+++ new/gcc/cfgrtl.c 2011-05-12 08:56:07 +0000
@@ -835,11 +835,10 @@
if (dump_file)
fprintf (dump_file, "Redirecting jump %i from %i to %i.\n",
INSN_UID (insn), e->dest->index, target->index);
- if (!redirect_jump (insn, block_label (target), 0))
- {
- gcc_assert (target == EXIT_BLOCK_PTR);
- return NULL;
- }
+ if (target == EXIT_BLOCK_PTR)
+ return NULL;
+ if (! redirect_jump (insn, block_label (target), 0))
+ gcc_unreachable ();
}
/* Cannot do anything for target exit block. */
@@ -1019,11 +1018,10 @@
/* If the substitution doesn't succeed, die. This can happen
if the back end emitted unrecognizable instructions or if
target is exit block on some arches. */
- if (!redirect_jump (insn, block_label (new_bb), 0))
- {
- gcc_assert (new_bb == EXIT_BLOCK_PTR);
- return false;
- }
+ if (new_bb == EXIT_BLOCK_PTR)
+ return false;
+ if (! redirect_jump (insn, block_label (new_bb), 0))
+ gcc_unreachable ();
}
}
return true;