flashrom: Add remaining RISCV support

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Cc: Ross Burton <ross.burton@arm.com>

meta-oe/recipes-bsp/flashrom/flashrom/0001-flashrom-Mark-RISCV-as-non-memory-mapped-I-O-archite.patch

@@ -0,0 +1,44 @@
+From 2c777126765b4095bf481d5cfe4a21470374d940 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Tue, 30 Mar 2021 15:12:09 -0700
+Subject: [PATCH] flashrom: Mark RISCV as non memory-mapped I/O architecture
+
+Upstream-Status: Submitted [https://review.coreboot.org/c/flashrom/+/51960]
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+Change-Id: I55c4e8529d36f0850dd56441c3fb8602c5d889fd
+---
+ Makefile   | 2 +-
+ hwaccess.h | 4 ++++
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/Makefile b/Makefile
+index 6d37d55..203e04b 100644
+--- a/Makefile
++++ b/Makefile
+@@ -559,7 +559,7 @@ endif
+ # Disable all drivers needing raw access (memory, PCI, port I/O) on
+ # architectures with unknown raw access properties.
+ # Right now those architectures are alpha hppa m68k sh s390
+-ifneq ($(ARCH),$(filter $(ARCH),x86 mips ppc arm sparc arc))
++ifneq ($(ARCH),$(filter $(ARCH),x86 mips ppc arm sparc arc riscv))
+ ifeq ($(CONFIG_RAYER_SPI), yes)
+ UNSUPPORTED_FEATURES += CONFIG_RAYER_SPI=yes
+ else
+diff --git a/hwaccess.h b/hwaccess.h
+index 5602c15..e79988a 100644
+--- a/hwaccess.h
++++ b/hwaccess.h
+@@ -295,6 +295,10 @@ int libpayload_wrmsr(int addr, msr_t msr);
+ 
+ /* Non memory mapped I/O is not supported on ARC. */
+ 
++#elif IS_RISCV
++
++/* Non memory mapped I/O is not supported on RISCV. */
++
+ #else
+ 
+ #error Unknown architecture, please check if it supports PCI port IO.
+-- 
+2.31.1
+

meta-oe/recipes-bsp/flashrom/flashrom_1.2.bb

@@ -6,6 +6,7 @@ LIC_FILES_CHKSUM = "file://COPYING;md5=751419260aa954499f7abaabaa882bbe"
 SRC_URI = "https://download.flashrom.org/releases/flashrom-v${PV}.tar.bz2 \
            file://0001-typecast-enum-conversions-explicitly.patch \
            file://meson-fixes.patch \
+           file://0001-flashrom-Mark-RISCV-as-non-memory-mapped-I-O-archite.patch \
            "
 SRC_URI[md5sum] = "7f8e4b87087eb12ecee0fcc5445b4956"
 SRC_URI[sha256sum] = "e1f8d95881f5a4365dfe58776ce821dfcee0f138f75d0f44f8a3cd032d9ea42b"