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rust-cross: Add riscv32 data layout information

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This was generated with:
    clang --target=riscv32  -emit-llvm -S -x c /dev/null -o aaa |  cat aaa | grep "target datalayout"

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis
2019-08-23 15:57:29 -07:00
parent c5ff05d1e9
commit 150b1591d6
1 changed files with 8 additions and 0 deletions
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recipes-devtools/rust/rust.inc
+8
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@@ -223,6 +223,14 @@ TARGET_POINTER_WIDTH[powerpc] = "32"
TARGET_C_INT_WIDTH[powerpc] = "32"
MAX_ATOMIC_WIDTH[powerpc] = "32"
## riscv32-unknown-linux-{gnu, musl}
DATA_LAYOUT[riscv32] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
LLVM_TARGET[riscv32] = "${RUST_TARGET_SYS}"
TARGET_ENDIAN[riscv32] = "little"
TARGET_POINTER_WIDTH[riscv32] = "32"
TARGET_C_INT_WIDTH[riscv32] = "32"
MAX_ATOMIC_WIDTH[riscv32] = "32"
## riscv64-unknown-linux-{gnu, musl}
DATA_LAYOUT[riscv64] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
LLVM_TARGET[riscv64] = "${RUST_TARGET_SYS}"