Merge pull request #182 from Fulkerson/master

Add support for the mips32 architecture

Jenkinsfile

@@ -1,4 +1,4 @@
-def targets = [ 'qemux86', 'qemux86-64', 'qemuarm', 'qemuarm64' ]
+def targets = [ 'qemux86', 'qemux86-64', 'qemuarm', 'qemuarm64', 'qemumips' ]
 
 def machine_builds = [:]
 

recipes-devtools/rust/rust-llvm.inc

@@ -8,7 +8,7 @@ LIC_FILES_CHKSUM = "file://LICENSE.TXT;md5=4c0bc17c954e99fd547528d938832bfa"
 inherit cmake pythonnative
 
 EXTRA_OECMAKE = " \
-    -DLLVM_TARGETS_TO_BUILD='X86;ARM;AArch64;PowerPC' \
+    -DLLVM_TARGETS_TO_BUILD='X86;ARM;AArch64;PowerPC;Mips' \
     -DLLVM_ENABLE_ASSERTIONS=OFF \
     -DLLVM_BUILD_DOCS=OFF \
     -DLLVM_ENABLE_TERMINFO=OFF \

recipes-devtools/rust/rust.inc

@@ -33,7 +33,7 @@ def llvm_features_from_tune(d):
     f = []
     feat = d.getVar('TUNE_FEATURES')
     if not feat:
-        return ""
+        return []
     feat = frozenset(feat.split())
 
     if 'vfpv4' in feat:
@@ -52,6 +52,12 @@ def llvm_features_from_tune(d):
     if 'aarch64' in feat:
         f.append("+v8")
 
+    if 'mips32' in feat:
+        f.append("+mips32")
+
+    if 'mips32r2' in feat:
+        f.append("+mips32r2")
+
     v7=frozenset(['armv7a', 'armv7r', 'armv7m', 'armv7ve'])
     if not feat.isdisjoint(v7):
         f.append("+v7")
@@ -77,12 +83,7 @@ def llvm_features_from_tune(d):
     if 'cortexa17' in feat:
         f.append("+a17")
 
-    # Seems like it could be infered by the lack of vfp options, but we'll
-    # include it anyhow
-    if 'soft' in feat:
-        f.append("+soft-float")
-
-    return ','.join(f)
+    return f
 
 # TARGET_CC_ARCH changes from build/cross/target so it'll do the right thing
 # this should go away when https://github.com/rust-lang/rust/pull/31709 is
@@ -91,7 +92,7 @@ def llvm_features_from_cc_arch(d):
     f = []
     feat = d.getVar('TARGET_CC_ARCH')
     if not feat:
-        return ""
+        return []
     feat = frozenset(feat.split())
 
     if '-mmmx' in feat:
@@ -115,7 +116,19 @@ def llvm_features_from_cc_arch(d):
     if '-mavx2' in feat:
         f.append("+avx2")
 
-    return ','.join(f)
+    return f
+
+def llvm_features_from_target_fpu(d):
+    # TARGET_FPU can be hard or soft. +soft-float tell llvm to use soft float
+    # ABI. There is no option for hard.
+
+    fpu = d.getVar('TARGET_FPU', True)
+    return ["+soft-float"] if fpu == "soft" else []
+
+def llvm_features(d):
+    return ','.join(llvm_features_from_tune(d) +
+                    llvm_features_from_cc_arch(d) +
+                    llvm_features_from_target_fpu(d))
 
 ## arm-unknown-linux-gnueabihf
 DATA_LAYOUT[arm] = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
@@ -158,6 +171,22 @@ TARGET_POINTER_WIDTH[i586] = "32"
 TARGET_C_INT_WIDTH[i586] = "32"
 MAX_ATOMIC_WIDTH[i586] = "64"
 
+## mips-unknown-linux-gnu
+DATA_LAYOUT[mips] = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
+LLVM_TARGET[mips] = "${RUST_TARGET_SYS}"
+TARGET_ENDIAN[mips] = "big"
+TARGET_POINTER_WIDTH[mips] = "32"
+TARGET_C_INT_WIDTH[mips] = "32"
+MAX_ATOMIC_WIDTH[mips] = "32"
+
+## mipsel-unknown-linux-gnu
+DATA_LAYOUT[mipsel] = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
+LLVM_TARGET[mipsel] = "${RUST_TARGET_SYS}"
+TARGET_ENDIAN[mipsel] = "little"
+TARGET_POINTER_WIDTH[mipsel] = "32"
+TARGET_C_INT_WIDTH[mipsel] = "32"
+MAX_ATOMIC_WIDTH[mipsel] = "32"
+
 def arch_for(d, thing):
     return d.getVar('{}_ARCH'.format(thing))
 
@@ -172,6 +201,8 @@ def prefix_for(d, thing):
 def arch_to_rust_target_arch(arch):
     if arch == "i586" or arch == "i686":
         return "x86"
+    elif arch == "mipsel":
+        return "mips"
     else:
         return arch
 
@@ -187,17 +218,26 @@ def llvm_cpu(d):
     trans['i686'] = "i686"
     trans['i586'] = "i586"
 
+    if target in ["mips", "mipsel"]:
+        feat = frozenset(d.getVar('TUNE_FEATURES').split())
+        if "mips32r2" in feat:
+            trans['mipsel'] = "mips32r2"
+            trans['mips'] = "mips32r2"
+        elif "mips32" in feat:
+            trans['mipsel'] = "mips32"
+            trans['mips'] = "mips32"
+
     try:
         return trans[cpu]
     except:
         return trans.get(target, "generic")
 
 TARGET_LLVM_CPU="${@llvm_cpu(d)}"
-TARGET_LLVM_FEATURES = "${@llvm_features_from_tune(d)} ${@llvm_features_from_cc_arch(d)}"
+TARGET_LLVM_FEATURES = "${@llvm_features(d)}"
 
 # class-native implies TARGET=HOST, and TUNE_FEATURES only describes the real
 # (original) target.
-TARGET_LLVM_FEATURES_class-native = "${@llvm_features_from_cc_arch(d)}"
+TARGET_LLVM_FEATURES_class-native = "${@','.join(llvm_features_from_cc_arch(d))}"
 
 def rust_gen_target(d, thing, wd):
     import json