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rust: Correct the data layout for riscv32

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This now matches with llvm target backend in llvm 11

Signed-off-by: Khem Raj <raj.khem@gmail.com>
This commit is contained in:
Khem Raj
2021-01-09 12:53:13 -08:00
parent fa5cdb0de4
commit a59ddd90d2
1 changed files with 1 additions and 1 deletions
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recipes-devtools/rust/rust.inc
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@@ -236,7 +236,7 @@ TARGET_C_INT_WIDTH[powerpc] = "32"
MAX_ATOMIC_WIDTH[powerpc] = "32"
## riscv32-unknown-linux-{gnu, musl}
DATA_LAYOUT[riscv32] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
DATA_LAYOUT[riscv32] = "e-m:e-p:32:32-i64:64-n32-S128"
LLVM_TARGET[riscv32] = "${RUST_TARGET_SYS}"
TARGET_ENDIAN[riscv32] = "little"
TARGET_POINTER_WIDTH[riscv32] = "32"