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rust-cross: Add riscv64 data layout information

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clang --target=riscv64  -emit-llvm -S -x c /dev/null -o aaa |  cat aaa | grep "target datalayout"

Signed-off-by: Khem Raj <raj.khem@gmail.com>
This commit is contained in:
Khem Raj
2018-12-26 14:41:00 -08:00
parent 1b00814593
commit bf01840f5b
1 changed files with 8 additions and 0 deletions
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recipes-devtools/rust/rust.inc
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@@ -218,6 +218,14 @@ TARGET_POINTER_WIDTH[powerpc] = "32"
TARGET_C_INT_WIDTH[powerpc] = "32"
MAX_ATOMIC_WIDTH[powerpc] = "32"
## riscv64-unknown-linux-{gnu, musl}
DATA_LAYOUT[riscv64] = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
LLVM_TARGET[riscv64] = "${RUST_TARGET_SYS}"
TARGET_ENDIAN[riscv64] = "little"
TARGET_POINTER_WIDTH[riscv64] = "64"
TARGET_C_INT_WIDTH[riscv64] = "64"
MAX_ATOMIC_WIDTH[riscv64] = "64"
def arch_for(d, thing):
return d.getVar('{}_ARCH'.format(thing))