mirror of
https://git.yoctoproject.org/meta-ti
synced 2026-01-12 01:20:20 +00:00
x-load git: update to 1.5.0
Tested on beagle-xm/angstrom and pandaboard/angstrom Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
This commit is contained in:
Koen Kooi
@@ -1,265 +0,0 @@
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From 7c5a2dd1e20702d220bd75910f7cfb6141230e5b Mon Sep 17 00:00:00 2001
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From: Rajendra Nayak <rnayak@ti.com>
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Date: Tue, 21 Dec 2010 11:55:01 -0200
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Subject: [PATCH 1/5] OMAP4: clocks: Enable only required clks
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X-loader untill now, was enabling all clks at bootup
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to help all modules to be functional at the kernel, even
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with drivers which do not handle clks well.
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Now that we are moving towards all drivers being adapted
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to request/release clks as expected, most of this code is
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useless and hence removed.
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Signed-off-by: Rajendra Nayak <rnayak@ti.com>
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Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
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---
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board/omap4430panda/clock.c | 225 ++++++++++++++++++++++---------------------
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1 files changed, 117 insertions(+), 108 deletions(-)
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diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
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index a83f1c6..b323885 100644
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--- a/board/omap4430panda/clock.c
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+++ b/board/omap4430panda/clock.c
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@@ -552,71 +552,73 @@ static void enable_all_clocks(void)
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{
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volatile int regvalue = 0;
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- /* Enable Ducati clocks */
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- sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
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- sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
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-
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- wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
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-
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- /* Enable ivahd and sl2 clocks */
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- sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
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- sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
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- sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
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-
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- wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
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-
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- /* wait for ivahd to become accessible */
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- //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
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- /* wait for sl2 to become accessible */
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- //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
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-
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- /* Enable Tesla clocks */
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- sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
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- sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
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-
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- wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
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-
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- /* wait for tesla to become accessible */
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- //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
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-
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- /* TODO: Some hack needed by MM: Clean this */
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- #if 0 /* Doesn't work on some Zebu */
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- *(volatile int*)0x4a306910 = 0x00000003;
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- *(volatile int*)0x550809a0 = 0x00000001;
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- *(volatile int*)0x55080a20 = 0x00000007;
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- #endif
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-
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- /* ABE clocks */
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- sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
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- sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
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- sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
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- /* Disable sleep transitions */
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- sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
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+ if (omap_revision() == OMAP4430_ES1_0) {
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+ /* Enable Ducati clocks */
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+ sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
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+ sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
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+
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+ wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
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+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
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+
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+ /* Enable ivahd and sl2 clocks */
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+ sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
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+ sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
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+ sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
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+
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+ wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
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+
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+ /* wait for ivahd to become accessible */
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+ //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
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+ /* wait for sl2 to become accessible */
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+ //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
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+
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+ /* Enable Tesla clocks */
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+ sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
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+ sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
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+
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+ wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
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+
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+ /* wait for tesla to become accessible */
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+ //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
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+
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+ /* TODO: Some hack needed by MM: Clean this */
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+ #if 0 /* Doesn't work on some Zebu */
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+ *(volatile int*)0x4a306910 = 0x00000003;
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+ *(volatile int*)0x550809a0 = 0x00000001;
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+ *(volatile int*)0x55080a20 = 0x00000007;
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+ #endif
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+
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+ /* ABE clocks */
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+ sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
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+ sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
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+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
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+ sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
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+ //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
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+ /* Disable sleep transitions */
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+ sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
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+ }
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/* L4PER clocks */
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sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
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@@ -723,50 +725,57 @@ static void enable_all_clocks(void)
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sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
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wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
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- /* Enable Camera clocks */
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- sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
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- sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
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- sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
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- sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
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-
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- /* Enable DSS clocks */
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- /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
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- *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
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- sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
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- sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
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- sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
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- /* Check for DSS Clocks */
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- while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
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- /* Set HW_AUTO transition mode */
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- sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
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-
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- /* Enable SGX clocks */
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- sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
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- sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
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- /* Check for SGX FCLK and ICLK */
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- while ( (*(volatile int*)0x4A009200) != 0x302 );
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- //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
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- /* Enable hsi/unipro/usb clocks */
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- sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
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- sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
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- sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
|
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
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- sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
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- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
|
||||
- sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
|
||||
- //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
|
||||
- sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
|
||||
- //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
|
||||
- /* enable the 32K, 48M optional clocks and enable the module */
|
||||
+ if (omap_revision() == OMAP4430_ES1_0) {
|
||||
+ /* Enable Camera clocks */
|
||||
+ sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
|
||||
+ sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
|
||||
+ sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
|
||||
+ sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
|
||||
+
|
||||
+ /* Enable DSS clocks */
|
||||
+ /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
|
||||
+ *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
|
||||
+ sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
|
||||
+ sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
|
||||
+ sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
|
||||
+ /* Check for DSS Clocks */
|
||||
+ while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
|
||||
+ /* Set HW_AUTO transition mode */
|
||||
+ sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
|
||||
+
|
||||
+ /* Enable SGX clocks */
|
||||
+ sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
|
||||
+ sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
|
||||
+ /* Check for SGX FCLK and ICLK */
|
||||
+ while ( (*(volatile int*)0x4A009200) != 0x302 );
|
||||
+ //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
|
||||
+ /* Enable hsi/unipro/usb clocks */
|
||||
+ sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
|
||||
+ sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
|
||||
+ sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
|
||||
+ sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
|
||||
+ sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
|
||||
+ //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
|
||||
+ sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
|
||||
+ //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
|
||||
+ /* enable the 32K, 48M optional clocks and enable the module */
|
||||
+ sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
|
||||
+ //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
|
||||
+ }
|
||||
+
|
||||
+ /* Enable clocks for USB fast boot to work */
|
||||
sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
|
||||
- //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
|
||||
+ sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
|
||||
+
|
||||
return;
|
||||
}
|
||||
|
||||
--
|
||||
1.6.6.1
|
||||
|
||||
@@ -1,32 +0,0 @@
|
||||
From 17028354b438883e98668803bf433d8a0bae12a1 Mon Sep 17 00:00:00 2001
|
||||
From: Rajeev Kulkarni <rajeevk@ti.com>
|
||||
Date: Tue, 26 Oct 2010 07:34:43 -0500
|
||||
Subject: [PATCH 2/5] OMAP4: Select DPLL PER Clock as source for SGX FCLK
|
||||
|
||||
The correct frequncy for SGX is 307.2 Mhz.. If DPLL_PER
|
||||
is set 1536 Mhz, There is no need to change dividers, just
|
||||
parent clock need to change. And DPLL PER is set at 1536.
|
||||
|
||||
Signed-off-by: Rajeev Kulkarni <rajeevk@ti.com>
|
||||
Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
|
||||
---
|
||||
board/omap4430panda/clock.c | 3 +++
|
||||
1 files changed, 3 insertions(+), 0 deletions(-)
|
||||
|
||||
diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
|
||||
index b323885..4404cc5 100644
|
||||
--- a/board/omap4430panda/clock.c
|
||||
+++ b/board/omap4430panda/clock.c
|
||||
@@ -772,6 +772,9 @@ static void enable_all_clocks(void)
|
||||
//wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
|
||||
}
|
||||
|
||||
+ /* Select DPLL PER CLOCK as source for SGX FCLK */
|
||||
+ sr32(CM_SGX_SGX_CLKCTRL, 24, 1, 0x1);
|
||||
+
|
||||
/* Enable clocks for USB fast boot to work */
|
||||
sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
|
||||
sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
|
||||
--
|
||||
1.6.6.1
|
||||
|
||||
@@ -1,33 +0,0 @@
|
||||
From 3421142b95238893a90032c3056123544c353752 Mon Sep 17 00:00:00 2001
|
||||
From: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
|
||||
Date: Tue, 21 Dec 2010 12:03:50 -0200
|
||||
Subject: [PATCH 3/5] MUX: Configure SYS_NIRQ2 pin in safe mode
|
||||
|
||||
SYS_NIRQ2 pin if not in safe mode, with audio driver
|
||||
enabled gates CORE RET. Hence configured in safe mode.
|
||||
Audio driver is expected to re-init the pin in the
|
||||
kernel.
|
||||
|
||||
Patch from sdp, by Rajendra Nayak <rnayak@ti.com>
|
||||
|
||||
Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
|
||||
---
|
||||
board/omap4430panda/omap4430panda.c | 2 +-
|
||||
1 files changed, 1 insertions(+), 1 deletions(-)
|
||||
|
||||
diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
|
||||
index a91e2aa..f6f515b 100644
|
||||
--- a/board/omap4430panda/omap4430panda.c
|
||||
+++ b/board/omap4430panda/omap4430panda.c
|
||||
@@ -910,7 +910,7 @@ int dram_init(void)
|
||||
MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \
|
||||
MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \
|
||||
MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \
|
||||
- MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \
|
||||
+ MV(CP(SYS_NIRQ2) , (M7_SAFE)) /* sys_nirq2 */ \
|
||||
MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \
|
||||
MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \
|
||||
MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \
|
||||
--
|
||||
1.6.6.1
|
||||
|
||||
@@ -1,34 +0,0 @@
|
||||
From 14a48e4b24aee2387f8e4cd3b480236451fe1294 Mon Sep 17 00:00:00 2001
|
||||
From: Rajendra Nayak <rnayak@ti.com>
|
||||
Date: Mon, 4 Oct 2010 18:49:18 +0530
|
||||
Subject: [PATCH 4/5] OMAP4: clocks: Disable slimbus and pad_clks
|
||||
|
||||
The slimbus and pad_clks if left enabled in x-loader
|
||||
would gate abe power domain from transitioning to RET.
|
||||
|
||||
These should be enabled by the audio driver (if present)
|
||||
in the kernel.
|
||||
|
||||
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
|
||||
Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
|
||||
---
|
||||
board/omap4430panda/clock.c | 3 ---
|
||||
1 files changed, 0 insertions(+), 3 deletions(-)
|
||||
|
||||
diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
|
||||
index 4404cc5..e41f327 100644
|
||||
--- a/board/omap4430panda/clock.c
|
||||
+++ b/board/omap4430panda/clock.c
|
||||
@@ -333,9 +333,6 @@ static void configure_abe_dpll(u32 clk_index)
|
||||
/* Select sys_clk as ref clk for ABE dpll */
|
||||
sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
|
||||
|
||||
- /* Enable slimbus and pad clocks */
|
||||
- sr32(CM_CLKSEL_ABE, 0, 32, 0x500);
|
||||
-
|
||||
/* Unlock the ABE dpll */
|
||||
sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);
|
||||
wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);
|
||||
--
|
||||
1.6.6.1
|
||||
|
||||
@@ -1,50 +0,0 @@
|
||||
From 76ebc9fdbfff91f226bc559706e3e7ece43ec30d Mon Sep 17 00:00:00 2001
|
||||
From: Sebastien Jan <s-jan@ti.com>
|
||||
Date: Wed, 22 Dec 2010 13:53:18 +0100
|
||||
Subject: [PATCH 5/5] omap4: Make 1GHz as default MPU clock
|
||||
|
||||
Signed-off-by: Aneesh V <aneesh@ti.com>
|
||||
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
|
||||
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
|
||||
Signed-off-by: Sebastien Jan <s-jan@ti.com>
|
||||
Signed-off-by: Ricardo Salveti de Araujo <ricardo.salveti@canonical.com>
|
||||
---
|
||||
Makefile | 9 +++++++++
|
||||
include/configs/omap4430panda.h | 1 -
|
||||
2 files changed, 9 insertions(+), 1 deletions(-)
|
||||
|
||||
diff --git a/Makefile b/Makefile
|
||||
index fd85142..6258324 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -235,6 +235,15 @@ igep0020_config : unconfig
|
||||
#########################################################################
|
||||
omap4430panda_config : unconfig
|
||||
@./mkconfig $(@:_config=) arm omap4 omap4430panda 1
|
||||
+ @./mkconfig $(@:_config=) arm omap4 omap4430panda 1
|
||||
+ @[ -n "$(findstring _MPU_600MHz,$@)" ] || \
|
||||
+ { echo "#define CONFIG_MPU_1000 1" >> $(obj)include/config.h; \
|
||||
+ echo "MPU at 1GHz revision.."; \
|
||||
+ }
|
||||
+ @[ -z "$(findstring _MPU_600MHz,$@)" ] || \
|
||||
+ { echo "#define CONFIG_MPU_600 1" >> $(obj)include/config.h; \
|
||||
+ echo "MPU at 600MHz revision.."; \
|
||||
+ }
|
||||
|
||||
#########################################################################
|
||||
|
||||
diff --git a/include/configs/omap4430panda.h b/include/configs/omap4430panda.h
|
||||
index 74e2f42..eae02ef 100644
|
||||
--- a/include/configs/omap4430panda.h
|
||||
+++ b/include/configs/omap4430panda.h
|
||||
@@ -44,7 +44,6 @@
|
||||
* On Phoenix board vlotage needs to be bumped up
|
||||
* before scaling the MPU up
|
||||
*/
|
||||
-#define CONFIG_MPU_600 1
|
||||
#define CORE_190MHZ 1
|
||||
/* Enable the below macro if MMC boot support is required */
|
||||
#define CONFIG_MMC 1
|
||||
--
|
||||
1.6.6.1
|
||||
|
||||
@@ -1,52 +0,0 @@
|
||||
From b35937bf29c828e311f1d9bb1385bd32d34ec060 Mon Sep 17 00:00:00 2001
|
||||
From: Jason Kridner <jkridner@beagleboard.org>
|
||||
Date: Mon, 7 Mar 2011 19:31:15 -0600
|
||||
Subject: [PATCH] Forced newer revisions to default to xM.
|
||||
|
||||
---
|
||||
board/omap3530beagle/omap3530beagle.c | 15 ++++++++++++++-
|
||||
1 files changed, 14 insertions(+), 1 deletions(-)
|
||||
|
||||
diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c
|
||||
index 1b3d8c7..d55d32e 100644
|
||||
--- a/board/omap3530beagle/omap3530beagle.c
|
||||
+++ b/board/omap3530beagle/omap3530beagle.c
|
||||
@@ -212,6 +212,7 @@ u32 cpu_is_3410(void)
|
||||
* GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
|
||||
* GPIO173, GPIO172, GPIO171: 1 0 1 => C4
|
||||
* GPIO173, GPIO172, GPIO171: 0 0 0 => XM
|
||||
+ * default => XM
|
||||
******************************************/
|
||||
int beagle_revision(void)
|
||||
{
|
||||
@@ -227,6 +228,18 @@ int beagle_revision(void)
|
||||
rev = omap_get_gpio_datain(173) << 2 |
|
||||
omap_get_gpio_datain(172) << 1 |
|
||||
omap_get_gpio_datain(171);
|
||||
+
|
||||
+ /* Default newer board revisions to XM */
|
||||
+ switch(rev) {
|
||||
+ case REVISION_AXBX:
|
||||
+ case REVISION_CX:
|
||||
+ case REVISION_C4:
|
||||
+ break;
|
||||
+ case REVISION_XM:
|
||||
+ default:
|
||||
+ rev = REVISION_XM;
|
||||
+ }
|
||||
+
|
||||
omap_free_gpio(171);
|
||||
omap_free_gpio(172);
|
||||
omap_free_gpio(173);
|
||||
@@ -662,7 +675,7 @@ int misc_init_r(void)
|
||||
printf("Beagle Rev C4\n");
|
||||
break;
|
||||
case REVISION_XM:
|
||||
- printf("Beagle xM Rev A\n");
|
||||
+ printf("Beagle xM\n");
|
||||
break;
|
||||
default:
|
||||
printf("Beagle unknown 0x%02x\n", rev);
|
||||
--
|
||||
1.6.1
|
||||
|
||||
@@ -2,18 +2,12 @@ require x-load.inc
|
||||
|
||||
#FILESPATHPKG_prepend = "x-load-git:x-load-git/${MACHINE}"
|
||||
|
||||
PV = "1.44+${PR}+gitr${SRCREV}"
|
||||
PR ="r21"
|
||||
PV = "1.5.0+${PR}+gitr${SRCREV}"
|
||||
PR ="r22"
|
||||
PE = "1"
|
||||
|
||||
SRCREV_pn-${PN} = "24b8b7f41a83540433024854736518876257672c"
|
||||
SRCREV_pn-${PN} = "b6bbfe7848de547b64edf1c363c86cec4921b517"
|
||||
SRC_URI = "git://gitorious.org/x-loader/x-loader.git;branch=master;protocol=git \
|
||||
file://0001-OMAP4-clocks-Enable-only-required-clks.patch \
|
||||
file://0002-OMAP4-Select-DPLL-PER-Clock-as-source-for-SGX-FCLK.patch \
|
||||
file://0003-MUX-Configure-SYS_NIRQ2-pin-in-safe-mode.patch \
|
||||
file://0004-OMAP4-clocks-Disable-slimbus-and-pad_clks.patch \
|
||||
file://0005-omap4-Make-1GHz-as-default-MPU-clock.patch \
|
||||
file://xmc.patch \
|
||||
"
|
||||
|
||||
S = "${WORKDIR}/git"
|
||||
|
||||
Reference in New Issue
Block a user