Update SRCREV to pick the latest artifacts. The GL headers are excluded
in the artifacts instead of it in the recipe.
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Directly take the images from ti-linux-firmware instead of using pdk
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Directly take the images from ti-linux-firmware instead of using pdk
Aldo drop build for k2g as firmwares are not yet available.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Update the hsr/prp firmwares to latest that includes support for
timestamping rx packets. Unfortunately version number is not
incremented for this update.
Also rename the bb file to add PV in it.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Rename gcc-arm-none-eabi to gcc-arm-baremetal.
As meta-arm now provides baremetal gcc-arm-none-eabi version 9, and due to layer
priorities, let's rename gcc-arm-none-eabi to gcc-arm-baremetal to force picking
the right version for RTOS builds.
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
As part of replacing hard-coded /lib with ${base_libdir}, rpmsg_lib.lib was
also mistakenly moved from ${libdir} to ${base_libdir}, which is incorrect
and breaks other recipes, when they try to link against this library from
${libdir}.
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
j7200-evm supports virtualization with Jailhouse hypervisor.
To use Jailhouse, kernel needs to boot with an additional
DTB overlay. Include this in the list of DTBs for the machine.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Initialize the cell names and console for the j7200-evm machine
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
capable dual Cortex-R5F MCUs and a Centralized Device Management and
Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
Signed-off-by: Denys Dmytriyenko <denys@ti.com>
Denys Dmytriyenko
Dan Murphy
Gowtham Tammana
Lokesh Vutla
Nikhil Devshatwar
Alessio Igor Bogani