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gcc: Fixes for ARC
A couple of fixes to be a part of 11.2 whenever it happens 1. https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0061fabeb9393c362601486105202cfe837a5a68 Fixes "harfbuzz" build, see https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/382 for all the gory details. 2. https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4186b7e93be73f8d68dc0fcc00a4cc8cc83e99a8 Fixes ext4 run-time issue: ------------------------->8--------------------------- Path: /bin/busybox CPU: 0 PID: 1 Comm: init Not tainted 5.13.0-rc2-dirty #23 Invalid Read @ 0x41c9e600 by insn @ __bio_try_merge_page+0x4e/0xfc ECR: 0x00050100 EFA: 0x41c9e600 ERET: 0x80159656 STAT: 0x80080202 [IE K ] BTA: 0x80159648 SP: 0x80821b88 FP: 0x00000008 BLK: bio_add_page+0x22/0x5c LPS: 0x801a6a94 LPE: 0x801a6a98 LPC: 0x00000000 r00: 0x80823300 r01: 0xbfb85e38 r02: 0x00002000 r03: 0x00000000 r04: 0x80821b9b r05: 0x80821bfc r06: 0x00000000 r07: 0x00000700 r08: 0x00000000 r09: 0xffffffff r10: 0x00000000 r11: 0x00000000 r12: 0x8080b300 Stack Trace: __bio_try_merge_page+0x4e/0xfc bio_add_page+0x22/0x5c do_mpage_readpage+0x534/0x65c mpage_readahead+0x30/0xdc read_pages+0x34/0x194 page_cache_ra_unbounded+0x56/0x154 filemap_fault+0x25a/0x5d8 __do_fault+0x94/0xe8 handle_mm_fault+0x4de/0xbd4 do_page_fault+0x108/0x21c ret_from_exception+0x0/0x8 ------------------------->8--------------------------- 3. https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=5a9b6a004f89fdd95b0470e1324dc4dee8c41d24 Precautious fix for rare corner cases which we don't wnat to really end-up in. (From OE-Core rev: 75110a9cc5e6840c65ed24bcca7d4cf1748ab67d) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
Alexey Brodkin
committed by
Richard Purdie
Richard Purdie
parent
319da63fc9
commit
29c42cf24d
@@ -69,6 +69,9 @@ SRC_URI = "\
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file://0036-mingw32-Enable-operation_not_supported.patch \
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file://0037-libatomic-Do-not-enforce-march-on-aarch64.patch \
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file://0001-Revert-libstdc-Install-libstdc-gdb.py-more-robustly-.patch \
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file://0038-arc-Update-64bit-move-split-patterns.patch \
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file://0039-arc-Fix-u-maddhisi-patterns.patch \
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file://0040-arc-Update-doloop_end-patterns.patch \
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"
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SRC_URI[sha256sum] = "4c4a6fb8a8396059241c2e674b85b351c26a5d678274007f076957afa1cc9ddf"
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SRC_URI[backports.sha256sum] = "69274bebd6c069a13443d4af61070e854740a639ec4d66eedf3e80070363587b"
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@@ -0,0 +1,290 @@
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From 0061fabeb9393c362601486105202cfe837a5a68 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <claziss@synopsys.com>
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Date: Wed, 9 Jun 2021 12:12:57 +0300
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Subject: [PATCH] arc: Update 64bit move split patterns.
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ARCv2HS can use a limited number of instructions to implement 64bit
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moves. The VADD2 is used as a 64bit move, the LDD/STD are 64 bit loads
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and stores. All those instructions are not baseline, hence we need to
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provide alternatives when they are not available or cannot be generate
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due to instruction restriction.
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This patch is cleaning up those move patterns, and updates splits
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instruction lengths.
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This is a backport from mainline gcc.
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gcc/
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2021-06-09 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc-protos.h (arc_split_move_p): New prototype.
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* config/arc/arc.c (arc_split_move_p): New function.
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(arc_split_move): Clean up.
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* config/arc/arc.md (movdi_insn): Clean up, use arc_split_move_p.
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(movdf_insn): Likewise.
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* config/arc/simdext.md (mov<VWH>_insn): Likewise.
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Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=0061fabeb9393c362601486105202cfe837a5a68]
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Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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(cherry picked from commit c0ba7a8af5366c37241f20e8be41e362f7260389)
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Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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---
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gcc/config/arc/arc-protos.h | 1 +
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gcc/config/arc/arc.c | 44 ++++++++++++----------
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gcc/config/arc/arc.md | 91 +++++++++------------------------------------
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gcc/config/arc/simdext.md | 38 ++++---------------
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4 files changed, 52 insertions(+), 122 deletions(-)
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diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
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index 1f56a0d82e4..62d7e45d29d 100644
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--- a/gcc/config/arc/arc-protos.h
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+++ b/gcc/config/arc/arc-protos.h
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@@ -50,6 +50,7 @@ extern void arc_split_ior (rtx *);
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extern bool arc_check_mov_const (HOST_WIDE_INT );
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extern bool arc_split_mov_const (rtx *);
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extern bool arc_can_use_return_insn (void);
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+extern bool arc_split_move_p (rtx *);
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#endif /* RTX_CODE */
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extern bool arc_ccfsm_branch_deleted_p (void);
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diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
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index 3201c3fefd7..db541bc11f5 100644
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--- a/gcc/config/arc/arc.c
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+++ b/gcc/config/arc/arc.c
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@@ -10129,6 +10129,31 @@ arc_process_double_reg_moves (rtx *operands)
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return true;
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}
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+
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+/* Check if we need to split a 64bit move. We do not need to split it if we can
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+ use vadd2 or ldd/std instructions. */
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+
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+bool
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+arc_split_move_p (rtx *operands)
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+{
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+ machine_mode mode = GET_MODE (operands[0]);
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+
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+ if (TARGET_LL64
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+ && ((memory_operand (operands[0], mode)
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+ && (even_register_operand (operands[1], mode)
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+ || satisfies_constraint_Cm3 (operands[1])))
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+ || (memory_operand (operands[1], mode)
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+ && even_register_operand (operands[0], mode))))
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+ return false;
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+
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+ if (TARGET_PLUS_QMACW
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+ && even_register_operand (operands[0], mode)
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+ && even_register_operand (operands[1], mode))
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+ return false;
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+
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+ return true;
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+}
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+
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/* operands 0..1 are the operands of a 64 bit move instruction.
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split it into two moves with operands 2/3 and 4/5. */
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@@ -10146,25 +10171,6 @@ arc_split_move (rtx *operands)
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return;
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}
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- if (TARGET_LL64
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- && ((memory_operand (operands[0], mode)
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- && (even_register_operand (operands[1], mode)
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- || satisfies_constraint_Cm3 (operands[1])))
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- || (memory_operand (operands[1], mode)
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- && even_register_operand (operands[0], mode))))
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- {
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- emit_move_insn (operands[0], operands[1]);
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- return;
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- }
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-
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- if (TARGET_PLUS_QMACW
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- && even_register_operand (operands[0], mode)
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- && even_register_operand (operands[1], mode))
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- {
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- emit_move_insn (operands[0], operands[1]);
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- return;
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- }
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-
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if (TARGET_PLUS_QMACW
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&& GET_CODE (operands[1]) == CONST_VECTOR)
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{
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diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
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index 7a52551eef5..91a838a38e4 100644
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--- a/gcc/config/arc/arc.md
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+++ b/gcc/config/arc/arc.md
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@@ -1329,47 +1329,20 @@ core_3, archs4x, archs4xd, archs4xd_slow"
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"register_operand (operands[0], DImode)
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|| register_operand (operands[1], DImode)
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|| (satisfies_constraint_Cm3 (operands[1])
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- && memory_operand (operands[0], DImode))"
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- "*
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-{
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- switch (which_alternative)
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- {
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- default:
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- return \"#\";
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-
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- case 0:
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- if (TARGET_PLUS_QMACW
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- && even_register_operand (operands[0], DImode)
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- && even_register_operand (operands[1], DImode))
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- return \"vadd2%?\\t%0,%1,0\";
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- return \"#\";
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-
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- case 2:
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- if (TARGET_LL64
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- && memory_operand (operands[1], DImode)
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- && even_register_operand (operands[0], DImode))
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- return \"ldd%U1%V1 %0,%1%&\";
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- return \"#\";
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-
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- case 3:
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- if (TARGET_LL64
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- && memory_operand (operands[0], DImode)
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- && (even_register_operand (operands[1], DImode)
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- || satisfies_constraint_Cm3 (operands[1])))
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- return \"std%U0%V0 %1,%0\";
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- return \"#\";
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- }
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-}"
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- "&& reload_completed"
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+ && memory_operand (operands[0], DImode))"
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+ "@
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+ vadd2\\t%0,%1,0
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+ #
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+ ldd%U1%V1\\t%0,%1
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+ std%U0%V0\\t%1,%0"
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+ "&& reload_completed && arc_split_move_p (operands)"
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[(const_int 0)]
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{
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arc_split_move (operands);
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DONE;
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}
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[(set_attr "type" "move,move,load,store")
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- ;; ??? The ld/st values could be 4 if it's [reg,bignum].
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- (set_attr "length" "8,16,*,*")])
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-
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+ (set_attr "length" "8,16,16,16")])
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;; Floating point move insns.
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@@ -1408,50 +1381,22 @@ core_3, archs4x, archs4xd, archs4xd_slow"
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(define_insn_and_split "*movdf_insn"
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[(set (match_operand:DF 0 "move_dest_operand" "=D,r,r,r,r,m")
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(match_operand:DF 1 "move_double_src_operand" "r,D,r,E,m,r"))]
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- "register_operand (operands[0], DFmode)
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- || register_operand (operands[1], DFmode)"
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- "*
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-{
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- switch (which_alternative)
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- {
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- default:
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- return \"#\";
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-
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- case 2:
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- if (TARGET_PLUS_QMACW
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- && even_register_operand (operands[0], DFmode)
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- && even_register_operand (operands[1], DFmode))
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- return \"vadd2%?\\t%0,%1,0\";
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- return \"#\";
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-
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- case 4:
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- if (TARGET_LL64
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- && ((even_register_operand (operands[0], DFmode)
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- && memory_operand (operands[1], DFmode))
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- || (memory_operand (operands[0], DFmode)
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- && even_register_operand (operands[1], DFmode))))
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- return \"ldd%U1%V1 %0,%1%&\";
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- return \"#\";
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-
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- case 5:
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- if (TARGET_LL64
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- && ((even_register_operand (operands[0], DFmode)
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- && memory_operand (operands[1], DFmode))
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- || (memory_operand (operands[0], DFmode)
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- && even_register_operand (operands[1], DFmode))))
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- return \"std%U0%V0 %1,%0\";
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- return \"#\";
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- }
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-}"
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- "reload_completed"
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+ "(register_operand (operands[0], DFmode)
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+ || register_operand (operands[1], DFmode))"
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+ "@
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+ #
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+ #
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+ vadd2\\t%0,%1,0
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+ #
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+ ldd%U1%V1\\t%0,%1
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+ std%U0%V0\\t%1,%0"
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+ "&& reload_completed && arc_split_move_p (operands)"
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[(const_int 0)]
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{
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arc_split_move (operands);
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DONE;
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}
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[(set_attr "type" "move,move,move,move,load,store")
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- (set_attr "predicable" "no,no,no,yes,no,no")
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- ;; ??? The ld/st values could be 16 if it's [reg,bignum].
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(set_attr "length" "4,16,8,16,16,16")])
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(define_insn_and_split "*movdf_insn_nolrsr"
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diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
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index f0900757452..36f41a5c3d0 100644
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--- a/gcc/config/arc/simdext.md
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+++ b/gcc/config/arc/simdext.md
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@@ -1402,41 +1402,19 @@
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(match_operand:VWH 1 "general_operand" "i,r,m,r"))]
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"(register_operand (operands[0], <MODE>mode)
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|| register_operand (operands[1], <MODE>mode))"
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- "*
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-{
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- switch (which_alternative)
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- {
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- default:
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- return \"#\";
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-
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- case 1:
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- if (TARGET_PLUS_QMACW
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- && even_register_operand (operands[0], <MODE>mode)
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- && even_register_operand (operands[1], <MODE>mode))
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- return \"vadd2%?\\t%0,%1,0\";
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- return \"#\";
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-
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- case 2:
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- if (TARGET_LL64)
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- return \"ldd%U1%V1 %0,%1\";
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- return \"#\";
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-
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- case 3:
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- if (TARGET_LL64)
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- return \"std%U0%V0 %1,%0\";
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- return \"#\";
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- }
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-}"
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- "reload_completed"
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+ "@
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+ #
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+ vadd2\\t%0,%1,0
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+ ldd%U1%V1\\t%0,%1
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+ std%U0%V0\\t%1,%0"
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+ "&& reload_completed && arc_split_move_p (operands)"
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[(const_int 0)]
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{
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arc_split_move (operands);
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DONE;
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}
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- [(set_attr "type" "move,multi,load,store")
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- (set_attr "predicable" "no,no,no,no")
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- (set_attr "iscompact" "false,false,false,false")
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- ])
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+ [(set_attr "type" "move,move,load,store")
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+ (set_attr "length" "16,8,16,16")])
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(define_expand "movmisalign<mode>"
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[(set (match_operand:VWH 0 "general_operand" "")
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--
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2.16.2
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@@ -0,0 +1,127 @@
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From 4186b7e93be73f8d68dc0fcc00a4cc8cc83e99a8 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <claziss@synopsys.com>
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Date: Wed, 9 Jun 2021 12:12:57 +0300
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Subject: [PATCH] arc: Fix (u)maddhisi patterns
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Rework the (u)maddhisi4 patterns and use VMAC2H(U) instruction instead
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of the 64bit MAC(U) instruction.
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This fixes the next execute.exp failures:
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arith-rand-ll.c -O2 execution test
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arith-rand-ll.c -O3 execution test
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pr78726.c -O2 execution test
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pr78726.c -O3 execution test
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gcc/
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2021-06-09 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.md (maddhisi4): Use VMAC2H instruction.
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(machi): New pattern.
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(umaddhisi4): Use VMAC2HU instruction.
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(umachi): New pattern.
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Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=4186b7e93be73f8d68dc0fcc00a4cc8cc83e99a8]
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Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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(cherry picked from commit dd4778a59b4693777c732075021375e19eee6a76)
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Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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---
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gcc/config/arc/arc.md | 66 ++++++++++++++++++++++++++++++++-------------------
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1 file changed, 41 insertions(+), 25 deletions(-)
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diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
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index 91a838a38e4..2a7e087ff72 100644
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--- a/gcc/config/arc/arc.md
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+++ b/gcc/config/arc/arc.md
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@@ -6053,48 +6053,64 @@ core_3, archs4x, archs4xd, archs4xd_slow"
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;; MAC and DMPY instructions
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-; Use MAC instruction to emulate 16bit mac.
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+; Use VMAC2H(U) instruction to emulate scalar 16bit mac.
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(define_expand "maddhisi4"
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[(match_operand:SI 0 "register_operand" "")
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(match_operand:HI 1 "register_operand" "")
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(match_operand:HI 2 "extend_operand" "")
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(match_operand:SI 3 "register_operand" "")]
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- "TARGET_PLUS_DMPY"
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+ "TARGET_PLUS_MACD"
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"{
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- rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
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- rtx tmp1 = gen_reg_rtx (SImode);
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- rtx tmp2 = gen_reg_rtx (SImode);
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- rtx accl = gen_lowpart (SImode, acc_reg);
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-
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- emit_move_insn (accl, operands[3]);
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- emit_insn (gen_rtx_SET (tmp1, gen_rtx_SIGN_EXTEND (SImode, operands[1])));
|
||||
- emit_insn (gen_rtx_SET (tmp2, gen_rtx_SIGN_EXTEND (SImode, operands[2])));
|
||||
- emit_insn (gen_mac (tmp1, tmp2));
|
||||
- emit_move_insn (operands[0], accl);
|
||||
+ rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
|
||||
+
|
||||
+ emit_move_insn (acc_reg, operands[3]);
|
||||
+ emit_insn (gen_machi (operands[1], operands[2]));
|
||||
+ emit_move_insn (operands[0], acc_reg);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
-; The same for the unsigned variant, but using MACU instruction.
|
||||
+(define_insn "machi"
|
||||
+ [(set (reg:SI ARCV2_ACC)
|
||||
+ (plus:SI
|
||||
+ (mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r"))
|
||||
+ (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))
|
||||
+ (reg:SI ARCV2_ACC)))]
|
||||
+ "TARGET_PLUS_MACD"
|
||||
+ "vmac2h\\t0,%0,%1"
|
||||
+ [(set_attr "length" "4")
|
||||
+ (set_attr "type" "multi")
|
||||
+ (set_attr "predicable" "no")
|
||||
+ (set_attr "cond" "nocond")])
|
||||
+
|
||||
+; The same for the unsigned variant, but using VMAC2HU instruction.
|
||||
(define_expand "umaddhisi4"
|
||||
[(match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:HI 1 "register_operand" "")
|
||||
- (match_operand:HI 2 "extend_operand" "")
|
||||
+ (match_operand:HI 2 "register_operand" "")
|
||||
(match_operand:SI 3 "register_operand" "")]
|
||||
- "TARGET_PLUS_DMPY"
|
||||
+ "TARGET_PLUS_MACD"
|
||||
"{
|
||||
- rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
|
||||
- rtx tmp1 = gen_reg_rtx (SImode);
|
||||
- rtx tmp2 = gen_reg_rtx (SImode);
|
||||
- rtx accl = gen_lowpart (SImode, acc_reg);
|
||||
-
|
||||
- emit_move_insn (accl, operands[3]);
|
||||
- emit_insn (gen_rtx_SET (tmp1, gen_rtx_ZERO_EXTEND (SImode, operands[1])));
|
||||
- emit_insn (gen_rtx_SET (tmp2, gen_rtx_ZERO_EXTEND (SImode, operands[2])));
|
||||
- emit_insn (gen_macu (tmp1, tmp2));
|
||||
- emit_move_insn (operands[0], accl);
|
||||
+ rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
|
||||
+
|
||||
+ emit_move_insn (acc_reg, operands[3]);
|
||||
+ emit_insn (gen_umachi (operands[1], operands[2]));
|
||||
+ emit_move_insn (operands[0], acc_reg);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
+(define_insn "umachi"
|
||||
+ [(set (reg:SI ARCV2_ACC)
|
||||
+ (plus:SI
|
||||
+ (mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r"))
|
||||
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
|
||||
+ (reg:SI ARCV2_ACC)))]
|
||||
+ "TARGET_PLUS_MACD"
|
||||
+ "vmac2hu\\t0,%0,%1"
|
||||
+ [(set_attr "length" "4")
|
||||
+ (set_attr "type" "multi")
|
||||
+ (set_attr "predicable" "no")
|
||||
+ (set_attr "cond" "nocond")])
|
||||
+
|
||||
(define_expand "maddsidi4"
|
||||
[(match_operand:DI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "register_operand" "")
|
||||
--
|
||||
2.16.2
|
||||
|
||||
@@ -0,0 +1,105 @@
|
||||
From 5a9b6a004f89fdd95b0470e1324dc4dee8c41d24 Mon Sep 17 00:00:00 2001
|
||||
From: Claudiu Zissulescu <claziss@synopsys.com>
|
||||
Date: Wed, 9 Jun 2021 12:12:57 +0300
|
||||
Subject: [PATCH] arc: Update doloop_end patterns
|
||||
|
||||
ARC processor can use LP instruction to implement zero overlay loops.
|
||||
The current inplementation doesn't handle the unlikely situation when
|
||||
the loop iterator is located in memory. Refurbish the loop_end insn
|
||||
pattern into a define_insn_and_split pattern.
|
||||
|
||||
gcc/
|
||||
2021-07-09 Claudiu Zissulescu <claziss@synopsys.com>
|
||||
|
||||
* config/arc/arc.md (loop_end): Change it to
|
||||
define_insn_and_split.
|
||||
|
||||
Upstream-Status: Backport [https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=5a9b6a004f89fdd95b0470e1324dc4dee8c41d24]
|
||||
|
||||
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
|
||||
(cherry picked from commit 174e75a210753b68de0f2c398a13ace0f512e35b)
|
||||
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
|
||||
---
|
||||
gcc/config/arc/arc.md | 46 ++++++++++++++++++++--------------------------
|
||||
1 file changed, 20 insertions(+), 26 deletions(-)
|
||||
|
||||
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
|
||||
index 2a7e087ff72..d704044c13f 100644
|
||||
--- a/gcc/config/arc/arc.md
|
||||
+++ b/gcc/config/arc/arc.md
|
||||
@@ -4986,7 +4986,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
|
||||
(define_expand "doloop_end"
|
||||
[(parallel [(set (pc)
|
||||
(if_then_else
|
||||
- (ne (match_operand 0 "" "")
|
||||
+ (ne (match_operand 0 "nonimmediate_operand")
|
||||
(const_int 1))
|
||||
(label_ref (match_operand 1 "" ""))
|
||||
(pc)))
|
||||
@@ -5012,44 +5012,38 @@ core_3, archs4x, archs4xd, archs4xd_slow"
|
||||
|
||||
;; if by any chance the lp_count is not used, then use an 'r'
|
||||
;; register, instead of going to memory.
|
||||
-(define_insn "loop_end"
|
||||
- [(set (pc)
|
||||
- (if_then_else (ne (match_operand:SI 2 "nonimmediate_operand" "0,m")
|
||||
- (const_int 1))
|
||||
- (label_ref (match_operand 1 "" ""))
|
||||
- (pc)))
|
||||
- (set (match_operand:SI 0 "nonimmediate_operand" "=r,m")
|
||||
- (plus (match_dup 2) (const_int -1)))
|
||||
- (unspec [(const_int 0)] UNSPEC_ARC_LP)
|
||||
- (clobber (match_scratch:SI 3 "=X,&r"))]
|
||||
- ""
|
||||
- "; ZOL_END, begins @%l1"
|
||||
- [(set_attr "length" "0")
|
||||
- (set_attr "predicable" "no")
|
||||
- (set_attr "type" "loop_end")])
|
||||
-
|
||||
;; split pattern for the very slim chance when the loop register is
|
||||
;; memory.
|
||||
-(define_split
|
||||
+(define_insn_and_split "loop_end"
|
||||
[(set (pc)
|
||||
- (if_then_else (ne (match_operand:SI 0 "memory_operand")
|
||||
+ (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+r,!m")
|
||||
(const_int 1))
|
||||
- (label_ref (match_operand 1 ""))
|
||||
+ (label_ref (match_operand 1 "" ""))
|
||||
(pc)))
|
||||
(set (match_dup 0) (plus (match_dup 0) (const_int -1)))
|
||||
(unspec [(const_int 0)] UNSPEC_ARC_LP)
|
||||
- (clobber (match_scratch:SI 2))]
|
||||
- "memory_operand (operands[0], SImode)"
|
||||
+ (clobber (match_scratch:SI 2 "=X,&r"))]
|
||||
+ ""
|
||||
+ "@
|
||||
+ ; ZOL_END, begins @%l1
|
||||
+ #"
|
||||
+ "reload_completed && memory_operand (operands[0], Pmode)"
|
||||
[(set (match_dup 2) (match_dup 0))
|
||||
- (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
|
||||
+ (parallel
|
||||
+ [(set (reg:CC_ZN CC_REG)
|
||||
+ (compare:CC_ZN (plus:SI (match_dup 2) (const_int -1))
|
||||
+ (const_int 0)))
|
||||
+ (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))])
|
||||
(set (match_dup 0) (match_dup 2))
|
||||
- (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))
|
||||
(set (pc)
|
||||
- (if_then_else (ne (reg:CC CC_REG)
|
||||
+ (if_then_else (ne (reg:CC_ZN CC_REG)
|
||||
(const_int 0))
|
||||
(label_ref (match_dup 1))
|
||||
(pc)))]
|
||||
- "")
|
||||
+ ""
|
||||
+ [(set_attr "length" "0,24")
|
||||
+ (set_attr "predicable" "no")
|
||||
+ (set_attr "type" "loop_end")])
|
||||
|
||||
(define_insn "loop_fail"
|
||||
[(set (reg:SI LP_COUNT)
|
||||
--
|
||||
2.16.2
|
||||
|
||||
Reference in New Issue
Block a user