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riscv: Add tunes for rv64 without compressed instructions

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(From OE-Core rev: 4790eaf98e030ffeecfbde6644137c9d6d1873d7)

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
Khem Raj
2022-04-13 19:52:25 -07:00
committed by Richard Purdie
parent b66928407a
commit 5d55cebe61
2 changed files with 10 additions and 0 deletions
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meta/conf/machine/include/riscv/arch-riscv.inc
+2
View File
@@ -7,6 +7,8 @@ TUNE_PKGARCH = "${TUNE_PKGARCH:tune-${DEFAULTTUNE}}"
TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', ' -mabi=lp64', ' ', d)}"
TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', ' -mabi=ilp32', ' ', d)}"
TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nc', ' -march=rv64imafd', ' ', d)}"
# Fix: ld: unrecognized option '--hash-style=sysv'
LINKER_HASH_STYLE:libc-newlib = ""
# Fix: ld: unrecognized option '--hash-style=gnu'
meta/conf/machine/include/riscv/tune-riscv.inc
+8
View File
@@ -6,6 +6,8 @@ TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
TUNEVALID[riscv64nc] = "Enable 64-bit RISC-V optimizations without compressed instructions"
TUNEVALID[bigendian] = "Big endian mode"
AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf"
@@ -31,3 +33,9 @@ TUNE_FEATURES:tune-riscv32nf = "${TUNE_FEATURES:tune-riscv32} riscv32nf"
TUNE_ARCH:tune-riscv32nf = "riscv32"
TUNE_PKGARCH:tune-riscv32nf = "riscv32nf"
PACKAGE_EXTRA_ARCHS:tune-riscv32nf = "riscv32nf"
# no compressed
TUNE_FEATURES:tune-riscv64nc = "${TUNE_FEATURES:tune-riscv64} riscv64nc"
TUNE_ARCH:tune-riscv64nc = "riscv64"
TUNE_PKGARCH:tune-riscv64nc = "riscv64nc"
PACKAGE_EXTRA_ARCHS:tune-riscv64nc = "riscv64nc"