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modification de la recette u-boot pour ajouter la gestion du tpm en SPI

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This commit is contained in:
BENOIT Vincent
2023-03-07 10:06:10 +00:00
parent f1063d08dc
commit 21c4abae13
5 changed files with 124 additions and 58 deletions
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2
recipes-bsp/u-boot/files/0001-pengwyn-defconfig.patch
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@@ -1267,7 +1267,7 @@
+#
+# TPM support
+#
+CONFIG_TPM_V1=y
+#CONFIG_TPM_V1=y
+# CONFIG_TPM_ATMEL_TWI is not set
+# CONFIG_TPM_AUTH_SESSIONS is not set
+# CONFIG_TPM_ST33ZP24_SPI is not set

13
recipes-bsp/u-boot/files/0002-pengwyn-spi-mux.patch
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@@ -1,5 +1,3 @@
diff --git a/board/silica/pengwyn/mux.c b/board/silica/pengwyn/mux.c
index 7583e833ed..06a372d052 100644
--- a/board/silica/pengwyn/mux.c
+++ b/board/silica/pengwyn/mux.c
@@ -30,6 +30,26 @@ static struct module_pin_mux i2c0_pin_mux[] = {
@@ -19,20 +17,21 @@ index 7583e833ed..06a372d052 100644
+
+/* SPI1 pins */
+static struct module_pin_mux spi1_pin_mux[] = {
+ {OFFSET(ecap0_in_pwm0_out), (MODE(4) | RXACTIVE | PULLUDEN)}, /* SPI1_SCLK */
+ {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN)}, /* SPI1_D0 */
+ {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUDEN)}, /* SPI1_D1 */
+ {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN)}, /* SPI1_CS0 */
+ {OFFSET(ecap0_in_pwm0_out), (MODE(4) | RXACTIVE | PULLUDEN)}, /* SPI1_SCLK */
+ {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN)}, /* SPI1_D0 */
+ {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUDEN)}, /* SPI1_D1 */
+ {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN)}, /* SPI1_CS0 */
+ {-1},
+};
+
/* MMC0 pins */
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
@@ -90,6 +110,7 @@ void enable_uart0_pin_mux(void)
@@ -90,6 +110,8 @@ void enable_uart0_pin_mux(void)
void enable_board_pin_mux()
{
configure_module_pin_mux(i2c0_pin_mux);
+ configure_module_pin_mux(spi0_pin_mux);
+ configure_module_pin_mux(spi1_pin_mux);
configure_module_pin_mux(uart0_pin_mux);
configure_module_pin_mux(mii1_pin_mux);

10
recipes-bsp/u-boot/files/0005-activate-spi1-clk.patch Normal file
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@@ -0,0 +1,10 @@
--- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
@@ -222,6 +222,7 @@ void enable_basic_clocks(void)
&cmper->i2c1clkctrl,
&cmper->cpgmac0clkctrl,
&cmper->spi0clkctrl,
+ &cmper->spi1clkctrl,
&cmrtc->rtcclkctrl,
&cmper->usb0clkctrl,
&cmper->emiffwclkctrl,

153
recipes-bsp/u-boot/files/am335x-pengwyn.dts
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@@ -14,11 +14,6 @@
model = "TI AM335x Silica Pengwyn";
compatible = "ti,am335x-pengwyn", "ti,am33xx";
chosen {
stdout-path = &uart0;
tick-timer = &timer2;
};
cpus {
cpu@0 {
cpu0-supply = <&vdd1_reg>;
@@ -30,6 +25,10 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
chosen {
stdout-path = &uart0;
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
@@ -48,7 +47,6 @@
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin>;
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
@@ -71,6 +69,20 @@
>;
};
spi1_pins: pinmux_spi1_pins {
pinctrl-single,pins = <
0x164 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* (C18) ecap0_in_pwm0_out.spi1_sclk */
0x194 (PIN_OUTPUT | MUX_MODE3) /* (B13) mcasp0_fsx.spi1_d0 */
0x198 (PIN_INPUT | MUX_MODE3) /* (D12) mcasp0_axr0.spi1_d1 */
0x19c (PIN_OUTPUT | MUX_MODE3) /* (C12) mcasp0_ahclkr.spi1_cs0 */
/* AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLUP, MUX_MODE3) */ /* mcasp0_ahclkr, spi1_cs0 */
/* AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLUP, MUX_MODE3) */ /* mcasp0_fsx, spi1_d0_mosi */
/* AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLUP, MUX_MODE3) */ /* mcasp0_axr0, spi1_d1_miso */
/* AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) */ /* ecap0_in_pwm0_out, spi1_sclk */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
@@ -78,6 +90,12 @@
>;
};
//clkout1_pin: pinmux_clkout1_pin {
// pinctrl-single,pins = <
// 0x (PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr0.clkout1 */
// >;
//};
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
@@ -107,24 +125,40 @@
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_er.mii1_rx_er */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_tx_en.mii1_tx_en */
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_dv.mii1_rx_dv */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_tx_clk.mii1_tx_clk */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_clk.mii1_rx_clk */
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
@@ -145,6 +179,9 @@
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
/* AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) */
>;
};
@@ -153,12 +190,23 @@
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
/* AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) */
/* AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
0x190 (PIN_INPUT | MUX_MODE4) /* mcasp0_aclkx.mmc0_sdcd */
0x1a0 (PIN_INPUT | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) */
/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) */
@@ -169,6 +217,18 @@
/* AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) */ /* mcasp0_aclkr.mmc0_sdwp */
>;
};
usb_pins: usb_pins {
pinctrl-single,pins = <
0x21c (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.gpio0_18 */
0x234 (PIN_OUTPUT | MUX_MODE0) /* usb1_drvvbus.gpio3_13 */
/* USB0 */
/* AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT, MUX_MODE0) */ /* gpmc_a9.gpio0_18 */
/* USB1 */
/* AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT, MUX_MODE0) */ /* usb1_drvvbus.gpio3_13 */
>;
};
};
&uart0 {
@@ -190,18 +250,6 @@
};
};
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
ti,pindir-d0-out-d1-in;
slb9670@0 {
compatible = "tis,tpm2-spi";
reg = <1>;
spi-max-frequency = <12000000>; // 12 MHz
};
};
&usb {
status = "okay";
@@ -228,6 +276,19 @@
dr_mode = "host";
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
ti,pindir-d0-out-d1-in;
slb9670@0 {
compatible = "tis,tpm2-spi";
reg = <0>;
spi-max-frequency = <12000000>; // 12 MHz
};
};
&cppi41dma {
status = "okay";
};
@@ -281,43 +342,35 @@
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
reg = <0x000000000000 0x000000080000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
reg = <0x000000080000 0x000000100000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
reg = <0x000000180000 0x000000180000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
reg = <0x000000300000 0x000000200000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
label = "NAND.u-boot";
reg = <0x000000500000 0x000000380000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000C0000 0x00100000>;
label = "NAND.u-boot-env";
reg = <0x000000880000 0x000000400000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001C0000 0x00020000>;
label = "NAND.kernel";
reg = <0x000000C80000 0x000001000000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001E0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00A00000 0x0F600000>;
reg = <0x000001C80000 0x00003E180000>;
};
};
};

4
recipes-bsp/u-boot/u-boot-ti-staging_2020.07.bb
View File

@@ -14,9 +14,13 @@ SRC_URI = " \
file://0002-pengwyn-spi-mux.patch \
file://0003-pengwyn-add-dts-to-makefile.patch \
file://0004-redeclaration-compile-error.patch \
file://0005-activate-spi1-clk.patch \
file://am335x-pengwyn.dts \
file://uEnv.txt \
"
# file://0010-debug-spi-uclass.patch
# Tag: v2020.07
SRCREV = "2f5fbb5b39f7b67044dda5c35e4a4b31685a3109"