passage de u-boot en version 2023.01
This commit is contained in:
+18
-17
@@ -9,8 +9,8 @@ IMAGE_CLASSES += "sdcard_image-pengwyn"
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#IMAGE_FSTYPES ?= "tar.bz2 ext4 wic wic.bmap"
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IMAGE_FSTYPES = "tar.bz2 ext4"
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#MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-image kernel-devicetree"
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#MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-image kernel-modules"
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MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-image"
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MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-image kernel-modules"
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#MACHINE_ESSENTIAL_EXTRA_RDEPENDS += "kernel-image"
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# A list of machine-dependent packages not essential for booting the image.
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# Thus, the build does not fail if the packages do not exist.
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@@ -30,7 +30,8 @@ EXTRA_IMAGEDEPENDS += "virtual/bootloader virtual/dtb"
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##########################################################
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PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot"
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PREFERRED_VERSION_u-boot ?= "u-boot-ti-staging_2020.07%"
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#PREFERRED_VERSION_u-boot ?= "u-boot-ti-staging_2020.07%"
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PREFERRED_VERSION_u-boot ?= "u-boot-ti-staging_2023.01%"
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# The file type for the Secondary Program Loader (SPL)
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SPL_BINARY = "MLO"
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@@ -93,21 +94,21 @@ PREFERRED_PROVIDER_virtual/kernel ?= "linux-ti-staging"
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PREFERRED_VERSION_linux-ti-staging ?= "5.4%"
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#KERNEL_IMAGETYPE = "zImage"
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#KERNEL_IMAGETYPE = "uImage"
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KERNEL_CLASSES ?= " kernel-fitimage "
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KERNEL_IMAGETYPE = "fitImage"
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KERNEL_IMAGETYPE = "uImage"
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#KERNEL_CLASSES ?= " kernel-fitimage "
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#KERNEL_IMAGETYPE = "fitImage"
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# Not necessary => see devicetree recipe
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#KERNEL_DEVICETREE = "am335x-pengwyn.dtb"
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# Remove dtb from ti33x.inc
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KERNEL_DEVICETREE:remove = " \
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am335x-evm.dtb \
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am335x-evmsk.dtb \
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am335x-icev2.dtb \
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am335x-pocketbeagle.dtb am335x-bone.dtb am335x-boneblue.dtb \
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am335x-bonegreen.dtb am335x-bonegreen-wireless.dtb \
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am335x-boneblack.dtb am335x-boneblack-wireless.dtb \
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am335x-sancloud-bbe.dtb \
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"
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#KERNEL_DEVICETREE:remove = " \
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# am335x-evm.dtb \
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# am335x-evmsk.dtb \
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# am335x-icev2.dtb \
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# am335x-pocketbeagle.dtb am335x-bone.dtb am335x-boneblue.dtb \
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# am335x-bonegreen.dtb am335x-bonegreen-wireless.dtb \
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# am335x-boneblack.dtb am335x-boneblack-wireless.dtb \
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# am335x-sancloud-bbe.dtb \
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#"
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KERNEL_EXTRA_ARGS += "LOADADDR=${UBOOT_ENTRYPOINT}"
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##########################################################
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@@ -121,7 +122,7 @@ PREFERRED_VERSION_dtb ?= "1.0%"
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MACHINE_FEATURES = "usbgadget usbhost vfat"
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#IMAGE_BOOT_FILES = "MLO u-boot.${UBOOT_SUFFIX} uEnv.txt uImage devicetree/am335x-pengwyn.dtb"
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IMAGE_BOOT_FILES = "MLO u-boot.${UBOOT_SUFFIX} uEnv.txt fitImage devicetree/am335x-pengwyn.dtb"
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IMAGE_BOOT_FILES = "MLO u-boot.${UBOOT_SUFFIX} uEnv.txt uImage devicetree/am335x-pengwyn.dtb"
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#IMAGE_BOOT_FILES = "MLO u-boot.${UBOOT_SUFFIX} uEnv.txt fitImage devicetree/am335x-pengwyn.dtb"
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RM_WORK_EXCLUDE += "u-boot-ti-staging linux-ti-staging"
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@@ -47,6 +47,7 @@
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&am33xx_pinmux {
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins &clkout2_pin>;
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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@@ -61,11 +62,6 @@
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0x154 (PIN_OUTPUT | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
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0x158 (PIN_INPUT | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
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0x15c (PIN_OUTPUT | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
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/* AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) */ /* spi0_d0_mosi, external pullup */
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/* AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) */ /* spi0_d1_miso */
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/* AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) */ /* external pullup */
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>;
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};
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@@ -75,11 +71,6 @@
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0x194 (PIN_OUTPUT | MUX_MODE3) /* (B13) mcasp0_fsx.spi1_d0 */
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0x198 (PIN_INPUT | MUX_MODE3) /* (D12) mcasp0_axr0.spi1_d1 */
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0x19c (PIN_OUTPUT | MUX_MODE3) /* (C12) mcasp0_ahclkr.spi1_cs0 */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLUP, MUX_MODE3) */ /* mcasp0_ahclkr, spi1_cs0 */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLUP, MUX_MODE3) */ /* mcasp0_fsx, spi1_d0_mosi */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLUP, MUX_MODE3) */ /* mcasp0_axr0, spi1_d1_miso */
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/* AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) */ /* ecap0_in_pwm0_out, spi1_sclk */
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>;
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};
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@@ -90,12 +81,6 @@
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>;
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};
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//clkout1_pin: pinmux_clkout1_pin {
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// pinctrl-single,pins = <
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// 0x (PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr0.clkout1 */
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// >;
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//};
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clkout2_pin: pinmux_clkout2_pin {
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pinctrl-single,pins = <
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0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
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@@ -124,7 +109,6 @@
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_er.mii1_rx_er */
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0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_tx_en.mii1_tx_en */
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0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_dv.mii1_rx_dv */
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@@ -138,26 +122,11 @@
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0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
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0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
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0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) */
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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@@ -176,23 +145,15 @@
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* MDIO */
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0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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/* AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) */
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>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
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pinctrl-single,pins = <
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/* MDIO reset value */
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0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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/* AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) */
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/* AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) */
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>;
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};
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@@ -206,15 +167,6 @@
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0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
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0x190 (PIN_INPUT | MUX_MODE4) /* mcasp0_aclkx.mmc0_sdcd */
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0x1a0 (PIN_INPUT | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT, MUX_MODE4) */ /* mcasp0_aclkx.mmc0_sdcd */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) */ /* mcasp0_aclkr.mmc0_sdwp */
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>;
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};
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@@ -222,11 +174,6 @@
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pinctrl-single,pins = <
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0x21c (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.gpio0_18 */
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0x234 (PIN_OUTPUT | MUX_MODE0) /* usb1_drvvbus.gpio3_13 */
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/* USB0 */
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/* AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT, MUX_MODE0) */ /* gpmc_a9.gpio0_18 */
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/* USB1 */
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/* AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT, MUX_MODE0) */ /* usb1_drvvbus.gpio3_13 */
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>;
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};
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};
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@@ -0,0 +1,10 @@
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -413,6 +413,7 @@ dtb-$(CONFIG_AM33XX) += \
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am335x-sancloud-bbe-lite.dtb \
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am335x-sancloud-bbe-extended-wifi.dtb \
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am335x-shc.dtb \
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+ am335x-pengwyn.dtb \
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am335x-pdu001.dtb \
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am335x-chiliboard.dtb \
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am335x-sl50.dtb \
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@@ -0,0 +1,26 @@
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--- a/arch/arm/mach-omap2/am33xx/Kconfig
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+++ b/arch/arm/mach-omap2/am33xx/Kconfig
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@@ -105,6 +105,14 @@ config TARGET_AM335X_SL50
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select DM_SERIAL
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imply CMD_DM
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+config TARGET_PENGWYN
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+ bool "Support Pengwyn"
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+ select BOARD_LATE_INIT
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+ select DM
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+ select DM_GPIO
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+ select DM_SERIAL
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+ imply CMD_DM
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+
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config TARGET_BRXRE1
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bool "Support BRXRE1"
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select BOARD_LATE_INIT
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--- a/arch/arm/mach-omap2/Kconfig
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+++ b/arch/arm/mach-omap2/Kconfig
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@@ -210,5 +210,6 @@ source "board/ti/am43xx/Kconfig"
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source "board/ti/am335x/Kconfig"
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source "board/compulab/cm_t43/Kconfig"
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source "board/phytec/phycore_am335x_r2/Kconfig"
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+source "board/silica/pengwyn/Kconfig"
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endif
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@@ -0,0 +1,17 @@
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if TARGET_PENGWYN
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config SYS_BOARD
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default "pengwyn"
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config SYS_VENDOR
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default "silica"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "pengwyn"
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source "board/ti/common/Kconfig"
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endif
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@@ -0,0 +1,6 @@
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PENGWYN BOARD
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M: Lothar Felten <lothar.felten@gmail.com>
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S: Maintained
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F: board/silica/pengwyn/
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F: include/configs/pengwyn.h
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F: configs/pengwyn_defconfig
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@@ -0,0 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Makefile
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#
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# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
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obj-y := mux.o
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endif
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obj-y += board.o
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@@ -0,0 +1,25 @@
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/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
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*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
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*/
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#include "am33xx-u-boot.dtsi"
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&am33xx_pinmux {
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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&i2c0 {
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u-boot,dm-pre-reloc;
|
||||
};
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||||
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&spi1 {
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u-boot,dm-pre-reloc;
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||||
};
|
||||
@@ -0,0 +1,464 @@
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||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
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||||
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||||
#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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||||
/ {
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||||
model = "TI AM335x Silica Pengwyn";
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compatible = "ti,am335x-pengwyn", "ti,am33xx";
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||||
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||||
cpus {
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||||
cpu@0 {
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||||
cpu0-supply = <&vdd1_reg>;
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||||
};
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||||
};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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||||
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chosen {
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stdout-path = &uart0;
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||||
};
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||||
|
||||
vbat: fixedregulator@0 {
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||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
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regulator-min-microvolt = <5000000>;
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||||
regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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||||
};
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vmmcsd_fixed: fixedregulator0 {
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compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
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||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins &clkout2_pin>;
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
spi0_pins: pinmux_spi0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
|
||||
0x154 (PIN_OUTPUT | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
|
||||
0x158 (PIN_INPUT | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
|
||||
0x15c (PIN_OUTPUT | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
|
||||
>;
|
||||
};
|
||||
|
||||
spi1_pins: pinmux_spi1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x164 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* (C18) ecap0_in_pwm0_out.spi1_sclk */
|
||||
0x194 (PIN_OUTPUT | MUX_MODE3) /* (B13) mcasp0_fsx.spi1_d0 */
|
||||
0x198 (PIN_INPUT | MUX_MODE3) /* (D12) mcasp0_axr0.spi1_d1 */
|
||||
0x19c (PIN_OUTPUT | MUX_MODE3) /* (C12) mcasp0_ahclkr.spi1_cs0 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins_s0: nandflash_pins_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
|
||||
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_er.mii1_rx_er */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_tx_en.mii1_tx_en */
|
||||
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_dv.mii1_rx_dv */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
|
||||
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_tx_clk.mii1_tx_clk */
|
||||
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_clk.mii1_rx_clk */
|
||||
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
|
||||
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
|
||||
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
|
||||
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
|
||||
0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
|
||||
0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
|
||||
0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
|
||||
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
|
||||
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
|
||||
0x190 (PIN_INPUT | MUX_MODE4) /* mcasp0_aclkx.mmc0_sdcd */
|
||||
0x1a0 (PIN_INPUT | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
|
||||
>;
|
||||
};
|
||||
|
||||
usb_pins: usb_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x21c (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.gpio0_18 */
|
||||
0x234 (PIN_OUTPUT | MUX_MODE0) /* usb1_drvvbus.gpio3_13 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_ctrl_mod {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
ti,pindir-d0-out-d1-in;
|
||||
|
||||
slb9670@0 {
|
||||
compatible = "tis,tpm2-spi";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <12000000>; // 12 MHz
|
||||
};
|
||||
};
|
||||
|
||||
&cppi41dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nandflash_pins_s0>;
|
||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
nand@0,0 {
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
* which can be independently programmable. For
|
||||
* NAND flash this is equal to size of erase-block */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "NAND.SPL";
|
||||
reg = <0x000000000000 0x000000080000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "NAND.SPL.backup1";
|
||||
reg = <0x000000080000 0x000000100000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "NAND.SPL.backup2";
|
||||
reg = <0x000000180000 0x000000180000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "NAND.SPL.backup3";
|
||||
reg = <0x000000300000 0x000000200000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "NAND.u-boot";
|
||||
reg = <0x000000500000 0x000000380000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "NAND.u-boot-env";
|
||||
reg = <0x000000880000 0x000000400000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "NAND.kernel";
|
||||
reg = <0x000000C80000 0x000001000000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "NAND.file-system";
|
||||
reg = <0x000001C80000 0x00003E180000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1312500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
status = "okay";
|
||||
slaves = <1>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy-handle = <ðphy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&tscadc {
|
||||
status = "okay";
|
||||
tsc {
|
||||
ti,wires = <4>;
|
||||
ti,x-plate-resistance = <200>;
|
||||
ti,coordinate-readouts = <5>;
|
||||
ti,wire-config = <0x00 0x11 0x22 0x33>;
|
||||
ti,charge-delay = <0x400>;
|
||||
};
|
||||
|
||||
adc {
|
||||
ti,adc-channels = <4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; // specify GPIOs for card detection
|
||||
wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; /* GPIO1_28 */
|
||||
};
|
||||
|
||||
&edma {
|
||||
ti,edma-xbar-event-map = /bits/ 16 <1 12
|
||||
2 13>;
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&aes {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -0,0 +1,230 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* board.c
|
||||
*
|
||||
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <hang.h>
|
||||
#include <image.h>
|
||||
#include <malloc.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/omap.h>
|
||||
#include <asm/arch/clk_synthesizer.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/mmc_host_def.h>
|
||||
#include <asm/arch/mem.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/emif.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/omap_common.h>
|
||||
#include <asm/omap_sec_common.h>
|
||||
#include <asm/omap_mmc.h>
|
||||
#include <miiphy.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/delay.h>
|
||||
#include <power/tps65217.h>
|
||||
#include <power/tps65910.h>
|
||||
#include <env_internal.h>
|
||||
#include <watchdog.h>
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <init.h>
|
||||
#include <net.h>
|
||||
#include <serial.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/ddr_defs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <i2c.h>
|
||||
#include <phy.h>
|
||||
#include <cpsw.h>
|
||||
#include "board.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
|
||||
/* DDR3 RAM timings */
|
||||
static const struct ddr_data ddr3_data = {
|
||||
.datardsratio0 = MT41K128MJT187E_RD_DQS,
|
||||
.datawdsratio0 = MT41K128MJT187E_WR_DQS,
|
||||
.datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
|
||||
.datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
|
||||
};
|
||||
|
||||
static const struct cmd_control ddr3_cmd_ctrl_data = {
|
||||
.cmd0csratio = MT41K128MJT187E_RATIO,
|
||||
.cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
|
||||
.cmd1csratio = MT41K128MJT187E_RATIO,
|
||||
.cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
|
||||
.cmd2csratio = MT41K128MJT187E_RATIO,
|
||||
.cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
|
||||
};
|
||||
|
||||
static struct emif_regs ddr3_emif_reg_data = {
|
||||
.sdram_config = MT41K128MJT187E_EMIF_SDCFG,
|
||||
.ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
|
||||
.sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
|
||||
.sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
|
||||
.sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
|
||||
.zq_config = MT41K128MJT187E_ZQ_CFG,
|
||||
.emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
|
||||
PHY_EN_DYN_PWRDN,
|
||||
};
|
||||
|
||||
const struct ctrl_ioregs ddr3_ioregs = {
|
||||
.cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
.cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
.cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
.dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
.dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
int spl_start_uboot(void)
|
||||
{
|
||||
/* break into full u-boot on 'c' */
|
||||
return serial_tstc() && serial_getc() == 'c';
|
||||
}
|
||||
#endif
|
||||
|
||||
#define OSC (V_OSCK/1000000)
|
||||
const struct dpll_params dpll_ddr_266 = {
|
||||
266, OSC-1, 1, -1, -1, -1, -1};
|
||||
const struct dpll_params dpll_ddr_303 = {
|
||||
303, OSC-1, 1, -1, -1, -1, -1};
|
||||
const struct dpll_params dpll_ddr_400 = {
|
||||
400, OSC-1, 1, -1, -1, -1, -1};
|
||||
|
||||
void am33xx_spl_board_init(void)
|
||||
{
|
||||
/*
|
||||
* The pengwyn board uses the TPS650250 PMIC without I2C
|
||||
* interface and will output the following fixed voltages:
|
||||
* DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
|
||||
* VLDO1=1V8 (IO) VLDO2=1V8(IO)
|
||||
* Vcore=1V1 is fixed, generated by TPS62231
|
||||
*/
|
||||
|
||||
/* Get the frequency */
|
||||
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
|
||||
|
||||
/* Set CORE Frequencies to OPP100 */
|
||||
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
|
||||
|
||||
/* 720MHz cpu, this might change on newer board revisions */
|
||||
dpll_mpu_opp100.m = MPUPLL_M_720;
|
||||
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
|
||||
}
|
||||
|
||||
const struct dpll_params *get_dpll_ddr_params(void)
|
||||
{
|
||||
/* future configs can return other clock settings */
|
||||
return &dpll_ddr_303;
|
||||
}
|
||||
|
||||
void set_uart_mux_conf(void)
|
||||
{
|
||||
enable_uart0_pin_mux();
|
||||
}
|
||||
|
||||
void set_mux_conf_regs(void)
|
||||
{
|
||||
enable_board_pin_mux();
|
||||
}
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
config_ddr(303, &ddr3_ioregs, &ddr3_data,
|
||||
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
|
||||
}
|
||||
#endif /* if CONFIG_SPL_BUILD */
|
||||
|
||||
/*
|
||||
* Basic board specific setup. Pinmux has been handled already.
|
||||
*/
|
||||
int board_init(void)
|
||||
{
|
||||
//i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
gpmc_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRIVER_TI_CPSW
|
||||
static void cpsw_control(int enabled)
|
||||
{
|
||||
/* VTP can be added here */
|
||||
return;
|
||||
}
|
||||
|
||||
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||
{
|
||||
.slave_reg_ofs = 0x208,
|
||||
.sliver_reg_ofs = 0xd80,
|
||||
.phy_addr = 1,
|
||||
.phy_if = PHY_INTERFACE_MODE_MII,
|
||||
},
|
||||
};
|
||||
|
||||
static struct cpsw_platform_data cpsw_data = {
|
||||
.mdio_base = CPSW_MDIO_BASE,
|
||||
.cpsw_base = CPSW_BASE,
|
||||
.mdio_div = 0xff,
|
||||
.channels = 8,
|
||||
.cpdma_reg_ofs = 0x800,
|
||||
.slaves = 1,
|
||||
.slave_data = cpsw_slaves,
|
||||
.ale_reg_ofs = 0xd00,
|
||||
.ale_entries = 1024,
|
||||
.host_port_reg_ofs = 0x108,
|
||||
.hw_stats_reg_ofs = 0x900,
|
||||
.bd_ram_ofs = 0x2000,
|
||||
.mac_control = (1 << 5),
|
||||
.control = cpsw_control,
|
||||
.host_port_num = 0,
|
||||
.version = CPSW_CTRL_VERSION_2,
|
||||
};
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
int rv, n = 0;
|
||||
uint8_t mac_addr[6];
|
||||
uint32_t mac_hi, mac_lo;
|
||||
|
||||
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
|
||||
printf("<ethaddr> not set. Reading from E-fuse\n");
|
||||
/* try reading mac address from efuse */
|
||||
mac_lo = readl(&cdev->macid0l);
|
||||
mac_hi = readl(&cdev->macid0h);
|
||||
mac_addr[0] = mac_hi & 0xFF;
|
||||
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||
mac_addr[4] = mac_lo & 0xFF;
|
||||
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||
|
||||
if (is_valid_ethaddr(mac_addr))
|
||||
eth_env_set_enetaddr("ethaddr", mac_addr);
|
||||
else
|
||||
return n;
|
||||
}
|
||||
|
||||
writel(MII_MODE_ENABLE, &cdev->miisel);
|
||||
|
||||
rv = cpsw_register(&cpsw_data);
|
||||
if (rv < 0)
|
||||
printf("Error %d registering CPSW switch\n", rv);
|
||||
else
|
||||
n += rv;
|
||||
return n;
|
||||
}
|
||||
#endif /* if CONFIG_DRIVER_TI_CPSW */
|
||||
@@ -0,0 +1,14 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* board.h
|
||||
*
|
||||
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
void enable_uart0_pin_mux(void);
|
||||
void enable_board_pin_mux(void);
|
||||
|
||||
#endif /* _BOARD_H_ */
|
||||
@@ -0,0 +1,119 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* mux.c
|
||||
*
|
||||
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/mux.h>
|
||||
#include <asm/io.h>
|
||||
#include "board.h"
|
||||
|
||||
/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
|
||||
static struct module_pin_mux uart0_pin_mux[] = {
|
||||
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
|
||||
|
||||
/* I2C pins C16(scl)/C17(sda) */
|
||||
static struct module_pin_mux i2c0_pin_mux[] = {
|
||||
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
|
||||
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* SPI0 pins */
|
||||
static struct module_pin_mux spi0_pin_mux[] = {
|
||||
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
|
||||
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
|
||||
{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
|
||||
{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
|
||||
PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* SPI1 pins */
|
||||
static struct module_pin_mux spi1_pin_mux[] = {
|
||||
{OFFSET(ecap0_in_pwm0_out), (MODE(4) | RXACTIVE | PULLUDEN)}, /* SPI1_SCLK */
|
||||
{OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN)}, /* SPI1_D0 */
|
||||
{OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUDEN)}, /* SPI1_D1 */
|
||||
{OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN)}, /* SPI1_CS0 */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* MMC0 pins */
|
||||
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* MII pins */
|
||||
static struct module_pin_mux mii1_pin_mux[] = {
|
||||
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
|
||||
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
|
||||
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
|
||||
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
|
||||
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
|
||||
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
|
||||
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
|
||||
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
|
||||
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
|
||||
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
|
||||
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
|
||||
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
|
||||
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
|
||||
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
||||
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||
{-1},
|
||||
};
|
||||
|
||||
/* NAND pins */
|
||||
static struct module_pin_mux nand_pin_mux[] = {
|
||||
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
|
||||
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
|
||||
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
|
||||
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
|
||||
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
|
||||
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
|
||||
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
|
||||
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
|
||||
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
|
||||
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
|
||||
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
|
||||
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
|
||||
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
|
||||
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
|
||||
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
|
||||
{-1},
|
||||
};
|
||||
|
||||
void enable_uart0_pin_mux(void)
|
||||
{
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
}
|
||||
|
||||
void enable_board_pin_mux()
|
||||
{
|
||||
configure_module_pin_mux(i2c0_pin_mux);
|
||||
configure_module_pin_mux(spi0_pin_mux);
|
||||
configure_module_pin_mux(spi1_pin_mux);
|
||||
configure_module_pin_mux(uart0_pin_mux);
|
||||
configure_module_pin_mux(mii1_pin_mux);
|
||||
configure_module_pin_mux(mmc0_pin_mux);
|
||||
configure_module_pin_mux(nand_pin_mux);
|
||||
}
|
||||
@@ -0,0 +1,40 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* pengwyn.h
|
||||
*
|
||||
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
|
||||
*
|
||||
* based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_PENGWYN_H
|
||||
#define __CONFIG_PENGWYN_H
|
||||
|
||||
#include <configs/ti_am335x_common.h>
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK)
|
||||
|
||||
/* NAND Configuration. */
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
|
||||
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
|
||||
34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,\
|
||||
50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,\
|
||||
66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,\
|
||||
82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\
|
||||
98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\
|
||||
114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\
|
||||
134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\
|
||||
154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\
|
||||
174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\
|
||||
194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209,}
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 26
|
||||
#define CONFIG_SYS_NAND_ECCSTEPS 8
|
||||
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
|
||||
/* END NAND Configuration. */
|
||||
/* NS16550 Configuration: primary UART via FTDI */
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000
|
||||
|
||||
#endif /* ! __CONFIG_PENGWYN_H */
|
||||
@@ -0,0 +1,165 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* pengwyn.h
|
||||
*
|
||||
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
|
||||
*
|
||||
* based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_PENGWYN_H
|
||||
#define __CONFIG_PENGWYN_H
|
||||
|
||||
#include <configs/ti_am335x_common.h>
|
||||
|
||||
/* Clock Defines */
|
||||
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||
#define V_SCLK (V_OSCK)
|
||||
|
||||
/* set env size */
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
DEFAULT_LINUX_BOOT_ENV \
|
||||
"loadaddr=0x80200000\0" \
|
||||
"fdtaddr=0x80F80000\0" \
|
||||
"bootpart=0:2\0" \
|
||||
"bootdir=/boot\0" \
|
||||
"bootfile=zImage\0" \
|
||||
"fdtfile=am335x-pengwyn.dtb\0" \
|
||||
"console=ttyO0,115200n8\0" \
|
||||
"optargs=\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 ro\0" \
|
||||
"mmcrootfstype=ext4 rootwait\0" \
|
||||
"rootpath=/export/rootfs\0" \
|
||||
"nfsopts=nolock\0" \
|
||||
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
|
||||
"::off\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${mmcroot} " \
|
||||
"rootfstype=${mmcrootfstype}\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=/dev/nfs " \
|
||||
"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
|
||||
"ip=dhcp\0" \
|
||||
"bootenv=uEnv.txt\0" \
|
||||
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||
"importbootenv=echo Importing environment from mmc ...; " \
|
||||
"env import -t $loadaddr $filesize\0" \
|
||||
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
|
||||
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
|
||||
"mmcloados=run mmcargs; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr};\0" \
|
||||
"mmcboot=mmc dev ${mmcdev}; " \
|
||||
"if mmc rescan; then " \
|
||||
"echo SD/MMC found on device ${mmcdev};" \
|
||||
"if run loadbootenv; then " \
|
||||
"echo Loaded environment from ${bootenv};" \
|
||||
"run importbootenv;" \
|
||||
"fi;" \
|
||||
"if test -n $uenvcmd; then " \
|
||||
"echo Running uenvcmd ...;" \
|
||||
"run uenvcmd;" \
|
||||
"fi;" \
|
||||
"if run loadimage; then " \
|
||||
"run loadfdt;" \
|
||||
"run mmcloados;" \
|
||||
"fi;" \
|
||||
"fi;\0" \
|
||||
"netboot=echo Booting from network ...; " \
|
||||
"setenv autoload no; " \
|
||||
"dhcp; " \
|
||||
"tftp ${loadaddr} ${bootfile}; " \
|
||||
"tftp ${fdtaddr} ${fdtfile}; " \
|
||||
"run netargs; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0" \
|
||||
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
|
||||
"nandargs=setenv bootargs console=${console} " \
|
||||
"${optargs} " \
|
||||
"root=${nandroot} " \
|
||||
"rootfstype=${nandrootfstype}\0" \
|
||||
"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
|
||||
"nandrootfstype=ubifs rootwait=1\0" \
|
||||
"nandboot=echo Booting from nand ...; " \
|
||||
"run nandargs; " \
|
||||
"nand read ${fdtaddr} u-boot-spl-os; " \
|
||||
"nand read ${loadaddr} kernel; " \
|
||||
"bootz ${loadaddr} - ${fdtaddr}\0"
|
||||
#endif
|
||||
|
||||
/* NS16550 Configuration: primary UART via FTDI */
|
||||
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
|
||||
|
||||
/* I2C Configuration */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_ENV_EEPROM_IS_ON_I2C
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
|
||||
/* SPL */
|
||||
|
||||
/* NAND support */
|
||||
|
||||
/* NAND Configuration. */
|
||||
//#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
//#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
|
||||
//#define CONFIG_SYS_NAND_PAGE_SIZE 4096
|
||||
//#define CONFIG_SYS_NAND_OOBSIZE 224
|
||||
//#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
//#define CONFIG_SYS_NAND_BLOCK_SIZE (128*4096)
|
||||
//#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
|
||||
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
|
||||
34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,\
|
||||
50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,\
|
||||
66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,\
|
||||
82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\
|
||||
98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\
|
||||
114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\
|
||||
134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\
|
||||
154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\
|
||||
174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\
|
||||
194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209}
|
||||
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 26
|
||||
#define CONFIG_SYS_NAND_ECCSTEPS 8
|
||||
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
|
||||
CONFIG_SYS_NAND_ECCSTEPS)
|
||||
//#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
|
||||
/* END NAND Configuration. */
|
||||
|
||||
//#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||
/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */
|
||||
//#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
|
||||
|
||||
/* Size must be a multiple of Nand erase size (524288 b) */
|
||||
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
||||
/* NAND: SPL falcon mode configs */
|
||||
//#ifdef CONFIG_SPL_OS_BOOT
|
||||
//#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
|
||||
//#endif
|
||||
|
||||
/*
|
||||
* USB configuration. We enable MUSB support, both for host and for
|
||||
* gadget. We set USB0 as peripheral and USB1 as host, based on the
|
||||
* board schematic and physical port wired to each. Then for host we
|
||||
* add mass storage support.
|
||||
*/
|
||||
//#define CONFIG_AM335X_USB0
|
||||
//#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
|
||||
//#define CONFIG_AM335X_USB1
|
||||
//#define CONFIG_AM335X_USB1_MODE MUSB_HOST
|
||||
|
||||
/* Network */
|
||||
//#define CONFIG_PHY_RESET 1
|
||||
//#define CONFIG_PHY_NATSEMI
|
||||
//#define CONFIG_PHY_REALTEK
|
||||
|
||||
#endif /* ! __CONFIG_PENGWYN_H */
|
||||
@@ -0,0 +1,127 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_OMAP2PLUS=y
|
||||
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="am335x-pengwyn"
|
||||
CONFIG_AM33XX=y
|
||||
CONFIG_TARGET_PENGWYN=y
|
||||
CONFIG_CLOCK_SYNTHESIZER=y
|
||||
CONFIG_AM335X_USB0=y
|
||||
CONFIG_AM335X_USB0_PERIPHERAL=y
|
||||
CONFIG_AM335X_USB1=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
|
||||
CONFIG_TIMESTAMP=y
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
# CONFIG_USE_SPL_FIT_GENERATOR is not set
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTCOMMAND="run findfdt; run init_console; run finduuid; run distro_bootcmd"
|
||||
CONFIG_LOGLEVEL=3
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
CONFIG_ARCH_MISC_INIT=y
|
||||
CONFIG_SYS_SPL_MALLOC=y
|
||||
CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
|
||||
CONFIG_SPL_FIT_IMAGE_TINY=y
|
||||
CONFIG_SPL_ETH=y
|
||||
# CONFIG_SPL_FS_EXT4 is not set
|
||||
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
|
||||
CONFIG_SPL_MTD_SUPPORT=y
|
||||
CONFIG_SPL_MUSB_NEW=y
|
||||
CONFIG_SPL_NAND_DRIVERS=y
|
||||
CONFIG_SPL_NAND_ECC=y
|
||||
CONFIG_SPL_NAND_BASE=y
|
||||
CONFIG_SPL_NET=y
|
||||
CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
|
||||
CONFIG_SPL_OS_BOOT=y
|
||||
CONFIG_SYS_NAND_SPL_KERNEL_OFFS=0x200000
|
||||
CONFIG_SPL_FALCON_BOOT_MMCSD=y
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
|
||||
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
|
||||
CONFIG_SPL_USB_GADGET=y
|
||||
CONFIG_SPL_USB_ETHER=y
|
||||
CONFIG_SYS_MAXARGS=64
|
||||
CONFIG_SYS_BOOTM_LEN=0x1000000
|
||||
CONFIG_CMD_SPL=y
|
||||
CONFIG_CMD_SPL_NAND_OFS=0x00080000
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_NAND=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_BOOTP_DNS2=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_LIST="am335x-pengwyn"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_SPL_ENV_IS_NOWHERE=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_NET_RETRY_COUNT=10
|
||||
CONFIG_BOOTP_SEND_HOSTNAME=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_SYS_BOOTCOUNT_BE=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_CDCE9XX=y
|
||||
CONFIG_CLK_TI_CTRL=y
|
||||
CONFIG_DFU_TFTP=y
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DFU_NAND=y
|
||||
CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y
|
||||
CONFIG_DFU_RAM=y
|
||||
CONFIG_USB_FUNCTION_FASTBOOT=y
|
||||
CONFIG_FASTBOOT_FLASH=y
|
||||
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
|
||||
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
|
||||
# CONFIG_MMC_HW_PARTITIONING is not set
|
||||
CONFIG_MMC_OMAP_HS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SYS_NAND_PAGE_COUNT=0x40
|
||||
CONFIG_SYS_NAND_PAGE_SIZE=0x1000
|
||||
CONFIG_SYS_NAND_OOBSIZE=0xe0
|
||||
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
||||
CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_SPEED=24000000
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_DRIVER_TI_CPSW=y
|
||||
CONFIG_DM_PMIC=y
|
||||
# CONFIG_SPL_DM_PMIC is not set
|
||||
CONFIG_PMIC_TPS65217=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_OMAP3_SPI=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_OMAP_TIMER=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_SPL_DM_USB_GADGET=y
|
||||
CONFIG_USB_MUSB_HOST=y
|
||||
CONFIG_USB_MUSB_GADGET=y
|
||||
CONFIG_USB_MUSB_TI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
|
||||
CONFIG_USB_ETHER=y
|
||||
CONFIG_WDT=y
|
||||
# CONFIG_SPL_WDT is not set
|
||||
CONFIG_DYNAMIC_CRC_TABLE=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_LZO=y
|
||||
@@ -0,0 +1,48 @@
|
||||
arch=arm
|
||||
baudrate=115200
|
||||
board=pengwyn
|
||||
board_name=pengwyn
|
||||
bootargs=console=ttyO0,115200n8 root=ubi0:rootfs rw ubi.mtd=7,2048 rootfstype=ubifs rootwait=1
|
||||
bootcmd=run mmcboot;run nandboot;
|
||||
bootdelay=2
|
||||
bootdir=/boot
|
||||
bootenv=uEnv.txt
|
||||
bootfile=fitImage
|
||||
bootpart=0:2
|
||||
console=ttyS0,115200n8
|
||||
cpu=armv7
|
||||
ethact=cpsw
|
||||
ethaddr=00:18:30:fc:c0:35
|
||||
fdtaddr=0x80F80000
|
||||
fdtfile=am335x-pengwyn.dtb
|
||||
importbootenv=echo Importing environment from mmc ...; env import -t $loadaddr $filesize
|
||||
loadaddr=0x80600000
|
||||
loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}
|
||||
loadfdt=fatload mmc ${mmcdev} ${fdtaddr} ${fdtfile}
|
||||
loadimage=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}
|
||||
mmcargs=setenv bootargs console=${console} ${optargs} root=${mmcroot} rootfstype=${mmcrootfstype}
|
||||
mmcboot=mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run uenvcmd;fi;if run loadimage; then run loadfdt;run mmcloados;fi;fi;
|
||||
mmcdev=0
|
||||
mmcloados=run mmcargs; bootm ${loadaddr} - ${fdtaddr};
|
||||
mmcroot=/dev/mmcblk0p2 rw
|
||||
mmcrootfstype=ext4 rootwait
|
||||
mtddevname=SPL
|
||||
mtddevnum=0
|
||||
mtdids=nand0=omap2-nand.0
|
||||
mtdparts=mtdparts=omap2-nand.0:512k(SPL),512k(SPL.backup1),512k(SPL.backup2),512k(SPL.backup3),1536k(u-boot),512k(u-boot-spl-os),512k(u-boot-env),5m(kernel),-(rootfs)
|
||||
nandargs=setenv bootargs console=${console} ${optargs} root=${nandroot} rootfstype=${nandrootfstype}
|
||||
nandboot=echo Booting from nand ...; run nandargs; nand read ${fdtaddr} u-boot-spl-os; nand read ${loadaddr} kernel; bootz ${loadaddr} - ${fdtaddr}
|
||||
nandroot=ubi0:rootfs rw ubi.mtd=7,2048
|
||||
nandrootfstype=ubifs rootwait=1
|
||||
netargs=setenv bootargs console=${console} ${optargs} root=/dev/nfs nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp
|
||||
netboot=echo Booting from network ...; setenv autoload no; dhcp; tftp ${loadaddr} ${bootfile}; tftp ${fdtaddr} ${fdtfile}; run netargs; bootz ${loadaddr} - ${fdtaddr}
|
||||
nfsopts=nolock
|
||||
partition=nand0,0
|
||||
rootpath=/export/rootfs
|
||||
soc=am33xx
|
||||
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
|
||||
stderr=serial@44e09000
|
||||
stdin=serial@44e09000
|
||||
stdout=serial@44e09000
|
||||
vendor=silica
|
||||
ver=U-Boot 2020.07-g2f5fbb5b39 (Jul 06 2020 - 19:22:53 +0000)
|
||||
@@ -0,0 +1,55 @@
|
||||
# Copyright (C) 2023 Vincent BENOIT <vincent.benoit@scle.fr>
|
||||
# Release under the MIT license (see COPYING.MIT for the terms)
|
||||
require u-boot-ti.inc
|
||||
|
||||
FILESEXTRAPATHS:prepend := "${THISDIR}/files2:"
|
||||
|
||||
LIC_FILES_CHKSUM = "file://Licenses/README;md5=2ca5f2c35c8cc335f0a19756634782f1"
|
||||
|
||||
PR = "r33"
|
||||
BRANCH = "master"
|
||||
SRC_URI = " \
|
||||
${UBOOT_GIT_URI};protocol=${UBOOT_GIT_PROTOCOL};branch=${BRANCH} \
|
||||
file://board.c \
|
||||
file://board.h \
|
||||
file://Kconfig \
|
||||
file://MAINTAINERS \
|
||||
file://Makefile \
|
||||
file://mux.c \
|
||||
file://pengwyn.h \
|
||||
file://pengwyn_defconfig \
|
||||
file://am335x-pengwyn.dts \
|
||||
file://am335x-pengwyn-u-boot.dtsi \
|
||||
file://uEnv.txt \
|
||||
file://0001-add-pengwyn-dts-to-makefile.patch \
|
||||
file://0002-add-target-pengwyn.patch \
|
||||
"
|
||||
|
||||
# Tag: v2023.01
|
||||
SRCREV = "62e2ad1ceafbfdf2c44d3dc1b6efc81e768a96b9"
|
||||
|
||||
S = "${WORKDIR}/git"
|
||||
|
||||
do_configure:prepend() {
|
||||
install -d ${S}/board/silica/pengwyn
|
||||
install -m 0644 ${WORKDIR}/board.c ${S}/board/silica/pengwyn
|
||||
install -m 0644 ${WORKDIR}/board.h ${S}/board/silica/pengwyn
|
||||
install -m 0644 ${WORKDIR}/Kconfig ${S}/board/silica/pengwyn
|
||||
install -m 0644 ${WORKDIR}/MAINTAINERS ${S}/board/silica/pengwyn
|
||||
install -m 0644 ${WORKDIR}/Makefile ${S}/board/silica/pengwyn
|
||||
install -m 0644 ${WORKDIR}/mux.c ${S}/board/silica/pengwyn
|
||||
|
||||
install -d ${S}/configs
|
||||
install -m 0644 ${WORKDIR}/pengwyn_defconfig ${S}/configs
|
||||
|
||||
install -d ${S}/include/configs/
|
||||
install -m 0644 ${WORKDIR}/pengwyn.h ${S}/include/configs/
|
||||
|
||||
install -d ${S}/arch/arm/dts
|
||||
install -m 0644 ${WORKDIR}/am335x-pengwyn.dts ${S}/arch/arm/dts
|
||||
install -m 0644 ${WORKDIR}/am335x-pengwyn-u-boot.dtsi ${S}/arch/arm/dts
|
||||
}
|
||||
|
||||
do_deploy:append() {
|
||||
install -m 0644 ${WORKDIR}/uEnv.txt ${DEPLOY_DIR_IMAGE}
|
||||
}
|
||||
Reference in New Issue
Block a user