518 lines
14 KiB
Plaintext
518 lines
14 KiB
Plaintext
/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "TI AM335x Silica Pengwyn";
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compatible = "ti,am335x-pengwyn", "ti,am33xx";
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cpus {
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cpu@0 {
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cpu0-supply = <&vdd1_reg>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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chosen {
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stdout-path = &uart0;
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};
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vbat: fixedregulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "vbat";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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};
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vmmcsd_fixed: fixedregulator0 {
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compatible = "regulator-fixed";
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regulator-name = "vmmcsd_fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&am33xx_pinmux {
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pinctrl-names = "default";
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i2c0_pins: pinmux_i2c0_pins {
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pinctrl-single,pins = <
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0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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};
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spi0_pins: pinmux_spi0_pins {
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pinctrl-single,pins = <
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0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
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0x154 (PIN_OUTPUT | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
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0x158 (PIN_INPUT | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
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0x15c (PIN_OUTPUT | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
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/* AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT, MUX_MODE0) */ /* spi0_d0_mosi, external pullup */
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/* AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE0) */ /* spi0_d1_miso */
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/* AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE0) */ /* external pullup */
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>;
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};
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spi1_pins: pinmux_spi1_pins {
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pinctrl-single,pins = <
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0x164 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* (C18) ecap0_in_pwm0_out.spi1_sclk */
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0x194 (PIN_OUTPUT | MUX_MODE3) /* (B13) mcasp0_fsx.spi1_d0 */
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0x198 (PIN_INPUT | MUX_MODE3) /* (D12) mcasp0_axr0.spi1_d1 */
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0x19c (PIN_OUTPUT | MUX_MODE3) /* (C12) mcasp0_ahclkr.spi1_cs0 */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLUP, MUX_MODE3) */ /* mcasp0_ahclkr, spi1_cs0 */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLUP, MUX_MODE3) */ /* mcasp0_fsx, spi1_d0_mosi */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLUP, MUX_MODE3) */ /* mcasp0_axr0, spi1_d1_miso */
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/* AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) */ /* ecap0_in_pwm0_out, spi1_sclk */
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>;
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};
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uart0_pins: pinmux_uart0_pins {
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pinctrl-single,pins = <
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0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
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0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
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>;
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};
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//clkout1_pin: pinmux_clkout1_pin {
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// pinctrl-single,pins = <
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// 0x (PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr0.clkout1 */
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// >;
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//};
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clkout2_pin: pinmux_clkout2_pin {
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pinctrl-single,pins = <
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0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
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>;
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};
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nandflash_pins_s0: nandflash_pins_s0 {
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pinctrl-single,pins = <
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0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
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0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
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>;
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};
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_er.mii1_rx_er */
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0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_tx_en.mii1_tx_en */
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0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_dv.mii1_rx_dv */
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0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
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0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
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0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
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0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
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0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_tx_clk.mii1_tx_clk */
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0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rx_clk.mii1_rx_clk */
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0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
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0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
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0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
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0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) */
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* MDIO */
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0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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/* AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) */
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>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
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pinctrl-single,pins = <
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/* MDIO reset value */
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0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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/* AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) */
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/* AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) */
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>;
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};
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
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0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
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0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
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0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
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0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
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0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
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0x190 (PIN_INPUT | MUX_MODE4) /* mcasp0_aclkx.mmc0_sdcd */
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0x1a0 (PIN_INPUT | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT, MUX_MODE4) */ /* mcasp0_aclkx.mmc0_sdcd */
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/* AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) */ /* mcasp0_aclkr.mmc0_sdwp */
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>;
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};
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usb_pins: usb_pins {
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pinctrl-single,pins = <
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0x21c (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.gpio0_18 */
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0x234 (PIN_OUTPUT | MUX_MODE0) /* usb1_drvvbus.gpio3_13 */
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/* USB0 */
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/* AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT, MUX_MODE0) */ /* gpmc_a9.gpio0_18 */
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/* USB1 */
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/* AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT, MUX_MODE0) */ /* usb1_drvvbus.gpio3_13 */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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clock-frequency = <400000>;
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tps: tps@2d {
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reg = <0x2d>;
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};
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};
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&usb {
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status = "okay";
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};
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&usb_ctrl_mod {
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status = "okay";
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};
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&usb0_phy {
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status = "okay";
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};
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&usb1_phy {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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dr_mode = "host";
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};
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&spi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi1_pins>;
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ti,pindir-d0-out-d1-in;
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slb9670@0 {
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compatible = "tis,tpm2-spi";
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reg = <0>;
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spi-max-frequency = <12000000>; // 12 MHz
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};
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};
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&cppi41dma {
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status = "okay";
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};
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&lcdc {
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status = "okay";
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nandflash_pins_s0>;
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ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
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nand@0,0 {
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reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <44>;
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gpmc,cs-wr-off-ns = <44>;
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gpmc,adv-on-ns = <6>;
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gpmc,adv-rd-off-ns = <34>;
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gpmc,adv-wr-off-ns = <44>;
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <40>;
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gpmc,oe-on-ns = <0>;
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gpmc,oe-off-ns = <54>;
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gpmc,access-ns = <64>;
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gpmc,rd-cycle-ns = <82>;
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gpmc,wr-cycle-ns = <82>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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/* All SPL-* partitions are sized to minimal length
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* which can be independently programmable. For
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* NAND flash this is equal to size of erase-block */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.SPL";
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reg = <0x000000000000 0x000000080000>;
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};
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partition@1 {
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label = "NAND.SPL.backup1";
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reg = <0x000000080000 0x000000100000>;
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};
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partition@2 {
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label = "NAND.SPL.backup2";
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reg = <0x000000180000 0x000000180000>;
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};
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partition@3 {
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label = "NAND.SPL.backup3";
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reg = <0x000000300000 0x000000200000>;
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};
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partition@4 {
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label = "NAND.u-boot";
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reg = <0x000000500000 0x000000380000>;
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};
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partition@5 {
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label = "NAND.u-boot-env";
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reg = <0x000000880000 0x000000400000>;
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};
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partition@6 {
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label = "NAND.kernel";
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reg = <0x000000C80000 0x000001000000>;
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};
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partition@7 {
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label = "NAND.file-system";
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reg = <0x000001C80000 0x00003E180000>;
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};
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};
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};
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#include "tps65910.dtsi"
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&tps {
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vcc1-supply = <&vbat>;
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|
vcc2-supply = <&vbat>;
|
|
vcc3-supply = <&vbat>;
|
|
vcc4-supply = <&vbat>;
|
|
vcc5-supply = <&vbat>;
|
|
vcc6-supply = <&vbat>;
|
|
vcc7-supply = <&vbat>;
|
|
vccio-supply = <&vbat>;
|
|
|
|
regulators {
|
|
vrtc_reg: regulator@0 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vio_reg: regulator@1 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdd1_reg: regulator@2 {
|
|
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
|
regulator-name = "vdd_mpu";
|
|
regulator-min-microvolt = <912500>;
|
|
regulator-max-microvolt = <1312500>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdd2_reg: regulator@3 {
|
|
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
|
regulator-name = "vdd_core";
|
|
regulator-min-microvolt = <912500>;
|
|
regulator-max-microvolt = <1150000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdd3_reg: regulator@4 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdig1_reg: regulator@5 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdig2_reg: regulator@6 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vpll_reg: regulator@7 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdac_reg: regulator@8 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vaux1_reg: regulator@9 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vaux2_reg: regulator@10 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vaux33_reg: regulator@11 {
|
|
regulator-always-on;
|
|
};
|
|
|
|
vmmc_reg: regulator@12 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
&mac {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&cpsw_default>;
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
status = "okay";
|
|
slaves = <1>;
|
|
};
|
|
|
|
&davinci_mdio {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
status = "okay";
|
|
|
|
ethphy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
&cpsw_emac0 {
|
|
phy-handle = <ðphy0>;
|
|
phy-mode = "rgmii-id";
|
|
};
|
|
|
|
&tscadc {
|
|
status = "okay";
|
|
tsc {
|
|
ti,wires = <4>;
|
|
ti,x-plate-resistance = <200>;
|
|
ti,coordinate-readouts = <5>;
|
|
ti,wire-config = <0x00 0x11 0x22 0x33>;
|
|
ti,charge-delay = <0x400>;
|
|
};
|
|
|
|
adc {
|
|
ti,adc-channels = <4 5 6 7>;
|
|
};
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
vmmc-supply = <&vmmcsd_fixed>;
|
|
bus-width = <4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins>;
|
|
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; // specify GPIOs for card detection
|
|
wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; /* GPIO1_28 */
|
|
};
|
|
|
|
&edma {
|
|
ti,edma-xbar-event-map = /bits/ 16 <1 12
|
|
2 13>;
|
|
};
|
|
|
|
&sham {
|
|
status = "okay";
|
|
};
|
|
|
|
&aes {
|
|
status = "okay";
|
|
};
|