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mirror of https://git.yoctoproject.org/meta-arm synced 2026-06-05 02:20:30 +00:00

arm-bsp/scp-firmware: set CCIX speed to GEN3 to work with interposer C2C setup

Set CCIX speed to GEN3 to work with interposer C2C setup.
In this usecase set downstream/upstream port transmitter preset value to 4.

Change-Id: I9795a46d9a349dc2813a4ed92944a481c0a2498e
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Signed-off-by: Jon Mason <jon.mason@arm.com>
This commit is contained in:
Khasim Mohammed
2020-09-08 12:57:26 +05:30
committed by Jon Mason
parent 87e8e14b9a
commit 1f3cf5812c
2 changed files with 91 additions and 0 deletions
@@ -0,0 +1,85 @@
Upstream-Status: Inappropriate [will not be submitted as its only required till hardware gets fixed]
The patch is picked from git repo:
https://git.linaro.org/landing-teams/working/arm/n1sdp-pcie-quirk.git/tree/scp/0001-product-n1sdp-set-CCIX-speed-to-GEN3-to-work-with-in.patch
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
From a6d545cf9b6c46f2ea415d64fa81eb4771cfb51c Mon Sep 17 00:00:00 2001
From: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
Date: Thu, 28 May 2020 16:19:12 +0530
Subject: [PATCH] product/n1sdp: set CCIX speed to GEN3 to work with interposer
C2C setup
Set CCIX speed to GEN3 to work with interposer C2C setup
In this use case set downstream/upstream port transmitter
preset value to 4.
Change-Id: I16e72a5eaa105386a64ab4ffe56f67134c670313
Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com>
---
.../module/n1sdp_pcie/src/mod_n1sdp_pcie.c | 33 +++++++++++++++----
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c
index 19fa5a5..a93e6cc 100644
--- a/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c
+++ b/product/n1sdp/module/n1sdp_pcie/src/mod_n1sdp_pcie.c
@@ -206,7 +206,13 @@ static int n1sdp_pcie_phy_init(fwk_id_t id)
if (dev_ctx == NULL)
return FWK_E_PARAM;
- gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3;
+ if ((n1sdp_get_chipid() != 0x0) ||
+ !dev_ctx->config->ccix_capable ||
+ pcie_ctx.c2c_api->is_slave_alive())
+ gen_speed = PCIE_GEN_3;
+ else
+ gen_speed = PCIE_GEN_4;
+
lane_count = LAN_COUNT_IN_X_16;
FWK_LOG_INFO("[%s] Initializing PHY...", pcie_type[did]);
@@ -239,7 +245,13 @@ static int n1sdp_pcie_controller_init(fwk_id_t id, bool ep_mode)
if (dev_ctx == NULL)
return FWK_E_PARAM;
- gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3;
+ if ((n1sdp_get_chipid() != 0x0) ||
+ !dev_ctx->config->ccix_capable ||
+ pcie_ctx.c2c_api->is_slave_alive())
+ gen_speed = PCIE_GEN_3;
+ else
+ gen_speed = PCIE_GEN_4;
+
lane_count = LAN_COUNT_IN_X_16;
if (ep_mode) {
@@ -282,12 +294,19 @@ static int n1sdp_pcie_link_training(fwk_id_t id, bool ep_mode)
if (dev_ctx == NULL)
return FWK_E_PARAM;
- gen_speed = dev_ctx->config->ccix_capable ? PCIE_GEN_4 : PCIE_GEN_3;
+ if ((n1sdp_get_chipid() != 0x0) ||
+ !dev_ctx->config->ccix_capable ||
+ pcie_ctx.c2c_api->is_slave_alive()) {
+ gen_speed = PCIE_GEN_3;
+ down_stream_tx_preset = PCIE_RC_TX_PRESET_VALUE;
+ up_stream_tx_preset = PCIE_RC_TX_PRESET_VALUE;
+ } else {
+ gen_speed = PCIE_GEN_4;
+ down_stream_tx_preset = CCIX_RC_TX_PRESET_VALUE;
+ up_stream_tx_preset = CCIX_RC_TX_PRESET_VALUE;
+ }
+
lane_count = LAN_COUNT_IN_X_16;
- down_stream_tx_preset = dev_ctx->config->ccix_capable ?
- CCIX_RC_TX_PRESET_VALUE : PCIE_RC_TX_PRESET_VALUE;
- up_stream_tx_preset = dev_ctx->config->ccix_capable ?
- CCIX_RC_TX_PRESET_VALUE : PCIE_RC_TX_PRESET_VALUE;
if (gen_speed >= PCIE_GEN_3 && !ep_mode) {
FWK_LOG_INFO(
--
2.25.0
@@ -4,6 +4,12 @@ SRCREV = "350be71a2ecef588b8ff5a095a0840de23506e45"
SCP_PLATFORM = "n1sdp"
SCP_LOG_LEVEL = "INFO"
FILESEXTRAPATHS_prepend := "${THISDIR}/files/:"
SRC_URI_append = " \
file://0001-product-n1sdp-set-CCIX-speed-to-GEN3-to-work-with-in.patch \
"
COMPATIBLE_MACHINE_n1sdp = "n1sdp"
PV = "2.6.0+git${SRCPV}"