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arm-bsp/tc0: Add patches in optee-os for FF-A ABI changes

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Adds below patches:
     - To use FFA_SECONDARY_EP_REGISTER
     - To align with latest FFA_ABIs in SPMC (hafnium)

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I4ae386e2dd846e747cbc426270fc0c489ccdfe1f
This commit is contained in:
Arunachalam Ganapathy
2021-04-15 10:29:19 +01:00
committed by Tushar Khandelwal
parent 853f3e0565
commit 29f0e5982c
3 changed files with 236 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
meta-arm-bsp/recipes-security/optee/files/optee-os/tc0/0012-core-Add-FFA_SECONDARY_EP_REGISTER-support.patch
+155
View File
@@ -0,0 +1,155 @@
From 5d903d035e376e3b4c411e4f8947f6508ef577d9 Mon Sep 17 00:00:00 2001
From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Date: Mon, 12 Apr 2021 15:42:29 +0100
Subject: [PATCH 1/2] core: Add FFA_SECONDARY_EP_REGISTER support
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I806b07b815278512abaecc7c77b29a0d395e3d35
Upstream-Status: Pending [Not submitted to upstream yet]
---
core/arch/arm/include/ffa.h | 3 +-
core/arch/arm/include/kernel/boot.h | 3 +-
core/arch/arm/kernel/entry_a64.S | 3 +-
core/arch/arm/plat-totalcompute/tc0_spmc_pm.c | 55 ++++---------------
4 files changed, 17 insertions(+), 47 deletions(-)
diff --git a/core/arch/arm/include/ffa.h b/core/arch/arm/include/ffa.h
index 6c78dacc..f5480c00 100644
--- a/core/arch/arm/include/ffa.h
+++ b/core/arch/arm/include/ffa.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2020, Linaro Limited
- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*/
#ifndef __FFA_H
@@ -68,6 +68,7 @@
#define FFA_MEM_RECLAIM U(0x84000077)
#define FFA_MEM_FRAG_RX U(0x8400007A)
#define FFA_MEM_FRAG_TX U(0x8400007B)
+#define FFA_SECONDARY_EP_REGISTER_64 U(0xC4000084)
/* Special value for traffic targeted to the Hypervisor or SPM */
#define FFA_TARGET_INFO_MBZ U(0x0)
diff --git a/core/arch/arm/include/kernel/boot.h b/core/arch/arm/include/kernel/boot.h
index 278d514f..30eb1596 100644
--- a/core/arch/arm/include/kernel/boot.h
+++ b/core/arch/arm/include/kernel/boot.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2015-2020, Linaro Limited
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
*/
#ifndef __KERNEL_BOOT_H
#define __KERNEL_BOOT_H
@@ -86,6 +87,6 @@ void *get_external_dt(void);
unsigned long get_aslr_seed(void *fdt);
-void ffa_secondary_cpu_boot_req(vaddr_t secondary_ep, uint64_t cookie);
+void ffa_secondary_cpu_ep_register(vaddr_t secondary_ep);
#endif /* __KERNEL_BOOT_H */
diff --git a/core/arch/arm/kernel/entry_a64.S b/core/arch/arm/kernel/entry_a64.S
index 9ae6b32e..7d7b8aaf 100644
--- a/core/arch/arm/kernel/entry_a64.S
+++ b/core/arch/arm/kernel/entry_a64.S
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2015, Linaro Limited
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
*/
#include <platform_config.h>
@@ -239,7 +240,7 @@ clear_nex_bss:
*/
ldr x1, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET
sub x0, x0, x1
- bl ffa_secondary_cpu_boot_req
+ bl ffa_secondary_cpu_ep_register
b thread_ffa_msg_wait
#else
/*
diff --git a/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c b/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c
index 3fb32823..f31324b9 100644
--- a/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c
+++ b/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-2-Clause
/*
- * Copyright (c) 2020, Arm Limited
+ * Copyright (c) 2020 - 2021, Arm Limited
*/
#include <arm.h>
@@ -8,51 +8,18 @@
#include <ffa.h>
#include <sm/psci.h>
-/*
- * Lookup table of core and cluster affinities on the TC0. In the absence of a
- * DT that provides the same information, this table is used to initialise
- * OP-TEE on secondary cores.
- */
-static const uint64_t core_clus_aff_array[] = {
- 0x0000, /* Cluster 0 Cpu 0 */
- 0x0001, /* Cluster 0 Cpu 1 */
- 0x0002, /* Cluster 0 Cpu 2 */
- 0x0003, /* Cluster 0 Cpu 3 */
- 0x0004, /* Cluster 0 Cpu 4 */
- 0x0005, /* Cluster 0 Cpu 5 */
- 0x0006, /* Cluster 0 Cpu 6 */
- 0x0007 /* Cluster 0 Cpu 7 */
-};
-
-void ffa_secondary_cpu_boot_req(vaddr_t secondary_ep, uint64_t cookie)
+void ffa_secondary_cpu_ep_register(vaddr_t secondary_ep)
{
- unsigned long mpidr = read_mpidr();
- unsigned int aff_shift = 0;
- unsigned long a1 = 0;
- unsigned int cnt = 0;
- int32_t ret = 0;
-
- if (mpidr & MPIDR_MT_MASK)
- aff_shift = MPIDR_CLUSTER_SHIFT;
+ unsigned int ret = 0;
- for (cnt = 0; cnt < ARRAY_SIZE(core_clus_aff_array); cnt++) {
- /* Clear out the affinity fields until level 2 */
- a1 = mpidr & ~(unsigned long)MPIDR_AARCH32_AFF_MASK;
+ /* Invoke FFA_SECONDARY_EP_REGISTER_64 to the SPMC */
+ ret = thread_smc(FFA_SECONDARY_EP_REGISTER_64, secondary_ep, 0, 0);
- /* Create an mpidr from core_clus_aff_array */
- a1 |= core_clus_aff_array[cnt] << aff_shift;
-
- /* Ignore current cpu */
- if (a1 == mpidr)
- continue;
-
- /* Invoke the PSCI_CPU_ON_SMC64 function */
- ret = thread_smc(PSCI_CPU_ON_SMC64, a1, secondary_ep, cookie);
-
- if (ret != PSCI_RET_SUCCESS)
- EMSG("PSCI_CPU_ON op on mpidr 0x%lx failed %"PRId32,
- a1, ret);
- else
- DMSG("PSCI_CPU_ON op on mpidr 0x%lx done", a1);
+ if (ret != FFA_SUCCESS_32) {
+ EMSG("FFA_SECONDARY_EP_REGISTER_64 ret %"PRId32, ret);
+ } else {
+ DMSG("FFA_SECONDARY_EP_REGISTER_64 done");
}
+
+ return;
}
--
2.29.2
meta-arm-bsp/recipes-security/optee/files/optee-os/tc0/0013-core-arm-modify-FFA-ABIs-with-supported-convention.patch
+79
View File
@@ -0,0 +1,79 @@
From 6b7edfa39991079fc735a2afcba23454ae0205ed Mon Sep 17 00:00:00 2001
From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Date: Mon, 12 Apr 2021 15:29:13 +0100
Subject: [PATCH 2/2] core: arm: modify FFA ABIs with supported convention
Use FFA_MEM_RETRIEVE_REQ_32 as SPMC at SEL2 (hafnium) only supports 32-bit variant
Fix warnings in thread_spmc.c
Change-Id: Ia3d206d24f7f12dca9332b40f45934e132a37f99
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Upstream-Status: Pending [Not submitted to upstream yet]
---
core/arch/arm/kernel/thread_spmc.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/core/arch/arm/kernel/thread_spmc.c b/core/arch/arm/kernel/thread_spmc.c
index 872221d6..f8a05412 100644
--- a/core/arch/arm/kernel/thread_spmc.c
+++ b/core/arch/arm/kernel/thread_spmc.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: BSD-2-Clause
/*
* Copyright (c) 2020, Linaro Limited.
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019 - 2021, Arm Limited. All rights reserved.
*/
#include <assert.h>
@@ -128,8 +128,10 @@ static unsigned int rxtx_size;
static unsigned int rxtx_spinlock;
static bool tx_buf_is_mine;
+#ifdef CFG_CORE_SEL1_SPMC
static SLIST_HEAD(mem_frag_state_head, mem_frag_state) frag_state_head =
SLIST_HEAD_INITIALIZER(&frag_state_head);
+#endif
static uint32_t swap_src_dst(uint32_t src_dst)
{
@@ -387,7 +389,8 @@ static void handle_partition_info_get(struct thread_smc_args *args)
cpu_spin_lock(&rxtx_spinlock);
if (rxtx_size && tx_buf_is_mine) {
- struct ffa_partition_info *fpi = tx_buf;
+ struct ffa_partition_info *fpi =
+ (struct ffa_partition_info *)tx_buf;
fpi->id = my_sp_id;
fpi->execution_context = CFG_TEE_CORE_NB_CORE;
@@ -874,7 +877,7 @@ void thread_spmc_msg_recv(struct thread_smc_args *args)
case FFA_FEATURES:
handle_features(args);
break;
-#if CFG_CORE_SEL1_SPMC
+#ifdef CFG_CORE_SEL1_SPMC
#ifdef ARM64
case FFA_RXTX_MAP_64:
#endif
@@ -901,7 +904,7 @@ void thread_spmc_msg_recv(struct thread_smc_args *args)
else
handle_blocking_call(args);
break;
-#if CFG_CORE_SEL1_SPMC
+#ifdef CFG_CORE_SEL1_SPMC
#ifdef ARM64
case FFA_MEM_SHARE_64:
#endif
@@ -1266,7 +1269,7 @@ static struct mem_transaction_descr *spmc_retrieve_req(uint64_t cookie)
uint64_t size = sizeof(*retrieve_region) +
1 * sizeof(struct mem_access_descr);
struct thread_smc_args args = {
- .a0 = FFA_MEM_RETRIEVE_REQ_64,
+ .a0 = FFA_MEM_RETRIEVE_REQ_32,
.a1 = size, // Total Length
.a2 = size, // Frag Length == Total length
.a3 = 0, // Address, Using TX -> MBZ
--
2.29.2
meta-arm-bsp/recipes-security/optee/optee-os-tc0.inc
+2
View File
@@ -25,6 +25,8 @@ SRC_URI_append = " \
file://0009-plat-totalcompute-add-Theodul-DSU-support.patch \
file://0010-WIP-OP-TEE-SP-declare-device-regions-in-manifest.patch \
file://0011-WIP-OP-TEE-SP-use-CNTVCT-in-place-of-CNTVCT.patch \
file://0012-core-Add-FFA_SECONDARY_EP_REGISTER-support.patch \
file://0013-core-arm-modify-FFA-ABIs-with-supported-convention.patch \
"
COMPATIBLE_MACHINE = "tc0"