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arm-bsp/tc0: Update TF-A revision, add trusted-services support
- Update TF-A revision - Add patch for trusted services support - Add patch for GICR changes to support latest tc0 model Change-Id: I3ba1fd9c1f89721fc6349db4e0270c8b42e9fcf0 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
This commit is contained in:
Arunachalam Ganapathy
committed by
Tushar Khandelwal
Tushar Khandelwal
parent
806bbb07ed
commit
853f3e0565
+199
@@ -0,0 +1,199 @@
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From bda42d4e1c56022692b60447279d5321f872aa2b Mon Sep 17 00:00:00 2001
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From: Davidson K <davidson.kumaresan@arm.com>
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Date: Wed, 10 Mar 2021 12:07:15 +0530
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Subject: [PATCH 1/2] product/tc0: Add support for Trusted Services Secure
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Partitions
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This patch adds support for the crypto and secure storage secure
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partitions for the Total Compute platform. These secure partitions
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have to be managed by Hafnium executing at S-EL2
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Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e
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Upstream-Status: Pending [Not submitted to upstream yet]
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---
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Makefile | 4 +
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docs/plat/arm/arm-build-options.rst | 4 +
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.../fdts/tc0_spmc_ts_optee_sp_manifest.dts | 118 ++++++++++++++++++
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plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts | 10 ++
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4 files changed, 136 insertions(+)
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create mode 100644 plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts
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diff --git a/Makefile b/Makefile
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index b6c8b210c..d85c52bb4 100644
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--- a/Makefile
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+++ b/Makefile
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@@ -514,6 +514,10 @@ ifneq (${SPD},none)
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ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp)
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DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG
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endif
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+
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+ ifeq ($(findstring ts_optee_sp,$(ARM_SPMC_MANIFEST_DTS)),ts_optee_sp)
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+ DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
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+ endif
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else
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# All other SPDs in spd directory
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SPD_DIR := spd
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diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
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index a1d231357..32cf19291 100644
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--- a/docs/plat/arm/arm-build-options.rst
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+++ b/docs/plat/arm/arm-build-options.rst
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@@ -98,6 +98,10 @@ Arm Platform Build Options
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device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest
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file name contains pattern optee_sp.
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+ - ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and
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+ secure-storage) as SP in tb_fw_config device tree. This flag is defined only
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+ when ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern ts_optee_sp.
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+
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For a better understanding of these options, the Arm development platform memory
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map is explained in the :ref:`Firmware Design`.
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diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts
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new file mode 100644
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index 000000000..ac91db238
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--- /dev/null
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+++ b/plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts
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@@ -0,0 +1,118 @@
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+/*
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+ * Copyright (c) 2020, Arm Limited. All rights reserved.
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+ *
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+ * SPDX-License-Identifier: BSD-3-Clause
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+ */
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+/dts-v1/;
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+
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+/ {
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+ compatible = "arm,ffa-core-manifest-1.0";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+
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+ attribute {
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+ spmc_id = <0x8000>;
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+ maj_ver = <0x1>;
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+ min_ver = <0x0>;
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+ exec_state = <0x0>;
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+ load_address = <0x0 0xfd000000>;
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+ entrypoint = <0x0 0xfd000000>;
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+ binary_size = <0x80000>;
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+ };
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+
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+ hypervisor {
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+ compatible = "hafnium,hafnium";
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+ vm1 {
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+ is_ffa_partition;
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+ debug_name = "op-tee";
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+ load_address = <0xfd280000>;
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+ vcpu_count = <8>;
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+ mem_size = <0x1980000>; /* 25MB TZC DRAM */
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+ };
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+ vm2 {
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+ is_ffa_partition;
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+ debug_name = "secure-storage";
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+ load_address = <0xfee00000>;
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+ vcpu_count = <1>;
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+ mem_size = <0x200000>; /* 2MB TZC DRAM */
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+ };
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+ vm3 {
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+ is_ffa_partition;
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+ debug_name = "crypto";
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+ load_address = <0xfec00000>;
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+ vcpu_count = <1>;
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+ mem_size = <0x200000>; /* 2MB TZC DRAM */
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+ };
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+ };
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+
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+ cpus {
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+ #address-cells = <0x2>;
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+ #size-cells = <0x0>;
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+
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+ CPU0:cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x0>;
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+ enable-method = "psci";
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+ };
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+
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+ /*
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+ * SPMC (Hafnium) requires secondary cpu nodes are declared in
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+ * descending order
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+ */
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+ CPU7:cpu@700 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x700>;
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+ enable-method = "psci";
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+ };
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+
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+ CPU6:cpu@600 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x600>;
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+ enable-method = "psci";
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+ };
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+
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+ CPU5:cpu@500 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x500>;
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+ enable-method = "psci";
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+ };
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+
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+ CPU4:cpu@400 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x400>;
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+ enable-method = "psci";
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+ };
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+
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+ CPU3:cpu@300 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x300>;
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+ enable-method = "psci";
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+ };
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+
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+ CPU2:cpu@200 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x200>;
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+ enable-method = "psci";
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+ };
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+
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+ CPU1:cpu@100 {
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+ device_type = "cpu";
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+ compatible = "arm,armv8";
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+ reg = <0x0 0x100>;
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+ enable-method = "psci";
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+ };
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+ };
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+
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+ /* 32MB of TC0_TZC_DRAM1_BASE */
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+ memory@fd000000 {
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+ device_type = "memory";
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+ reg = <0x0 0xfd000000 0x2000000>;
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+ };
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+};
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diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
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index de5f95d5e..82c6ccb27 100644
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--- a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
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+++ b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
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@@ -27,6 +27,16 @@
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secure-partitions {
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compatible = "arm,sp";
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+#if TS_SP_FW_CONFIG
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+ secure-storage {
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+ uuid = <0xdc1eef48 0x4ccfb17a 0xcfdf8bac 0x141b71f7>;
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+ load-address = <0xfee00000>;
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+ };
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+ crypto {
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+ uuid = <0xd9df52d5 0x4bb216a2 0x6dd2a49a 0xc0e8843b>;
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+ load-address = <0xfec00000>;
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+ };
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+#endif
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#if OPTEE_SP_FW_CONFIG
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op-tee {
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uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
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--
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2.29.2
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+59
@@ -0,0 +1,59 @@
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From bc31cd2454854ab44aa9861b98f13848c2b474aa Mon Sep 17 00:00:00 2001
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From: Usama Arif <usama.arif@arm.com>
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Date: Tue, 30 Mar 2021 16:39:19 +0100
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Subject: [PATCH 2/2] tc0: update GICR base address
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The number of ITS have changed from 4 to 1, resulting
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in GICR base address change.
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Signed-off-by: Usama Arif <usama.arif@arm.com>
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Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
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Upstream-Status: Pending [Not submitted to upstream yet]
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---
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fdts/tc0.dts | 4 ++--
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plat/arm/board/tc0/include/platform_def.h | 4 ++--
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2 files changed, 4 insertions(+), 4 deletions(-)
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diff --git a/fdts/tc0.dts b/fdts/tc0.dts
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index 2d7611cf2..382860d9d 100644
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--- a/fdts/tc0.dts
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+++ b/fdts/tc0.dts
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (c) 2020, Arm Limited. All rights reserved.
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+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@@ -236,7 +236,7 @@
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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- <0x0 0x30140000 0 0x200000>; /* GICR */
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+ <0x0 0x30080000 0 0x200000>; /* GICR */
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interrupts = <0x1 0x9 0x4>;
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};
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diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h
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index 30b5ab716..b169d7720 100644
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--- a/plat/arm/board/tc0/include/platform_def.h
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+++ b/plat/arm/board/tc0/include/platform_def.h
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (c) 2020, Arm Limited. All rights reserved.
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+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@@ -220,7 +220,7 @@
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/* GIC related constants */
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#define PLAT_ARM_GICD_BASE UL(0x30000000)
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#define PLAT_ARM_GICC_BASE UL(0x2C000000)
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-#define PLAT_ARM_GICR_BASE UL(0x30140000)
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+#define PLAT_ARM_GICR_BASE UL(0x30080000)
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/*
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* PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
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--
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2.29.2
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@@ -3,9 +3,16 @@
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# Intermediate SHA with 2.4 baseline version, required for Theodul DSU
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# --- This SRC_URI will be removed once below SRCREV_tfa gets merged to TF-A master
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SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https;branch=integration;name=tfa"
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SRCREV_tfa = "9bc3007d3bb9363dbd5f6655d2b17d599e22bac4"
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SRCREV_tfa = "8078b5c5a0c2a47710df96412d88df53486e2b29"
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PV = "2.4+git${SRCPV}"
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FILESEXTRAPATHS_prepend_tc0 := "${THISDIR}/files/tc0:"
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SRC_URI_append = " \
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file://0001-product-tc0-Add-support-for-Trusted-Services-Secure-.patch \
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file://0002-tc0-update-GICR-base-address.patch \
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"
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DEPENDS += "scp-firmware"
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COMPATIBLE_MACHINE = "tc0"
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