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arm-bsp/trusted-firmware-a: fix the Corstone-500 system timer issue
This commit applies the TF-A fix allowing to use the right FPGA system timer clock frequency for Corstone-500. Change-Id: Iaa09d33eb76d9b2b74cb3400897c8cc0e3c694db Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Signed-off-by: Ross Burton <ross.burton@arm.com>
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committed by
Ross Burton
parent
39ae13d44e
commit
42b114e5e0
+34
@@ -0,0 +1,34 @@
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Upstream-Status: Backport [e3c152d1156af8a4b6453376454ecdceaf81704c]
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Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
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From e3c152d1156af8a4b6453376454ecdceaf81704c Mon Sep 17 00:00:00 2001
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From: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com>
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Date: Fri, 17 Apr 2020 12:52:19 +0100
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Subject: [PATCH] fdts: a5ds: Fix for the system timer issue.
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A5DS FPGA system timer clock frequency is 7.5Mhz.
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The dt is file updated inline with the hardware
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clock frequency.
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Change-Id: I3f6c2e0d4a7b293175a42cf398a8730448504af9
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Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com>
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---
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fdts/a5ds.dts | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts
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index 7334c4559..c6f5be6fa 100644
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--- a/fdts/a5ds.dts
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+++ b/fdts/a5ds.dts
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@@ -128,7 +128,7 @@
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#size-cells = <1>;
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ranges;
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reg = <0x1a040000 0x1000>;
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- clock-frequency = <50000000>;
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+ clock-frequency = <7500000>;
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frame@1a050000 {
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frame-number = <0>;
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--
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2.17.1
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@@ -12,6 +12,8 @@ SRCREV_tfa = "ecd27ad85f1eba29f6bf92c39dc002c85b07dad5"
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LIC_FILES_CHKSUM += "file://docs/license.rst;md5=189505435dbcdcc8caa63c46fe93fa89"
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SRC_URI += "file://0001-fdts-a5ds-Fix-for-the-system-timer-issue.patch"
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#
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# mbed TLS source
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# Those are used in trusted-firmware-a.inc if TFA_MBEDTLS is set to 1
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