CI: pin to kas 3.2 as 3.2.1 fails

For some reason the kas 3.2.1 container fails: No such file or directory: '/builds/engineering/yocto/meta-arm/ci/ci/base.yml' Note the repeated /ci/, which is wrong. Pin the kas container to 3.2 for now until this is resolved. Signed-off-by: Ross Burton <ross.burton@arm.com>
arm-bsp/juno: move to compressed initramfs image
2026-07-17 16:17:09 +00:00 · 2023-02-19 11:46:04 -05:00 · 2023-01-18 12:42:04 -05:00 · 2022-09-07 09:34:13 -04:00 · 2022-08-08 14:55:23 -04:00 · 2022-08-04 14:08:10 -04:00
284 changed files with 50211 additions and 921 deletions
@@ -0,0 +1 @@
+__pycache__
@@ -1,9 +1,7 @@
-image: ghcr.io/siemens/kas/kas
+image: ghcr.io/siemens/kas/kas:3.2

-# First do a common bootstrap, and then build all the targets
 stages:
  - prep
-  - bootstrap
  - build

 # Common job fragment to get a worker ready
@@ -27,12 +25,13 @@ stages:
    - mkdir --verbose --parents $KAS_WORK_DIR $KAS_REPO_REF_DIR $SSTATE_DIR $DL_DIR $TOOLCHAIN_DIR $TOOLCHAIN_LINK_DIR
    # Must do this here, as it's the only way to make sure the toolchain is installed on the same builder
    - ./ci/get-binary-toolchains $DL_DIR $TOOLCHAIN_DIR $TOOLCHAIN_LINK_DIR
+    - sudo apt update && sudo apt install telnet -y

 # Generalised fragment to do a Kas build
 .build:
  extends: .setup
  script:
-    - KASFILES=$(./ci/jobs-to-kas $CI_JOB_NAME)
+    - KASFILES=$(./ci/jobs-to-kas "$CI_JOB_NAME")
    - kas shell --update --force-checkout $KASFILES -c 'cat conf/*.conf'
    - kas build $KASFILES
    - ./ci/check-warnings $KAS_WORK_DIR/build/warnings.log
@@ -41,7 +40,7 @@ stages:
 .build_and_test:
  extends: .setup
  script:
-    - KASFILES=$(./ci/jobs-to-kas $CI_JOB_NAME)
+    - KASFILES=$(./ci/jobs-to-kas "$CI_JOB_NAME")
    - kas shell --update --force-checkout $KASFILES -c 'cat conf/*.conf'
    - kas build $KASFILES
    - kas build $KASFILES -c testimage
@@ -57,23 +56,10 @@ update-repos:
  script:
    - flock --verbose --timeout 60 $KAS_REPO_REF_DIR ./ci/update-repos

-#
-# Bootstrap stage, bootstrap and machine coverage
-#
-
-# Build a number of native tools first to ensure the other builders don't race
-# over them
-n1sdp/bootstrap:
-  extends: .build
-  stage: bootstrap
-
-n1sdp/clang/clang-bootstrap:
-  extends: .build
-  stage: bootstrap

 # What percentage of machines in the layer do we build
 machine-coverage:
-  stage: bootstrap
+  stage: build
  interruptible: true
  script:
    - ./ci/check-machine-coverage
@@ -82,6 +68,11 @@ machine-coverage:
 #
 # Build stage, the actual build jobs
 #
+# Available options for building are
+#  TOOLCHAINS: [gcc, clang, armgcc, external-gccarm]
+#  TCLIBC: [glibc, musl]
+#  VIRT: [none, xen]
+#  TESTING: testimage

 # Validate layers are Yocto Project Compatible
 check-layers:
@@ -108,14 +99,25 @@ corstone700-fvp:
 corstone700-mps3:
  extends: .build

+corstone1000-fvp:
+  extends: .build
+
+corstone1000-mps3:
+  extends: .build
+
 fvp-base:
  extends: .build
+  parallel:
+    matrix:
+      - TESTING: testimage
+  tags:
+    - x86_64

 fvp-base-arm32:
  extends: .build
-
-fvp-base-arm32/external-gccarm:
-  extends: .build
+  parallel:
+    matrix:
+      - TOOLCHAINS: [gcc, external-gccarm]

 fvp-baser-aemv8r64:
  extends: .build
@@ -125,9 +127,9 @@ fvps:

 gem5-arm64:
  extends: .build
-
-gem5-arm64/xen:
-  extends: .build
+  parallel:
+    matrix:
+      - VIRT: [none, xen]

 gem5-atp-arm64:
  extends: .build
@@ -137,12 +139,15 @@ generic-arm64:

 juno:
  extends: .build
+  parallel:
+    matrix:
+      - TOOLCHAINS: [gcc, clang]

-juno/clang:
-  extends: .build
-
-microbit-v1/testimage-zephyr:
+microbit-v1:
  extends: .build_and_test
+  parallel:
+    matrix:
+      - TESTING: testimage-zephyr

 musca-b1:
  extends: .build
@@ -152,48 +157,49 @@ musca-s1:

 n1sdp:
  extends: .build
-
-n1sdp/armgcc:
-  extends: .build
+  parallel:
+    matrix:
+      - TOOLCHAINS: [gcc, armgcc]

 qemu-cortex-a53:
  extends: .build

-qemu-cortex-m3/testimage-zephyr:
+qemu-cortex-m3:
  extends: .build_and_test
+  parallel:
+    matrix:
+      - TESTING: testimage-zephyr

 qemu-cortex-r5:
  extends: .build

-qemuarm64-sbsa:
+qemuarm64-secureboot:
  extends: .build
+  parallel:
+    matrix:
+      - TOOLCHAINS: [gcc, clang]
+        TCLIBC: [glibc, musl]
+        TESTING: testimage

-qemuarm64-secureboot/testimage:
+qemuarm64:
  extends: .build
+  parallel:
+    matrix:
+      - VIRT: xen

-qemuarm64-secureboot/clang/testimage:
+qemuarm:
  extends: .build
+  parallel:
+    matrix:
+      - TOOLCHAINS: [gcc, clang]
+        TESTING: testimage
+      - VIRT: xen

-qemuarm64-secureboot/clang/musl/testimage:
-  extends: .build
-
-qemuarm64-secureboot/musl/testimage:
-  extends: .build
-
-qemuarm64/xen:
-  extends: .build
-
-qemuarm/clang/testimage:
-  extends: .build
-
-qemuarm/testimage:
-  extends: .build
-
-qemuarm/xen:
-  extends: .build
-
-qemuarmv5/testimage:
+qemuarmv5:
  extends: .build
+  parallel:
+    matrix:
+      - TESTING: testimage

 sgi575:
  extends: .build
@@ -210,54 +216,3 @@ tc1:

 toolchains:
  extends: .build
-
-#
-# Utility tasks, not executed automatically
-#
-
-delete-dl-dir:
-  extends: .setup
-  stage: prep
-  when: manual
-  script:
-    - rm -rf $DL_DIR/*
-
-delete-repo-dir:
-  extends: .setup
-  stage: prep
-  when: manual
-  script:
-    - rm -rf $KAS_REPO_REF_DIR/*
-
-# Delete all sstate
-delete-sstate:
-  extends: .setup
-  stage: prep
-  when: manual
-  script:
-    - rm -rf $SSTATE_DIR/*
-
-delete-toolchains:
-  extends: .setup
-  stage: prep
-  when: manual
-  script:
-    - rm -rf $TOOLCHAIN_DIR/*
-
-# Wipe out old sstate
-prune-sstate:
-  extends: .setup
-  stage: prep
-  when: manual
-  script:
-    - du -h -s $SSTATE_DIR
-    - find $SSTATE_DIR -type f -atime +30 -delete
-    - du -h -s $SSTATE_DIR
-
-# Report on disk usage
-usage:
-  extends: .setup
-  stage: prep
-  when: manual
-  script:
-    - du -h -s $DL_DIR $SSTATE_DIR $KAS_REPO_REF_DIR $TOOLCHAIN_DIR
@@ -37,11 +37,6 @@ local_conf_header:
    PACKAGECONFIG:append:pn-perf = " coresight"
  noptest: |
    DISTRO_FEATURES:remove = "ptest"
-  sstate_mirror: |
-    BB_HASHSERVE_UPSTREAM = "typhoon.yocto.io:8687"
-    BB_HASHSERVE = "auto"
-    BB_SIGNATURE_HANDLER = "OEEquivHash"
-    SSTATE_MIRRORS = "file://.* https://sstate.yoctoproject.org/dev/PATH;downloadfilename=PATH"

 machine: unset

@@ -1,9 +0,0 @@
-header:
-  version: 9
-
-target:
-  - binutils-cross-aarch64
-  - gcc-cross-aarch64
-  - python3-native
-  - opkg-native
-  - rpm-native
@@ -1,10 +0,0 @@
-header:
-  version: 9
-
-target:
-  - binutils-cross-aarch64
-  - clang-cross-aarch64
-  - clang-native
-  - python3-native
-  - opkg-native
-  - rpm-native
@@ -4,7 +4,6 @@ header:
 repos:
  meta-clang:
    url: https://github.com/kraj/meta-clang
-    refspec: master

 local_conf_header:
  clang: |
@@ -0,0 +1,13 @@
+header:
+  version: 9
+  includes:
+    - base.yml
+    - meta-openembedded.yml
+
+local_conf_header:
+    custom-local-conf: |
+        INITRAMFS_IMAGE_BUNDLE = "0"
+        INITRAMFS_IMAGE:remove = "corstone1000-initramfs-image"
+
+machine: corstone1000-fvp
+
@@ -0,0 +1,12 @@
+header:
+  version: 9
+  includes:
+    - base.yml
+    - meta-openembedded.yml
+
+local_conf_header:
+    custom-local-conf: |
+        INITRAMFS_IMAGE_BUNDLE = "0"
+        INITRAMFS_IMAGE:remove = "corstone1000-initramfs-image"
+
+machine: corstone1000-mps3
@@ -5,3 +5,12 @@ header:

 machine: fvp-base

+local_conf_header:
+  testimagefvp: |
+    INHERIT = "fvpboot"
+    # This fails but we can't add to the ignorelist from meta-arm yet
+    # https://bugzilla.yoctoproject.org/show_bug.cgi?id=14604
+    TEST_SUITES:remove = "parselogs"
+    # Tell testimage to connect to localhost:8022, and forward that to SSH in the FVP.
+    TEST_TARGET_IP = "localhost:8022"
+    FVP_CONFIG[bp.virtio_net.hostbridge.userNetPorts] ?= "8022=22"
@@ -1,19 +1,27 @@
 #! /bin/bash

-# Read a GitLab CI job name on $1 and transform it to a
-# list of Kas yaml files
+# This script is expecting an input of machine name, optionally followed by a
+# colon and a list of one or more parameters separated by commas between
+# brackets.  For example, the following are acceptable:
+# corstone500
+# fvp-base: [testimage]
+# qemuarm64-secureboot: [clang, glibc, testimage]
+#
+# Turn this list into a series of yml files separated by colons to pass to kas

 set -e -u

-# Read Job namne from $1 and split on /
-IFS=/ read -r -a PARTS<<<$1
+FILES="ci/$(echo $1 | cut -d ':' -f 1).yml"

-# Prefix each part with ci/
-PARTS=("${PARTS[@]/#/ci/}")
+for i in $(echo $1 | cut -s -d ':' -f 2 | sed 's/[][,]//g'); do
+	# Given that there are no yml files for gcc or glibc, as those are the
+	# defaults, we can simply ignore those parameters.  They are necessary
+	# to pass in so that matrix can correctly setup all of the permutations
+	# of each individual run.
+	if [[ $i == 'none' || $i == 'gcc' || $i == 'glibc' ]]; then
+		continue
+	fi
+	FILES+=":ci/$i.yml"
+done

-# Suffix each part with .yml
-PARTS=("${PARTS[@]/%/.yml}")
-
-# Print colon-separated
-IFS=":"
-echo "${PARTS[*]}"
+echo $FILES
@@ -6,4 +6,3 @@ header:
 repos:
  meta-zephyr:
    url: https://git.yoctoproject.org/git/meta-zephyr
-    refspec: master
@@ -14,3 +14,6 @@ target:
  - core-image-base
  - perf
  - optee-examples
+  - optee-test
+  - optee-spdevkit
+  - optee-os-tadevkit
@@ -0,0 +1,48 @@
+header:
+  version: 11
+
+distro: poky-tiny
+
+defaults:
+  repos:
+    refspec: honister
+
+repos:
+  meta-arm:
+    layers:
+      meta-arm:
+      meta-arm-bsp:
+      meta-arm-toolchain:
+
+  poky:
+    url: https://git.yoctoproject.org/git/poky
+    refspec: b6b0af0889de9da0e4128cef8c9069b770b7d5a0
+    layers:
+      meta:
+      meta-poky:
+      meta-yocto-bsp:
+
+  meta-openembedded:
+    url: https://git.openembedded.org/meta-openembedded
+    refspec: ad52a41de8b4b7d619d1376d0a0090ebcfff56da
+    layers:
+      meta-oe:
+      meta-python:
+
+  meta-arm-image:
+     url: https://git.gitlab.arm.com/arm-reference-solutions/meta-arm-image.git
+     refspec: 9f611833ef58394b707836d69356c4e27d0265fc
+
+local_conf_header:
+  base: |
+    CONF_VERSION = "2"
+    PACKAGE_CLASSES = "package_ipk"
+    LICENSE_FLAGS_WHITELIST += "armcompiler"
+    BB_NUMBER_THREADS ?= "16"
+    PARALLEL_MAKE ?= "-j16"
+    PACKAGECONFIG:append:pn-perf = " coresight"
+
+machine: unset
+
+target:
+  - corstone1000-image
@@ -0,0 +1,23 @@
+header:
+  version: 11
+  includes:
+    - kas/corstone1000-base.yml
+
+repos:
+  run-scripts:
+     url: https://git.gitlab.arm.com/arm-reference-solutions/model-scripts.git
+     refspec: b40b4227fe6b6fc8e4b688db8928f4be76e94eb7
+     layers:
+      .: 'excluded'
+
+machine: corstone1000-fvp
+
+local_conf_header:
+    fvp-config: |
+        # Remove Dropbear SSH as it will not fit into the corstone1000 image.
+        IMAGE_FEATURES:remove = " ssh-server-dropbear"
+        INHERIT = " ${@bb.utils.contains('BUILD_ARCH', 'x86_64', 'fvpboot', '', d)}"
+        LICENSE_FLAGS_WHITELIST:append = " Arm-FVP-EULA"
+
+target:
+  - corstone1000-image
@@ -0,0 +1,6 @@
+header:
+  version: 11
+  includes:
+    - kas/corstone1000-base.yml
+
+machine: corstone1000-mps3
@@ -6,7 +6,7 @@ machine: fvp-baser-aemv8r64

 defaults:
  repos:
-    refspec: master
+    refspec: honister

 repos:
  meta-arm:
@@ -33,7 +33,8 @@ local_conf_header:
    CONF_VERSION = "2"
    PACKAGE_CLASSES = "package_ipk"
    PACKAGECONFIG:remove:pn-qemu-system-native = "gtk+ sdl"
-    EXTRA_IMAGE_FEATURES:append = " debug-tweaks"
+    EXTRA_IMAGE_FEATURES:append = " debug-tweaks ssh-server-openssh"
+    FVP_CONFIG[bp.virtio_net.hostbridge.userNetPorts] ?= "8022=22"
    IMAGE_CLASSES:append = " ${@oe.utils.ifelse(d.getVar('FVP_BASE_R_AEM_TARBALL_URI'), 'fvpboot', '')}"
    LICENSE_FLAGS_WHITELIST:append = " ${@oe.utils.vartrue('FVP_BASE_R_ARM_EULA_ACCEPT', 'Arm-FVP-EULA', '', d)}"

@@ -1,7 +1,7 @@
 header:
  version: 9
  includes:
-    - fvp-baser-aemv8r64-bsp.yml
+    - kas/fvp-baser-aemv8r64-bsp.yml

 local_conf_header:
  base-rt: |
@@ -38,4 +38,14 @@
            /delete-property/ iommu-map;
        };
    };
+
+    /*
+     * Delete module node for Dom0, #size-cells and #address-cells because Grub2
+     * is responsible to create them
+     */
+    chosen {
+        /delete-property/ #size-cells;
+        /delete-property/ #address-cells;
+        /delete-node/ module@0;
+    };
 };
@@ -1,16 +1,13 @@
 / {
    chosen {
+        #size-cells = <0x00000001>;
+        #address-cells = <0x00000001>;
        xen,dom0-bootargs = "###XEN_DOM0_BOOTARGS###";
        xen,xen-bootargs = "###XEN_XEN_BOOTARGS###";

-        modules {
-            #size-cells = <0x00000001>;
-            #address-cells = <0x00000001>;
-
-            module@0 {
-                reg = <###XEN_DOM0_ADDR### ###XEN_DOM0_SIZE###>;
-                compatible = "multiboot,module";
-            };
+        module@0 {
+            reg = <###XEN_DOM0_ADDR### ###XEN_DOM0_SIZE###>;
+            compatible = "multiboot,module";
        };
    };
 };
@@ -13,6 +13,7 @@ LAYERSERIES_COMPAT_meta-arm-bsp = "honister"

 LAYERDEPENDS_meta-arm-bsp = "core meta-arm"
 # This won't be used by layerindex-fetch, but works everywhere else
+LAYERDEPENDS_meta-arm-bsp:append:corstone1000 = " meta-python openembedded-layer"
 LAYERDEPENDS_meta-arm-bsp:append:musca-b1 = " meta-python"
 LAYERDEPENDS_meta-arm-bsp:append:musca-s1 = " meta-python"

@@ -0,0 +1,41 @@
+#@TYPE: Machine
+#@NAME: corstone1000-fvp machine
+#@DESCRIPTION: Machine configuration for Corstone1000 64-bit FVP
+require conf/machine/include/corstone1000.inc
+
+TFA_TARGET_PLATFORM = "fvp"
+
+TFM_PLATFORM_IS_FVP = "TRUE"
+
+# testimage config
+TEST_TARGET = "OEFVPTarget"
+TEST_SUITES = "noop"
+
+# FVP Config
+FVP_PROVIDER ?= "fvp-corstone1000-native"
+FVP_EXE ?= "FVP_Corstone-1000"
+FVP_CONSOLE ?= "host_terminal_0"
+
+# FVP Parameters
+FVP_CONFIG[se.trustedBootROMloader.fname] ?= "${DEPLOY_DIR_IMAGE}/bl1.bin"
+FVP_CONFIG[board.xnvm_size] ?= "64"
+FVP_CONFIG[se.trustedSRAM_config] ?= "6"
+FVP_CONFIG[se.BootROM_config] ?= "3"
+FVP_CONFIG[board.hostbridge.interfaceName] ?= "tap0"
+FVP_CONFIG[board.smsc_91c111.enabled] ?= "1"
+FVP_CONFIG[board.hostbridge.userNetworking] ?= "true"
+FVP_CONFIG[board.hostbridge.userNetPorts] ?= "5555=5555,8080=80,8022=22"
+FVP_CONFIG[board.se_flash_size] ?= "8192"
+FVP_CONFIG[diagnostics] ?= "4"
+FVP_CONFIG[disable_visualisation] ?= "true"
+FVP_CONFIG[se.nvm.update_raw_image] ?= "0"
+
+# Boot image
+FVP_DATA ?= "board.flash0=${DEPLOY_DIR_IMAGE}/${IMAGE_NAME}.rootfs.wic.nopt@0x68100000"
+
+# FVP Terminals
+FVP_TERMINALS[host.host_terminal_0] ?= "Normal World Console"
+FVP_TERMINALS[host.host_terminal_1] ?= "Secure World Console"
+FVP_TERMINALS[se.secenc_terminal] ?= "Secure Enclave Console"
+FVP_TERMINALS[extsys0.extsys_terminal] ?= "Cortex M3"
+
@@ -0,0 +1,9 @@
+#@TYPE: Machine
+#@NAME: corstone1000-mps3 machine
+#@DESCRIPTION: Machine configuration for Corstone1000 64-bit MPS3 FPGA board
+
+require conf/machine/include/corstone1000.inc
+
+TFA_TARGET_PLATFORM = "fpga"
+
+PLATFORM_IS_FVP = "FALSE"
@@ -15,10 +15,14 @@ PREFERRED_VERSION_linux-yocto-rt ?= "5.14%"
 KERNEL_IMAGETYPE = "Image"
 KERNEL_DEVICETREE = "arm/fvp-baser-aemv8r64.dtb"

+UBOOT_MACHINE ?= "vexpress_aemv8r_defconfig"
+
 SERIAL_CONSOLES = "115200;ttyAMA0"

 IMAGE_FSTYPES += "wic"
-WKS_FILE ?= "fvp-base.wks"
+WKS_FILE ?= "efi-disk.wks.in"
+EFI_PROVIDER ?= "grub-efi"
+MACHINE_FEATURES:append = " efi"

 # As this is a virtual target that will not be used in the real world there is
 # no need for real SSH keys.  Disable rng-tools (which takes too long to
@@ -35,7 +39,6 @@ FVP_CONSOLE ?= "terminal_0"
 FVP_CONFIG[bp.virtioblockdevice.image_path] ?= "${DEPLOY_DIR_IMAGE}/${IMAGE_NAME}.rootfs.wic"
 FVP_CONFIG[bp.dram_metadata.init_value] ?= "0"
 FVP_CONFIG[bp.dram_metadata.is_enabled] ?= "true"
-FVP_CONFIG[bp.dram_size] ?= "8"
 FVP_CONFIG[bp.exclusive_monitor.monitor_access_level] ?= "1"
 FVP_CONFIG[bp.pl011_uart0.unbuffered_output] ?= "1"
 FVP_CONFIG[bp.pl011_uart0.untimed_fifos] ?= "true"
@@ -58,4 +61,5 @@ FVP_CONFIG[gic_distributor.has-two-security-states] ?= "0"
 FVP_CONFIG[pctl.startup] ?= "0.0.0.*"
 FVP_CONFIG[bp.virtio_net.enabled] ?= "1"
 FVP_CONFIG[bp.virtio_net.hostbridge.userNetworking] ?= "1"
-FVP_CONFIG[bp.vis.rate_limit-enable] ?= "0"
+FVP_CONFIG[bp.vis.rate_limit-enable] ?= "0"
+FVP_CONFIG[bp.refcounter.use_real_time] ?= "1"
@@ -25,3 +25,5 @@ EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-a u-boot"
 # initialise) and install the pre-generated keys.
 PACKAGECONFIG:remove:pn-openssh = "rng-tools"
 MACHINE_EXTRA_RRECOMMENDS += "ssh-pregen-hostkeys"
+
+TEST_TARGET = "OEFVPTarget"
@@ -0,0 +1,68 @@
+require conf/machine/include/arm/armv8a/tune-cortexa35.inc
+
+MACHINEOVERRIDES =. "corstone1000:"
+
+# TF-A
+TFA_PLATFORM = "corstone1000"
+PREFERRED_VERSION_trusted-firmware-a ?= "2.6%"
+EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-a"
+
+TFA_BL2_BINARY = "bl2-corstone1000.bin"
+TFA_FIP_BINARY = "fip-corstone1000.bin"
+
+# TF-M
+PREFERRED_VERSION_trusted-firmware-m ?= "1.5%"
+TFM_PLATFORM = "arm/corstone1000"
+EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-m"
+
+# TF-M settings for signing host images
+TFA_BL2_RE_IMAGE_LOAD_ADDRESS = "0x62353000"
+TFA_BL2_RE_SIGN_BIN_SIZE = "0x2d000"
+TFA_FIP_RE_IMAGE_LOAD_ADDRESS = "0x68130000"
+TFA_FIP_RE_SIGN_BIN_SIZE = "0x00200000"
+RE_LAYOUT_WRAPPER_VERSION = "0.0.7"
+TFM_SIGN_PRIVATE_KEY = "${S}/bl2/ext/mcuboot/root-RSA-3072_1.pem"
+RE_IMAGE_OFFSET = "0x1000"
+
+# u-boot
+PREFERRED_VERSION_u-boot ?= "2021.07"
+EXTRA_IMAGEDEPENDS += "u-boot"
+
+UBOOT_CONFIG ??= "EFI"
+UBOOT_CONFIG[EFI] = "corstone1000_defconfig"
+UBOOT_ENTRYPOINT  = "0x80000000"
+UBOOT_LOADADDRESS = "0x80000000"
+UBOOT_BOOTARGS = "earlycon=pl011,0x1a510000 console=ttyAMA0 loglevel=9"
+UBOOT_ARCH = "arm"
+UBOOT_EXTLINUX = "0"
+
+# optee
+EXTRA_IMAGEDEPENDS += "optee-os"
+OPTEE_ARCH = "arm64"
+OPTEE_BINARY = "tee-pager_v2.bin"
+
+# Trusted Services(TS)
+EXTRA_IMAGEDEPENDS += "secure-partitions"
+
+# Linux kernel
+PREFERRED_PROVIDER_virtual/kernel:forcevariable = "linux-yocto"
+PREFERRED_VERSION_linux-yocto = "5.10%"
+KERNEL_IMAGETYPE = "Image"
+
+INITRAMFS_IMAGE_BUNDLE ?= "1"
+
+RDEPENDS:${KERNEL_PACKAGE_NAME}-base ?= ""
+
+#telling the build system which image is responsible of the generation of the initramfs rootfs
+INITRAMFS_IMAGE = "corstone1000-initramfs-image"
+
+# enable this feature for kernel debugging
+# MACHINE_FEATURES += "corstone1000_kernel_debug"
+
+# login terminal serial port settings
+SERIAL_CONSOLES ?= "115200;ttyAMA0"
+
+# making sure EXTRA_IMAGEDEPENDS will be used while creating the image
+WKS_FILE_DEPENDS:append = " ${EXTRA_IMAGEDEPENDS}"
+
+WKS_FILE ?= "corstone1000-image.corstone1000.wks"
@@ -10,10 +10,10 @@ require conf/machine/include/arm/arch-armv8a.inc

 MACHINE_FEATURES = "usbhost usbgadget alsa screen wifi bluetooth optee pci"

-KERNEL_IMAGETYPE = "Image"
+KERNEL_IMAGETYPE = "Image.gz"
 KERNEL_DEVICETREE = "arm/juno.dtb arm/juno-r1.dtb arm/juno-r2.dtb"

-IMAGE_FSTYPES += "tar.bz2 ext4"
+IMAGE_FSTYPES += "tar.bz2 ext4 cpio.gz"

 SERIAL_CONSOLES = "115200;ttyAMA0"

@@ -27,3 +27,6 @@ EXTRA_IMAGEDEPENDS += "virtual/trusted-firmware-a u-boot firmware-image-juno"

 # Juno u-boot configuration
 UBOOT_MACHINE = "vexpress_aemv8a_juno_defconfig"
+
+INITRAMFS_IMAGE_BUNDLE ?= "1"
+INITRAMFS_IMAGE = "core-image-minimal"
@@ -28,12 +28,65 @@ where either a standard or Real-Time Linux kernel (PREEMPT\_RT) can be built
 and run:

 - boot-wrapper-aarch64: provides PSCI support
+ - U-Boot: v2021.07 - provides UEFI services
 - Linux kernel: linux-yocto-5.14
 - Linux kernel with PREEMPT\_RT support: linux-yocto-rt-5.14

 Note that the Real-Time Linux kernel (PREEMPT\_RT) does not use the real-time
 architectural extensions of the Armv8-R feature set.

+High-Level Architecture
+-----------------------
+
+The diagram below shows the current boot flow:
+
+    +---------------------------------------------------------------+
+    |                         Linux kernel                          |
+    +---------------------------------------------------------------+
+               /|\                                     /|\
+                |                                       |
+                | UEFI services                         |
+                |                         PSCI services |
+               \|/                                      |
+        +----------------+                              |     S-EL1
+    ----|     U-Boot     |------------------------------|-----------
+        +----------------+                              |     S-EL2
+               /|\                                      |
+                |                                       |
+                |                                       |
+                |                                       |
+    +--------------------------------------------------\|/----------+
+    |                        +----------------+ +----------------+  |
+    |  boot-wrapper-aarch64  |  Device tree   | |  PSCI handler  |  |
+    |                        +----------------+ +----------------+  |
+    +---------------------------------------------------------------+
+
+
+The firmware binary (generated as `linux-system.axf`) includes
+boot-wrapper-aarch64, the flattened device tree and U-Boot. U-Boot is configured
+to automatically detect a virtio block device and boot the UEFI payload at the
+path `/efi/boot/bootaa64.efi`. Using the standard build, the first partition
+contains a Grub image at this path, which boots the Linux kernel at `/Image` on
+the same partition. The second partition of the image contains the Linux root
+file system.
+
+There is no EL3 or non-secure world in the Armv8-R AArch64 architecture, so the
+reset vector starts boot-wrapper-aarch64 at S-EL2. Boot-wrapper-aarch64 is
+compiled with the `--enable-keep-el` flag, which causes it to boot U-Boot at
+S-EL2 too. U-Boot is compiled with the `CONFIG_ARMV8_SWITCH_TO_EL1` flag, which
+causes it to switch to S-EL1 before booting Linux.
+
+The bundled device tree is passed to U-Boot via register x0. U-Boot passes the
+same device tree to Linux via the UEFI system table.
+
+Power state management is provided by PSCI services in boot-wrapper-aarch64.
+Linux accesses the PSCI handler via HVC calls to S-EL2. U-Boot has been patched
+to prevent it from overriding the exception vector at S-EL2. The PSCI handler
+memory region is added to a `/memreserve/` node in the device tree.
+
+Please note that the final firmware architecture for the fvp-baser-aemv8r64 is
+not yet stabilized. The patches in this layer are provided for development and
+evaluation purposes only, and should not be used in production firmware.

 Quick start: Howto Build and Run
 --------------------------------
@@ -44,26 +97,27 @@ Ubuntu 20.04.
 Install the required packages for the build host:
 https://docs.yoctoproject.org/singleindex.html#required-packages-for-the-build-host

-Install the kas setup tool for bitbake based projects:
+Kas is a setup tool for bitbake based projects. The minimal supported version
+is 2.6, install it like so:

-    pip3 install --user kas
+    pip3 install --user --upgrade kas

 For more details on kas, see https://kas.readthedocs.io/.

 To build the images for fvp-base machine, you also need to:

- - download the ``FVP_Base_AEMv8R_11.15_14.tgz`` image AEM V8-R FVP Installer
+ - download the ``FVP_Base_AEMv8R_11.17_21.tgz`` image AEM V8-R FVP Installer
  (Linux) package from Arm's website:
-  https://silver.arm.com/download/download.tm?pv=4858045&p=4029857. You need
+  https://silver.arm.com/download/download.tm?pv=4865959&p=4029857. You need
   to have an account and be logged in to be able to download it
- - set absolute path to the ``FVP_Base_AEMv8R_11.15_14.tgz`` downloaded
+ - set absolute path to the ``FVP_Base_AEMv8R_11.17_21.tgz`` downloaded
   package in ``FVP_BASE_R_AEM_TARBALL_URI``
 - accept EULA in ``FVP_BASE_R_ARM_EULA_ACCEPT``


 The variables should be set like so:

-    FVP_BASE_R_AEM_TARBALL_URI="file:///absolute/path/to/FVP_Base_AEMv8R_11.15_14.tgz"
+    FVP_BASE_R_AEM_TARBALL_URI="file:///absolute/path/to/FVP_Base_AEMv8R_11.17_21.tgz"
    FVP_BASE_R_ARM_EULA_ACCEPT="True"

 **Note:** The host machine should have at least 50 GBytes of free disk space
@@ -81,21 +135,21 @@ Fetch the meta-arm repository into a build directory:

    mkdir -p ~/fvp-baser-aemv8r64-build
    cd ~/fvp-baser-aemv8r64-build
-    git clone https://git.yoctoproject.org/git/meta-arm
+    git clone https://git.yoctoproject.org/git/meta-arm -b honister


 ### Build
 Building with the standard Linux kernel:

    cd ~/fvp-baser-aemv8r64-build
-    export FVP_BASE_R_AEM_TARBALL_URI="file:///absolute/path/to/FVP_Base_AEMv8R_11.15_14.tgz"
+    export FVP_BASE_R_AEM_TARBALL_URI="file:///absolute/path/to/FVP_Base_AEMv8R_11.17_21.tgz"
    export FVP_BASE_R_ARM_EULA_ACCEPT="True"
    kas build meta-arm/kas/fvp-baser-aemv8r64-bsp.yml

 Building with the Real-Time Linux kernel (PREEMPT\_RT):

    cd ~/fvp-baser-aemv8r64-build
-    export FVP_BASE_R_AEM_TARBALL_URI="file:///absolute/path/to/FVP_Base_AEMv8R_11.15_14.tgz"
+    export FVP_BASE_R_AEM_TARBALL_URI="file:///absolute/path/to/FVP_Base_AEMv8R_11.17_21.tgz"
    export FVP_BASE_R_ARM_EULA_ACCEPT="True"
    kas build meta-arm/kas/fvp-baser-aemv8r64-rt-bsp.yml

@@ -117,17 +171,28 @@ To run an image after the build is done with the Real-Time Linux kernel

 **Note:** The terminal console login is `root` without password.

-To finish the fvp emulation, you need to close the telnet session and stop the
-runfvp script:
-
-1. To close the telnet session:
+To finish the fvp emulation, you need to close the telnet session:

 - Escape to telnet console with ``ctrl+]``.
 - Run ``quit`` to close the session.

-2. To stop the runfvp:
+### Networking
+The FVP is configured by default to use "user-mode networking", which simulates
+an IP router and DHCP server to avoid additional host dependencies and
+networking configuration. Outbound connections work automatically, e.g. by
+running:

- - Type ``ctrl+c`` and wait for kas process to finish.
+    wget www.arm.com
+
+Inbound connections require an explicit port mapping from the host. By default,
+port 8022 on the host is mapped to port 22 on the FVP, so that the following
+command will connect to an ssh server running on the FVP:
+
+    ssh root@localhost -p 8022
+
+Note that user-mode networking does not support ICMP, so `ping` will not work.
+For more information about user-mode networking, please see
+https://developer.arm.com/documentation/100964/1117/Introduction-to-Fast-Models/User-mode-networking?lang=en

 ### File sharing between host and fvp
 It is possible to share a directory between the host machine and the fvp using
@@ -141,6 +206,14 @@ launching the model:

    --parameter 'bp.virtiop9device.root_path=/path/to/host-mount-dir'

+e.g. for the standard Linux kernel:
+
+    kas shell --keep-config-unchanged \
+       meta-arm/kas/fvp-baser-aemv8r64-bsp.yml \
+           --command "../layers/meta-arm/scripts/runfvp \
+           --console -- --parameter \
+           'bp.virtiop9device.root_path=/path/to/host-mount-dir'"
+
 Once you are logged into the fvp, the host directory can be mounted in a
 directory on the model using the following command:

@@ -162,16 +235,27 @@ Known Issues and Limitations
 - Only PSCI CPU\_ON and CPU\_OFF functions are supported
 - Linux kernel does not support booting from secure EL2 on Armv8-R AArch64
 - Linux KVM does not support Armv8-R AArch64
+- Device DMA memory cache-coherence issue: the FVP `cache_state_modelled`
+  parameter will affect the cache coherence behavior of peripherals’ DMA. When
+  users set `cache_state_modelled=1`, they also have to set
+  `cci400.force_on_from_start=1` to force the FVP to enable snooping on upstream
+  ports.

 Change Log
 ----------

- Added virtio_net User Networking mode by default and removed instructions
+- Added U-Boot v2021.07 for UEFI support.
+- Updated boot-wrapper-aarch64 revision and added support for booting U-Boot.
+- Included boot-wrapper-aarch64 PSCI services in `/memreserve/` region.
+- Fixed the counter frequency initialization in boot-wrapper-aarch64.
+- Configured the FVP to use the default RAM size of 4 Gb
+- Fixed PL011 and SP805 register sizes in the device tree.
+- Added virtio\_net User Networking mode by default and removed instructions
  about tap networking setup.
 - Updated Linux kernel version from 5.10 to 5.14 for both standard and
  Real-Time (PREEMPT\_RT) builds.
- Enabled SMP support via boot-wrapper-aarch64 providing the PSCI CPU_ON and
-  CPU_OFF functions.
+- Enabled SMP support via boot-wrapper-aarch64 providing the PSCI CPU\_ON and
+  CPU\_OFF functions.
 - Introduced Armv8-R64 compiler flags.
 - Added Linux PREEMPT\_RT support via linux-yocto-rt-5.10.
 - Added support for file sharing with the host machine using Virtio P9.
@@ -2,14 +2,30 @@ COMPATIBLE_MACHINE = "fvp-baser-aemv8r64"

 FILESEXTRAPATHS:prepend := "${THISDIR}/files/${MACHINE}:"
 SRC_URI:append = " \
-    file://0001-Decouple-V2M_SYS-config-by-auto-detect-dtb-node.patch \
-    file://0002-arch64-Introduce-EL2-boot-code-for-v8-r64.patch \
-    file://0003-Allow-enable-psci-to-choose-between-smc-and-hvc.patch \
+    file://0001-aarch64-Rename-labels-and-prepare-for-lower-EL-booti.patch \
+    file://0002-aarch64-Prepare-for-EL1-booting.patch \
+    file://0003-aarch64-Prepare-for-lower-EL-booting.patch \
+    file://0004-gic-v3-Prepare-for-gicv3-with-EL2.patch \
+    file://0005-aarch64-Prepare-for-booting-with-EL2.patch \
+    file://0006-aarch64-Introduce-EL2-boot-code-for-Armv8-R-AArch64.patch \
+    file://0007-Allow-enable-psci-to-choose-between-smc-and-hvc.patch \
+    file://0008-aarch64-Disable-CNTPCT_EL0-trap-for-v8-R64.patch \
+    file://0009-lds-Mark-the-mem-range.patch \
+    file://0010-common-Introduce-the-libfdt.patch \
+    file://0011-common-Add-essential-libc-functions.patch \
+    file://0012-Makefile-Add-the-libfdt-to-the-Makefile-system.patch \
+    file://0013-platform-Add-print_hex-func.patch \
+    file://0014-common-Add-mem-usage-to-memreserve.patch \
+    file://0015-boot-Add-the-enable-keep-el-compile-option.patch \
+    file://0016-Makefile-Change-COUNTER_FREQ-to-100-MHz.patch \
    "

 BOOT_WRAPPER_AARCH64_CMDLINE = "\
 earlycon console=ttyAMA0 loglevel=8 rootfstype=ext4 root=/dev/vda1 rw"

-EXTRA_OECONF += "--enable-psci=hvc"
+EXTRA_OECONF += "--enable-psci=hvc --enable-keep-el"

 TUNE_CCARGS = ""
+
+BOOT_WRAPPER_AARCH64_KERNEL = "u-boot.bin"
+do_deploy[depends] += "u-boot:do_deploy"
@@ -1,67 +0,0 @@
-From 7b8c821c22929cd2d3532f937672fcf05dc7d5d0 Mon Sep 17 00:00:00 2001
-Message-Id: <7b8c821c22929cd2d3532f937672fcf05dc7d5d0.1616744115.git.diego.sueiro@arm.com>
-From: Jaxson Han <jaxson.han@arm.com>
-Date: Thu, 25 Mar 2021 12:35:13 +0800
-Subject: [PATCH 1/2] Decouple V2M_SYS config by auto-detect dtb node
-
-An auto-detect switch is added to make it an option to enable/disable
-'arm,vexpress-sysreg', because not all platforms support this feature.
-
-Issue-ID: SCM-2221
-Signed-off-by: Jaxson Han <jaxson.han@arm.com>
-Change-Id: Ib8738aa62ca3902f7bdae2ad9a5a63aa2d225abf
-
-Upstream-Status: Pending
-Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
---
- Makefile.am | 2 +-
- platform.c  | 4 ++++
- 2 files changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/Makefile.am b/Makefile.am
-index af694b7..e131207 100644
--- a/Makefile.am
-+++ b/Makefile.am
-@@ -19,7 +19,7 @@ NR_CPUS         := $(shell echo $(CPU_IDS) | tr ',' ' ' | wc -w)
- DEFINES		= -DCNTFRQ=$(CNTFRQ)
- DEFINES		+= -DCPU_IDS=$(CPU_IDS)
- DEFINES		+= -DNR_CPUS=$(NR_CPUS)
-DEFINES		+= -DSYSREGS_BASE=$(SYSREGS_BASE)
-+DEFINES		+= $(if $(SYSREGS_BASE), -DSYSREGS_BASE=$(SYSREGS_BASE), )
- DEFINES		+= -DUART_BASE=$(UART_BASE)
- DEFINES		+= -DSTACK_SIZE=256
- 
-diff --git a/platform.c b/platform.c
-index a528a55..d11f568 100644
--- a/platform.c
-+++ b/platform.c
-@@ -23,10 +23,12 @@
- 
- #define PL011(reg)	((void *)UART_BASE + PL011_##reg)
- 
-+#ifdef SYSREGS_BASE
- #define V2M_SYS_CFGDATA		0xa0
- #define V2M_SYS_CFGCTRL		0xa4
- 
- #define V2M_SYS(reg)	((void *)SYSREGS_BASE + V2M_SYS_##reg)
-+#endif
- 
- static void print_string(const char *str)
- {
-@@ -59,6 +61,7 @@ void init_platform(void)
- 
- 	print_string("Boot-wrapper v0.2\r\n\r\n");
- 
-+#ifdef SYSREGS_BASE
- 	/*
- 	 * CLCD output site MB
- 	 */
-@@ -66,4 +69,5 @@ void init_platform(void)
- 	/* START | WRITE | MUXFPGA | SITE_MB */
- 	raw_writel((1 << 31) | (1 << 30) | (7 << 20) | (0 << 16),
- 				V2M_SYS(CFGCTRL));
-+#endif
- }
-- 
-2.17.1
-
@@ -0,0 +1,135 @@
+From 3e7cfbe39a2a053d2a6b0d928cc172ed9d1c6da8 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 25 May 2021 07:25:00 +0100
+Subject: [PATCH] aarch64: Rename labels and prepare for lower EL booting
+
+Prepare for booting from lower EL. Rename *_el3 relavant labels with
+*_el_max and *_no_el3 with *_keep_el. Since the original _no_el3 means
+"We neither do init sequence at this highest EL nor drop to lower EL
+when entering to kernel", we rename it with _keep_el to make it more
+clear for lower EL initialisation.
+
+Upstream-Status: Pending
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+---
+ arch/aarch64/boot.S | 28 ++++++++++++++++++++--------
+ arch/aarch64/psci.S |  9 +++++----
+ arch/aarch64/spin.S |  4 ++--
+ 3 files changed, 27 insertions(+), 14 deletions(-)
+
+diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
+index 27ba449..84e1646 100644
+--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
+@@ -21,18 +21,30 @@ ASM_FUNC(_start)
+ 
+ 	/*
+ 	 * EL3 initialisation
+	 * Boot sequence
+	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
+	 *   lower EL before entering the kernel.
+	 * Else, no initialisation and keep the current EL before
+	 *   entering the kernel.
+ 	 */
+ 	mrs	x0, CurrentEL
+ 	cmp	x0, #CURRENTEL_EL3
+-	b.eq	1f
+	b.eq	el3_init
+ 
+	/*
+	 * We stay in the current EL for entering the kernel
+	 */
+ 	mov	w0, #1
+-	ldr	x1, =flag_no_el3
+	ldr	x1, =flag_keep_el
+ 	str	w0, [x1]
+ 
+-	b	start_no_el3
+	b	start_keep_el
+ 
+-1:	mov	x0, #0x30			// RES1
+	/*
+	 * EL3 initialisation
+	 */
+el3_init:
+	mov	x0, #0x30			// RES1
+ 	orr	x0, x0, #(1 << 0)		// Non-secure EL1
+ 	orr	x0, x0, #(1 << 8)		// HVC enable
+ 
+@@ -124,7 +136,7 @@ ASM_FUNC(_start)
+ 
+ 	bl	gic_secure_init
+ 
+-	b	start_el3
+	b	start_el_max
+ 
+ err_invalid_id:
+ 	b	.
+@@ -151,7 +163,7 @@ ASM_FUNC(jump_kernel)
+ 	bl	find_logical_id
+ 	bl	setup_stack		// Reset stack pointer
+ 
+-	ldr	w0, flag_no_el3
+	ldr	w0, flag_keep_el
+ 	cmp	w0, #0			// Prepare Z flag
+ 
+ 	mov	x0, x20
+@@ -160,7 +172,7 @@ ASM_FUNC(jump_kernel)
+ 	mov	x3, x23
+ 
+ 	b.eq	1f
+-	br	x19			// No EL3
+	br	x19			// Keep current EL
+ 
+ 1:	mov	x4, #SPSR_KERNEL
+ 
+@@ -178,5 +190,5 @@ ASM_FUNC(jump_kernel)
+ 
+ 	.data
+ 	.align 3
+-flag_no_el3:
+flag_keep_el:
+ 	.long 0
+diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S
+index 8bd224b..7b8919a 100644
+--- a/arch/aarch64/psci.S
+++ b/arch/aarch64/psci.S
+@@ -79,7 +79,7 @@ smc_exit:
+ 	ldp	x18, x19, [sp], #16
+ 	eret
+ 
+-ASM_FUNC(start_el3)
+ASM_FUNC(start_el_max)
+ 	ldr	x0, =vector
+ 	bl	setup_vector
+ 
+@@ -89,10 +89,11 @@ ASM_FUNC(start_el3)
+ 	b	psci_first_spin
+ 
+ /*
+- * This PSCI implementation requires EL3. Without EL3 we'll only boot the
+- * primary cpu, all others will be trapped in an infinite loop.
+ * This PSCI implementation requires the highest EL(EL3 or Armv8-R EL2).
+ * Without the highest EL, we'll only boot the primary cpu, all othersr
+ * will be trapped in an infinite loop.
+  */
+-ASM_FUNC(start_no_el3)
+ASM_FUNC(start_keep_el)
+ 	cpuid	x0, x1
+ 	bl	find_logical_id
+ 	cbz	x0, psci_first_spin
+diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S
+index 1ea1c0b..bfb1d47 100644
+--- a/arch/aarch64/spin.S
+++ b/arch/aarch64/spin.S
+@@ -12,8 +12,8 @@
+ 
+ 	.text
+ 
+-ASM_FUNC(start_el3)
+-ASM_FUNC(start_no_el3)
+ASM_FUNC(start_el_max)
+ASM_FUNC(start_keep_el)
+ 	cpuid	x0, x1
+ 	bl	find_logical_id
+ 
@@ -0,0 +1,48 @@
+From 26f9b5354c2de9cc052531096ff92b04c3a3846f Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 25 May 2021 07:25:00 +0100
+Subject: [PATCH] aarch64: Prepare for EL1 booting
+
+When booting from EL1, add a check and skip the init of
+sctlr_el2 in jump_kernel
+
+Upstream-Status: Pending
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/aarch64/boot.S            | 6 +++++-
+ arch/aarch64/include/asm/cpu.h | 1 +
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
+index 84e1646..b589744 100644
+--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
+@@ -156,10 +156,14 @@ ASM_FUNC(jump_kernel)
+ 	ldr	x0, =SCTLR_EL1_KERNEL
+ 	msr	sctlr_el1, x0
+ 
+	mrs	x0, CurrentEL
+	cmp	x0, #CURRENTEL_EL2
+	b.lt	1f
+
+ 	ldr	x0, =SCTLR_EL2_KERNEL
+ 	msr	sctlr_el2, x0
+ 
+-	cpuid	x0, x1
+1:	cpuid	x0, x1
+ 	bl	find_logical_id
+ 	bl	setup_stack		// Reset stack pointer
+ 
+diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
+index 63eb1c3..b1003f4 100644
+--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
+@@ -11,6 +11,7 @@
+ 
+ #define MPIDR_ID_BITS		0xff00ffffff
+ 
+#define CURRENTEL_EL2		(2 << 2)
+ #define CURRENTEL_EL3		(3 << 2)
+ 
+ /*
@@ -1,314 +0,0 @@
-From 81fcc5cc80c9c3c812d92000b9116f6a02ff7e6c Mon Sep 17 00:00:00 2001
-Message-Id: <81fcc5cc80c9c3c812d92000b9116f6a02ff7e6c.1616744115.git.diego.sueiro@arm.com>
-In-Reply-To: <7b8c821c22929cd2d3532f937672fcf05dc7d5d0.1616744115.git.diego.sueiro@arm.com>
-References: <7b8c821c22929cd2d3532f937672fcf05dc7d5d0.1616744115.git.diego.sueiro@arm.com>
-From: Jaxson Han <jaxson.han@arm.com>
-Date: Thu, 25 Mar 2021 12:47:02 +0800
-Subject: [PATCH 2/2] arch64: Introduce EL2 boot code for v8-r64
-
-The v8-r64 boots from EL2 mode. In order to boot linux, EL2 boot mode
-is needed. Because there is no MMU supported for v8-r64 under EL2 mode,
-bootwrapper needs to switch to EL1 mode when jumpping to the kernel.
-
-Some register in gic-v3.h need to be auto-detected.
-
-Issue-ID: SCM-2221
-Signed-off-by: Jaxson Han <jaxson.han@arm.com>
-Change-Id: I52ca3f045f1ab50f32945420144752f396d95193
-
-Upstream-Status: Pending
-Signed-off-by: Diego Sueiro <diego.sueiro@arm.com>
---
- arch/aarch64/boot.S               | 76 +++++++++++++++++++++++++++----
- arch/aarch64/include/asm/cpu.h    |  3 ++
- arch/aarch64/include/asm/gic-v3.h | 23 ++++++++--
- arch/aarch64/psci.S               | 13 +++---
- arch/aarch64/spin.S               |  8 ++--
- arch/aarch64/utils.S              |  8 ++++
- 6 files changed, 110 insertions(+), 21 deletions(-)
-
-diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
-index e47cf59..5c3eb73 100644
--- a/arch/aarch64/boot.S
-+++ b/arch/aarch64/boot.S
-@@ -22,20 +22,30 @@ _start:
- 	bl	setup_stack
- 
- 	/*
-	 * EL3 initialisation
-+	 * Boot sequence
-+	 * If EL3, goto EL3 initialisation
-+	 * If EL2 && id_aa64mmfr0_el1.MSA == 0xf, do Armv8r initialisation
-+	 * Else no initialisation sequence
- 	 */
- 	mrs	x0, CurrentEL
- 	cmp	x0, #CURRENTEL_EL3
-	b.eq	1f
-+	beq	el3_init
-+	cmp	x0, #CURRENTEL_EL2
-+	beq	el2_init
- 
-+no_el_max:
- 	mov	w0, #1
- 	ldr	x1, =flag_no_el3
- 	str	w0, [x1]
- 
- 	bl	setup_stack
-	b	start_no_el3
-+	b	start_no_el_max
- 
-1:	mov	x0, #0x30			// RES1
-+	/*
-+	 * EL3 initialisation
-+	 */
-+el3_init:
-+	mov	x0, #0x30			// RES1
- 	orr	x0, x0, #(1 << 0)		// Non-secure EL1
- 	orr	x0, x0, #(1 << 8)		// HVC enable
- 
-@@ -93,14 +103,54 @@ _start:
- 	mov	x0, #ZCR_EL3_LEN_MASK		// SVE: Enable full vector len
- 	msr	ZCR_EL3, x0			// for EL2.
- 
-1:
-+	mov	w0, #SPSR_KERNEL
-+	ldr	x1, =spsr_to_elx
-+	str	w0, [x1]
-+	b	el_max_init
-+
-+	/*
-+	 * EL2 Armv8r initialisation
-+	 */
-+el2_init:
-+	/* Detect Armv8r */
-+	mrs	x1, id_aa64mmfr0_el1
-+	ubfx	x1, x1, #48, #4			// MSA
-+	cmp	x1, 0xf				// 0xf means Armv8r
-+	bne	no_el_max
-+
-+	mrs	x0, midr_el1
-+	msr	vpidr_el2, x0
-+
-+	mrs	x0, mpidr_el1
-+	msr	vmpidr_el2, x0
-+
-+	mov	x0, #(1 << 31)			// VTCR_MSA: VMSAv8-64 support
-+	msr	vtcr_el2, x0
-+
-+	/* Enable pointer authentication if present */
-+	mrs	x1, id_aa64isar1_el1
-+	ldr	x2, =(((0xff) << 24) | (0xff << 4))
-+	and	x1, x1, x2
-+	cbz	x1, 1f
-+
-+	mrs	x0, hcr_el2
-+	orr	x0, x0, #(1 << 40)		// AP key enable
-+	orr	x0, x0, #(1 << 41)		// AP insn enable
-+	msr	hcr_el2, x0
-+
-+1:	isb
-+	mov	w0, #SPSR_KERNEL_EL1
-+	ldr	x1, =spsr_to_elx
-+	str	w0, [x1]
-+	b	el_max_init
-+
-+el_max_init:
- 	ldr	x0, =CNTFRQ
- 	msr	cntfrq_el0, x0
- 
- 	bl	gic_secure_init
- 
-	b	start_el3
-
-+	b	start_el_max
- err_invalid_id:
- 	b	.
- 
-@@ -137,7 +187,7 @@ jump_kernel:
- 	b.eq	1f
- 	br	x19			// No EL3
- 
-1:	mov	x4, #SPSR_KERNEL
-+1:	ldr	w4, spsr_to_elx
- 
- 	/*
- 	 * If bit 0 of the kernel address is set, we're entering in AArch32
-@@ -145,13 +195,23 @@ jump_kernel:
- 	 */
- 	bfi	x4, x19, #5, #1
- 
-+	mrs	x18, CurrentEL
-+	cmp	x18, #CURRENTEL_EL2
-+	b.eq	1f
-+
- 	msr	elr_el3, x19
- 	msr	spsr_el3, x4
- 	eret
- 
-+1:	msr	elr_el2, x19
-+	msr	spsr_el2, x4
-+	eret
-+
- 	.ltorg
- 
- 	.data
- 	.align 3
- flag_no_el3:
- 	.long 0
-+spsr_to_elx:
-+	.long 0
-diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
-index ccb5397..2b3a0a4 100644
--- a/arch/aarch64/include/asm/cpu.h
-+++ b/arch/aarch64/include/asm/cpu.h
-@@ -11,6 +11,7 @@
- 
- #define MPIDR_ID_BITS		0xff00ffffff
- 
-+#define CURRENTEL_EL2		(2 << 2)
- #define CURRENTEL_EL3		(3 << 2)
- 
- /*
-@@ -24,6 +25,7 @@
- #define SPSR_I			(1 << 7)	/* IRQ masked */
- #define SPSR_F			(1 << 6)	/* FIQ masked */
- #define SPSR_T			(1 << 5)	/* Thumb */
-+#define SPSR_EL1H		(5 << 0)	/* EL1 Handler mode */
- #define SPSR_EL2H		(9 << 0)	/* EL2 Handler mode */
- #define SPSR_HYP		(0x1a << 0)	/* M[3:0] = hyp, M[4] = AArch32 */
- 
-@@ -42,6 +44,7 @@
- #else
- #define SCTLR_EL1_RESET		SCTLR_EL1_RES1
- #define SPSR_KERNEL		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H)
-+#define SPSR_KERNEL_EL1		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H)
- #endif
- 
- #ifndef __ASSEMBLY__
-diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
-index e743c02..f8ddb27 100644
--- a/arch/aarch64/include/asm/gic-v3.h
-+++ b/arch/aarch64/include/asm/gic-v3.h
-@@ -15,21 +15,38 @@
- #define ICC_CTLR_EL3	"S3_6_C12_C12_4"
- #define ICC_PMR_EL1	"S3_0_C4_C6_0"
- 
-+static inline uint32_t current_el(void)
-+{
-+	uint32_t val;
-+
-+	asm volatile ("mrs %0, CurrentEL" : "=r" (val));
-+	return val;
-+}
-+
- static inline uint32_t gic_read_icc_sre(void)
- {
- 	uint32_t val;
-	asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
-+
-+	if(current_el() == CURRENTEL_EL3)
-+		asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
-+	else
-+		asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val));
-+
- 	return val;
- }
- 
- static inline void gic_write_icc_sre(uint32_t val)
- {
-	asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
-+	if(current_el() == CURRENTEL_EL3)
-+		asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
-+	else
-+		asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
- }
- 
- static inline void gic_write_icc_ctlr(uint32_t val)
- {
-	asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
-+	if(current_el() == CURRENTEL_EL3)
-+		asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
- }
- 
- #endif
-diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S
-index 01ebe7d..0681d5e 100644
--- a/arch/aarch64/psci.S
-+++ b/arch/aarch64/psci.S
-@@ -45,8 +45,8 @@ vector:
- 
- 	.text
- 
-	.globl start_no_el3
-	.globl start_el3
-+	.globl start_no_el_max
-+	.globl start_el_max
- 
- err_exception:
- 	b err_exception
-@@ -101,7 +101,7 @@ smc_exit:
- 	eret
- 
- 
-start_el3:
-+start_el_max:
- 	ldr	x0, =vector
- 	bl	setup_vector
- 
-@@ -111,10 +111,11 @@ start_el3:
- 	b	psci_first_spin
- 
- /*
- * This PSCI implementation requires EL3. Without EL3 we'll only boot the
- * primary cpu, all others will be trapped in an infinite loop.
-+ * This PSCI implementation requires EL3 or AArch64-R EL2. Without EL max
-+ * we'll only boot the primary cpu, all others will be trapped in an infinite
-+ * loop.
-  */
-start_no_el3:
-+start_no_el_max:
- 	cpuid	x0, x1
- 	bl	find_logical_id
- 	cbz	x0, psci_first_spin
-diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S
-index 72603cf..fa1d657 100644
--- a/arch/aarch64/spin.S
-+++ b/arch/aarch64/spin.S
-@@ -11,11 +11,11 @@
- 
- 	.text
- 
-	.globl start_no_el3
-	.globl start_el3
-+	.globl start_no_el_max
-+	.globl start_el_max
- 
-start_el3:
-start_no_el3:
-+start_el_max:
-+start_no_el_max:
- 	cpuid	x0, x1
- 	bl	find_logical_id
- 
-diff --git a/arch/aarch64/utils.S b/arch/aarch64/utils.S
-index ae22ea7..2a63fa7 100644
--- a/arch/aarch64/utils.S
-+++ b/arch/aarch64/utils.S
-@@ -41,6 +41,14 @@ find_logical_id:
-  * x0: vector address
-  */
- setup_vector:
-+	mrs	x1, CurrentEL
-+	cmp	x1, #CURRENTEL_EL2
-+	b.eq	1f
-+
- 	msr	VBAR_EL3, x0
- 	isb
- 	ret
-+
-+1:	msr	VBAR_EL2, x0
-+	isb
-+	ret
-- 
-2.17.1
-
@@ -0,0 +1,55 @@
+From ce628de7699dd6401ddf713efaa49872e2733619 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 25 May 2021 07:25:00 +0100
+Subject: [PATCH] aarch64: Prepare for lower EL booting
+
+Save SPSR_KERNEL into spsr_to_elx during el3_init.
+The jump_kernel will load spsr_to_elx into spsr_el3.
+
+This change will make it easier to control whether drop to lower EL
+before jumping to the kernel.
+
+Upstream-Status: Pending
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/aarch64/boot.S | 15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
+index b589744..6b45afc 100644
+--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
+@@ -130,7 +130,16 @@ el3_init:
+ 	mov	x0, #ZCR_EL3_LEN_MASK		// SVE: Enable full vector len
+ 	msr	ZCR_EL3, x0			// for EL2.
+ 
+-1:
+	/*
+	 * Save SPSR_KERNEL into spsr_to_elx.
+	 * The jump_kernel will load spsr_to_elx into spsr_el3
+	 */
+1:	mov	w0, #SPSR_KERNEL
+	ldr	x1, =spsr_to_elx
+	str	w0, [x1]
+	b	el_max_init
+
+el_max_init:
+ 	ldr	x0, =COUNTER_FREQ
+ 	msr	cntfrq_el0, x0
+ 
+@@ -178,7 +187,7 @@ ASM_FUNC(jump_kernel)
+ 	b.eq	1f
+ 	br	x19			// Keep current EL
+ 
+-1:	mov	x4, #SPSR_KERNEL
+1:	ldr	w4, spsr_to_elx
+ 
+ 	/*
+ 	 * If bit 0 of the kernel address is set, we're entering in AArch32
+@@ -196,3 +205,5 @@ ASM_FUNC(jump_kernel)
+ 	.align 3
+ flag_keep_el:
+ 	.long 0
+spsr_to_elx:
+	.long 0
@@ -0,0 +1,105 @@
+From 483d363bf825082b6db6de3c57d169e741861891 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 25 May 2021 07:25:00 +0100
+Subject: [PATCH] gic-v3: Prepare for gicv3 with EL2
+
+This is a preparation for allowing boot-wrapper configuring the gicv3
+with EL2.
+
+When confiuring with EL2, since there is no ICC_CTLR_EL2, the
+ICC_CTLR_EL3 cannot be replaced with ICC_CTLR_EL2 simply.
+See [https://developer.arm.com/documentation/ihi0069/latest/].
+
+As the caller, gic_secure_init expects the ICC_CTLR to be written,
+we change the function into gic_init_icc_ctlr(). In the GIC spec,
+the r/w bits in this register ([6:0]) either affect EL3 IRQ routing
+(not applicable since no EL3), non-secure IRQ handling (not applicable
+since only secure state in Armv8-R aarch64), or are aliased to
+ICC_CTLR_EL1 bits.
+So, based on this, the new gic_init_icc_ctlr() would be:
+When currentEL is EL3, init ICC_CTLR_EL3 as before.
+When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET.
+
+Upstream-Status: Pending
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/aarch32/include/asm/gic-v3.h |  7 +++++++
+ arch/aarch64/include/asm/gic-v3.h | 23 ++++++++++++++++++++---
+ common/gic-v3.c                   |  2 +-
+ 3 files changed, 28 insertions(+), 4 deletions(-)
+
+diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
+index 65f38de..11e7bc7 100644
+--- a/arch/aarch32/include/asm/gic-v3.h
+++ b/arch/aarch32/include/asm/gic-v3.h
+@@ -9,6 +9,8 @@
+ #ifndef __ASM_AARCH32_GICV3_H
+ #define __ASM_AARCH32_GICV3_H
+ 
+#define ICC_CTLR_RESET (0UL)
+
+ static inline void gic_write_icc_sre(uint32_t val)
+ {
+ 	asm volatile ("mcr p15, 6, %0, c12, c12, 5" : : "r" (val));
+@@ -19,4 +21,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
+ 	asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));
+ }
+ 
+static inline void gic_init_icc_ctlr()
+{
+	gic_write_icc_ctlr(ICC_CTLR_RESET);
+}
+
+ #endif
+diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
+index 5b32380..090ab0b 100644
+--- a/arch/aarch64/include/asm/gic-v3.h
+++ b/arch/aarch64/include/asm/gic-v3.h
+@@ -15,14 +15,31 @@
+ #define ICC_CTLR_EL3	"S3_6_C12_C12_4"
+ #define ICC_PMR_EL1	"S3_0_C4_C6_0"
+ 
+#define ICC_CTLR_EL3_RESET     (0UL)
+#define ICC_CTLR_EL1_RESET     (0UL)
+
+static inline uint32_t current_el(void)
+{
+	uint32_t val;
+
+	asm volatile ("mrs %0, CurrentEL" : "=r" (val));
+	return val;
+}
+
+ static inline void gic_write_icc_sre(uint32_t val)
+ {
+-	asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
+	if (current_el() == CURRENTEL_EL3)
+		asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
+	else
+		asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
+ }
+ 
+-static inline void gic_write_icc_ctlr(uint32_t val)
+static inline void gic_init_icc_ctlr()
+ {
+-	asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
+	if (current_el() == CURRENTEL_EL3)
+		asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (ICC_CTLR_EL3_RESET));
+	else
+		asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (ICC_CTLR_EL1_RESET));
+ }
+ 
+ #endif
+diff --git a/common/gic-v3.c b/common/gic-v3.c
+index 6207007..a0fe564 100644
+--- a/common/gic-v3.c
+++ b/common/gic-v3.c
+@@ -117,6 +117,6 @@ void gic_secure_init(void)
+ 	gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE);
+ 	isb();
+ 
+-	gic_write_icc_ctlr(0);
+	gic_init_icc_ctlr();
+ 	isb();
+ }
@@ -0,0 +1,63 @@
+From be814863cdd5f61d9a16eec012d500550053c8c6 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 25 May 2021 07:25:00 +0100
+Subject: [PATCH] aarch64: Prepare for booting with EL2
+
+Prepare for allowing boot-wrapper to be entered in EL2.
+Detect current EL and set the corresponding EL registers.
+
+Upstream-Status: Pending
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/aarch64/boot.S  |  8 ++++++++
+ arch/aarch64/utils.S | 10 +++++++++-
+ 2 files changed, 17 insertions(+), 1 deletion(-)
+
+diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
+index 6b45afc..908764a 100644
+--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
+@@ -195,10 +195,18 @@ ASM_FUNC(jump_kernel)
+ 	 */
+ 	bfi	x4, x19, #5, #1
+ 
+	mrs	x5, CurrentEL
+	cmp	x5, #CURRENTEL_EL2
+	b.eq	1f
+
+ 	msr	elr_el3, x19
+ 	msr	spsr_el3, x4
+ 	eret
+ 
+1:	msr	elr_el2, x19
+	msr	spsr_el2, x4
+	eret
+
+ 	.ltorg
+ 
+ 	.data
+diff --git a/arch/aarch64/utils.S b/arch/aarch64/utils.S
+index 85c7f8a..f02a249 100644
+--- a/arch/aarch64/utils.S
+++ b/arch/aarch64/utils.S
+@@ -34,10 +34,18 @@ ASM_FUNC(find_logical_id)
+ 	ret
+ 
+ /*
+- * Setup EL3 vectors
+ * Setup EL3/EL2 vectors
+  * x0: vector address
+  */
+ ASM_FUNC(setup_vector)
+	mrs	x1, CurrentEL
+	cmp	x1, #CURRENTEL_EL2
+	b.eq    1f
+
+ 	msr	VBAR_EL3, x0
+ 	isb
+ 	ret
+
+1:	msr	VBAR_EL2, x0
+	isb
+	ret
@@ -0,0 +1,182 @@
+From 81df76f8d94cb6c31c01739b078a72bdb8497441 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 25 May 2021 07:25:00 +0100
+Subject: [PATCH] aarch64: Introduce EL2 boot code for Armv8-R AArch64
+
+The Armv8-R AArch64 profile does not support the EL3 exception level.
+The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU
+at EL1, which allows to run off-the-shelf Linux. However EL2 only
+supports a PMSA, which is not supported by Linux, so we need to drop
+into EL1 before entering the kernel.
+
+We add a new err_invalid_arch symbol as a dead loop. If we detect the
+current Armv8-R aarch64 only supports with PMSA, meaning we cannot boot
+Linux anymore, then we jump to err_invalid_arch.
+
+During Armv8-R aarch64 init, to make sure nothing unexpected traps into
+EL2, we auto-detect and config FIEN and EnSCXT in HCR_EL2.
+
+The boot sequence is:
+If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
+  before entering the kernel.
+If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64),
+  if id_aa64mmfr0_el1.MSA_frac == 0x2,
+    then goto Armv8-R AArch64 initialisation and drop to EL1 before
+    entering the kernel.
+  else, which means VMSA unsupported and cannot boot Linux,
+    goto err_invalid_arch (dead loop).
+Else, no initialisation and keep the current EL before entering the
+  kernel.
+
+Upstream-Status: Pending
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+---
+ arch/aarch64/boot.S            | 92 +++++++++++++++++++++++++++++++++-
+ arch/aarch64/include/asm/cpu.h |  2 +
+ 2 files changed, 92 insertions(+), 2 deletions(-)
+
+diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
+index 908764a..def9192 100644
+--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
+@@ -24,16 +24,24 @@ ASM_FUNC(_start)
+ 	 * Boot sequence
+ 	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
+ 	 *   lower EL before entering the kernel.
+	 * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf, then
+	 *   If id_aa64mmfr0_el1.MSA_frac == 0x2, then goto
+	 *     Armv8-R AArch64 initialisation and drop to EL1 before
+	 *     entering the kernel.
+	 *   Else, which means VMSA unsupported and cannot boot Linux,
+	 *     goto err_invalid_arch (dead loop).
+ 	 * Else, no initialisation and keep the current EL before
+ 	 *   entering the kernel.
+ 	 */
+ 	mrs	x0, CurrentEL
+-	cmp	x0, #CURRENTEL_EL3
+-	b.eq	el3_init
+	cmp	x0, #CURRENTEL_EL2
+	bgt	el3_init
+	beq	el2_init
+ 
+ 	/*
+ 	 * We stay in the current EL for entering the kernel
+ 	 */
+keep_el:
+ 	mov	w0, #1
+ 	ldr	x1, =flag_keep_el
+ 	str	w0, [x1]
+@@ -139,6 +147,85 @@ el3_init:
+ 	str	w0, [x1]
+ 	b	el_max_init
+ 
+	/*
+	 * EL2 Armv8-R AArch64 initialisation
+	 */
+el2_init:
+	/* Detect Armv8-R AArch64 */
+	mrs	x1, id_aa64mmfr0_el1
+	/*
+	 * Check MSA, bits [51:48]:
+	 * 0xf means Armv8-R AArch64.
+	 * If not 0xf, proceed in Armv8-A EL2.
+	 */
+	ubfx	x0, x1, #48, #4			// MSA
+	cmp	x0, 0xf
+	bne	keep_el
+	/*
+	 * Check MSA_frac, bits [55:52]:
+	 * 0x2 means EL1&0 translation regime also supports VMSAv8-64.
+	 */
+	ubfx	x0, x1, #52, #4			// MSA_frac
+	cmp	x0, 0x2
+	/*
+	 * If not 0x2, no VMSA, so cannot boot Linux and dead loop.
+	 * Also, since the architecture guarantees that those CPUID
+	 * fields never lose features when the value in a field
+	 * increases, we use blt to cover it.
+	*/
+	blt	err_invalid_arch
+
+	mrs	x0, midr_el1
+	msr	vpidr_el2, x0
+
+	mrs	x0, mpidr_el1
+	msr	vmpidr_el2, x0
+
+	mov	x0, #(1 << 31)			// VTCR_MSA: VMSAv8-64 support
+	msr	vtcr_el2, x0
+
+	/* Init HCR_EL2 */
+	mov	x0, #(1 << 31)			// RES1: Armv8-R aarch64 only
+
+	mrs	x1, id_aa64pfr0_el1
+	ubfx	x2, x1, #56, 4			// ID_AA64PFR0_EL1.CSV2
+	cmp	x2, 0x2
+	b.lt	1f
+	/*
+	 * Disable trap when accessing SCTXNUM_EL0 or SCTXNUM_EL1
+	 * if FEAT_CSV2.
+	 */
+	orr	x0, x0, #(1 << 53)		// HCR_EL2.EnSCXT
+
+1:	ubfx	x2, x1, #28, 4			// ID_AA64PFR0_EL1.RAS
+	cmp	x2, 0x2
+	b.lt	1f
+	/* Disable trap when accessing ERXPFGCDN_EL1 if FEAT_RASv1p1. */
+	orr	x0, x0, #(1 << 47)		// HCR_EL2.FIEN
+
+	/* Enable pointer authentication if present */
+1:	mrs	x1, id_aa64isar1_el1
+	/*
+	 * If ID_AA64ISAR1_EL1.{GPI, GPA, API, APA} == {0000, 0000, 0000, 0000}
+	 *   then HCR_EL2.APK and HCR_EL2.API are RES 0.
+	 * Else
+	 *   set HCR_EL2.APK and HCR_EL2.API.
+	 */
+	ldr	x2, =(((0xff) << 24) | (0xff << 4))
+	and	x1, x1, x2
+	cbz	x1, 1f
+
+	orr	x0, x0, #(1 << 40)		// HCR_EL2.APK
+	orr	x0, x0, #(1 << 41)		// HCR_EL2.API
+
+1:	msr	hcr_el2, x0
+	isb
+
+	mov	w0, #SPSR_KERNEL_EL1
+	ldr	x1, =spsr_to_elx
+	str	w0, [x1]
+	// fall through
+
+ el_max_init:
+ 	ldr	x0, =COUNTER_FREQ
+ 	msr	cntfrq_el0, x0
+@@ -148,6 +235,7 @@ el_max_init:
+ 	b	start_el_max
+ 
+ err_invalid_id:
+err_invalid_arch:
+ 	b	.
+ 
+ 	/*
+diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
+index b1003f4..91f803c 100644
+--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
+@@ -25,6 +25,7 @@
+ #define SPSR_I			(1 << 7)	/* IRQ masked */
+ #define SPSR_F			(1 << 6)	/* FIQ masked */
+ #define SPSR_T			(1 << 5)	/* Thumb */
+#define SPSR_EL1H		(5 << 0)	/* EL1 Handler mode */
+ #define SPSR_EL2H		(9 << 0)	/* EL2 Handler mode */
+ #define SPSR_HYP		(0x1a << 0)	/* M[3:0] = hyp, M[4] = AArch32 */
+ 
+@@ -43,6 +44,7 @@
+ #else
+ #define SCTLR_EL1_KERNEL	SCTLR_EL1_RES1
+ #define SPSR_KERNEL		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H)
+#define SPSR_KERNEL_EL1		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H)
+ #endif
+ 
+ #ifndef __ASSEMBLY__
@@ -1,4 +1,4 @@
-From 5120127e5f767b44a087c741a3438cef1e22ed50 Mon Sep 17 00:00:00 2001
+From f5a31b4f4ea8daaa0d337d5a2322ddb1912083fc Mon Sep 17 00:00:00 2001
 From: Qi Feng <qi.feng@arm.com>
 Date: Wed, 26 May 2021 17:52:01 +0800
 Subject: [PATCH] Allow --enable-psci to choose between smc and hvc
@@ -28,38 +28,47 @@ To use hvc, use --enable-psci=hvc.
 [1]: https://developer.arm.com/documentation/ddi0600/latest/

 Issue-Id: SCM-2654
+Upstream-Status: Pending
 Signed-off-by: Qi Feng <qi.feng@arm.com>
 Change-Id: Ib8afabdad2d98bc37371d165bbb6f1f9b88bfc87

 Upstream-Status: Pending
 Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
 ---
- Makefile.am  |  2 +-
+ Makefile.am  | 10 +++++-----
 configure.ac | 14 +++++++++-----
- 2 files changed, 10 insertions(+), 6 deletions(-)
+ 2 files changed, 14 insertions(+), 10 deletions(-)

 diff --git a/Makefile.am b/Makefile.am
-index ef6b793..a9ddd16 100644
+index f941b07..88a27de 100644
 --- a/Makefile.am
 +++ b/Makefile.am
-@@ -47,7 +47,7 @@ BOOTMETHOD	:= psci.o
- OFILES		+= psci.o
- PSCI_NODE	:= psci {				\
- 			compatible = \"arm,psci\";	\
+@@ -50,11 +50,11 @@ endif
+ if PSCI
+ ARCH_OBJ	+= psci.o
+ COMMON_OBJ	+= psci.o
+-PSCI_NODE	:= psci {				\
+-			compatible = \"arm,psci\";	\
 -			method = \"smc\";		\
-+			method = \"$(PSCI_METHOD)\";	\
- 			cpu_on = <$(PSCI_CPU_ON)>;	\
- 			cpu_off = <$(PSCI_CPU_OFF)>;	\
+-			cpu_on = <$(PSCI_CPU_ON)>;	\
+-			cpu_off = <$(PSCI_CPU_OFF)>;	\
+PSCI_NODE	:= psci {						\
+			compatible = \"arm,psci\";			\
+			method = \"$(PSCI_METHOD)\";			\
+			cpu_on = <$(PSCI_CPU_ON)>;			\
+			cpu_off = <$(PSCI_CPU_OFF)>;			\
 		   };
+ CPU_NODES	:= $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/addpsci.pl $(KERNEL_DTB))
+ else
 diff --git a/configure.ac b/configure.ac
-index 6914eb4..9aab4a1 100644
+index 9e3b722..53e51be 100644
 --- a/configure.ac
 +++ b/configure.ac
@@ -83,13 +83,17 @@ AS_IF([test "x$X_IMAGE" != "x"],
 # Allow a user to pass --enable-psci
 AC_ARG_ENABLE([psci],
- 	AS_HELP_STRING([--enable-psci], [enable the psci boot method]),
-	[USE_PSCI=$enableval])
+ 	AS_HELP_STRING([--disable-psci], [disable the psci boot method]),
+-	[USE_PSCI=$enableval], [USE_PSCI="yes"])
 -AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes"])
 -AS_IF([test "x$USE_PSCI" = "xyes"], [], [USE_PSCI=no])
 -
@@ -68,7 +77,7 @@ index 6914eb4..9aab4a1 100644
 +		yes|smc) USE_PSCI=smc ;;
 +		hvc) USE_PSCI=hvc ;;
 +		*) AC_MSG_ERROR([Bad value "${enableval}" for --enable-psci. Use "smc" or "hvc"]) ;;
-+	esac])
+	esac], [USE_PSCI="yes"])
 +AM_CONDITIONAL([PSCI], [test "x$USE_PSCI" = "xyes" -o "x$USE_PSCI" = "xsmc" -o "x$USE_PSCI" = "xhvc"])
 +
 +AS_IF([test "x$USE_PSCI" = "xno" -a "x$KERNEL_ES" = "x32"],
@@ -78,6 +87,3 @@ index 6914eb4..9aab4a1 100644
 
 # Allow a user to pass --with-initrd
 AC_ARG_WITH([initrd],
-- 
-2.32.0
-
@@ -0,0 +1,48 @@
+From 3f4614e02f0f8d2522510578da2752f8e3511bb3 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Mon, 25 Oct 2021 17:09:13 +0800
+Subject: [PATCH] aarch64: Disable CNTPCT_EL0 trap for v8-R64
+
+To allow EL1 to access CNTPCT_EL0 without traping into EL2, we need to
+set CNTHCTL_EL2.EL1PCTEN to 1.
+
+For v8-R64, the CNTHCTL_EL2 register follows the v8-A architecture.
+However, as described in the v8-A architecture profile, the
+CNTHCTL_EL2's bit assignments are different according to whether the
+FEAT_VHE is implemented.
+
+Since v8-R64 does not support FEAT_VHE, we do not need to detect
+FEAT_VHE. We can simply set CNTHCTL_EL2.EL1PCTEN to 1.
+
+Issue-ID: SCM-3508
+Upstream-Status: Inappropriate [other]
+  Temporary patch
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Change-Id: I4147e66341c8153312021e6f2ab67d0037246da1
+---
+ arch/aarch64/boot.S | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
+index def9192..6dbd5cc 100644
+--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
+@@ -219,6 +219,18 @@ el2_init:
+ 	orr	x0, x0, #(1 << 41)		// HCR_EL2.API
+ 
+ 1:	msr	hcr_el2, x0
+
+	/*
+	 * To disable trap when accessing CNTPCT_EL0, we need to set
+	 * CNTHCTL_EL2.EL1PCTEN to 1. However, the CNTHCTL_EL2 bit assignments
+	 * are different according to whether the FEAT_VHE is implemented.
+	 *
+	 * For Armv8-R AArch64, FEAT_VHE is not supported, so we do not need to
+	 * detect FEAT_VHE(ID_AA64MMFR1_EL1.VH) and simply set
+	 * CNTHCTL_EL2.EL1PCTEN to 1.
+	 */
+	mov	x0, #1				// CNTHCTL_EL2.EL1PCTEN
+	msr	cnthctl_el2, x0
+ 	isb
+ 
+ 	mov	w0, #SPSR_KERNEL_EL1
@@ -0,0 +1,38 @@
+From 2851f0e6c1216894b9498d7b91256bb1ef49e544 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 2 Nov 2021 15:10:28 +0800
+Subject: [PATCH] lds: Mark the mem range
+
+Add firmware_start and firmware_end, so that we can use them to
+calculate the mem range of boot-wrapper and then set the range to
+/memreserve/ of dtb.
+
+Issue-ID: SCM-3815
+Upstream-Status: Inappropriate [other]
+  Temporary patch
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Change-Id: Idc5a2894e193c75381049a0f359b4b2a51c567ee
+---
+ model.lds.S | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/model.lds.S b/model.lds.S
+index d4e7e13..ab98ddf 100644
+--- a/model.lds.S
+++ b/model.lds.S
+@@ -64,6 +64,7 @@ SECTIONS
+ #endif
+ 
+ 	.boot PHYS_OFFSET: {
+		PROVIDE(firmware_start = .);
+ 		*(.init)
+ 		*(.text*)
+ 		*(.data* .rodata* .bss* COMMON)
+@@ -76,6 +77,7 @@ SECTIONS
+ 		mbox = .;
+ 		QUAD(0x0)
+ 	}
+	PROVIDE(firmware_end = .);
+ 
+ 	ASSERT(etext <= (PHYS_OFFSET + TEXT_LIMIT), ".text overflow!")
+ }
@@ -0,0 +1,101 @@
+From 0f2c7ca446063be6b193fbf870d38c0af19e15c5 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 28 Dec 2021 17:28:25 +0800
+Subject: [PATCH] common: Add essential libc functions
+
+The libfdt uses some of the libc functions, e.g. memcmp, memmove,
+strlen .etc. Add them in lib.c.
+
+The code is copied from TF-A (v2.5) [1] project, which is under the
+terms of BSD license. It is the same with boot-wrapper.
+
+[1]: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+
+Issue-Id: SCM-3814
+Upstream-Status: Inappropriate [other]
+  Temporary patch
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Change-Id: If3b55b00afa8694c7522df989a41e0b38eda1d38
+---
+ common/lib.c | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 70 insertions(+), 1 deletion(-)
+
+diff --git a/common/lib.c b/common/lib.c
+index fcf5f69..0be1c4a 100644
+--- a/common/lib.c
+++ b/common/lib.c
+@@ -32,4 +32,73 @@ void *memset(void *s, int c, size_t n)
+ 	return s;
+ }
+ 
+-/* TODO: memmove and memcmp could also be called */
+int memcmp(const void *s1, const void *s2, size_t len)
+{
+	const unsigned char *s = s1;
+	const unsigned char *d = s2;
+	unsigned char sc;
+	unsigned char dc;
+
+	while (len--) {
+		sc = *s++;
+		dc = *d++;
+		if (sc - dc)
+			return (sc - dc);
+	}
+
+	return 0;
+}
+
+void *memmove(void *dst, const void *src, size_t len)
+{
+	if ((size_t)dst - (size_t)src >= len) {
+		/* destination not in source data, so can safely use memcpy */
+		return memcpy(dst, src, len);
+	} else {
+		/* copy backwards... */
+		const char *end = dst;
+		const char *s = (const char *)src + len;
+		char *d = (char *)dst + len;
+		while (d != end)
+			*--d = *--s;
+	}
+	return dst;
+}
+
+void *memchr(const void *src, int c, size_t len)
+{
+	const unsigned char *s = src;
+
+	while (len--) {
+		if (*s == (unsigned char)c)
+			return (void *) s;
+		s++;
+	}
+
+	return NULL;
+}
+
+char *strrchr(const char *p, int ch)
+{
+	char *save;
+	char c;
+
+	c = ch;
+	for (save = NULL;; ++p) {
+		if (*p == c)
+			save = (char *)p;
+		if (*p == '\0')
+			return (save);
+	}
+	/* NOTREACHED */
+}
+
+size_t strlen(const char *s)
+{
+	const char *cursor = s;
+
+	while (*cursor)
+		cursor++;
+
+	return cursor - s;
+}
@@ -0,0 +1,61 @@
+From de5d2b6c200ae5dd8113751e58bf7cf5844eec5a Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 28 Dec 2021 17:42:48 +0800
+Subject: [PATCH] Makefile: Add the libfdt to the Makefile system
+
+Add the libfdt into Makefile system. The libfdt uses const value and
+thus gcc will enable the stack guard. The stack guard will fail the
+compile. Add -fno-stack-protector to fix it.
+
+Issue-Id: SCM-3814
+Upstream-Status: Inappropriate [other]
+  Temporary patch
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Change-Id: I472bc28cdc5cde3b22461a4b7d7a3752ae382b4b
+---
+ Makefile.am | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/Makefile.am b/Makefile.am
+index 88a27de..5e8668a 100644
+--- a/Makefile.am
+++ b/Makefile.am
+@@ -36,6 +36,9 @@ PSCI_CPU_OFF	:= 0x84000002
+ COMMON_SRC	:= common/
+ COMMON_OBJ	:= boot.o bakery_lock.o platform.o lib.o
+ 
+LIBFDT_SRC	:= common/libfdt/
+LIBFDT_OBJS	:= fdt.o fdt_ro.o fdt_rw.o
+
+ ARCH_OBJ	:= boot.o stack.o utils.o
+ 
+ if BOOTWRAPPER_32
+@@ -125,11 +128,12 @@ CHOSEN_NODE	:= chosen {						\
+ CPPFLAGS	+= $(INITRD_FLAGS)
+ CFLAGS		+= -I$(top_srcdir)/include/ -I$(top_srcdir)/$(ARCH_SRC)/include/
+ CFLAGS		+= -Wall -fomit-frame-pointer
+CFLAGS 		+= -fno-stack-protector
+ CFLAGS		+= -ffunction-sections -fdata-sections
+ CFLAGS		+= -fno-pic -fno-pie
+ LDFLAGS		+= --gc-sections
+ 
+-OBJ		:= $(addprefix $(ARCH_SRC),$(ARCH_OBJ)) $(addprefix $(COMMON_SRC),$(COMMON_OBJ))
+OBJ		:= $(addprefix $(ARCH_SRC),$(ARCH_OBJ)) $(addprefix $(COMMON_SRC),$(COMMON_OBJ)) $(addprefix $(LIBFDT_SRC),$(LIBFDT_OBJS))
+ 
+ # Don't lookup all prerequisites in $(top_srcdir), only the source files. When
+ # building outside the source tree $(ARCH_SRC) needs to be created.
+@@ -150,10 +154,13 @@ $(ARCH_SRC):
+ $(COMMON_SRC):
+ 	$(MKDIR_P) $@
+ 
+$(LIBFDT_SRC):
+	$(MKDIR_P) $@
+
+ %.o: %.S Makefile | $(ARCH_SRC)
+ 	$(CC) $(CPPFLAGS) -D__ASSEMBLY__ $(CFLAGS) $(DEFINES) -c -o $@ $<
+ 
+-%.o: %.c Makefile | $(COMMON_SRC)
+%.o: %.c Makefile | $(COMMON_SRC) $(LIBFDT_SRC)
+ 	$(CC) $(CPPFLAGS) $(CFLAGS) $(DEFINES) -c -o $@ $<
+ 
+ model.lds: $(LD_SCRIPT) Makefile
@@ -0,0 +1,67 @@
+From 5b8cb5192dbd0332e027e8999c3afe4433983291 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Wed, 29 Dec 2021 10:50:21 +0800
+Subject: [PATCH] platform: Add print_hex func
+
+Refine the print functions, and add a new print_hex func to print hex
+numbers.
+
+Issue-Id: SCM-3814
+Upstream-Status: Inappropriate [other]
+  Temporary patch
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Change-Id: Ic960345d9ef0b41d81d30c4a4dbd9c31139907c4
+---
+ common/platform.c | 33 +++++++++++++++++++++++++--------
+ 1 file changed, 25 insertions(+), 8 deletions(-)
+
+diff --git a/common/platform.c b/common/platform.c
+index d11f568..8269392 100644
+--- a/common/platform.c
+++ b/common/platform.c
+@@ -30,20 +30,37 @@
+ #define V2M_SYS(reg)	((void *)SYSREGS_BASE + V2M_SYS_##reg)
+ #endif
+ 
+-static void print_string(const char *str)
+static void print_char(const char c)
+ {
+ 	uint32_t flags;
+	do {
+		flags = raw_readl(PL011(UARTFR));
+	} while (flags & PL011_UARTFR_FIFO_FULL);
+ 
+	raw_writel(c, PL011(UARTDR));
+
+	do {
+		flags = raw_readl(PL011(UARTFR));
+	} while (flags & PL011_UARTFR_BUSY);
+}
+
+void print_string(const char *str)
+{
+ 	while (*str) {
+-		do
+-			flags = raw_readl(PL011(UARTFR));
+-		while (flags & PL011_UARTFR_FIFO_FULL);
+		print_char(*str++);
+	}
+}
+ 
+-		raw_writel(*str++, PL011(UARTDR));
+#define HEX_CHARS_PER_INT (2 * sizeof(int))
+
+void print_hex(unsigned int val)
+{
+ 
+-		do
+-			flags = raw_readl(PL011(UARTFR));
+-		while (flags & PL011_UARTFR_BUSY);
+	const char hex_chars[16] = "0123456789abcdef";
+	int i;
+	for (i = HEX_CHARS_PER_INT - 1; i >= 0; i--) {
+		int v = (val >> (4 * i)) & 0xf;
+		print_char(hex_chars[v]);
+ 	}
+ }
+ 
@@ -0,0 +1,96 @@
+From b447242cd2457bec20d47fe6a8a5758d97a3bde3 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Wed, 19 Jan 2022 16:19:02 +0800
+Subject: [PATCH] common: Add mem usage to /memreserve/
+
+Set /memreserve/ to prevent next boot stages from overrding PSCI
+services with libfdt.
+
+Issue-Id: SCM-3815
+Upstream-Status: Inappropriate [other]
+  Temporary patch
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Change-Id: I2ea80cdf736a910fa2c3deb622e21d50f04be960
+---
+ Makefile.am          |  2 +-
+ common/boot.c        |  1 +
+ common/device_tree.c | 34 ++++++++++++++++++++++++++++++++++
+ include/boot.h       |  1 +
+ 4 files changed, 37 insertions(+), 1 deletion(-)
+ create mode 100644 common/device_tree.c
+
+diff --git a/Makefile.am b/Makefile.am
+index 5e8668a..734de92 100644
+--- a/Makefile.am
+++ b/Makefile.am
+@@ -34,7 +34,7 @@ endif
+ PSCI_CPU_OFF	:= 0x84000002
+ 
+ COMMON_SRC	:= common/
+-COMMON_OBJ	:= boot.o bakery_lock.o platform.o lib.o
+COMMON_OBJ	:= boot.o bakery_lock.o platform.o lib.o device_tree.o
+ 
+ LIBFDT_SRC	:= common/libfdt/
+ LIBFDT_OBJS	:= fdt.o fdt_ro.o fdt_rw.o
+diff --git a/common/boot.c b/common/boot.c
+index c74d34c..ee2bea0 100644
+--- a/common/boot.c
+++ b/common/boot.c
+@@ -63,6 +63,7 @@ void __noreturn first_spin(unsigned int cpu, unsigned long *mbox,
+ {
+ 	if (cpu == 0) {
+ 		init_platform();
+		dt_add_memreserve();
+ 
+ 		*mbox = (unsigned long)&entrypoint;
+ 		sevl();
+diff --git a/common/device_tree.c b/common/device_tree.c
+new file mode 100644
+index 0000000..4d0876c
+--- /dev/null
+++ b/common/device_tree.c
+@@ -0,0 +1,34 @@
+/*
+ * device_tree.c - Basic device tree node handler
+ *
+ * Copyright (C) 2021 ARM Limited. All rights reserved.
+ *
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE.txt file.
+ */
+#include <libfdt.h>
+
+extern unsigned long dtb;
+extern char firmware_start[], firmware_end[];
+
+extern void print_string(const char *str);
+
+static void *blob;
+
+
+void dt_add_memreserve(void)
+{
+	int ret;
+
+	blob = (void*)&dtb;
+	print_string("Add /memreserve/\n\r");
+
+	fdt_open_into(blob, blob, fdt_totalsize(blob) +
+		      sizeof(struct fdt_reserve_entry));
+	ret = fdt_add_mem_rsv(blob, (uint64_t)firmware_start,
+			      (uint64_t)(firmware_end - firmware_start));
+
+	if(ret < 0) {
+		print_string("reserve mem add err\n\r");
+	}
+}
+diff --git a/include/boot.h b/include/boot.h
+index d75e013..c3e2ec1 100644
+--- a/include/boot.h
+++ b/include/boot.h
+@@ -16,4 +16,5 @@ void __noreturn spin(unsigned long *mbox, unsigned long invalid, int is_entry);
+ void __noreturn first_spin(unsigned int cpu, unsigned long *mbox,
+ 			   unsigned long invalid_addr);
+ 
+void dt_add_memreserve(void);
+ #endif
@@ -0,0 +1,102 @@
+From 8271c21bcff260295203214b7b8c87cdb8236453 Mon Sep 17 00:00:00 2001
+From: Jaxson Han <jaxson.han@arm.com>
+Date: Tue, 4 Jan 2022 17:01:55 +0800
+Subject: [PATCH] boot: Add the --enable-keep-el compile option
+
+Add --enable-keep-el compile option to enable boot-wrapper booting next
+stage at EL2.
+The Armv8R AArch64 boots at EL2. If the next stage requires EL2 booting,
+the boot-wrapper should not drop to EL1.
+Currently, this option only works for Armv8R AArch64. Also, to work with
+Linux PSCI, this option will cause secondary cores booting at EL1.
+
+Issue-Id: SCM-3813
+Upstream-Status: Inappropriate [other]
+  Temporary patch
+Signed-off-by: Jaxson Han <jaxson.han@arm.com>
+Change-Id: I3ba9c87cf0b59d163ca433f74c9e3a46e5ca2c63
+---
+ Makefile.am         | 4 ++++
+ arch/aarch64/boot.S | 6 +++++-
+ common/psci.c       | 6 ++++++
+ configure.ac        | 5 +++++
+ 4 files changed, 20 insertions(+), 1 deletion(-)
+
+diff --git a/Makefile.am b/Makefile.am
+index 734de92..054becd 100644
+--- a/Makefile.am
+++ b/Makefile.am
+@@ -33,6 +33,10 @@ PSCI_CPU_ON	:= 0xc4000003
+ endif
+ PSCI_CPU_OFF	:= 0x84000002
+ 
+if KEEP_EL
+DEFINES		+= -DKEEP_EL
+endif
+
+ COMMON_SRC	:= common/
+ COMMON_OBJ	:= boot.o bakery_lock.o platform.o lib.o device_tree.o
+ 
+diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
+index 6dbd5cc..157c097 100644
+--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
+@@ -233,7 +233,11 @@ el2_init:
+ 	msr	cnthctl_el2, x0
+ 	isb
+ 
+#ifdef KEEP_EL
+	mov	w0, #SPSR_KERNEL
+#else
+ 	mov	w0, #SPSR_KERNEL_EL1
+#endif
+ 	ldr	x1, =spsr_to_elx
+ 	str	w0, [x1]
+ 	// fall through
+@@ -313,5 +317,5 @@ ASM_FUNC(jump_kernel)
+ 	.align 3
+ flag_keep_el:
+ 	.long 0
+-spsr_to_elx:
+ASM_DATA(spsr_to_elx)
+ 	.long 0
+diff --git a/common/psci.c b/common/psci.c
+index a0e8700..945780b 100644
+--- a/common/psci.c
+++ b/common/psci.c
+@@ -18,6 +18,8 @@
+ #error "No MPIDRs provided"
+ #endif
+ 
+extern unsigned int spsr_to_elx;
+
+ static unsigned long branch_table[NR_CPUS];
+ 
+ bakery_ticket_t branch_table_lock[NR_CPUS];
+@@ -44,6 +46,10 @@ static int psci_cpu_on(unsigned long target_mpidr, unsigned long address)
+ 	ret = psci_store_address(cpu, address);
+ 	bakery_unlock(branch_table_lock, this_cpu);
+ 
+#ifdef KEEP_EL
+	spsr_to_elx = SPSR_KERNEL_EL1;
+#endif
+
+ 	return ret;
+ }
+ 
+diff --git a/configure.ac b/configure.ac
+index 53e51be..0e07db3 100644
+--- a/configure.ac
+++ b/configure.ac
+@@ -25,6 +25,11 @@ AS_IF([test "x$BOOTWRAPPER_ES" = x32 -a "x$KERNEL_ES" != x32],
+ 	[AC_MSG_ERROR([a 32-bit boot-wrapper cannot launch a 64-bit kernel])]
+ )
+ 
+AC_ARG_ENABLE([keep-el],
+	AC_HELP_STRING([--enable-keep-el], [keep exception level when start kernel]),
+	[KEEP_EL=yes], [KEEP_EL=no])
+AM_CONDITIONAL([KEEP_EL], [test "x$KEEP_EL" = xyes])
+
+ # Allow a user to pass --with-kernel-dir
+ AC_ARG_WITH([kernel-dir],
+ 	AS_HELP_STRING([--with-kernel-dir], [specify the root Linux kernel build directory (required)]),
@@ -0,0 +1,34 @@
+From dd3e3f414d0e6ed1643c2e2ccac676b7fc1dc7a9 Mon Sep 17 00:00:00 2001
+From: Peter Hoyes <Peter.Hoyes@arm.com>
+Date: Tue, 1 Feb 2022 11:28:46 +0000
+Subject: [PATCH] Makefile: Change COUNTER_FREQ to 100 MHz
+
+Older Arm Fast Models (AEM < RevC) had a base frequency of 24 MHz. but
+the RevC base models use 100 MHz. There is not a robust method of
+determining the configured base frequency at runtime, so update
+COUNTER_FREQ to be 100 MHz.
+
+Issue-Id: SCM-3871
+Upstream-Status: Pending
+Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
+Change-Id: Ia9ad0f8ee488d1a887791f1fa1d8f3bf9c5887fd
+---
+ Makefile.am | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/Makefile.am b/Makefile.am
+index 40bc5d6..b48173c 100644
+--- a/Makefile.am
+++ b/Makefile.am
+@@ -13,7 +13,7 @@ SCRIPT_DIR	:= $(top_srcdir)/scripts
+ PHYS_OFFSET	:= $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findmem.pl $(KERNEL_DTB))
+ UART_BASE	:= $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,pl011')
+ SYSREGS_BASE	:= $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,vexpress-sysreg' 2> /dev/null)
+-COUNTER_FREQ	:= 24000000
+COUNTER_FREQ	:= 100000000
+ 
+ CPU_IDS		:= $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findcpuids.pl $(KERNEL_DTB))
+ NR_CPUS         := $(shell echo $(CPU_IDS) | tr ',' ' ' | wc -w)
+-- 
+2.25.1
+
@@ -62,7 +62,7 @@ do_deploy() {
    done

    if [ "${INITRAMFS_IMAGE_BUNDLE}" -eq 1 ]; then
-        cp -L -f ${DEPLOY_DIR_IMAGE}/Image-initramfs-juno.bin \
+        cp -L -f ${DEPLOY_DIR_IMAGE}/Image.gz-initramfs-juno.bin \
            ${D}/${UNPACK_DIR}/SOFTWARE/Image
    else
        cp -L -f ${DEPLOY_DIR_IMAGE}/Image ${D}/${UNPACK_DIR}/SOFTWARE/
@@ -0,0 +1,52 @@
+# Corstone1000 64-bit machines specific TFA support
+
+COMPATIBLE_MACHINE = "(corstone1000)"
+
+SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https;name=tfa"
+
+# TF-A master branch with all Corstone1000 patches merged
+SRCREV_tfa = "459b24451a0829460783ce8dfa15561e36d901d8"
+PV .= "+git${SRCREV_tfa}"
+
+LIC_FILES_CHKSUM="file://docs/license.rst;md5=b2c740efedc159745b9b31f88ff03dde file://mbedtls/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57"
+
+FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:"
+SRCREV_tfa = "cf89fd57ed3286d7842eef41cd72a3977eb6d317"
+PV = "2.6+git${SRCPV}"
+
+SRC_URI:remove = " \
+     file://ssl.patch \
+     "  
+
+TFA_DEBUG = "1"
+TFA_UBOOT = "1"
+TFA_MBEDTLS = "1"
+TFA_BUILD_TARGET = "bl2 bl31 fip"
+
+# Enabling Secure-EL1 Payload Dispatcher (SPD)
+TFA_SPD = "spmd"
+# Cortex-A35 supports Armv8.0-A (no S-EL2 execution state).
+# So, the SPD SPMC component should run at the S-EL1 execution state
+TFA_SPMD_SPM_AT_SEL2 = "0"
+
+# BL2 loads BL32 (optee). So, optee needs to be built first:
+DEPENDS += "optee-os"
+
+EXTRA_OEMAKE:append = " \
+                        ARCH=aarch64 \
+                        TARGET_PLATFORM=${TFA_TARGET_PLATFORM} \
+                        ENABLE_STACK_PROTECTOR=strong \
+                        ENABLE_PIE=1 \
+                        BL2_AT_EL3=1 \
+                        CREATE_KEYS=1 \
+                        GENERATE_COT=1 \
+                        TRUSTED_BOARD_BOOT=1 \
+                        COT=tbbr \
+                        ARM_ROTPK_LOCATION=devel_rsa  \
+                        ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
+                        BL32=${RECIPE_SYSROOT}/lib/firmware/tee-pager_v2.bin \
+                        LOG_LEVEL=50 \
+                        "
+
+# trigger TF-M build so TF-A binaries get signed
+do_deploy[depends]+= "virtual/trusted-firmware-m:do_prepare_recipe_sysroot"
@@ -3,6 +3,7 @@
 MACHINE_TFA_REQUIRE ?= ""
 MACHINE_TFA_REQUIRE:corstone500 = "trusted-firmware-a-corstone500.inc"
 MACHINE_TFA_REQUIRE:corstone700 = "trusted-firmware-a-corstone700.inc"
+MACHINE_TFA_REQUIRE:corstone1000 = "trusted-firmware-a-corstone1000.inc"
 MACHINE_TFA_REQUIRE:fvp-base = "trusted-firmware-a-fvp.inc"
 MACHINE_TFA_REQUIRE:fvp-base-arm32 = "trusted-firmware-a-fvp-arm32.inc"
 MACHINE_TFA_REQUIRE:juno = "trusted-firmware-a-juno.inc"
@@ -0,0 +1,33 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From beb8a8d92537b9574717f0a9a914642c15b439b1 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Wed, 29 Sep 2021 04:58:59 +0100
+Subject: [PATCH 01/15] corstone1000: disable secure debug temporarily
+
+Until ARM-DS is ready to use psa-adac secure debug protocol,
+disable the secure debug in the platform. At present, the
+secure debug integration is tested with the PyOCD based
+scripts.
+
+Change-Id: I3dd0f20e5714a2db69425607d9404172ce52129e
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ platform/ext/target/arm/corstone1000/config.cmake | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
+index dc12d27f9c..203e6b79a6 100644
+--- a/platform/ext/target/arm/corstone1000/config.cmake
+++ b/platform/ext/target/arm/corstone1000/config.cmake
+@@ -37,5 +37,5 @@ set(OPENAMP_VERSION                     "33037b04e0732e58fc0fa36afc244999ef632e1
+ if (${PLATFORM_IS_FVP})
+     set(PLATFORM_PSA_ADAC_SECURE_DEBUG      FALSE        CACHE BOOL      "Whether to use psa-adac secure debug.")
+ else()
+-    set(PLATFORM_PSA_ADAC_SECURE_DEBUG      TRUE        CACHE BOOL      "Whether to use psa-adac secure debug.")
+    set(PLATFORM_PSA_ADAC_SECURE_DEBUG      FALSE        CACHE BOOL      "Whether to use psa-adac secure debug.")
+ endif()
+-- 
+2.17.1
+
@@ -0,0 +1,470 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 8e2b5cee153763dd35bba1bff3568e2e3c6f58d3 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Fri, 1 Oct 2021 14:20:55 +0100
+Subject: [PATCH 02/15] corstone1000: provision firmware update metadata (fwu)
+
+Firmware update metadata region in the flash is provisioned.
+The metadata is provisioned assuming images are present in
+bank-0.
+
+Change-Id: I2a2274505d80528a3a0cc9211c1c6263415015d8
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../arm/corstone1000/bl1/CMakeLists.txt       |   2 +
+ .../arm/corstone1000/bl1/bl1_boot_hal.c       |  18 +
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 309 ++++++++++++++++++
+ .../corstone1000/fw_update_agent/fwu_agent.h  |  31 ++
+ .../arm/corstone1000/partition/flash_layout.h |  11 +-
+ 5 files changed, 369 insertions(+), 2 deletions(-)
+ create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+ create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+
+diff --git a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+index 0634fed4b8..92a78c1168 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+@@ -238,6 +238,7 @@ target_sources(bl1_main
+         ../Device/Source/system_core_init.c
+         ../Native_Driver/firewall.c
+         ../Native_Driver/uart_pl011_drv.c
+        ../fw_update_agent/fwu_agent.c
+         bl1_boot_hal.c
+         bl1_flash_map.c
+         bl1_security_cnt.c
+@@ -267,6 +268,7 @@ target_include_directories(bl1_main
+         ../CMSIS_Driver/Config
+         ../Device/Config
+         ../Native_Driver
+        ../fw_update_agent
+ )
+ 
+ ############################### SIGNING BL2 image ##################################
+diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+index 3d1e3e72fc..5e5e5c9e68 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+@@ -12,8 +12,12 @@
+ #include "Driver_Flash.h"
+ #include "flash_layout.h"
+ #include "bootutil/fault_injection_hardening.h"
+#include "bootutil/bootutil_log.h"
+ #include "firewall.h"
+ #include "mpu_config.h"
+#include "tfm_plat_otp.h"
+#include "tfm_plat_provisioning.h"
+#include "fwu_agent.h"
+ 
+ #if defined(CRYPTO_HW_ACCELERATOR) || \
+     defined(CRYPTO_HW_ACCELERATOR_OTP_PROVISIONING)
+@@ -595,6 +599,20 @@ int32_t boot_platform_init(void)
+     }
+ #endif /* CRYPTO_HW_ACCELERATOR */
+ 
+    result = tfm_plat_otp_init();
+    if (result != TFM_PLAT_ERR_SUCCESS) {
+        BOOT_LOG_ERR("OTP system initialization failed");
+        FIH_PANIC;
+    }
+
+    if (tfm_plat_provisioning_is_required()) {
+        result = fwu_metadata_provision();
+        if (result != FWU_AGENT_SUCCESS) {
+            BOOT_LOG_ERR("Provisioning FWU Metadata failed");
+            FIH_PANIC;
+        }
+    }
+
+     return 0;
+ }
+ 
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+new file mode 100644
+index 0000000000..b9c507e4ef
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "fwu_agent.h"
+#include "Driver_Flash.h"
+#include "flash_layout.h"
+#include "fip_parser/external/uuid.h"
+
+/* Properties of image in a bank */
+struct fwu_image_properties {
+
+        /* UUID of the image in this bank */
+        uuid_t img_uuid;
+
+        /* [0]: bit describing the image acceptance status –
+         *      1 means the image is accepted
+         * [31:1]: MBZ
+         */
+        uint32_t accepted;
+
+        /* NOTE: using the reserved field */
+        /* image version */
+        uint32_t version;
+
+} __packed;
+
+/* Image entry information */
+struct fwu_image_entry {
+
+        /* UUID identifying the image type */
+        uuid_t img_type_uuid;
+
+        /* UUID of the storage volume where the image is located */
+        uuid_t location_uuid;
+
+        /* Properties of images with img_type_uuid in the different FW banks */
+        struct fwu_image_properties img_props[NR_OF_FW_BANKS];
+
+} __packed;
+
+struct fwu_metadata {
+
+        /* Metadata CRC value */
+        uint32_t crc_32;
+
+        /* Metadata version */
+        uint32_t version;
+
+        /* Bank index with which device boots */
+        uint32_t active_index;
+
+        /* Previous bank index with which device booted successfully */
+        uint32_t previous_active_index;
+
+        /* Image entry information */
+        struct fwu_image_entry img_entry[NR_OF_IMAGES_IN_FW_BANK];
+
+} __packed;
+
+/* This is Corstone1000 speific metadata for OTA.
+ * Private metadata is written at next sector following
+ * FWU METADATA location */
+struct fwu_private_metadata {
+
+       /* boot_index: the bank from which system is booted from */
+       uint32_t boot_index;
+
+} __packed;
+
+struct fwu_metadata _metadata;
+int is_initialized = 0;
+
+#define IMAGE_ACCEPTED          (1)
+#define IMAGE_NOT_ACCEPTED      (0)
+#define BANK_0                  (0)
+#define BANK_1                  (1)
+#define IMAGE_0                 (0)
+#define IMAGE_1                 (1)
+#define IMAGE_2                 (2)
+#define IMAGE_3                 (3)
+#define INVALID_VERSION         (0xffffffff)
+
+#ifndef FWU_METADATA_FLASH_DEV
+    #ifndef FLASH_DEV_NAME
+    #error "FWU_METADATA_FLASH_DEV or FLASH_DEV_NAME must be defined in flash_layout.h"
+    #else
+    #define FWU_METADATA_FLASH_DEV FLASH_DEV_NAME
+    #endif
+#endif
+
+/* Import the CMSIS flash device driver */
+extern ARM_DRIVER_FLASH FWU_METADATA_FLASH_DEV;
+
+static enum fwu_agent_error_t private_metadata_read(
+        struct fwu_private_metadata* p_metadata)
+{
+    int ret;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    if (!p_metadata) {
+        return FWU_AGENT_ERROR;
+    }
+
+    ret = FWU_METADATA_FLASH_DEV.ReadData(FWU_PRIVATE_AREA_OFFSET, p_metadata,
+                                          sizeof(struct fwu_private_metadata));
+    if (ret != ARM_DRIVER_OK) {
+        return FWU_AGENT_ERROR;
+    }
+
+    FWU_LOG_MSG("%s: success: boot_index = %u\n\r", __func__,
+                        p_metadata->boot_index);
+
+    return FWU_AGENT_SUCCESS;
+}
+
+static enum fwu_agent_error_t private_metadata_write(
+        struct fwu_private_metadata* p_metadata)
+{
+    int ret;
+
+    FWU_LOG_MSG("%s: enter: boot_index = %u\n\r", __func__,
+                        p_metadata->boot_index);
+
+    if (!p_metadata) {
+        return FWU_AGENT_ERROR;
+    }
+
+    ret = FWU_METADATA_FLASH_DEV.EraseSector(FWU_PRIVATE_AREA_OFFSET);
+    if (ret != ARM_DRIVER_OK) {
+        return FWU_AGENT_ERROR;
+    }
+
+    ret = FWU_METADATA_FLASH_DEV.ProgramData(FWU_PRIVATE_AREA_OFFSET,
+                                p_metadata, sizeof(struct fwu_private_metadata));
+    if (ret != ARM_DRIVER_OK) {
+        return FWU_AGENT_ERROR;
+    }
+
+    FWU_LOG_MSG("%s: success\n\r", __func__);
+    return FWU_AGENT_SUCCESS;
+}
+
+static enum fwu_agent_error_t metadata_read(struct fwu_metadata *p_metadata)
+{
+    int ret;
+
+    FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
+                  FWU_METADATA_REPLICA_1_OFFSET, sizeof(struct fwu_metadata));
+
+    if (!p_metadata) {
+        return FWU_AGENT_ERROR;
+    }
+
+    ret = FWU_METADATA_FLASH_DEV.ReadData(FWU_METADATA_REPLICA_1_OFFSET,
+                                p_metadata, sizeof(struct fwu_metadata));
+    if (ret != ARM_DRIVER_OK) {
+        return FWU_AGENT_ERROR;
+    }
+
+    FWU_LOG_MSG("%s: success: active = %u, previous = %d\n\r", __func__,
+                  p_metadata->active_index, p_metadata->previous_active_index);
+
+    return FWU_AGENT_SUCCESS;
+}
+
+static enum fwu_agent_error_t metadata_write(
+                        struct fwu_metadata *p_metadata)
+{
+    int ret;
+
+    FWU_LOG_MSG("%s: enter: flash addr = %u, size = %d\n\r", __func__,
+                  FWU_METADATA_REPLICA_1_OFFSET, sizeof(struct fwu_metadata));
+
+    if (!p_metadata) {
+        return FWU_AGENT_ERROR;
+    }
+
+    ret = FWU_METADATA_FLASH_DEV.EraseSector(FWU_METADATA_REPLICA_1_OFFSET);
+    if (ret != ARM_DRIVER_OK) {
+        return FWU_AGENT_ERROR;
+    }
+
+    ret = FWU_METADATA_FLASH_DEV.ProgramData(FWU_METADATA_REPLICA_1_OFFSET,
+                                p_metadata, sizeof(struct fwu_metadata));
+    if (ret != ARM_DRIVER_OK) {
+        return FWU_AGENT_ERROR;
+    }
+
+    FWU_LOG_MSG("%s: success: active = %u, previous = %d\n\r", __func__,
+                  p_metadata->active_index, p_metadata->previous_active_index);
+    return FWU_AGENT_SUCCESS;
+}
+
+enum fwu_agent_error_t fwu_metadata_init(void)
+{
+    enum fwu_agent_error_t ret;
+    ARM_FLASH_INFO* flash_info;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    if (is_initialized) {
+        return FWU_AGENT_SUCCESS;
+    }
+
+    /* Code assumes everything fits into a sector */
+    if (sizeof(struct fwu_metadata) > FWU_METADATA_FLASH_SECTOR_SIZE) {
+        return FWU_AGENT_ERROR;
+    }
+
+    if (sizeof(struct fwu_private_metadata) > FWU_METADATA_FLASH_SECTOR_SIZE) {
+        return FWU_AGENT_ERROR;
+    }
+
+    ret = FWU_METADATA_FLASH_DEV.Initialize(NULL);
+    if (ret != ARM_DRIVER_OK) {
+        return FWU_AGENT_ERROR;
+    }
+
+    flash_info = FWU_METADATA_FLASH_DEV.GetInfo();
+    if (flash_info->program_unit != 1) {
+        FWU_METADATA_FLASH_DEV.Uninitialize();
+        return FWU_AGENT_ERROR;
+    }
+
+    is_initialized = 1;
+
+    FWU_LOG_MSG("%s: is_initialized = %d\n\r", __func__, is_initialized);
+
+    return FWU_AGENT_SUCCESS;
+}
+
+enum fwu_agent_error_t fwu_metadata_provision(void)
+{
+    enum fwu_agent_error_t ret;
+    struct fwu_private_metadata priv_metadata;
+    uint32_t image_version = 0;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    ret = fwu_metadata_init();
+    if (ret) {
+        return ret;
+    }
+
+    /* Provision FWU Agent Metadata */
+
+    memset(&_metadata, 0, sizeof(struct fwu_metadata));
+
+    _metadata.version = 1;
+    _metadata.active_index = 0;
+    _metadata.previous_active_index = 1;
+
+    /* bank 0 is the place where images are located at the
+     * start of device lifecycle */
+
+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+
+        _metadata.img_entry[i].img_props[BANK_0].accepted = IMAGE_ACCEPTED;
+        _metadata.img_entry[i].img_props[BANK_0].version = image_version;
+
+        _metadata.img_entry[i].img_props[BANK_1].accepted = IMAGE_NOT_ACCEPTED;
+        _metadata.img_entry[i].img_props[BANK_1].version = INVALID_VERSION;
+    }
+
+    ret = metadata_write(&_metadata);
+    if (ret) {
+        return ret;
+    }
+
+    memset(&_metadata, 0, sizeof(struct fwu_metadata));
+    ret = metadata_read(&_metadata);
+    if (ret) {
+        return ret;
+    }
+    FWU_LOG_MSG("%s: provisioned values: active = %u, previous = %d\n\r",
+             __func__, _metadata.active_index, _metadata.previous_active_index);
+
+
+    /* Provision Private metadata for update agent which is shared
+       beween BL1 and tf-m of secure enclave */
+
+    memset(&priv_metadata, 0, sizeof(struct fwu_private_metadata));
+
+    priv_metadata.boot_index = BANK_0;
+
+    ret = private_metadata_write(&priv_metadata);
+    if (ret) {
+        return ret;
+    }
+
+    memset(&priv_metadata, 0, sizeof(struct fwu_private_metadata));
+    ret = private_metadata_read(&priv_metadata);
+    if (ret) {
+        return ret;
+    }
+    FWU_LOG_MSG("%s: provisioned values: boot_index = %u\n\r", __func__,
+                        priv_metadata.boot_index);
+
+    FWU_LOG_MSG("%s: FWU METADATA PROVISIONED.\n\r", __func__);
+    return FWU_AGENT_SUCCESS;
+}
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+new file mode 100644
+index 0000000000..449d354100
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FWU_AGENT_H
+#define FWU_AGENT_H
+
+/* Set 1 to enable debug messages */
+#define ENABLE_DEBUG_LOGS         1
+
+#if (ENABLE_DEBUG_LOGS == 1)
+    #include <stdio.h>
+    #define FWU_LOG_MSG(f_, ...) printf((f_), ##__VA_ARGS__)
+#else
+    #define FWU_LOG_MSG(f_, ...)
+#endif
+
+enum fwu_agent_error_t {
+        FWU_AGENT_SUCCESS = 0,
+        FWU_AGENT_ERROR = (-1)
+};
+
+enum fwu_agent_error_t fwu_metadata_provision(void);
+enum fwu_agent_error_t fwu_metadata_init(void);
+
+
+#endif /* FWU_AGENT_H */
+
+diff --git a/platform/ext/target/arm/corstone1000/partition/flash_layout.h b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+index f120a7b8ee..47445d9d29 100644
+--- a/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+++ b/platform/ext/target/arm/corstone1000/partition/flash_layout.h
+@@ -117,11 +117,18 @@
+ 
+ 
+ /* 1MB: space in flash to store metadata and uefi variables */
+#define FWU_METADATA_FLASH_DEV          (FLASH_DEV_NAME)
+#define FWU_METADATA_FLASH_SECTOR_SIZE  (FLASH_SECTOR_SIZE)
+
+ #define FWU_METADATA_PARTITION_OFFSET   (FLASH_BASE_OFFSET)
+-#define FWU_METADATA_AREA_SIZE          (FLASH_SECTOR_SIZE)     /* 4KB */
+#define FWU_METADATA_AREA_SIZE          (FWU_METADATA_FLASH_SECTOR_SIZE)
+ #define FWU_METADATA_REPLICA_1_OFFSET   (FLASH_BASE_OFFSET)
+ #define FWU_METADATA_REPLICA_2_OFFSET   (FWU_METADATA_REPLICA_1_OFFSET + \
+                                          FWU_METADATA_AREA_SIZE)
+#define FWU_PRIVATE_AREA_SIZE           (FLASH_SECTOR_SIZE)
+#define FWU_PRIVATE_AREA_OFFSET         (FWU_METADATA_REPLICA_2_OFFSET + \
+                                         FWU_METADATA_AREA_SIZE)
+
+ #define NR_OF_FW_BANKS                  (2)
+ #define NR_OF_IMAGES_IN_FW_BANK         (4) /* Secure Enclave: BL2 and TF-M \
+                                              * Host: FIP and Kernel image
+@@ -217,7 +224,7 @@
+ /*** ITS, PS and NV Counters ***/
+ /*******************************/
+ 
+-#define FLASH_ITS_AREA_OFFSET           (0)
+#define FLASH_ITS_AREA_OFFSET           (0x10000)  /* 64 KB */
+ #define FLASH_ITS_AREA_SIZE             (4 * FLASH_SECTOR_SIZE)  /* 4 KiB */
+ 
+ #define FLASH_PS_AREA_OFFSET            (FLASH_ITS_AREA_OFFSET + \
+-- 
+2.17.1
+
@@ -0,0 +1,243 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 22aeb7708773c2cc9df2cc501d411b94c09fd0bd Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Sat, 2 Oct 2021 12:31:07 +0100
+Subject: [PATCH 03/15] corstone1000: parse the uefi firmware update capsule
+
+The Host (OTA Client) sends a capsule containing fwu images
+to secure enclave. The commit parses the capsule to retrieve
+images.
+
+Change-Id: Icf097cf88911a568bdc9eba8c98e2da93994f0bc
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../target/arm/corstone1000/CMakeLists.txt    |   2 +
+ .../fw_update_agent/uefi_capsule_parser.c     | 155 ++++++++++++++++++
+ .../fw_update_agent/uefi_capsule_parser.h     |  31 ++++
+ 3 files changed, 188 insertions(+)
+ create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c
+ create mode 100644 platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.h
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index 16d256bc34..f34035d361 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -51,6 +51,7 @@ target_include_directories(platform_s
+         services/include
+     INTERFACE
+         cc312
+        fw_update_agent
+ )
+ 
+ target_sources(platform_s
+@@ -67,6 +68,7 @@ target_sources(platform_s
+         tfm_hal_platform.c
+         ${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_nvic.c
+         $<$<BOOL:TFM_PARTITION_PLATFORM>:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c>
+        fw_update_agent/uefi_capsule_parser.c
+ )
+ 
+ if (PLATFORM_IS_FVP)
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c
+new file mode 100644
+index 0000000000..32133b2eb2
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.c
+@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "uefi_capsule_parser.h"
+#include "fwu_agent.h"
+#include <string.h>
+
+/*
+Update Capsule Structure (UEFI spec 2.9 1004)
+    EFI_CAPSULE_HEADER
+    ...
+    ...
+    ...
+    CAPSULE_BODY
+        efi_firmware_management_capsule_header
+        Optional Driver 1 (item_offset[0])
+        Optional Driver 2 (item_offset[1])
+            Payload 1 (item_offset[2])
+                efi_firmware_management_capsule_iamge_header
+                Binary Update image (Image_length == update_image_size)
+                Vendor Code bytes  (Data lenght == update_vendorcode_size)
+            Payload 2 (item_offset[3])
+            ...
+            ...
+            Payload n (item_offset[embedded_driver_count + payload_item_count -1])
+*/
+
+typedef struct {
+    struct efi_guid         capsule_guid;
+    uint32_t                header_size;
+    uint32_t                flags;
+    uint32_t                capsule_image_size;
+} efi_capsule_header_t;
+
+typedef struct {
+    uint32_t                version;
+    uint16_t                embedded_driver_count;
+    uint16_t                payload_item_count;
+    uint64_t                item_offset_list[];
+} efi_firmware_management_capsule_header_t;
+
+typedef struct {
+    uint32_t                version;
+    struct efi_guid         update_image_type_id;
+    uint8_t                 update_image_index;
+    uint8_t                 reserved_bytes[3];
+    uint32_t                update_image_size;
+    uint32_t                update_vendorcode_size;
+    uint64_t                update_hardware_instance; //introduced in v2
+    uint64_t                image_capsule_support; //introduced in v3
+} efi_firmware_management_capsule_image_header_t;
+
+#define ANYSIZE_ARRAY 0
+
+typedef struct {
+    uint32_t                dwLength;
+    uint16_t                wRevision;
+    uint16_t                wCertificateType;
+    uint8_t                 bCertificate[ANYSIZE_ARRAY];
+} WIN_CERTIFICATE;
+
+typedef struct {
+    WIN_CERTIFICATE         hdr;
+    struct efi_guid         cert_type;
+    uint8_t                 cert_data[ANYSIZE_ARRAY];
+} win_certificate_uefi_guid_t;
+
+typedef struct {
+    uint64_t                    monotonic_count;
+    win_certificate_uefi_guid_t   auth_info;
+} efi_firmware_image_authentication_t;
+
+
+enum uefi_capsule_error_t uefi_capsule_retrieve_images(void* capsule_ptr,
+        capsule_image_info_t* images_info)
+{
+    char *ptr = (char*)capsule_ptr;
+    efi_capsule_header_t* capsule_header;
+    efi_firmware_management_capsule_header_t* payload_header;
+    efi_firmware_management_capsule_image_header_t* image_header;
+    efi_firmware_image_authentication_t* image_auth;
+    uint32_t total_size;
+    uint32_t image_count;
+    uint32_t auth_size;
+
+    FWU_LOG_MSG("%s: enter, capsule ptr = 0x%p\n\r", __func__, capsule_ptr);
+
+    if (!capsule_ptr) {
+        return UEFI_CAPSULE_PARSER_ERROR;
+    }
+
+    capsule_header = (efi_capsule_header_t*)ptr;
+    ptr += sizeof(efi_capsule_header_t) + sizeof(uint32_t);
+    payload_header = (efi_firmware_management_capsule_header_t*)ptr;
+
+    total_size = capsule_header->capsule_image_size;
+    image_count = payload_header->payload_item_count;
+    images_info->nr_image = image_count;
+
+    FWU_LOG_MSG("%s: capsule size = %u, image count = %u\n\r", __func__,
+                        total_size, image_count);
+
+    if ((image_count == 0) || (image_count > NR_OF_IMAGES_IN_FW_BANK)) {
+        return UEFI_CAPSULE_PARSER_ERROR;
+    }
+
+    for (int i = 0; i < image_count; i++) {
+
+        image_header = (efi_firmware_management_capsule_image_header_t*)(ptr +
+                                payload_header->item_offset_list[i]);
+
+        images_info->size[i] = image_header->update_image_size;
+        images_info->version[i] = image_header->version;
+        FWU_LOG_MSG("%s: image %i version = %u\n\r", __func__, i,
+                                images_info->version[i]);
+
+        image_auth = (efi_firmware_image_authentication_t*)(
+                        (char*)image_header +
+                        sizeof (efi_firmware_management_capsule_image_header_t)
+                     );
+        auth_size = sizeof(uint64_t) /* monotonic_count */  +
+                    image_auth->auth_info.hdr.dwLength /* WIN_CERTIFICATE + cert_data */ +
+                    sizeof(struct efi_guid) /* cert_type */;
+
+        FWU_LOG_MSG("%s: auth size = %u\n\r", __func__, auth_size);
+
+        images_info->size[i] -= auth_size;
+
+        images_info->image[i] = (
+                (char*)image_header +
+                sizeof(efi_firmware_management_capsule_image_header_t) +
+                auth_size);
+
+        memcpy(&images_info->guid[i], &(image_header->update_image_type_id),
+                                                        sizeof(struct efi_guid));
+
+        FWU_LOG_MSG("%s: image %d at %p, size=%u\n\r", __func__, i,
+                        images_info->image[i], images_info->size[i]);
+
+        if ((payload_header->item_offset_list[i] +
+             sizeof(efi_firmware_management_capsule_image_header_t) +
+             image_header->update_image_size) > total_size)
+        {
+            return UEFI_CAPSULE_PARSER_ERROR;
+        }
+
+    }
+
+    FWU_LOG_MSG("%s: exit\n\r", __func__);
+    return UEFI_CAPSULE_PARSER_SUCCESS;
+}
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.h b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.h
+new file mode 100644
+index 0000000000..a890a709e9
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/uefi_capsule_parser.h
+@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef UEFI_CAPSULE_PARSER_H
+#define UEFI_CAPSULE_PARSER_H
+
+#include <stdint.h>
+#include "fip_parser/external/uuid.h"
+#include "flash_layout.h"
+
+enum uefi_capsule_error_t {
+    UEFI_CAPSULE_PARSER_SUCCESS = 0,
+    UEFI_CAPSULE_PARSER_ERROR = (-1)
+};
+
+typedef struct capsule_image_info {
+    uint32_t nr_image;
+    void *image[NR_OF_IMAGES_IN_FW_BANK];
+    struct efi_guid guid[NR_OF_IMAGES_IN_FW_BANK];
+    uint32_t size[NR_OF_IMAGES_IN_FW_BANK];
+    uint32_t version[NR_OF_IMAGES_IN_FW_BANK];
+} capsule_image_info_t;
+
+enum uefi_capsule_error_t uefi_capsule_retrieve_images(void* capsule_ptr,
+        capsule_image_info_t* images_info);
+
+#endif /* UEFI_CAPSULE_PARSER_H */
+-- 
+2.17.1
+
@@ -0,0 +1,106 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From c1ae09844562f33ddf07b8f5ca6b7d98ccbaf24c Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Sat, 2 Oct 2021 18:48:31 +0100
+Subject: [PATCH 04/15] corstone1000: add firmware update (fwu) agent into TF-M
+
+The commit links the firmware-update (fwu) agent into the
+TF-M.
+
+The commit also configures the secure enclave firewall to
+access DRAM, where uefi capsule will be written by ota client
+for fwu agent to parse.
+
+Change-Id: I89617a9b515d6aa5cc4f383b5a75a4beef73cc33
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../ext/target/arm/corstone1000/CMakeLists.txt  |  1 +
+ .../Device/Include/platform_base_address.h      |  1 +
+ .../target/arm/corstone1000/bl1/bl1_boot_hal.c  | 17 +++++++++++++++++
+ .../target/arm/corstone1000/tfm_hal_platform.c  |  5 +++++
+ 4 files changed, 24 insertions(+)
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index f34035d361..81623f16ff 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -69,6 +69,7 @@ target_sources(platform_s
+         ${CMAKE_SOURCE_DIR}/platform/ext/common/tfm_hal_nvic.c
+         $<$<BOOL:TFM_PARTITION_PLATFORM>:${CMAKE_CURRENT_SOURCE_DIR}/services/src/tfm_platform_system.c>
+         fw_update_agent/uefi_capsule_parser.c
+        fw_update_agent/fwu_agent.c
+ )
+ 
+ if (PLATFORM_IS_FVP)
+diff --git a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
+index 5f37caa09c..e86ddcfbc9 100644
+--- a/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
+++ b/platform/ext/target/arm/corstone1000/Device/Include/platform_base_address.h
+@@ -75,5 +75,6 @@
+ #define CORSTONE1000_HOST_FPGA_SCC_REGISTERS       (0x80000000U) /* FPGA SCC Registers                */
+ #define CORSTONE1000_HOST_SE_SECURE_FLASH_BASE_FVP (0x80010000U) /* SE Flash                          */
+ #define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE   (0x80050000U) /* AXI QSPI Controller               */
+#define CORSTONE1000_HOST_DRAM_UEFI_CAPSULE        (0xA0000000U) /* 1.5 GB DDR                        */
+ 
+ #endif  /* __PLATFORM_BASE_ADDRESS_H__ */
+diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+index 5e5e5c9e68..54042495d7 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+@@ -47,6 +47,7 @@ REGION_DECLARE(Image$$, ARM_LIB_HEAP, $$ZI$$Limit)[];
+ #define HOST_AXI_QSPI_CTRL_REG_BASE_SE_SECURE_FLASH    0x60010000
+ 
+ #define HOST_DRAM_BASE                  0x80000000
+#define HOST_DRAM_UEFI_CAPSULE          0x80000000
+ 
+ #define SE_MID                          0
+ 
+@@ -249,6 +250,22 @@ static void setup_se_firewall(void)
+     fc_enable_mpe(RGN_MPE0);
+     fc_enable_regions();
+ 
+    /* DDR/DRAM/UEFI_CAPSULE: 32MB */
+    fc_select_region(6);
+    fc_disable_regions();
+    fc_disable_mpe(RGN_MPE0);
+    fc_prog_rgn(RGN_SIZE_32MB, CORSTONE1000_HOST_DRAM_UEFI_CAPSULE);
+    fc_prog_rgn_upper_addr(HOST_DRAM_UEFI_CAPSULE);
+    fc_enable_addr_trans();
+    fc_init_mpl(RGN_MPE0);
+    mpl_rights = (RGN_MPL_SECURE_READ_MASK |
+                  RGN_MPL_SECURE_WRITE_MASK);
+
+    fc_enable_mpl(RGN_MPE0, mpl_rights);
+    fc_prog_mid(RGN_MPE0, SE_MID);
+    fc_enable_mpe(RGN_MPE0);
+    fc_enable_regions();
+
+ 
+     fc_pe_enable();
+ }
+diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+index 71472ea08c..0072b5b928 100644
+--- a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+++ b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+@@ -8,11 +8,16 @@
+ #include "cmsis.h"
+ #include "tfm_hal_platform.h"
+ #include "uart_stdout.h"
+#include "fwu_agent.h"
+ 
+ enum tfm_hal_status_t tfm_hal_platform_init(void)
+ {
+     __enable_irq();
+     stdio_init();
+ 
+    if (fwu_metadata_init()) {
+        return TFM_HAL_ERROR_GENERIC;
+    }
+
+     return TFM_HAL_SUCCESS;
+ }
+-- 
+2.17.1
+
@@ -0,0 +1,437 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 593087034655eca09ff8e80e67c3252399fa0ce7 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Sat, 2 Oct 2021 18:51:21 +0100
+Subject: [PATCH 05/15] corstone1000: implement corstone1000_fwu_flash_images
+
+The API, corstone1000_fwu_flash_images, is an non-secure host
+inteface (firmware update client) to send new updatable images,
+and to start the update process. The implementation of the API does
+version verfification before coping the images to the update bank.
+After copy, the platform is reset.
+
+On successful call to the API, the firmware update state of the
+system changes from regular state to trial state. On reset,
+the system is expected but not guaranteed to boot from the
+update/trial bank.
+
+Change-Id: I6c278145ec95ec522f7e59d00e1640a039c9778e
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../corstone1000/CMSIS_Driver/Driver_Flash.c  |  11 +
+ .../corstone1000/Native_Driver/flash_common.h |   1 +
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 225 ++++++++++++++++++
+ .../corstone1000/fw_update_agent/fwu_agent.h  |  11 +
+ .../include/corstone1000_ioctl_requests.h     |  32 +++
+ .../services/src/tfm_platform_system.c        |  24 +-
+ 6 files changed, 300 insertions(+), 4 deletions(-)
+ create mode 100644 platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h
+
+diff --git a/platform/ext/target/arm/corstone1000/CMSIS_Driver/Driver_Flash.c b/platform/ext/target/arm/corstone1000/CMSIS_Driver/Driver_Flash.c
+index 10952d4cbe..01c535e094 100644
+--- a/platform/ext/target/arm/corstone1000/CMSIS_Driver/Driver_Flash.c
+++ b/platform/ext/target/arm/corstone1000/CMSIS_Driver/Driver_Flash.c
+@@ -175,6 +175,11 @@ int32_t Select_XIP_Mode_For_Shared_Flash(void)
+     return ARM_DRIVER_OK;
+ }
+ 
+int32_t Select_Write_Mode_For_Shared_Flash(void)
+{
+    return ARM_DRIVER_OK;
+}
+
+ static int32_t STRATAFLASHJ3_Initialize(ARM_Flash_SignalEvent_t cb_event)
+ {
+     ARG_UNUSED(cb_event);
+@@ -392,6 +397,12 @@ int32_t Select_XIP_Mode_For_Shared_Flash(void)
+     return ARM_DRIVER_OK;
+ }
+ 
+int32_t Select_Write_Mode_For_Shared_Flash(void)
+{
+    select_qspi_mode(&AXI_QSPI_DEV_S);
+    return ARM_DRIVER_OK;
+}
+
+ static ARM_FLASH_CAPABILITIES N25Q256A_Driver_GetCapabilities(void)
+ {
+     return N25Q256ADriverCapabilities;
+diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/flash_common.h b/platform/ext/target/arm/corstone1000/Native_Driver/flash_common.h
+index 76d5303f83..2e91fb2db4 100644
+--- a/platform/ext/target/arm/corstone1000/Native_Driver/flash_common.h
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/flash_common.h
+@@ -18,6 +18,7 @@ extern "C"
+ #include "Driver_Common.h"
+ 
+ int32_t Select_XIP_Mode_For_Shared_Flash(void);
+int32_t Select_Write_Mode_For_Shared_Flash(void);
+ 
+ #ifdef  __cplusplus
+ }
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index b9c507e4ef..7fa64db0f7 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -11,6 +11,10 @@
+ #include "Driver_Flash.h"
+ #include "flash_layout.h"
+ #include "fip_parser/external/uuid.h"
+#include "region_defs.h"
+#include "uefi_capsule_parser.h"
+#include "flash_common.h"
+#include "platform_base_address.h"
+ 
+ /* Properties of image in a bank */
+ struct fwu_image_properties {
+@@ -73,9 +77,27 @@ struct fwu_private_metadata {
+ 
+ } __packed;
+ 
+
+ struct fwu_metadata _metadata;
+
+ int is_initialized = 0;
+ 
+capsule_image_info_t capsule_info;
+
+enum fwu_agent_state_t {
+    FWU_AGENT_STATE_UNKNOWN = -1,
+    FWU_AGENT_STATE_REGULAR = 0,
+    FWU_AGENT_STATE_TRIAL,
+};
+
+struct efi_guid full_capsule_image_guid = {
+    .time_low = 0x3a770ddc,
+    .time_mid = 0x409b,
+    .time_hi_and_version = 0x48b2,
+    .clock_seq_and_node = {0x81, 0x41, 0x93, 0xb7, 0xc6, 0x0b, 0x20, 0x9e}
+};
+
+
+ #define IMAGE_ACCEPTED          (1)
+ #define IMAGE_NOT_ACCEPTED      (0)
+ #define BANK_0                  (0)
+@@ -84,8 +106,12 @@ int is_initialized = 0;
+ #define IMAGE_1                 (1)
+ #define IMAGE_2                 (2)
+ #define IMAGE_3                 (3)
+#define IMAGE_END               (IMAGE_3)
+#define IMAGE_ALL               (IMAGE_END + 1)
+#define IMAGE_NOT_RECOGNIZED    (-1)
+ #define INVALID_VERSION         (0xffffffff)
+ 
+
+ #ifndef FWU_METADATA_FLASH_DEV
+     #ifndef FLASH_DEV_NAME
+     #error "FWU_METADATA_FLASH_DEV or FLASH_DEV_NAME must be defined in flash_layout.h"
+@@ -307,3 +333,202 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
+     return FWU_AGENT_SUCCESS;
+ }
+ 
+static enum fwu_agent_state_t get_fwu_agent_state(
+        struct fwu_metadata *metadata_ptr,
+        struct fwu_private_metadata *priv_metadata_ptr)
+{
+    uint32_t boot_index;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    boot_index = priv_metadata_ptr->boot_index;
+
+    if (boot_index != metadata_ptr->active_index) {
+        return FWU_AGENT_STATE_TRIAL;
+    }
+
+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+        if ((metadata_ptr->img_entry[i].img_props[boot_index].accepted)
+                == (IMAGE_NOT_ACCEPTED)) {
+            return FWU_AGENT_STATE_TRIAL;
+        }
+    }
+
+    FWU_LOG_MSG("%s: exit: FWU_AGENT_STATE_REGULAR\n\r", __func__);
+    return FWU_AGENT_STATE_REGULAR;
+}
+
+static int get_image_info_in_bank(struct efi_guid* guid, uint32_t* image_bank_offset)
+{
+    if ((memcmp(guid, &full_capsule_image_guid, sizeof(struct efi_guid))) == 0) {
+        *image_bank_offset = 0;
+        return IMAGE_ALL;
+    }
+
+    return IMAGE_NOT_RECOGNIZED;
+}
+
+static enum fwu_agent_error_t erase_bank(uint32_t bank_offset)
+{
+    int ret;
+    uint32_t sectors;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    if ((bank_offset % FWU_METADATA_FLASH_SECTOR_SIZE) != 0) {
+        return FWU_AGENT_ERROR;
+    }
+
+    if ((BANK_PARTITION_SIZE % FWU_METADATA_FLASH_SECTOR_SIZE) != 0) {
+        return FWU_AGENT_ERROR;
+    }
+
+    sectors = BANK_PARTITION_SIZE / FWU_METADATA_FLASH_SECTOR_SIZE;
+
+    FWU_LOG_MSG("%s: erasing sectors = %u, from offset = %u\n\r", __func__,
+                     sectors, bank_offset);
+
+    for (int i = 0; i < sectors; i++) {
+        ret = FWU_METADATA_FLASH_DEV.EraseSector(
+                bank_offset + (i * FWU_METADATA_FLASH_SECTOR_SIZE));
+        if (ret != ARM_DRIVER_OK) {
+            return FWU_AGENT_ERROR;
+        }
+    }
+
+    FWU_LOG_MSG("%s: exit\n\r", __func__);
+    return FWU_AGENT_SUCCESS;
+}
+
+
+static enum fwu_agent_error_t flash_full_capsule(
+        struct fwu_metadata* metadata, void* images, uint32_t size,
+        uint32_t version)
+{
+    int ret;
+    uint32_t active_index = metadata->active_index;
+    uint32_t bank_offset;
+    uint32_t previous_active_index;
+
+    FWU_LOG_MSG("%s: enter: image = 0x%p, size = %u, version = %u\n\r"
+                , __func__, images, size, version);
+
+    if (!metadata || !images) {
+        return FWU_AGENT_ERROR;
+    }
+
+    if (size > BANK_PARTITION_SIZE) {
+        return FWU_AGENT_ERROR;
+    }
+
+    if (version <=
+            (metadata->img_entry[IMAGE_0].img_props[active_index].version)) {
+        return FWU_AGENT_ERROR;
+    }
+
+    if (active_index == BANK_0) {
+        previous_active_index = BANK_1;
+        bank_offset = BANK_1_PARTITION_OFFSET;
+    } else if (active_index == BANK_1) {
+        previous_active_index = BANK_0;
+        bank_offset = BANK_0_PARTITION_OFFSET;
+    } else {
+        return FWU_AGENT_ERROR;
+    }
+
+    if (erase_bank(bank_offset)) {
+        return FWU_AGENT_ERROR;
+    }
+
+    FWU_LOG_MSG("%s: writing capsule to the flash at offset = %u...\n\r",
+                      __func__, bank_offset);
+    ret = FWU_METADATA_FLASH_DEV.ProgramData(bank_offset, images, size);
+    if (ret != ARM_DRIVER_OK) {
+        return FWU_AGENT_ERROR;
+    }
+    FWU_LOG_MSG("%s: images are written to bank offset = %u\n\r", __func__,
+                     bank_offset);
+
+    /* Change system state to trial bank state */
+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+        metadata->img_entry[i].img_props[previous_active_index].accepted =
+                                                        IMAGE_NOT_ACCEPTED;
+        metadata->img_entry[i].img_props[previous_active_index].version = version;
+    }
+    metadata->active_index = previous_active_index;
+    metadata->previous_active_index = active_index;
+
+    ret = metadata_write(metadata);
+    if (ret) {
+        return ret;
+    }
+
+    FWU_LOG_MSG("%s: exit\n\r", __func__);
+    return FWU_AGENT_SUCCESS;
+}
+
+enum fwu_agent_error_t corstone1000_fwu_flash_image(void)
+{
+    enum fwu_agent_error_t ret;
+    struct fwu_private_metadata priv_metadata;
+    enum fwu_agent_state_t current_state;
+    void *capsule_ptr = (char*)CORSTONE1000_HOST_DRAM_UEFI_CAPSULE;
+    int image_index;
+    uint32_t image_bank_offset;
+    uint32_t nr_images;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    if (!is_initialized) {
+        return FWU_AGENT_ERROR;
+    }
+
+    Select_Write_Mode_For_Shared_Flash();
+
+    if (metadata_read(&_metadata)) {
+        ret =  FWU_AGENT_ERROR;
+        goto out;
+    }
+
+    if (private_metadata_read(&priv_metadata)) {
+        ret =  FWU_AGENT_ERROR;
+        goto out;
+    }
+
+    /* Firmware update process can only start in regular state. */
+    current_state = get_fwu_agent_state(&_metadata, &priv_metadata);
+    if (current_state != FWU_AGENT_STATE_REGULAR) {
+        ret =  FWU_AGENT_ERROR;
+        goto out;
+    }
+
+    memset(&capsule_info, 0, sizeof(capsule_image_info_t));
+    if (uefi_capsule_retrieve_images(capsule_ptr, &capsule_info)) {
+        ret =  FWU_AGENT_ERROR;
+        goto out;
+    }
+    nr_images = capsule_info.nr_image;
+
+    for (int i = 0; i < nr_images; i++) {
+        image_index = get_image_info_in_bank(&capsule_info.guid[i],
+                                &image_bank_offset);
+        switch(image_index) {
+            case IMAGE_ALL:
+                ret = flash_full_capsule(&_metadata, capsule_info.image[i],
+                                         capsule_info.size[i],
+                                         capsule_info.version[i]);
+                break;
+            default:
+                FWU_LOG_MSG("%s: sent image not recognized\n\r", __func__);
+                ret = FWU_AGENT_ERROR;
+                break;
+        }
+    }
+
+out:
+    Select_XIP_Mode_For_Shared_Flash();
+
+    FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
+    return ret;
+}
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+index 449d354100..f5ab877ef1 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+@@ -23,9 +23,20 @@ enum fwu_agent_error_t {
+         FWU_AGENT_ERROR = (-1)
+ };
+ 
+#define FWU_ASSERT(_c_)                                                        \
+                if (!(_c_)) {                                                  \
+                    FWU_LOG_MSG("%s:%d assert hit\n\r", __func__, __LINE__);   \
+                    while(1) {};                                               \
+                }                                                              \
+
+
+ enum fwu_agent_error_t fwu_metadata_provision(void);
+ enum fwu_agent_error_t fwu_metadata_init(void);
+ 
+/* host to secure enclave:
+ * firwmare update image is sent accross
+ */
+enum fwu_agent_error_t corstone1000_fwu_flash_image(void);
+ 
+ #endif /* FWU_AGENT_H */
+ 
+diff --git a/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h b/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h
+new file mode 100644
+index 0000000000..8ac67346b6
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/services/include/corstone1000_ioctl_requests.h
+@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CORSTONE1000_IOCTL_REQUESTS_H
+#define CORSTONE1000_IOCTL_REQUESTS_H
+
+#include<stdint.h>
+
+
+enum corstone1000_ioctl_id_t {
+   IOCTL_CORSTONE1000_FWU_FLASH_IMAGES = 0,
+   IOCTL_CORSTONE1000_FWU_HOST_ACK,
+};
+
+
+typedef struct corstone1000_ioctl_in_params {
+
+    uint32_t ioctl_id;
+
+} corstone1000_ioctl_in_params_t;
+
+typedef struct corstone1000_ioctl_out_params {
+
+    int32_t result;
+
+} corstone1000_ioctl_out_params_t;
+
+#endif /* CORSTONE1000_IOCTL_REQUESTS_H */
+diff --git a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+index ed31c8895a..f9629a1688 100644
+--- a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+++ b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+@@ -7,6 +7,8 @@
+ 
+ #include "tfm_platform_system.h"
+ #include "platform_description.h"
+#include "corstone1000_ioctl_requests.h"
+#include "fwu_agent.h"
+ 
+ void tfm_platform_hal_system_reset(void)
+ {
+@@ -18,8 +20,22 @@ enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
+                                                psa_invec  *in_vec,
+                                                psa_outvec *out_vec)
+ {
+-    (void)in_vec;
+-    (void)out_vec;
+-    /* No IOCTL is ipmlemented */
+-    return TFM_PLATFORM_ERR_NOT_SUPPORTED;
+    int32_t ret = TFM_PLATFORM_ERR_SUCCESS;
+    const corstone1000_ioctl_in_params_t *in_params =
+                                    (corstone1000_ioctl_in_params_t *)in_vec->base;
+    corstone1000_ioctl_out_params_t *out_params = (corstone1000_ioctl_out_params_t *)out_vec->base;
+
+    switch(in_params->ioctl_id) {
+        case IOCTL_CORSTONE1000_FWU_FLASH_IMAGES:
+            out_params->result = corstone1000_fwu_flash_image();
+            if (!out_params->result) {
+                NVIC_SystemReset();
+            }
+            break;
+        default:
+            ret = TFM_PLATFORM_ERR_NOT_SUPPORTED;
+            break;
+    }
+
+    return ret;
+ }
+-- 
+2.17.1
+
@@ -0,0 +1,266 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 7ec8812451a4e25ca0790f84c7a0ee1f260f864c Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Mon, 11 Oct 2021 20:12:46 +0100
+Subject: [PATCH 06/15] corstone1000: add logic to select boot bank
+
+Bl1 selects the boot bank depending upon the firmware update state
+of the system. When in the trial state, new images are being tried,
+BL1 select trial/update image bank for a pre-determined number of
+times. If in all attempts, the trial bank fails to boot, BL1 falls
+back to the previous active bank. For any reason, if previous active
+bank also fails to boot for that pre-determined number of times,
+the BL1 simply goes into an assert halt state. Idealy a recovery
+mechanism should boot but this is currently out-of-scope for the
+project.
+
+BL2 logic simply tries to boot from the bank selected by the BL1.
+
+It is expected that the fail boots are detected by secure enclave,
+and in those cases, reset of the system is triggered.
+
+Change-Id: I773752f789bf8b402436c61134ac79bb405553b5
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../target/arm/corstone1000/CMakeLists.txt    |   2 +
+ .../arm/corstone1000/bl1/bl1_boot_hal.c       |   6 +-
+ .../target/arm/corstone1000/bl2_boot_hal.c    |   8 +-
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 102 ++++++++++++++++++
+ .../corstone1000/fw_update_agent/fwu_agent.h  |   5 +-
+ 5 files changed, 117 insertions(+), 6 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index 81623f16ff..a2191c835f 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -109,6 +109,7 @@ target_sources(platform_bl2
+         Native_Driver/uart_pl011_drv.c
+         fip_parser/fip_parser.c
+         bl2_boot_hal.c
+        fw_update_agent/fwu_agent.c
+ )
+ 
+ if (PLATFORM_IS_FVP)
+@@ -155,6 +156,7 @@ target_include_directories(platform_bl2
+         ${MCUBOOT_PATH}/boot/bootutil/include # for fault_injection_hardening.h only
+         ${CMAKE_BINARY_DIR}/bl2/ext/mcuboot # for mcuboot_config.h only
+         $<BUILD_INTERFACE:${BL2_SOURCE}/ext/mcuboot/include>
+        fw_update_agent
+ )
+ 
+ #========================= BL1 component =======================================#
+diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+index 54042495d7..2af5b8c846 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+@@ -587,7 +587,7 @@ extern void add_bank_offset_to_image_offset(uint32_t bank_offset);
+ int32_t boot_platform_init(void)
+ {
+     int32_t result;
+-    uint32_t bank_offset = BANK_0_PARTITION_OFFSET;
+    uint32_t bank_offset;
+ 
+ #if !(PLATFORM_IS_FVP)
+     setup_mpu();
+@@ -596,7 +596,6 @@ int32_t boot_platform_init(void)
+ #if !(PLATFORM_IS_FVP)
+     setup_host_firewall();
+ #endif
+-    add_bank_offset_to_image_offset(bank_offset);
+ 
+     result = FLASH_DEV_NAME.Initialize(NULL);
+     if (result != ARM_DRIVER_OK) {
+@@ -630,6 +629,9 @@ int32_t boot_platform_init(void)
+         }
+     }
+ 
+    bl1_get_boot_bank(&bank_offset);
+    add_bank_offset_to_image_offset(bank_offset);
+
+     return 0;
+ }
+ 
+diff --git a/platform/ext/target/arm/corstone1000/bl2_boot_hal.c b/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
+index 75d2cb60d8..4f5b48a2e0 100644
+--- a/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
+++ b/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
+@@ -18,6 +18,7 @@
+ #include <string.h>
+ #include "tfm_plat_otp.h"
+ #include "tfm_plat_provisioning.h"
+#include "fwu_agent.h"
+ 
+ #ifdef PLATFORM_PSA_ADAC_SECURE_DEBUG
+ #include "psa_adac_platform.h"
+@@ -112,15 +113,13 @@ int32_t boot_platform_init(void)
+ {
+     int32_t result;
+     enum tfm_plat_err_t plat_err;
+-    uint32_t bank_offset = BANK_0_PARTITION_OFFSET;
+    uint32_t bank_offset;
+ 
+     result = fill_bl2_flash_map_by_parsing_fips(BANK_0_PARTITION_OFFSET);
+     if (result) {
+         return 1;
+     }
+ 
+-    add_bank_offset_to_image_offset(bank_offset);
+-
+     result = FLASH_DEV_NAME.Initialize(NULL);
+     if (result != ARM_DRIVER_OK) {
+         return 1;
+@@ -154,6 +153,9 @@ int32_t boot_platform_init(void)
+     }
+ #endif
+ 
+    bl2_get_boot_bank(&bank_offset);
+    add_bank_offset_to_image_offset(bank_offset);
+
+     return 0;
+ }
+ 
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index 7fa64db0f7..23a15ee71b 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -75,8 +75,12 @@ struct fwu_private_metadata {
+        /* boot_index: the bank from which system is booted from */
+        uint32_t boot_index;
+ 
+       /* counter: tracking number of boot attempted so far */
+       uint32_t boot_attempted;
+
+ } __packed;
+ 
+#define MAX_BOOT_ATTEMPTS_PER_BANK 3
+ 
+ struct fwu_metadata _metadata;
+ 
+@@ -315,6 +319,7 @@ enum fwu_agent_error_t fwu_metadata_provision(void)
+     memset(&priv_metadata, 0, sizeof(struct fwu_private_metadata));
+ 
+     priv_metadata.boot_index = BANK_0;
+    priv_metadata.boot_attempted = 0;
+ 
+     ret = private_metadata_write(&priv_metadata);
+     if (ret) {
+@@ -532,3 +537,100 @@ out:
+     return ret;
+ }
+ 
+void bl1_get_boot_bank(uint32_t *bank_offset)
+{
+    struct fwu_private_metadata priv_metadata;
+    enum fwu_agent_state_t current_state;
+    uint32_t boot_attempted;
+    uint32_t boot_index;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    if (fwu_metadata_init()) {
+        FWU_ASSERT(0);
+    }
+
+    if (private_metadata_read(&priv_metadata)) {
+        FWU_ASSERT(0);
+    }
+
+    if (metadata_read(&_metadata)) {
+        FWU_ASSERT(0);
+    }
+
+    current_state = get_fwu_agent_state(&_metadata, &priv_metadata);
+
+    if (current_state == FWU_AGENT_STATE_REGULAR) {
+        boot_index = _metadata.active_index;
+        FWU_ASSERT(boot_index == priv_metadata.boot_index);
+        boot_attempted = 0;
+    } else if (current_state == FWU_AGENT_STATE_TRIAL) {
+        boot_attempted = (++priv_metadata.boot_attempted);
+        FWU_LOG_MSG("%s: attempting boot number = %u\n\r",
+                                        __func__, boot_attempted);
+        if (boot_attempted <= MAX_BOOT_ATTEMPTS_PER_BANK) {
+            boot_index = _metadata.active_index;
+            FWU_LOG_MSG("%s: booting from trial bank: %u\n\r",
+                                        __func__, boot_index);
+        } else if (boot_attempted <= (2 * MAX_BOOT_ATTEMPTS_PER_BANK)) {
+            boot_index = _metadata.previous_active_index;
+            FWU_LOG_MSG("%s: gave up booting from trial bank\n\r", __func__);
+            FWU_LOG_MSG("%s: booting from previous active bank: %u\n\r",
+                                        __func__, boot_index);
+        } else {
+            FWU_LOG_MSG("%s: cannot boot system from any bank, halting...\n\r", __func__);
+            FWU_ASSERT(0);
+        }
+    } else {
+        FWU_ASSERT(0);
+    }
+
+    priv_metadata.boot_index = boot_index;
+    if (private_metadata_write(&priv_metadata)) {
+        FWU_ASSERT(0);
+    }
+
+    if (boot_index == BANK_0) {
+        *bank_offset = BANK_0_PARTITION_OFFSET;
+    } else if (boot_index == BANK_1) {
+        *bank_offset = BANK_1_PARTITION_OFFSET;
+    } else {
+        FWU_ASSERT(0);
+    }
+
+    FWU_LOG_MSG("%s: exit: booting from bank = %u, offset = %x\n\r", __func__,
+                        boot_index, *bank_offset);
+
+    return;
+}
+
+void bl2_get_boot_bank(uint32_t *bank_offset)
+{
+    uint32_t boot_index;
+    struct fwu_private_metadata priv_metadata;
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    if (fwu_metadata_init()) {
+        FWU_ASSERT(0);
+    }
+
+    if (private_metadata_read(&priv_metadata)) {
+        FWU_ASSERT(0);
+    }
+
+    boot_index = priv_metadata.boot_index;
+
+    if (boot_index == BANK_0) {
+        *bank_offset = BANK_0_PARTITION_OFFSET;
+    } else if (boot_index == BANK_1) {
+        *bank_offset = BANK_1_PARTITION_OFFSET;
+    } else {
+        FWU_ASSERT(0);
+    }
+
+    FWU_LOG_MSG("%s: exit: booting from bank = %u, offset = %x\n\r", __func__,
+                        boot_index, *bank_offset);
+
+    return;
+}
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+index f5ab877ef1..389381c326 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+@@ -38,5 +38,8 @@ enum fwu_agent_error_t fwu_metadata_init(void);
+  */
+ enum fwu_agent_error_t corstone1000_fwu_flash_image(void);
+ 
+-#endif /* FWU_AGENT_H */
+ 
+void bl1_get_boot_bank(uint32_t *bank_offset);
+void bl2_get_boot_bank(uint32_t *bank_offset);
+
+#endif /* FWU_AGENT_H */
+-- 
+2.17.1
+
@@ -0,0 +1,645 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From d8c6e41ee040d19748915d2c598df1c4b90a93a8 Mon Sep 17 00:00:00 2001
+From: Harry Moulton <harry.moulton@arm.com>
+Date: Tue, 5 Oct 2021 12:40:57 +0100
+Subject: [PATCH 07/15] corstone1000: integrate watchdog driver
+
+This change integrates and enables the watchdog timer driver
+inside the BL1, BL2 and TF-M. SoC and SE watchdogs are enabled,
+meaning the system should get reset if software becomes
+unresponsive.
+
+Signed-off-by: Harry Moulton <harry.moulton@arm.com>
+Change-Id: Iab957a58025aac98140bb71289a269443529e8ed
+---
+ .../target/arm/corstone1000/CMakeLists.txt    |   4 +
+ .../Native_Driver/arm_watchdog_drv.c          | 190 ++++++++++++++++++
+ .../Native_Driver/arm_watchdog_drv.h          | 179 +++++++++++++++++
+ .../arm/corstone1000/Native_Driver/watchdog.c |  81 ++++++++
+ .../arm/corstone1000/Native_Driver/watchdog.h |  32 +++
+ .../arm/corstone1000/bl1/CMakeLists.txt       |   2 +
+ .../arm/corstone1000/bl1/bl1_boot_hal.c       |   6 +
+ .../target/arm/corstone1000/bl2_boot_hal.c    |   6 +
+ .../arm/corstone1000/tfm_hal_platform.c       |   5 +
+ 9 files changed, 505 insertions(+)
+ create mode 100644 platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.c
+ create mode 100644 platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.h
+ create mode 100644 platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
+ create mode 100644 platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index a2191c835f..cb66bd48d6 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -62,6 +62,8 @@ target_sources(platform_s
+         Device/Source/system_core_init.c
+         Native_Driver/uart_pl011_drv.c
+         Native_Driver/mhu_v2_x.c
+        Native_Driver/watchdog.c
+        Native_Driver/arm_watchdog_drv.c
+         spm_hal.c
+         tfm_hal_multi_core.c
+         tfm_hal_isolation.c
+@@ -107,6 +109,8 @@ target_sources(platform_bl2
+         Device/Source/device_definition.c
+         Device/Source/system_core_init.c
+         Native_Driver/uart_pl011_drv.c
+        Native_Driver/watchdog.c
+        Native_Driver/arm_watchdog_drv.c
+         fip_parser/fip_parser.c
+         bl2_boot_hal.c
+         fw_update_agent/fwu_agent.c
+diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.c b/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.c
+new file mode 100644
+index 0000000000..b6323c99a5
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.c
+@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2016-2020 Arm Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_watchdog_drv.h"
+
+/* Watchdog control definitions */
+#define ARM_WATCHDOG_CTRL_INTEN        (0x1UL << 0)
+#define ARM_WATCHDOG_CTRL_RESEN        (0x1UL << 1)
+#define ARM_WATCHDOG_INTCLR            1UL
+#define ARM_WATCHDOG_RAWINTSTAT        1UL
+#define ARM_WATCHDOG_MASKINTSTAT       1UL
+#define ARM_WATCHDOG_UNLOCK_VALUE      0x1ACCE551
+#define ARM_WATCHDOG_LOCK_VALUE        0x00000001
+#define ARM_WATCHDOG_INTEGTESTEN       1UL
+#define ARM_WATCHDOG_INTEGTESTOUTSET   1UL
+#define ARM_WATCHDOG_MAX_VALUE         0xFFFFFFFF
+
+/* Watchdog state definitions */
+#define ARM_WATCHDOG_INITIALIZED  (1ul << 0)
+#define ARM_WATCHDOG_ENABLED      (1ul << 1)
+
+/* ARM watchdog memory mapped register access structure */
+struct arm_watchdog_t {
+    volatile uint32_t  load;          /* Offset: 0x000 (R/W) Load register */
+    volatile uint32_t  value;         /* Offset: 0x004 (R/ ) Value register */
+    volatile uint32_t  ctrl;          /* Offset: 0x008 (R/W) Control register */
+    volatile uint32_t  intclr;        /* Offset: 0x00C ( /W) Clear interrupt
+                                       *                     register */
+    volatile uint32_t  rawintstat;    /* Offset: 0x010 (R/ ) Raw interrupt
+                                       *                     status register */
+    volatile uint32_t  maskintstat;   /* Offset: 0x014 (R/ ) Interrupt status
+                                       *                     register */
+    volatile uint32_t  reserved0[762];
+    volatile uint32_t  lock;          /* Offset: 0xC00 (R/W) Lock register */
+    volatile uint32_t  reserved1[191];
+    volatile uint32_t  itcr;          /* Offset: 0xF00 (R/W) Integration test
+                                       *                     control register */
+    volatile uint32_t  itop;          /* Offset: 0xF04 ( /W) Integration Test
+                                       *                     output set
+                                       *                     register */
+};
+
+void arm_watchdog_init(struct arm_watchdog_dev_t* dev, uint32_t timeout)
+{
+    /*
+     * The init function leaves the watchdog in a clean state:
+     *  - initialized;
+     *  - disabled;
+     *  - locked.
+     */
+    if (arm_watchdog_is_enabled(dev)) {
+        arm_watchdog_unlock(dev);
+        (void)arm_watchdog_disable(dev);
+    }
+    arm_watchdog_lock(dev);
+
+    if (timeout == 0)
+        dev->data->timeout = ARM_WATCHDOG_MAX_VALUE;
+    else
+        dev->data->timeout = timeout;
+
+    dev->data->state = ARM_WATCHDOG_INITIALIZED;
+}
+
+enum arm_watchdog_error_t arm_watchdog_feed(struct arm_watchdog_dev_t* dev)
+{
+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
+
+    if (!arm_watchdog_is_enabled(dev))
+        return ARM_WATCHDOG_ERR_NOT_ENAB;
+
+    if (arm_watchdog_is_locked(dev))
+        return ARM_WATCHDOG_ERR_LOCKED;
+
+    p_wdog->load = dev->data->timeout;
+
+    return ARM_WATCHDOG_ERR_NONE;
+}
+
+enum arm_watchdog_error_t
+arm_watchdog_clear_interrupt_and_refresh_counter(struct arm_watchdog_dev_t* dev)
+{
+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
+
+    if (!arm_watchdog_is_enabled(dev))
+        return ARM_WATCHDOG_ERR_NOT_ENAB;
+
+    if (arm_watchdog_is_locked(dev))
+        return ARM_WATCHDOG_ERR_LOCKED;
+
+    p_wdog->intclr = ARM_WATCHDOG_INTCLR;
+
+    return ARM_WATCHDOG_ERR_NONE;
+}
+
+enum arm_watchdog_error_t arm_watchdog_enable(struct arm_watchdog_dev_t* dev)
+{
+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
+
+    if (!arm_watchdog_is_initialized(dev))
+        return ARM_WATCHDOG_ERR_NOT_INIT;
+
+    if (arm_watchdog_is_locked(dev))
+        return ARM_WATCHDOG_ERR_LOCKED;
+
+    p_wdog->load = dev->data->timeout;
+
+    /* Starts the watchdog counter */
+    p_wdog->ctrl = (ARM_WATCHDOG_CTRL_RESEN | ARM_WATCHDOG_CTRL_INTEN);
+    dev->data->state |= ARM_WATCHDOG_ENABLED;
+
+    return ARM_WATCHDOG_ERR_NONE;
+}
+
+uint32_t arm_watchdog_is_enabled(struct arm_watchdog_dev_t* dev)
+{
+    return (dev->data->state & ARM_WATCHDOG_ENABLED);
+}
+
+enum arm_watchdog_error_t arm_watchdog_disable(struct arm_watchdog_dev_t* dev)
+{
+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
+
+    if (!arm_watchdog_is_enabled(dev))
+        return ARM_WATCHDOG_ERR_NOT_ENAB;
+
+    if (arm_watchdog_is_locked(dev))
+        return ARM_WATCHDOG_ERR_LOCKED;
+
+    /* Stops the watchdog */
+    p_wdog->ctrl &= ~(ARM_WATCHDOG_CTRL_RESEN | ARM_WATCHDOG_CTRL_INTEN);
+    dev->data->state &= ~ARM_WATCHDOG_ENABLED;
+
+    return ARM_WATCHDOG_ERR_NONE;
+}
+
+void arm_watchdog_lock(struct arm_watchdog_dev_t* dev)
+{
+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
+
+    /* Prevents writing to all of the registers */
+    p_wdog->lock = ARM_WATCHDOG_LOCK_VALUE;
+}
+
+uint32_t arm_watchdog_is_locked(struct arm_watchdog_dev_t* dev)
+{
+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
+
+    /* The lock register can only return 0 or 1 when read */
+    return p_wdog->lock;
+}
+
+void arm_watchdog_unlock(struct arm_watchdog_dev_t* dev)
+{
+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
+
+    p_wdog->lock = ARM_WATCHDOG_UNLOCK_VALUE;
+}
+
+inline uint32_t arm_watchdog_is_initialized(struct arm_watchdog_dev_t* dev)
+{
+    return (dev->data->state & ARM_WATCHDOG_INITIALIZED);
+}
+
+uint32_t arm_watchdog_get_remaining_time(struct arm_watchdog_dev_t* dev)
+{
+    struct arm_watchdog_t* p_wdog = (struct arm_watchdog_t*)dev->cfg->base;
+
+    if (!arm_watchdog_is_enabled(dev))
+        return 0;
+
+    if (arm_watchdog_is_locked(dev))
+        return 0;
+
+    return p_wdog->value;
+}
+
+diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.h b/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.h
+new file mode 100644
+index 0000000000..3b163625f5
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/arm_watchdog_drv.h
+@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2016-2020 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file arm_watchdog_drv.h
+ * \brief Generic driver for ARM watchdogs.
+ */
+
+#ifndef __ARM_WATCHDOG_DRV_H__
+#define __ARM_WATCHDOG_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum arm_watchdog_error_t {
+    ARM_WATCHDOG_ERR_NONE = 0,  /*!< No error */
+    ARM_WATCHDOG_ERR_NOT_INIT,  /*!< Watchdog is not initialized */
+    ARM_WATCHDOG_ERR_NOT_ENAB,  /*!< Watchdog is not enabled */
+    ARM_WATCHDOG_ERR_LOCKED     /*!< Watchdog is locked */
+};
+
+/* ARM watchdog device configuration structure */
+struct arm_watchdog_dev_cfg_t {
+    const uint32_t base;  /*!< Watchdog base address */
+};
+
+/* ARM watchdog device data structure */
+struct arm_watchdog_dev_data_t {
+    uint32_t state;    /*!< Indicates if the watchdog
+                            is initialized and enabled */
+    uint32_t timeout;  /*!< Timeout to reset in cycles */
+};
+
+/* ARM watchdog device structure */
+struct arm_watchdog_dev_t {
+    const struct arm_watchdog_dev_cfg_t* const cfg;  /*!< Watchdog
+                                                          configuration */
+    struct arm_watchdog_dev_data_t* const data;      /*!< Watchdog data */
+};
+
+/**
+ * \brief Initializes a watchdog hardware.
+ *
+ * \param[in] dev      Watchdog to be initialized \ref arm_watchdog_dev_t
+ * \param[in] timeout  Timeout in cycles - 0 assings timeout to max value.
+ *
+ * \note This function doesn't check if dev is NULL.
+ *       This function leaves the watchdog locked. Before any further
+ *       operations, it needs to be unlocked and locked again.
+ */
+void arm_watchdog_init(struct arm_watchdog_dev_t* dev, uint32_t timeout);
+
+/**
+ * \brief Feeds the watchdog to not cause a reset.
+ *
+ * \param[in] dev  Watchdog to be fed \ref arm_watchdog_dev_t
+ *
+ * \return Returns error code as specified in \ref arm_watchdog_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_watchdog_error_t arm_watchdog_feed(struct arm_watchdog_dev_t* dev);
+
+/**
+ * \brief Clear the interrupt and load timeout value to the load register.
+ *
+ * \param[in] dev   Watchdog to be fed \ref arm_watchdog_dev_t
+ *
+ * \return Returns error code as specified in \ref arm_watchdog_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_watchdog_error_t
+arm_watchdog_clear_interrupt_and_refresh_counter(
+    struct arm_watchdog_dev_t* dev);
+
+/**
+ * \brief Enables the watchdog.
+ *
+ * \param[in] dev  Watchdog to be enabled \ref arm_watchdog_dev_t
+ *
+ * \return Returns error code as specified in \ref arm_watchdog_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_watchdog_error_t arm_watchdog_enable(struct arm_watchdog_dev_t* dev);
+
+/**
+ * \brief Checks if the watchdog is enabled
+ *
+ * \param[in] dev Watchdog to be checked \ref arm_watchdog_dev_t
+ *
+ * \return 1 if watchdog is enabled, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_watchdog_is_enabled(struct arm_watchdog_dev_t* dev);
+
+/**
+ * \brief Disables the watchdog.
+ *
+ * \param[in] dev  Watchdog to be disabled \ref arm_watchdog_dev_t
+ *
+ * \return 1 if watchdog is enabled, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_watchdog_error_t arm_watchdog_disable(struct arm_watchdog_dev_t* dev);
+
+/**
+ * \brief Locks the registers to not be written again.
+ *
+ * \param[in] dev  Watchdog to be locked \ref arm_watchdog_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_watchdog_lock(struct arm_watchdog_dev_t* dev);
+
+/**
+ * \brief Checks if the watchdog registers are locked
+ *
+ * \param[in] dev Watchdog to be checked \ref arm_watchdog_dev_t
+ *
+ * \return 1 if the registers are locked, 0 otherwise
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_watchdog_is_locked(struct arm_watchdog_dev_t* dev);
+
+/**
+ * \brief Unlocks the registers to configure the watchdog again.
+ *
+ * \param[in] dev  Watchdog to be unlocked \ref arm_watchdog_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_watchdog_unlock(struct arm_watchdog_dev_t* dev);
+
+/**
+ * \brief Gets if watchdog driver is initialized
+ *
+ * \param[in] dev  Watchdog to be initialized \ref arm_watchdog_dev_t
+ *
+ * \returns 1 if watchdog driver is initialized. Otherwise 0.
+ */
+uint32_t arm_watchdog_is_initialized(struct arm_watchdog_dev_t* dev);
+
+/**
+ * \brief Provides watchdog remaining time before reset.
+ *
+ * \param[in] dev  Watchdog to get the remaining time \ref arm_watchdog_dev_t
+ *
+ * \return 0 if watchdog is disabled.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_watchdog_get_remaining_time(struct arm_watchdog_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ARM_WATCHDOG_DRV_H__ */
+
+diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
+new file mode 100644
+index 0000000000..d375af3afb
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
+@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "watchdog.h"
+
+#include "arm_watchdog_drv.h"
+#include "platform_base_address.h"
+#include "Driver_Common.h"
+#include "cmsis.h"
+#include <stdio.h>
+
+/* SoC watchdog config */
+struct arm_watchdog_dev_cfg_t SOC_WD_DEV_CFG = {CORSTONE1000_SOC_WATCHDOG_BASE};
+struct arm_watchdog_dev_data_t SOC_WD_DEV_DATA;
+struct arm_watchdog_dev_t SOC_WD_DEV = {&SOC_WD_DEV_CFG, &SOC_WD_DEV_DATA};
+#define SOC_WD_TIMEOUT 0x00030000
+
+/* SE watchdog config */
+struct arm_watchdog_dev_cfg_t SE_WD_DEV_CFG = {CORSTONE1000_WATCHDOG_TIMER_BASE};
+struct arm_watchdog_dev_data_t SE_WD_DEV_DATA;
+struct arm_watchdog_dev_t SE_WD_DEV = {&SE_WD_DEV_CFG, &SE_WD_DEV_DATA};
+#define SE_WD_TIMEOUT 0x0FFFFFFF
+#define SE_WD_IRQn SE_WATCHDOG_TIMER_IRQn
+
+
+/* SoC watchdog */
+void NMI_Handler(void)
+{
+    /* Unlock, clear and lock the watchdog timer */
+    arm_watchdog_unlock(&SOC_WD_DEV);
+    arm_watchdog_clear_interrupt_and_refresh_counter(&SOC_WD_DEV);
+    arm_watchdog_lock(&SOC_WD_DEV);
+}
+
+/* SE watchdog */
+void SE_WATCHDOG_TIMER_IRQHandler(void)
+{
+    /* Unlock, clear and lock the watchdog timer */
+    arm_watchdog_unlock(&SE_WD_DEV);
+    arm_watchdog_clear_interrupt_and_refresh_counter(&SE_WD_DEV);
+    arm_watchdog_lock(&SE_WD_DEV);
+}
+
+int corstone1000_watchdog_init()
+{
+    __disable_irq();
+
+    /* SoC Watchdog setup */
+    arm_watchdog_init(&SOC_WD_DEV, SOC_WD_TIMEOUT);
+    arm_watchdog_unlock(&SOC_WD_DEV);
+    arm_watchdog_enable(&SOC_WD_DEV);
+    arm_watchdog_lock(&SOC_WD_DEV);
+
+    if (!arm_watchdog_is_initialized(&SOC_WD_DEV))
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    if (!arm_watchdog_is_enabled(&SOC_WD_DEV))
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    /* SE Watchdog setup */
+    arm_watchdog_init(&SE_WD_DEV, SE_WD_TIMEOUT);
+    arm_watchdog_unlock(&SE_WD_DEV);
+    arm_watchdog_enable(&SE_WD_DEV);
+    arm_watchdog_lock(&SE_WD_DEV);
+
+    NVIC_EnableIRQ(SE_WD_IRQn);
+
+    if (!arm_watchdog_is_initialized(&SE_WD_DEV))
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    if (!arm_watchdog_is_enabled(&SE_WD_DEV))
+        return ARM_DRIVER_ERROR_UNSUPPORTED;
+
+    __enable_irq();
+    
+    return ARM_DRIVER_OK;
+}
+diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
+new file mode 100644
+index 0000000000..fd1b7cf124
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
+@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef WATCHDOG_H
+#define WATCHDOG_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include "Driver_Common.h"
+#include "arm_watchdog_drv.h"
+#include "platform_base_address.h"
+
+/**
+ *  \brief Initializes Secure Enclave & SoC Watchdog.
+ *
+ *  \returns ARM Driver return code.
+ */
+int corstone1000_watchdog_init();
+
+/**
+ *  \brief Reset the Secure Enclave & SoC Watchdog's.
+ * 
+ *  \returns ARM Driver return code.
+ */
+int corstone1000_watchdog_reset_timer();
+
+#endif /* watchdog_h */
+diff --git a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+index 92a78c1168..1737fbee91 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/bl1/CMakeLists.txt
+@@ -239,6 +239,8 @@ target_sources(bl1_main
+         ../Native_Driver/firewall.c
+         ../Native_Driver/uart_pl011_drv.c
+         ../fw_update_agent/fwu_agent.c
+        ../Native_Driver/arm_watchdog_drv.c
+        ../Native_Driver/watchdog.c
+         bl1_boot_hal.c
+         bl1_flash_map.c
+         bl1_security_cnt.c
+diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+index 2af5b8c846..edde6fb24e 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_boot_hal.c
+@@ -14,6 +14,7 @@
+ #include "bootutil/fault_injection_hardening.h"
+ #include "bootutil/bootutil_log.h"
+ #include "firewall.h"
+#include "watchdog.h"
+ #include "mpu_config.h"
+ #include "tfm_plat_otp.h"
+ #include "tfm_plat_provisioning.h"
+@@ -589,6 +590,11 @@ int32_t boot_platform_init(void)
+     int32_t result;
+     uint32_t bank_offset;
+ 
+    result = corstone1000_watchdog_init();
+    if (result != ARM_DRIVER_OK) {
+        return 1;
+    }
+
+ #if !(PLATFORM_IS_FVP)
+     setup_mpu();
+ #endif
+diff --git a/platform/ext/target/arm/corstone1000/bl2_boot_hal.c b/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
+index 4f5b48a2e0..5c6b78ffb3 100644
+--- a/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
+++ b/platform/ext/target/arm/corstone1000/bl2_boot_hal.c
+@@ -15,6 +15,7 @@
+ #include "bootutil/bootutil_log.h"
+ #include "fip_parser.h"
+ #include "flash_map/flash_map.h"
+#include "watchdog.h"
+ #include <string.h>
+ #include "tfm_plat_otp.h"
+ #include "tfm_plat_provisioning.h"
+@@ -115,6 +116,11 @@ int32_t boot_platform_init(void)
+     enum tfm_plat_err_t plat_err;
+     uint32_t bank_offset;
+ 
+    result = corstone1000_watchdog_init();
+    if (result != ARM_DRIVER_OK) {
+        return 1;
+    }
+
+     result = fill_bl2_flash_map_by_parsing_fips(BANK_0_PARTITION_OFFSET);
+     if (result) {
+         return 1;
+diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+index 0072b5b928..7faa71eb63 100644
+--- a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+++ b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+@@ -9,12 +9,17 @@
+ #include "tfm_hal_platform.h"
+ #include "uart_stdout.h"
+ #include "fwu_agent.h"
+#include "watchdog.h"
+ 
+ enum tfm_hal_status_t tfm_hal_platform_init(void)
+ {
+     __enable_irq();
+     stdio_init();
+ 
+    if (corstone1000_watchdog_init()) {
+        return TFM_HAL_ERROR_GENERIC;
+    }
+
+     if (fwu_metadata_init()) {
+         return TFM_HAL_ERROR_GENERIC;
+     }
+-- 
+2.17.1
+
@@ -0,0 +1,119 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 9b2b4e284d36d0433f5aa0af6f13e7eda5c783c0 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Thu, 14 Oct 2021 05:08:04 +0100
+Subject: [PATCH 08/15] corstone1000: impelment accept image logic
+
+Until all new images in the update/trial bank is accepted,
+the firmware update state of the system remains in the trial
+state. The state changes automatically to regular state when
+all new images in the trial bank is accepted.
+
+This commit adds the logic to accept one of the image type.
+
+Change-Id: I1f18d77b185f2e5dd26d6e02bed792689019b7b8
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 70 +++++++++++++++++++
+ .../services/src/tfm_platform_system.c        |  2 +-
+ 2 files changed, 71 insertions(+), 1 deletion(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index 23a15ee71b..a70638e993 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -537,6 +537,76 @@ out:
+     return ret;
+ }
+ 
+static enum fwu_agent_error_t accept_full_capsule(
+          struct fwu_metadata* metadata,
+          struct fwu_private_metadata* priv_metadata)
+{
+    uint32_t active_index = metadata->active_index;
+    enum fwu_agent_error_t ret;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+        metadata->img_entry[i].img_props[active_index].accepted =
+                                                            IMAGE_ACCEPTED;
+    }
+
+    priv_metadata->boot_attempted = 0;
+
+    ret = private_metadata_write(priv_metadata);
+    if (ret) {
+        return ret;
+    }
+
+    ret = metadata_write(metadata);
+    if (ret) {
+        return ret;
+    }
+
+    FWU_LOG_MSG("%s: exit: fwu state is changed to regular\n\r", __func__);
+    return FWU_AGENT_SUCCESS;
+}
+
+static enum fwu_agent_error_t fwu_accept_image(struct efi_guid* guid,
+        struct fwu_metadata *metadata,
+        struct fwu_private_metadata *priv_metadata)
+{
+    enum fwu_agent_state_t current_state;
+    int image_index;
+    uint32_t image_bank_offset;
+    enum fwu_agent_error_t ret;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    /* it is expected to receive this call only when
+       in trial state */
+    current_state = get_fwu_agent_state(metadata, priv_metadata);
+    if (current_state != FWU_AGENT_STATE_TRIAL) {
+        return FWU_AGENT_ERROR;
+    }
+
+    /* booted from previous_active_bank, not expected
+     * to receive this call in this state, rather host should
+     * call corstone1000_fwu_select_previous */
+    if (metadata->active_index != priv_metadata->boot_index) {
+        return FWU_AGENT_ERROR;
+    }
+
+    image_index = get_image_info_in_bank(guid, &image_bank_offset);
+    switch(image_index) {
+        case IMAGE_ALL:
+            ret = accept_full_capsule(metadata, priv_metadata);
+            break;
+        default:
+            FWU_LOG_MSG("%s: sent image not recognized\n\r", __func__);
+            ret = FWU_AGENT_ERROR;
+            break;
+    }
+
+    FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
+    return ret;
+}
+
+ void bl1_get_boot_bank(uint32_t *bank_offset)
+ {
+     struct fwu_private_metadata priv_metadata;
+diff --git a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+index f9629a1688..16ad975c32 100644
+--- a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+++ b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+@@ -21,7 +21,7 @@ enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
+                                                psa_outvec *out_vec)
+ {
+     int32_t ret = TFM_PLATFORM_ERR_SUCCESS;
+-    const corstone1000_ioctl_in_params_t *in_params =
+    corstone1000_ioctl_in_params_t *in_params =
+                                     (corstone1000_ioctl_in_params_t *)in_vec->base;
+     corstone1000_ioctl_out_params_t *out_params = (corstone1000_ioctl_out_params_t *)out_vec->base;
+ 
+-- 
+2.17.1
+
@@ -0,0 +1,91 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From a565999300cf5d40c772d3ff29e2020b786a2a10 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Sat, 16 Oct 2021 09:07:17 +0100
+Subject: [PATCH 09/15] corstone1000: implement select previous bank logic
+
+When firmware update process is not successful, the commit logic
+reverts the system state to previous active bank. With this,
+the state of the system also changes from the trial to regular
+state. System gets reverted back to its previous known good state.
+
+Change-Id: I265635ea984ae9542518a0e389c98e1242e78d10
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 58 +++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index a70638e993..89f0a08eb5 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -607,6 +607,64 @@ static enum fwu_agent_error_t fwu_accept_image(struct efi_guid* guid,
+     return ret;
+ }
+ 
+static enum fwu_agent_error_t fwu_select_previous(
+        struct fwu_metadata *metadata,
+        struct fwu_private_metadata *priv_metadata)
+{
+    enum fwu_agent_error_t ret;
+    enum fwu_agent_state_t current_state;
+    uint32_t index;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    /* it is expected to receive this call only when
+       in trial state */
+    current_state = get_fwu_agent_state(metadata, priv_metadata);
+    if (current_state != FWU_AGENT_STATE_TRIAL) {
+        return FWU_AGENT_ERROR;
+    }
+
+    /* not expected to receive this call in this state, system
+     * did not boot from previous active index */
+    if (metadata->previous_active_index != priv_metadata->boot_index) {
+        return FWU_AGENT_ERROR;
+    }
+
+    FWU_LOG_MSG("%s: trial state: active index = %u, previous active = %u\n\r",
+            __func__, metadata->active_index, metadata->previous_active_index);
+
+    index = metadata->previous_active_index;
+    for (int i = 0; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+        if (metadata->img_entry[i].img_props[index].accepted != IMAGE_ACCEPTED)
+        {
+            FWU_ASSERT(0);
+        }
+    }
+
+    index = metadata->active_index;
+    metadata->active_index = metadata->previous_active_index;
+    metadata->previous_active_index = index;
+
+    priv_metadata->boot_attempted = 0;
+
+    ret = private_metadata_write(priv_metadata);
+    if (ret) {
+        return ret;
+    }
+
+    ret = metadata_write(metadata);
+    if (ret) {
+        return ret;
+    }
+
+    FWU_LOG_MSG("%s: in regular state by choosing previous active bank\n\r",
+                 __func__);
+
+    FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
+    return ret;
+
+}
+
+ void bl1_get_boot_bank(uint32_t *bank_offset)
+ {
+     struct fwu_private_metadata priv_metadata;
+-- 
+2.17.1
+
@@ -0,0 +1,136 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 0a4c27173e9ac31e6bfe424b6856c4dc612e247a Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Tue, 16 Nov 2021 04:56:52 +0000
+Subject: [PATCH 10/15] corstone1000: implement corstone1000_fwu_host_ack
+
+The host uses the api 'corstone1000_fwu_host_ack' to acknowledge its
+successful boot to the secure enclave. Based on the fwu state of
+the system, the secure enalve decides where to move in the fwu state
+machine. If in regular state, there is nothing to be done. If in
+trial state and firmware update is a success, state moves to regular
+by accepting images in the trial/update bank. Finaly if in trial
+state and firmware update is a failure, state moves to regular by
+reverting to previous known state.
+
+Change-Id: I16657537909916bd19520eac3899501fdb14ecb4
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 47 +++++++++++++++++++
+ .../corstone1000/fw_update_agent/fwu_agent.h  |  5 ++
+ .../services/src/tfm_platform_system.c        | 14 +++++-
+ 3 files changed, 64 insertions(+), 2 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index 89f0a08eb5..5e87fd8d5e 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -762,3 +762,50 @@ void bl2_get_boot_bank(uint32_t *bank_offset)
+     return;
+ }
+ 
+enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+{
+    enum fwu_agent_error_t ret;
+    struct fwu_private_metadata priv_metadata;
+    enum fwu_agent_state_t current_state;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    if (!is_initialized) {
+        return FWU_AGENT_ERROR;
+    }
+
+    Select_Write_Mode_For_Shared_Flash();
+
+    if (metadata_read(&_metadata)) {
+        ret = FWU_AGENT_ERROR;
+        goto out;
+    }
+
+    if (private_metadata_read(&priv_metadata)) {
+        ret = FWU_AGENT_ERROR;
+        goto out;
+    }
+
+    current_state = get_fwu_agent_state(&_metadata, &priv_metadata);
+    if (current_state == FWU_AGENT_STATE_REGULAR) {
+        ret = FWU_AGENT_SUCCESS; /* nothing to be done */
+        goto out;
+    } else if (current_state != FWU_AGENT_STATE_TRIAL) {
+        FWU_ASSERT(0);
+    }
+
+    if (_metadata.active_index != priv_metadata.boot_index) {
+        /* firmware update failed, revert back to previous bank */
+        ret = fwu_select_previous(&_metadata, &priv_metadata);
+    } else {
+        /* firmware update successful */
+        ret = fwu_accept_image(&full_capsule_image_guid, &_metadata,
+                                &priv_metadata);
+    }
+
+out:
+    Select_XIP_Mode_For_Shared_Flash();
+
+    FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
+    return ret;
+}
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+index 389381c326..b8f7c676d7 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+@@ -38,6 +38,11 @@ enum fwu_agent_error_t fwu_metadata_init(void);
+  */
+ enum fwu_agent_error_t corstone1000_fwu_flash_image(void);
+ 
+/* host to secure enclave:
+ * host responds with this api to acknowledge its successful
+ * boot.
+ */
+enum fwu_agent_error_t corstone1000_fwu_host_ack(void);
+ 
+ void bl1_get_boot_bank(uint32_t *bank_offset);
+ void bl2_get_boot_bank(uint32_t *bank_offset);
+diff --git a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+index 16ad975c32..068234dcda 100644
+--- a/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+++ b/platform/ext/target/arm/corstone1000/services/src/tfm_platform_system.c
+@@ -21,20 +21,30 @@ enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
+                                                psa_outvec *out_vec)
+ {
+     int32_t ret = TFM_PLATFORM_ERR_SUCCESS;
+
+     corstone1000_ioctl_in_params_t *in_params =
+-                                    (corstone1000_ioctl_in_params_t *)in_vec->base;
+-    corstone1000_ioctl_out_params_t *out_params = (corstone1000_ioctl_out_params_t *)out_vec->base;
+                              (corstone1000_ioctl_in_params_t *)in_vec->base;
+
+    corstone1000_ioctl_out_params_t *out_params =
+                              (corstone1000_ioctl_out_params_t *)out_vec->base;
+ 
+     switch(in_params->ioctl_id) {
+
+         case IOCTL_CORSTONE1000_FWU_FLASH_IMAGES:
+             out_params->result = corstone1000_fwu_flash_image();
+             if (!out_params->result) {
+                 NVIC_SystemReset();
+             }
+             break;
+
+        case IOCTL_CORSTONE1000_FWU_HOST_ACK:
+            out_params->result = corstone1000_fwu_host_ack();
+            break;
+
+         default:
+             ret = TFM_PLATFORM_ERR_NOT_SUPPORTED;
+             break;
+
+     }
+ 
+     return ret;
+-- 
+2.17.1
+
@@ -0,0 +1,39 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 35ab33099d7b091630ec677cbad57abd60105f91 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Sun, 14 Nov 2021 11:49:11 +0000
+Subject: [PATCH 11/15] SPM: multiple core: initailize multi-core communication
+ before the non-secure core is out of rest
+
+Tf-m should be ready to receive the communication before non-secure
+has been taken out of rest.
+
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+Change-Id: I0b609fffbed0fc2f09b521389fd50f4e992ad00d
+---
+ secure_fw/spm/cmsis_psa/tfm_multi_core.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/secure_fw/spm/cmsis_psa/tfm_multi_core.c b/secure_fw/spm/cmsis_psa/tfm_multi_core.c
+index f830a6f5f7..946d1a60eb 100644
+--- a/secure_fw/spm/cmsis_psa/tfm_multi_core.c
+++ b/secure_fw/spm/cmsis_psa/tfm_multi_core.c
+@@ -25,11 +25,11 @@ void tfm_nspm_thread_entry(void)
+     SPMLOG_DBGMSG("Enabling non-secure core...");
+ #endif
+ 
+    tfm_inter_core_comm_init();
+
+     tfm_hal_boot_ns_cpu(tfm_spm_hal_get_ns_VTOR());
+     tfm_hal_wait_for_ns_cpu_ready();
+ 
+-    tfm_inter_core_comm_init();
+-
+     /*
+      * TODO
+      * The infinite-loop can be replaced with platform-specific low-power sleep
+-- 
+2.17.1
+
@@ -0,0 +1,169 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 1a891fc818526bfb8b546c86a93b81353330a466 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Mon, 8 Nov 2021 18:10:44 +0000
+Subject: [PATCH 12/15] corstone1000: implement timer to track host progress
+
+When in fwu trial state, the secure enclave starts the timer to
+keep track of host progress. Secure enclave expects that the host
+acknowledges before the timer expires. If host fails to do so,
+the secure enclave resets the system.
+
+Change-Id: Ib63778b6c813f1b0d3517e0c05226d6f88927b04
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../corstone1000/fw_update_agent/fwu_agent.c  | 78 +++++++++++++++++++
+ .../corstone1000/fw_update_agent/fwu_agent.h  |  7 ++
+ .../arm/corstone1000/tfm_hal_multi_core.c     |  5 +-
+ 3 files changed, 89 insertions(+), 1 deletion(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index 5e87fd8d5e..e8686704b8 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -15,6 +15,7 @@
+ #include "uefi_capsule_parser.h"
+ #include "flash_common.h"
+ #include "platform_base_address.h"
+#include "platform_description.h"
+ 
+ /* Properties of image in a bank */
+ struct fwu_image_properties {
+@@ -127,6 +128,8 @@ struct efi_guid full_capsule_image_guid = {
+ /* Import the CMSIS flash device driver */
+ extern ARM_DRIVER_FLASH FWU_METADATA_FLASH_DEV;
+ 
+#define HOST_ACK_TIMEOUT_SEC    (6 * 60) /* ~seconds, not exact */
+
+ static enum fwu_agent_error_t private_metadata_read(
+         struct fwu_private_metadata* p_metadata)
+ {
+@@ -762,6 +765,13 @@ void bl2_get_boot_bank(uint32_t *bank_offset)
+     return;
+ }
+ 
+static void disable_host_ack_timer(void)
+{
+    FWU_LOG_MSG("%s: timer to reset is disabled\n\r", __func__);
+    SysTick->CTRL &= (~SysTick_CTRL_ENABLE_Msk);
+}
+
+
+ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+ {
+     enum fwu_agent_error_t ret;
+@@ -803,9 +813,77 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+                                 &priv_metadata);
+     }
+ 
+    if (ret == FWU_AGENT_SUCCESS) {
+        disable_host_ack_timer();
+    }
+
+ out:
+     Select_XIP_Mode_For_Shared_Flash();
+ 
+     FWU_LOG_MSG("%s: exit: ret = %d\n\r", __func__, ret);
+     return ret;
+ }
+
+static int systic_counter = 0;
+
+void SysTick_Handler(void)
+{
+    systic_counter++;
+    if ((systic_counter % 10) == 0) {
+        FWU_LOG_MSG("%s: counted = %d, expiring on = %u\n\r", __func__,
+                                systic_counter, HOST_ACK_TIMEOUT_SEC);
+    }
+    if (systic_counter == HOST_ACK_TIMEOUT_SEC) {
+        FWU_LOG_MSG("%s, timer expired, reseting the system\n\r", __func__);
+        NVIC_SystemReset();
+    }
+}
+
+/* When in trial state, start the timer for host to respond.
+ * Diable timer when host responds back either by calling
+ * corstone1000_fwu_accept_image or corstone1000_fwu_select_previous.
+ * Otherwise, resets the system.
+ */
+void host_acknowledgement_timer_to_reset(void)
+{
+    struct fwu_private_metadata priv_metadata;
+    enum fwu_agent_state_t current_state;
+    uint32_t boot_attempted;
+    uint32_t boot_index;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    Select_Write_Mode_For_Shared_Flash();
+
+    if (!is_initialized) {
+        FWU_ASSERT(0);
+    }
+
+    if (private_metadata_read(&priv_metadata)) {
+        FWU_ASSERT(0);
+    }
+
+    if (metadata_read(&_metadata)) {
+        FWU_ASSERT(0);
+    }
+
+    Select_XIP_Mode_For_Shared_Flash();
+
+    current_state = get_fwu_agent_state(&_metadata, &priv_metadata);
+
+    if (current_state == FWU_AGENT_STATE_TRIAL) {
+        FWU_LOG_MSG("%s: in trial state, starting host ack timer\n\r",
+                        __func__);
+        systic_counter = 0;
+        if (SysTick_Config(SysTick_LOAD_RELOAD_Msk)) {
+            FWU_LOG_MSG("%s: timer init failed\n\r", __func__);
+            FWU_ASSERT(0);
+        } else {
+            FWU_LOG_MSG("%s: timer started: seconds to expire : %u\n\r",
+                        __func__, HOST_ACK_TIMEOUT_SEC);
+        }
+    }
+
+    FWU_LOG_MSG("%s: exit\n\r", __func__);
+    return;
+}
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+index b8f7c676d7..80f72e2bd6 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+@@ -47,4 +47,11 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void);
+ void bl1_get_boot_bank(uint32_t *bank_offset);
+ void bl2_get_boot_bank(uint32_t *bank_offset);
+ 
+/* When in trial state, start the timer for host to respond.
+ * Diable timer when host responds back either by calling
+ * corstone1000_fwu_accept_image or corstone1000_fwu_select_previous.
+ * Otherwise, resets the system.
+ */
+void host_acknowledgement_timer_to_reset(void);
+
+ #endif /* FWU_AGENT_H */
+diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+index 834ebc33e3..cc94055b94 100644
+--- a/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+++ b/platform/ext/target/arm/corstone1000/tfm_hal_multi_core.c
+@@ -56,7 +56,10 @@ void tfm_hal_boot_ns_cpu(uintptr_t start_addr)
+ 
+ void tfm_hal_wait_for_ns_cpu_ready(void)
+ {
+-    /* Synchronization between Host and SE is done by OpenAMP */
+    /* start the reset timer if firwmare update process is ongoing */
+#if !(PLATFORM_IS_FVP)
+    host_acknowledgement_timer_to_reset();
+#endif
+ }
+ 
+ void tfm_hal_get_mem_security_attr(const void *p, size_t s,
+-- 
+2.17.1
+
@@ -0,0 +1,369 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From eb02f01cd9095f11bbd737db8b1723358e463d73 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Wed, 17 Nov 2021 07:30:26 +0000
+Subject: [PATCH 13/15] corstone1000: fwu nv-counter anti-rollback support
+
+The patch implements anti-rollback protection on the nv-counters.
+The nv-counters are staged onto the flash, and only updated when
+firmware update process is successful. Before update, one more
+time verification is performed.
+
+Change-Id: Ibe9df7f65c7aecdb9d712bd76c4dbff4e8fd1023
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ .../target/arm/corstone1000/CMakeLists.txt    |   1 +
+ .../arm/corstone1000/bl1/bl1_security_cnt.c   |  20 ++-
+ .../arm/corstone1000/bl2_security_cnt.c       | 114 ++++++++++++++++++
+ .../ext/target/arm/corstone1000/config.cmake  |   2 +
+ .../corstone1000/fw_update_agent/fwu_agent.c  |  95 +++++++++++++++
+ .../corstone1000/fw_update_agent/fwu_agent.h  |  16 +++
+ 6 files changed, 245 insertions(+), 3 deletions(-)
+ create mode 100644 platform/ext/target/arm/corstone1000/bl2_security_cnt.c
+
+diff --git a/platform/ext/target/arm/corstone1000/CMakeLists.txt b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+index cb66bd48d6..7b1ee53b15 100644
+--- a/platform/ext/target/arm/corstone1000/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/CMakeLists.txt
+@@ -114,6 +114,7 @@ target_sources(platform_bl2
+         fip_parser/fip_parser.c
+         bl2_boot_hal.c
+         fw_update_agent/fwu_agent.c
+        bl2_security_cnt.c
+ )
+ 
+ if (PLATFORM_IS_FVP)
+diff --git a/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c b/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c
+index f275cbfecb..e56defa09a 100644
+--- a/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c
+++ b/platform/ext/target/arm/corstone1000/bl1/bl1_security_cnt.c
+@@ -10,6 +10,8 @@
+ #include "tfm_plat_defs.h"
+ #include "bootutil/fault_injection_hardening.h"
+ #include <stdint.h>
+#include "tfm_plat_provisioning.h"
+#include "fwu_agent.h"
+ 
+ fih_int boot_nv_security_counter_init(void)
+ {
+@@ -47,14 +49,26 @@ int32_t boot_nv_security_counter_update(uint32_t image_id,
+                                         uint32_t img_security_cnt)
+ {
+     enum tfm_plat_err_t err;
+    enum fwu_agent_error_t fwu_err;
+ 
+     if (image_id != 0) {
+         return -1;
+     }
+ 
+-    err = tfm_plat_set_nv_counter(PLAT_NV_COUNTER_BL1_0, img_security_cnt);
+-    if (err != TFM_PLAT_ERR_SUCCESS) {
+-        return -1;
+    if (tfm_plat_provisioning_is_required()) {
+
+        err = tfm_plat_set_nv_counter(PLAT_NV_COUNTER_BL1_0, img_security_cnt);
+        if (err != TFM_PLAT_ERR_SUCCESS) {
+            return -1;
+        }
+
+    } else {
+
+        fwu_err = fwu_stage_nv_counter(FWU_BL2_NV_COUNTER, img_security_cnt);
+        if (fwu_err != FWU_AGENT_SUCCESS) {
+            return -1;
+        }
+
+     }
+ 
+     return 0;
+diff --git a/platform/ext/target/arm/corstone1000/bl2_security_cnt.c b/platform/ext/target/arm/corstone1000/bl2_security_cnt.c
+new file mode 100644
+index 0000000000..adb0c13039
+--- /dev/null
+++ b/platform/ext/target/arm/corstone1000/bl2_security_cnt.c
+@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "bootutil/security_cnt.h"
+#include "tfm_plat_nv_counters.h"
+#include "tfm_plat_defs.h"
+#include "bootutil/fault_injection_hardening.h"
+#include <stdint.h>
+#include "tfm_plat_provisioning.h"
+#include "fwu_agent.h"
+
+#define TFM_BOOT_NV_COUNTER_0    PLAT_NV_COUNTER_BL2_0   /* NV counter of Image 0 */
+#define TFM_BOOT_NV_COUNTER_1    PLAT_NV_COUNTER_BL2_1   /* NV counter of Image 1 */
+#define TFM_BOOT_NV_COUNTER_2    PLAT_NV_COUNTER_BL2_2   /* NV counter of Image 2 */
+#define TFM_BOOT_NV_COUNTER_MAX  PLAT_NV_COUNTER_BL2_2 + 1
+
+static enum tfm_nv_counter_t get_nv_counter_from_image_id(uint32_t image_id)
+{
+    uint32_t nv_counter;
+
+    /* Avoid integer overflow */
+    if ((UINT32_MAX - TFM_BOOT_NV_COUNTER_0) < image_id) {
+        return TFM_BOOT_NV_COUNTER_MAX;
+    }
+
+    nv_counter = TFM_BOOT_NV_COUNTER_0 + image_id;
+
+    /* Check the existence of the enumerated counter value */
+    if (nv_counter >= TFM_BOOT_NV_COUNTER_MAX) {
+        return TFM_BOOT_NV_COUNTER_MAX;
+    }
+
+    return (enum tfm_nv_counter_t)nv_counter;
+}
+
+fih_int boot_nv_security_counter_init(void)
+{
+    fih_int fih_rc = FIH_FAILURE;
+
+    fih_rc = fih_int_encode_zero_equality(tfm_plat_init_nv_counter());
+
+    FIH_RET(fih_rc);
+}
+
+fih_int boot_nv_security_counter_get(uint32_t image_id, fih_int *security_cnt)
+{
+    enum tfm_nv_counter_t nv_counter;
+    fih_int fih_rc = FIH_FAILURE;
+    uint32_t security_cnt_soft;
+
+    /* Check if it's a null-pointer. */
+    if (!security_cnt) {
+        FIH_RET(FIH_FAILURE);
+    }
+
+    nv_counter = get_nv_counter_from_image_id(image_id);
+    if (nv_counter >= TFM_BOOT_NV_COUNTER_MAX) {
+        FIH_RET(FIH_FAILURE);
+    }
+
+    fih_rc = fih_int_encode_zero_equality(
+             tfm_plat_read_nv_counter(nv_counter,
+                                      sizeof(security_cnt_soft),
+                                      (uint8_t *)&security_cnt_soft));
+    *security_cnt = fih_int_encode(security_cnt_soft);
+
+    printf("%s: security_cnt=%d\n\r", __func__, *security_cnt);
+
+    FIH_RET(fih_rc);
+}
+
+int32_t boot_nv_security_counter_update(uint32_t image_id,
+                                        uint32_t img_security_cnt)
+{
+    enum tfm_nv_counter_t nv_counter;
+    enum tfm_plat_err_t err;
+    enum fwu_agent_error_t fwu_err;
+
+    nv_counter = get_nv_counter_from_image_id(image_id);
+    if (nv_counter >= TFM_BOOT_NV_COUNTER_MAX) {
+        return -1;
+    }
+
+    printf("%s: security_cnt=%u:%u\n\r", __func__, nv_counter, img_security_cnt);
+
+    if (tfm_plat_provisioning_is_required()) {
+
+        err = tfm_plat_set_nv_counter(nv_counter, img_security_cnt);
+        if (err != TFM_PLAT_ERR_SUCCESS) {
+            return -1;
+        }
+
+    } else {
+
+        if (nv_counter == PLAT_NV_COUNTER_BL2_0) {
+            fwu_err = fwu_stage_nv_counter(FWU_TFM_NV_COUNTER, img_security_cnt);
+        } else if (nv_counter == PLAT_NV_COUNTER_BL2_1) {
+            fwu_err = fwu_stage_nv_counter(FWU_TFA_NV_COUNTER, img_security_cnt);
+        } else {
+            return -1;
+        }
+
+        if (fwu_err != FWU_AGENT_SUCCESS) {
+            return -1;
+        }
+
+    }
+
+    return 0;
+}
+diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
+index 203e6b79a6..d6f3ef7d21 100644
+--- a/platform/ext/target/arm/corstone1000/config.cmake
+++ b/platform/ext/target/arm/corstone1000/config.cmake
+@@ -39,3 +39,5 @@ if (${PLATFORM_IS_FVP})
+ else()
+     set(PLATFORM_PSA_ADAC_SECURE_DEBUG      FALSE        CACHE BOOL      "Whether to use psa-adac secure debug.")
+ endif()
+
+set(DEFAULT_MCUBOOT_SECURITY_COUNTERS   OFF          CACHE BOOL      "Whether to use the default security counter configuration defined by TF-M project")
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+index e8686704b8..cd7f901287 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c
+@@ -16,6 +16,8 @@
+ #include "flash_common.h"
+ #include "platform_base_address.h"
+ #include "platform_description.h"
+#include "tfm_plat_nv_counters.h"
+#include "tfm_plat_defs.h"
+ 
+ /* Properties of image in a bank */
+ struct fwu_image_properties {
+@@ -79,6 +81,9 @@ struct fwu_private_metadata {
+        /* counter: tracking number of boot attempted so far */
+        uint32_t boot_attempted;
+ 
+       /* staged nv_counter: temprary location before written to the otp */
+       uint32_t nv_counter[NR_OF_IMAGES_IN_FW_BANK];
+
+ } __packed;
+ 
+ #define MAX_BOOT_ATTEMPTS_PER_BANK 3
+@@ -771,6 +776,56 @@ static void disable_host_ack_timer(void)
+     SysTick->CTRL &= (~SysTick_CTRL_ENABLE_Msk);
+ }
+ 
+static enum fwu_agent_error_t update_nv_counters(
+                        struct fwu_private_metadata* priv_metadata)
+{
+    enum tfm_plat_err_t err;
+    uint32_t security_cnt;
+    enum tfm_nv_counter_t tfm_nv_counter_i;
+
+    FWU_LOG_MSG("%s: enter\n\r", __func__);
+
+    for (int i = 0; i <= FWU_MAX_NV_COUNTER_INDEX; i++) {
+
+        switch (i) {
+            case FWU_BL2_NV_COUNTER:
+                tfm_nv_counter_i = PLAT_NV_COUNTER_BL1_0;
+                break;
+            case FWU_TFM_NV_COUNTER:
+                tfm_nv_counter_i = PLAT_NV_COUNTER_BL2_0;
+                break;
+            case FWU_TFA_NV_COUNTER:
+                tfm_nv_counter_i = PLAT_NV_COUNTER_BL2_1;
+                break;
+            default:
+                FWU_ASSERT(0);
+                break;
+        }
+
+        err = tfm_plat_read_nv_counter(tfm_nv_counter_i,
+                        sizeof(security_cnt), (uint8_t *)&security_cnt);
+        if (err != TFM_PLAT_ERR_SUCCESS) {
+            return FWU_AGENT_ERROR;
+        }
+
+        if (priv_metadata->nv_counter[i] < security_cnt) {
+            return FWU_AGENT_ERROR;
+        } else if (priv_metadata->nv_counter[i] > security_cnt) {
+            FWU_LOG_MSG("%s: updaing index = %u nv counter = %u->%u\n\r",
+                        __func__, i, security_cnt,
+                        priv_metadata->nv_counter[FWU_BL2_NV_COUNTER]);
+            err = tfm_plat_set_nv_counter(tfm_nv_counter_i,
+                                    priv_metadata->nv_counter[FWU_BL2_NV_COUNTER]);
+            if (err != TFM_PLAT_ERR_SUCCESS) {
+                return FWU_AGENT_ERROR;
+            }
+        }
+
+    }
+
+    FWU_LOG_MSG("%s: exit\n\r", __func__);
+    return FWU_AGENT_SUCCESS;
+}
+ 
+ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+ {
+@@ -811,6 +866,9 @@ enum fwu_agent_error_t corstone1000_fwu_host_ack(void)
+         /* firmware update successful */
+         ret = fwu_accept_image(&full_capsule_image_guid, &_metadata,
+                                 &priv_metadata);
+        if (!ret) {
+            ret = update_nv_counters(&priv_metadata);
+        }
+     }
+ 
+     if (ret == FWU_AGENT_SUCCESS) {
+@@ -887,3 +945,40 @@ void host_acknowledgement_timer_to_reset(void)
+     FWU_LOG_MSG("%s: exit\n\r", __func__);
+     return;
+ }
+
+/* stage nv counter into private metadata section of the flash.
+ * staged nv counters are written to the otp when firmware update
+ * is successful
+ * the function assumes that the api is called in the boot loading
+ * stage
+ */
+enum fwu_agent_error_t fwu_stage_nv_counter(enum fwu_nv_counter_index_t index,
+        uint32_t img_security_cnt)
+{
+    struct fwu_private_metadata priv_metadata;
+
+    FWU_LOG_MSG("%s: enter: index = %u, val = %u\n\r", __func__,
+                                index, img_security_cnt);
+
+    if (!is_initialized) {
+        FWU_ASSERT(0);
+    }
+
+    if (index > FWU_MAX_NV_COUNTER_INDEX) {
+        return FWU_AGENT_ERROR;
+    }
+
+    if (private_metadata_read(&priv_metadata)) {
+        FWU_ASSERT(0);
+    }
+
+    if (priv_metadata.nv_counter[index] != img_security_cnt) {
+        priv_metadata.nv_counter[index] = img_security_cnt;
+        if (private_metadata_write(&priv_metadata)) {
+            FWU_ASSERT(0);
+        }
+    }
+
+    FWU_LOG_MSG("%s: exit\n\r", __func__);
+    return FWU_AGENT_SUCCESS;
+}
+diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+index 80f72e2bd6..57b07e8d2c 100644
+--- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.h
+@@ -54,4 +54,20 @@ void bl2_get_boot_bank(uint32_t *bank_offset);
+  */
+ void host_acknowledgement_timer_to_reset(void);
+ 
+enum fwu_nv_counter_index_t {
+    FWU_BL2_NV_COUNTER = 0,
+    FWU_TFM_NV_COUNTER,
+    FWU_TFA_NV_COUNTER,
+    FWU_MAX_NV_COUNTER_INDEX = FWU_TFA_NV_COUNTER
+};
+
+/* stage nv counter into private metadata section of the flash.
+ * staged nv counters are written to the otp when firmware update
+ * is successful
+ * the function assumes that the api is called in the boot loading
+ * stage
+ */
+enum fwu_agent_error_t fwu_stage_nv_counter(enum fwu_nv_counter_index_t index,
+        uint32_t img_security_cnt);
+
+ #endif /* FWU_AGENT_H */
+-- 
+2.17.1
+
@@ -0,0 +1,50 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 55d0c63bf6b097b6853e93355f5a1524df56f47b Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Mon, 1 Nov 2021 08:03:42 +0000
+Subject: [PATCH 14/15] corstone1000: bug fix in openamp version
+
+Typing mistake in openamp version parameter, leads the cmake
+to fetch the head of the master branch.
+
+Also, the previous hash used for code version is deleted from the
+openamp github. New hash from the master branch is in use.
+
+Change-Id: Iee5980ba14f8bb9b964eb10c71ebb68664c1d441
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ platform/ext/target/arm/corstone1000/config.cmake               | 2 +-
+ .../arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt      | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/platform/ext/target/arm/corstone1000/config.cmake b/platform/ext/target/arm/corstone1000/config.cmake
+index d6f3ef7d21..2dab210e0a 100644
+--- a/platform/ext/target/arm/corstone1000/config.cmake
+++ b/platform/ext/target/arm/corstone1000/config.cmake
+@@ -32,7 +32,7 @@ set(LIBMETAL_SRC_PATH                   "DOWNLOAD"  CACHE PATH      "Path to Lib
+ set(LIBMETAL_VERSION                    "f252f0e007fbfb8b3a52b1d5901250ddac96baad"  CACHE STRING    "The version of libmetal to use")
+ 
+ set(LIBOPENAMP_SRC_PATH                 "DOWNLOAD"  CACHE PATH      "Path to Libopenamp (or DOWNLOAD to fetch automatically")
+-set(OPENAMP_VERSION                     "33037b04e0732e58fc0fa36afc244999ef632e10"  CACHE STRING    "The version of openamp to use")
+set(OPENAMP_VERSION                     "347397decaa43372fc4d00f965640ebde042966d"  CACHE STRING    "The version of openamp to use")
+ 
+ if (${PLATFORM_IS_FVP})
+     set(PLATFORM_PSA_ADAC_SECURE_DEBUG      FALSE        CACHE BOOL      "Whether to use psa-adac secure debug.")
+diff --git a/platform/ext/target/arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt b/platform/ext/target/arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt
+index d91dc7d845..9b1602a04f 100644
+--- a/platform/ext/target/arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt
+++ b/platform/ext/target/arm/corstone1000/openamp/ext/libopenamp/CMakeLists.txt
+@@ -16,7 +16,7 @@ endif()
+ if ("${LIBOPENAMP_SRC_PATH}" STREQUAL "DOWNLOAD")
+     FetchContent_Declare(libopenamp
+         GIT_REPOSITORY https://github.com/OpenAMP/open-amp.git
+-        GIT_TAG ${OEPNAMP_VERSION}
+        GIT_TAG ${OPENAMP_VERSION}
+     )
+ 
+     FetchContent_GetProperties(libopenamp)
+-- 
+2.17.1
+
@@ -0,0 +1,80 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From c33289422948ccb0bd6985512e5d0fc6936c0cd1 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Thu, 18 Nov 2021 12:49:10 +0000
+Subject: [PATCH 15/15] corstone1000: secure host watchdog interrupt handler
+
+With this commit, the host secure watchdog interrupt 1
+(WS1) will be handled by the secure enclave. The commit
+implements and enables the SECURE_WATCHDOG_WS1_IRQHandler
+in NVIC controller. The host can now trigger a reboot
+using the secure watchdog.
+
+Change-Id: Ied82cc04496f5daf678ad1cdc7bcf6d3a7879186
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+---
+ .../arm/corstone1000/Native_Driver/watchdog.c   | 17 +++++++++++++++++
+ .../arm/corstone1000/Native_Driver/watchdog.h   |  9 +++++++++
+ .../target/arm/corstone1000/tfm_hal_platform.c  |  2 ++
+ 3 files changed, 28 insertions(+)
+
+diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
+index d375af3afb..d7faa3067d 100644
+--- a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.c
+@@ -79,3 +79,20 @@ int corstone1000_watchdog_init()
+     
+     return ARM_DRIVER_OK;
+ }
+
+/* Secure Host Watchdog WS1 Handler 
+ * efi_reset_system from the host triggers "Secure 
+ * watchdog WS1 interrupt" to reset the system. Host 
+ * cannot access this interrupt by design, so SE 
+ * resets the system using this handler
+ * */ 
+void SECURE_WATCHDOG_WS1_IRQHandler(void){
+    NVIC_SystemReset();
+}
+
+/*Enable Secure Watchdog WS1 Interrupt
+ * in NVIC controller (asserted by host)*/
+void corstone1000_host_watchdog_handler_init(){
+    NVIC_EnableIRQ(SECURE_WATCHDOG_WS1_IRQn);
+}
+
+diff --git a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
+index fd1b7cf124..cd9bed3f63 100644
+--- a/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
+++ b/platform/ext/target/arm/corstone1000/Native_Driver/watchdog.h
+@@ -29,4 +29,13 @@ int corstone1000_watchdog_init();
+  */
+ int corstone1000_watchdog_reset_timer();
+ 
+/**
+ *  \brief Initializes Interrupt Handler for
+ *   Secure Host Watchdog (WS1).
+ *
+ *  \returns  VOID
+ */
+void corstone1000_host_watchdog_handler_init();
+
+
+ #endif /* watchdog_h */
+diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+index 7faa71eb63..e3c6b78950 100644
+--- a/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+++ b/platform/ext/target/arm/corstone1000/tfm_hal_platform.c
+@@ -24,5 +24,7 @@ enum tfm_hal_status_t tfm_hal_platform_init(void)
+         return TFM_HAL_ERROR_GENERIC;
+     }
+ 
+    corstone1000_host_watchdog_handler_init();
+
+     return TFM_HAL_SUCCESS;
+ }
+-- 
+2.17.1
+
@@ -0,0 +1,45 @@
+# Corstone1000 machines specific TFM support
+
+COMPATIBLE_MACHINE = "(corstone1000)"
+
+TFM_DEBUG = "1"
+
+## Default is the MPS3 board
+TFM_PLATFORM_IS_FVP ?= "FALSE"
+EXTRA_OECMAKE += "-DPLATFORM_IS_FVP=${TFM_PLATFORM_IS_FVP}"
+EXTRA_OECMAKE += "-DCC312_LEGACY_DRIVER_API_ENABLED=OFF"
+
+SRCBRANCH_tfm = "master"
+SRCREV_tfm = "f8c7e5361b92b16108165601ea81c5d01feb3c22"
+SRCREV_mbedtls = "d65aeb37349ad1a50e0f6c9b694d4b5290d60e49"
+SRCREV_mcuboot = "29099e1d17f93ae1d09fe945ad191b703aacd3d8"
+
+PV = "1.5+git${SRCREV_tfm}"
+
+SRCREV_FORMAT = "tfm_mcuboot_tfm-tests_mbedtls"
+
+# The install task signs the TF-A BL2 and FIP binaries.
+# So they need to be copied to the sysroot. Hence the dependencies below:
+do_prepare_recipe_sysroot[depends]+= "virtual/trusted-firmware-a:do_populate_sysroot"
+
+# adding host images signing support
+require trusted-firmware-m-sign-host-images.inc
+
+do_install() {
+  install -D -p -m 0644 ${B}/install/outputs/tfm_s_signed.bin ${D}/firmware/tfm_s_signed.bin
+  install -D -p -m 0644 ${B}/install/outputs/bl2_signed.bin ${D}/firmware/bl2_signed.bin
+  install -D -p -m 0644 ${B}/install/outputs/bl1.bin ${D}/firmware/bl1.bin
+
+  #
+  # Signing TF-A BL2 and the FIP image
+  #
+
+  sign_host_image ${TFA_BL2_BINARY} ${RECIPE_SYSROOT}/firmware ${TFA_BL2_RE_IMAGE_LOAD_ADDRESS} ${TFA_BL2_RE_SIGN_BIN_SIZE}
+
+  fiptool update \
+      --tb-fw ${D}/firmware/signed_${TFA_BL2_BINARY} \
+      ${RECIPE_SYSROOT}/firmware/${TFA_FIP_BINARY}
+
+  sign_host_image ${TFA_FIP_BINARY} ${RECIPE_SYSROOT}/firmware ${TFA_FIP_RE_IMAGE_LOAD_ADDRESS} ${TFA_FIP_RE_SIGN_BIN_SIZE}
+
+}
@@ -0,0 +1,50 @@
+# Signing host images using TF-M tools
+
+DEPENDS += "python3-imgtool-native fiptool-native"
+
+#
+# sign_host_image
+#
+# Description:
+#
+# A generic function that signs a host image
+# using MCUBOOT format
+#
+# Arguments:
+#
+# $1 ... host binary to sign
+# $2 ... host binary path
+# $3 ... load address of the given binary
+# $4 ... signed binary size
+#
+# Note: The signed binary is copied to ${D}/firmware
+#
+sign_host_image() {
+
+    host_binary_filename="`basename -s .bin ${1}`"
+    host_binary_layout="${host_binary_filename}_ns"
+
+    cat << EOF > ${B}/${host_binary_layout}
+enum image_attributes {
+    RE_IMAGE_LOAD_ADDRESS = ${3},
+    RE_SIGN_BIN_SIZE = ${4},
+};
+EOF
+
+    host_binary="${2}/`basename ${1}`"
+    host_binary_signed="${D}/firmware/signed_`basename ${1}`"
+
+    ${PYTHON} ${S}/bl2/ext/mcuboot/scripts/wrapper/wrapper.py \
+            -v ${RE_LAYOUT_WRAPPER_VERSION} \
+            --layout ${B}/${host_binary_layout} \
+            -k  ${TFM_SIGN_PRIVATE_KEY} \
+            --public-key-format full \
+            --align 1 \
+            --pad \
+            --pad-header \
+            -H ${RE_IMAGE_OFFSET} \
+            -s auto \
+            ${host_binary} \
+            ${host_binary_signed}
+
+}
@@ -0,0 +1,6 @@
+# Machine specific configurations
+
+MACHINE_TFM_REQUIRE ?= ""
+MACHINE_TFM_REQUIRE:corstone1000 = "trusted-firmware-m-corstone1000.inc"
+
+require ${MACHINE_TFM_REQUIRE}
@@ -0,0 +1,27 @@
+From 097a43223da4fa42335944295903ede2755e2dfd Mon Sep 17 00:00:00 2001
+From: Jon Mason <jdmason@kudzu.us>
+Date: Mon, 19 Dec 2022 11:36:04 -0500
+Subject: [PATCH] configs: vexpress: modify to boot compressed initramfs
+
+Signed-off-by: Jon Mason <jdmason@kudzu.us>
+Upstream-Status: Inappropriate
+---
+ include/configs/vexpress_aemv8a.h       | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8a.h
+index cd7f6c1b9ba0..c2f5eb302076 100644
+--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
+@@ -164,6 +164,8 @@
+ 				"kernel_name=norkern\0"	\
+ 				"kernel_alt_name=Image\0"	\
+ 				"kernel_addr_r=0x80080000\0" \
+				"kernel_comp_addr_r=0x90000000\0" \
+				"kernel_comp_size=0x3000000\0" \
+ 				"initrd_name=ramdisk.img\0"	\
+ 				"initrd_addr_r=0x88000000\0"	\
+ 				"fdtfile=board.dtb\0" \
+-- 
+2.30.2
+
@@ -0,0 +1,330 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From 3feb071c77bb6297165c7b671b5c92d6ba306238 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Fri, 4 Jun 2021 10:58:24 +0100
+Subject: [PATCH 01/16] arm: add corstone1000 platform
+
+Add support for new corstone1000 platform.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+Signed-off-by: Rui Miguel Silva <rui.silva@arm.com>
+---
+ arch/arm/Kconfig                |  9 ++++
+ board/armltd/corstone1000/Kconfig     | 12 +++++
+ board/armltd/corstone1000/MAINTAINERS |  6 +++
+ board/armltd/corstone1000/Makefile    |  7 +++
+ board/armltd/corstone1000/corstone1000.c    | 92 +++++++++++++++++++++++++++++++++
+ configs/corstone1000_defconfig        | 39 ++++++++++++++
+ include/configs/corstone1000.h        | 80 ++++++++++++++++++++++++++++
+ 7 files changed, 245 insertions(+)
+ create mode 100644 board/armltd/corstone1000/Kconfig
+ create mode 100644 board/armltd/corstone1000/MAINTAINERS
+ create mode 100644 board/armltd/corstone1000/Makefile
+ create mode 100644 board/armltd/corstone1000/corstone1000.c
+ create mode 100644 configs/corstone1000_defconfig
+ create mode 100644 include/configs/corstone1000.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 0448787b8b..25d2a707be 100644
+--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
+@@ -1173,6 +1173,13 @@ config TARGET_VEXPRESS64_JUNO
+ 	select USB
+ 	select DM_USB
+ 
+config TARGET_CORSTONE1000
+	bool "Support Corstone1000 Platform"
+	select ARM64
+	select PL01X_SERIAL
+	select DM
+	select OF_BOARD
+
+ config TARGET_TOTAL_COMPUTE
+ 	bool "Support Total Compute Platform"
+ 	select ARM64
+@@ -1985,6 +1992,8 @@ source "arch/arm/mach-nexell/Kconfig"
+ 
+ source "board/armltd/total_compute/Kconfig"
+ 
+source "board/armltd/corstone1000/Kconfig"
+
+ source "board/bosch/shc/Kconfig"
+ source "board/bosch/guardian/Kconfig"
+ source "board/CarMediaLab/flea3/Kconfig"
+diff --git a/board/armltd/corstone1000/Kconfig b/board/armltd/corstone1000/Kconfig
+new file mode 100644
+index 000000000000..90e6b7af59cb
+--- /dev/null
+++ b/board/armltd/corstone1000/Kconfig
+@@ -0,0 +1,12 @@
+if TARGET_CORSTONE1000
+
+config SYS_BOARD
+	default "corstone1000"
+
+config SYS_VENDOR
+	default "armltd"
+
+config SYS_CONFIG_NAME
+	default "corstone1000"
+
+endif
+diff --git a/board/armltd/corstone1000/MAINTAINERS b/board/armltd/corstone1000/MAINTAINERS
+new file mode 100644
+index 000000000000..601cff17b666
+--- /dev/null
+++ b/board/armltd/corstone1000/MAINTAINERS
+@@ -0,0 +1,6 @@
+CORSTONE1000 BOARD
+M:	Rui Miguel Silva <rui.silva@linaro.org>
+S:	Maintained
+F:	board/armltd/corstone1000/
+F:	include/configs/corstone1000.h
+F:	configs/corstone1000_defconfig
+diff --git a/board/armltd/corstone1000/Makefile b/board/armltd/corstone1000/Makefile
+new file mode 100644
+index 000000000000..7bad6f57f1ce
+--- /dev/null
+++ b/board/armltd/corstone1000/Makefile
+@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2021 Arm Limited
+# (C) Copyright 2021 Linaro
+# Rui Miguel Silva <rui.silva@linaro.org>
+
+obj-y	:= corstone1000.o
+diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c
+new file mode 100644
+index 000000000000..fe986ceba1c5
+--- /dev/null
+++ b/board/armltd/corstone1000/corstone1000.c
+@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 ARM Limited
+ * (C) Copyright 2021 Linaro
+ * Rui Miguel Silva <rui.silva@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+
+
+static const struct pl01x_serial_plat serial_plat = {
+	.base = V2M_UART0,
+	.type = TYPE_PL011,
+	.clock = CONFIG_PL011_CLOCK,
+};
+
+U_BOOT_DRVINFO(corstone1000_serials) = {
+	.name = "serial_pl01x",
+	.plat = &serial_plat,
+};
+
+static struct mm_region corstone1000_mem_map[] = {
+	{
+		/* CVM */
+		.virt = 0x02000000UL,
+		.phys = 0x02000000UL,
+		.size = 0x02000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* QSPI */
+		.virt = 0x08000000UL,
+		.phys = 0x08000000UL,
+		.size = 0x08000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* Host Peripherals */
+		.virt = 0x1A000000UL,
+		.phys = 0x1A000000UL,
+		.size = 0x26000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* OCVM */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = corstone1000_mem_map;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+#ifdef PHYS_SDRAM_2
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+new file mode 100644
+index 000000000000..47d4bf3771e0
+--- /dev/null
+++ b/configs/corstone1000_defconfig
+@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_ARM64=y
+CONFIG_TARGET_CORSTONE1000=y
+CONFIG_SYS_TEXT_BASE=0x02100000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_IDENT_STRING=" corstone1000 aarch64 "
+CONFIG_BOOTDELAY=3
+CONFIG_OF_BOARD=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="corstone1000# "
+# CONFIG_CMD_CONSOLE is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTM=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_ARMFLASH=y
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_FIT=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
+CONFIG_DM=y
+# CONFIG_MMC is not set
+# CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_DM_SERIAL=y
+CONFIG_OF_LIBFDT=y
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+new file mode 100644
+index 000000000000..c8e630c5d857
+--- /dev/null
+++ b/include/configs/corstone1000.h
+@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2020 ARM Limited
+ * (C) Copyright 2020 Linaro
+ * Rui Miguel Silva <rui.silva@linaro.org>
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ *
+ * Configuration for Corstone1000. Parts were derived from other ARM
+ * configurations.
+ */
+
+#ifndef __CORSTONE1000_H
+#define __CORSTONE1000_H
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x03f00000)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_HZ		1000
+
+#define V2M_SRAM0		0x02000000
+#define V2M_QSPI		0x08000000
+
+#define V2M_DEBUG		0x10000000
+#define V2M_BASE_PERIPH		0x1A000000
+
+#define V2M_BASE		0x80000000
+
+#define V2M_PERIPH_OFFSET(x)	(x << 16)
+
+#define V2M_SYSID		(V2M_BASE_PERIPH)
+#define V2M_SYSCTL		(V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1))
+
+#define V2M_COUNTER_CTL		(V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32))
+#define V2M_COUNTER_READ	(V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33))
+
+#define V2M_TIMER_CTL		(V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34))
+#define V2M_TIMER_BASE0		(V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35))
+
+#define V2M_UART0		(V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(81))
+#define V2M_UART1		(V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(82))
+
+#define CONFIG_PL011_CLOCK	50000000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1		(V2M_BASE)
+#define PHYS_SDRAM_2		(V2M_QSPI)
+
+/* Top 16MB reserved for secure world use (maybe not needed) */
+#define DRAM_SEC_SIZE		0x01000000
+#define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
+
+#define PHYS_SDRAM_2_SIZE	0x02000000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (8 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR	(V2M_BASE + 0x10000000)
+
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+				"fdt_addr=0x08330000\0"		\
+				"fdt_addr_r=0x82000000\0"		\
+				"kernel_addr=0x08430000\0"		\
+				"kernel_addr_r=0x82100000\0"		\
+				"fdt_high=0xffffffff\0"
+
+#define CONFIG_BOOTCOMMAND					\
+				"echo Copying devicetree to memory ... ;" \
+				"cp.b $fdt_addr $fdt_addr_r 0x100000;" \
+				"echo Copying Kernel to memory ... ;" \
+				"cp.b $kernel_addr $kernel_addr_r 0xa00000;" \
+				"bootm $kernel_addr_r - $fdt_addr_r; "
+
+#endif
+-- 
+2.33.0
+
@@ -0,0 +1,59 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From 1a034bd9397f96939d58a86e9cf8cd9c206db647 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Tue, 22 Jun 2021 17:00:24 +0100
+Subject: [PATCH 02/16] arm: corstone1000: enable devicetree in defconfig
+
+Add support and setup the default device tree for corstone1000.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+Signed-off-by: Rui Miguel Silva <rui.silva@arm.com>
+---
+ configs/corstone1000_defconfig |  3 ++-
+ include/configs/corstone1000.h | 10 +++-------
+ 2 files changed, 5 insertions(+), 8 deletions(-)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index bc983e6555..54c746d829 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -6,7 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
+ CONFIG_NR_DRAM_BANKS=1
+ CONFIG_IDENT_STRING=" corstone1000 aarch64 "
+ CONFIG_BOOTDELAY=3
+-CONFIG_OF_BOARD=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3"
+ CONFIG_USE_BOOTARGS=y
+ CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9"
+ # CONFIG_DISPLAY_CPUINFO is not set
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index 1fe909463f..389ac45a58 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -64,17 +64,13 @@
+ #define CONFIG_SYS_MAXARGS		64	/* max command args */
+ 
+ #define CONFIG_EXTRA_ENV_SETTINGS					\
+-				"fdt_addr=0x08330000\0"		\
+ 				"fdt_addr_r=0x82000000\0"		\
+-				"kernel_addr=0x08430000\0"		\
+				"kernel_addr=0x08330000\0"		\
+ 				"kernel_addr_r=0x82100000\0"		\
+ 				"fdt_high=0xffffffff\0"
+ 
+ #define CONFIG_BOOTCOMMAND					\
+-				"echo Copying devicetree to memory ... ;" \
+-				"cp.b $fdt_addr $fdt_addr_r 0x100000;" \
+ 				"echo Copying Kernel to memory ... ;" \
+-				"cp.b $kernel_addr $kernel_addr_r 0xa00000;" \
+-				"bootm $kernel_addr_r - $fdt_addr_r; "
+-
+                                "cp.b $kernel_addr $kernel_addr_r 0xc00000;" \
+                                "booti $kernel_addr_r - $fdtcontroladdr; "
+ #endif
+-- 
+2.33.0
+
@@ -0,0 +1,508 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From 84b3b8f2443d0b4f6ac8ef95c941b27d734afbde Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Mon, 28 Jun 2021 23:20:55 +0100
+Subject: [PATCH 03/16] usb: common: move urb code to common
+
+Move urb code from musb only use to a more common scope, so other
+drivers in the future can use the handling of urb in usb.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ drivers/usb/common/Makefile                   |   2 +
+ drivers/usb/common/usb_urb.c                  | 160 ++++++++++++++++++
+ drivers/usb/host/r8a66597-hcd.c               |  30 +---
+ drivers/usb/musb-new/musb_core.c              |   2 +-
+ drivers/usb/musb-new/musb_host.c              |   2 +-
+ drivers/usb/musb-new/musb_host.h              |   2 +-
+ drivers/usb/musb-new/musb_uboot.c             |  38 +----
+ drivers/usb/musb-new/musb_uboot.h             |   2 +-
+ .../linux/usb/usb_urb_compat.h                |  52 ++++--
+ include/usb_defs.h                            |  32 ++++
+ 10 files changed, 240 insertions(+), 82 deletions(-)
+ create mode 100644 drivers/usb/common/usb_urb.c
+ rename drivers/usb/musb-new/usb-compat.h => include/linux/usb/usb_urb_compat.h (57%)
+
+diff --git a/drivers/usb/common/Makefile b/drivers/usb/common/Makefile
+index 3bedbf213f..dc05cb0a50 100644
+--- a/drivers/usb/common/Makefile
+++ b/drivers/usb/common/Makefile
+@@ -4,5 +4,7 @@
+ #
+ 
+ obj-$(CONFIG_$(SPL_)DM_USB) += common.o
+obj-$(CONFIG_USB_MUSB_HCD) += usb_urb.o
+obj-$(CONFIG_USB_MUSB_UDC) += usb_urb.o
+ obj-$(CONFIG_USB_EHCI_FSL) += fsl-dt-fixup.o fsl-errata.o
+ obj-$(CONFIG_USB_XHCI_FSL) += fsl-dt-fixup.o fsl-errata.o
+diff --git a/drivers/usb/common/usb_urb.c b/drivers/usb/common/usb_urb.c
+new file mode 100644
+index 0000000000..be3b6b9f32
+--- /dev/null
+++ b/drivers/usb/common/usb_urb.c
+@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Common code for usb urb handling, based on the musb-new code
+ *
+ * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org>
+ *
+ */
+
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <linux/usb/usb_urb_compat.h>
+
+#include <time.h>
+#include <usb.h>
+
+#if CONFIG_IS_ENABLED(DM_USB)
+struct usb_device *usb_dev_get_parent(struct usb_device *udev)
+{
+	struct udevice *parent = udev->dev->parent;
+
+	/*
+	 * When called from usb-uclass.c: usb_scan_device() udev->dev points
+	 * to the parent udevice, not the actual udevice belonging to the
+	 * udev as the device is not instantiated yet.
+	 *
+	 * If dev is an usb-bus, then we are called from usb_scan_device() for
+	 * an usb-device plugged directly into the root port, return NULL.
+	 */
+	if (device_get_uclass_id(udev->dev) == UCLASS_USB)
+		return NULL;
+
+	/*
+	 * If these 2 are not the same we are being called from
+	 * usb_scan_device() and udev itself is the parent.
+	 */
+	if (dev_get_parent_priv(udev->dev) != udev)
+		return udev;
+
+	/* We are being called normally, use the parent pointer */
+	if (device_get_uclass_id(parent) == UCLASS_USB_HUB)
+		return dev_get_parent_priv(parent);
+
+	return NULL;
+}
+#else
+struct usb_device *usb_dev_get_parent(struct usb_device *udev)
+{
+	return udev->parent;
+}
+#endif
+
+static void usb_urb_complete(struct urb *urb)
+{
+	urb->dev->status &= ~USB_ST_NOT_PROC;
+	urb->dev->act_len = urb->actual_length;
+
+	if (urb->status == -EINPROGRESS)
+		urb->status = 0;
+}
+
+void usb_urb_fill(struct urb *urb, struct usb_host_endpoint *hep,
+		  struct usb_device *dev, int endpoint_type,
+		  unsigned long pipe, void *buffer, int len,
+		  struct devrequest *setup, int interval)
+{
+	int epnum = usb_pipeendpoint(pipe);
+	int is_in = usb_pipein(pipe);
+	u16 maxpacketsize = is_in ? dev->epmaxpacketin[epnum] :
+					dev->epmaxpacketout[epnum];
+
+	memset(urb, 0, sizeof(struct urb));
+	memset(hep, 0, sizeof(struct usb_host_endpoint));
+	INIT_LIST_HEAD(&hep->urb_list);
+	INIT_LIST_HEAD(&urb->urb_list);
+	urb->ep = hep;
+	urb->complete = usb_urb_complete;
+	urb->status = -EINPROGRESS;
+	urb->dev = dev;
+	urb->pipe = pipe;
+	urb->transfer_buffer = buffer;
+	urb->transfer_dma = (unsigned long)buffer;
+	urb->transfer_buffer_length = len;
+	urb->setup_packet = (unsigned char *)setup;
+
+	urb->ep->desc.wMaxPacketSize = __cpu_to_le16(maxpacketsize);
+	urb->ep->desc.bmAttributes = endpoint_type;
+	urb->ep->desc.bEndpointAddress = ((is_in ? USB_DIR_IN : USB_DIR_OUT) |
+					  epnum);
+	urb->ep->desc.bInterval = interval;
+}
+
+int usb_urb_submit(struct usb_hcd *hcd, struct urb *urb)
+{
+	const struct usb_urb_ops *ops = hcd->urb_ops;
+	unsigned long timeout;
+	int ret;
+
+	if (!ops)
+		return -EINVAL;
+
+	ret = ops->urb_enqueue(hcd, urb, 0);
+	if (ret < 0) {
+		printf("Failed to enqueue URB to controller\n");
+		return ret;
+	}
+
+	timeout = get_timer(0) + USB_TIMEOUT_MS(urb->pipe);
+	do {
+		if (ctrlc())
+			return -EIO;
+		ops->isr(0, hcd);
+	} while (urb->status == -EINPROGRESS && get_timer(0) < timeout);
+
+	if (urb->status == -EINPROGRESS)
+		ops->urb_dequeue(hcd, urb, -ETIME);
+
+	return urb->status;
+}
+
+int usb_urb_submit_control(struct usb_hcd *hcd, struct urb *urb,
+			   struct usb_host_endpoint *hep,
+			   struct usb_device *dev, unsigned long pipe,
+			   void *buffer, int len, struct devrequest *setup,
+			   int interval, enum usb_device_speed speed)
+{
+	const struct usb_urb_ops *ops = hcd->urb_ops;
+
+	usb_urb_fill(urb, hep, dev, USB_ENDPOINT_XFER_CONTROL, pipe, buffer,
+		     len, setup, 0);
+
+	/* Fix speed for non hub-attached devices */
+	if (!usb_dev_get_parent(dev)) {
+		dev->speed = speed;
+		if (ops->hub_control)
+			return ops->hub_control(hcd, dev, pipe, buffer, len,
+						setup);
+	}
+
+	return usb_urb_submit(hcd, urb);
+}
+
+int usb_urb_submit_bulk(struct usb_hcd *hcd, struct urb *urb,
+			struct usb_host_endpoint *hep, struct usb_device *dev,
+			unsigned long pipe, void *buffer, int len)
+{
+	usb_urb_fill(urb, hep, dev, USB_ENDPOINT_XFER_BULK, pipe, buffer, len,
+		     NULL, 0);
+
+	return usb_urb_submit(hcd, urb);
+}
+
+int usb_urb_submit_irq(struct usb_hcd *hcd, struct urb *urb,
+		       struct usb_host_endpoint *hep, struct usb_device *dev,
+		       unsigned long pipe, void *buffer, int len, int interval)
+{
+	usb_urb_fill(urb, hep, dev, USB_ENDPOINT_XFER_INT, pipe, buffer, len,
+		     NULL, interval);
+
+	return usb_urb_submit(hcd, urb);
+}
+diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
+index f1fc93f3d4..3ccbc16da3 100644
+--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
+@@ -14,6 +14,7 @@
+ #include <dm/device_compat.h>
+ #include <linux/delay.h>
+ #include <linux/iopoll.h>
+#include <linux/usb/usb_urb_compat.h>
+ #include <power/regulator.h>
+ 
+ #include "r8a66597.h"
+@@ -24,35 +25,6 @@
+ #define R8A66597_DPRINT(...)
+ #endif
+ 
+-static inline struct usb_device *usb_dev_get_parent(struct usb_device *udev)
+-{
+-	struct udevice *parent = udev->dev->parent;
+-
+-	/*
+-	 * When called from usb-uclass.c: usb_scan_device() udev->dev points
+-	 * to the parent udevice, not the actual udevice belonging to the
+-	 * udev as the device is not instantiated yet.
+-	 *
+-	 * If dev is an usb-bus, then we are called from usb_scan_device() for
+-	 * an usb-device plugged directly into the root port, return NULL.
+-	 */
+-	if (device_get_uclass_id(udev->dev) == UCLASS_USB)
+-		return NULL;
+-
+-	/*
+-	 * If these 2 are not the same we are being called from
+-	 * usb_scan_device() and udev itself is the parent.
+-	 */
+-	if (dev_get_parent_priv(udev->dev) != udev)
+-		return udev;
+-
+-	/* We are being called normally, use the parent pointer */
+-	if (device_get_uclass_id(parent) == UCLASS_USB_HUB)
+-		return dev_get_parent_priv(parent);
+-
+-	return NULL;
+-}
+-
+ static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport)
+ {
+ 	struct usb_device *parent = usb_dev_get_parent(dev);
+diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c
+index 22811a5efb..d1d4ee2da3 100644
+--- a/drivers/usb/musb-new/musb_core.c
+++ b/drivers/usb/musb-new/musb_core.c
+@@ -89,9 +89,9 @@
+ #include <linux/usb/ch9.h>
+ #include <linux/usb/gadget.h>
+ #include <linux/usb/musb.h>
+#include <linux/usb/usb_urb_compat.h>
+ #include <asm/io.h>
+ #include "linux-compat.h"
+-#include "usb-compat.h"
+ #endif
+ 
+ #include "musb_core.h"
+diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c
+index acb2d40f3b..e5905d90d6 100644
+--- a/drivers/usb/musb-new/musb_host.c
+++ b/drivers/usb/musb-new/musb_host.c
+@@ -26,8 +26,8 @@
+ #include <dm/device_compat.h>
+ #include <usb.h>
+ #include <linux/bug.h>
+#include <linux/usb/usb_urb_compat.h>
+ #include "linux-compat.h"
+-#include "usb-compat.h"
+ #endif
+ 
+ #include "musb_core.h"
+diff --git a/drivers/usb/musb-new/musb_host.h b/drivers/usb/musb-new/musb_host.h
+index afc8fa35a7..5a604bdb0c 100644
+--- a/drivers/usb/musb-new/musb_host.h
+++ b/drivers/usb/musb-new/musb_host.h
+@@ -10,7 +10,7 @@
+ #ifndef _MUSB_HOST_H
+ #define _MUSB_HOST_H
+ #ifdef __UBOOT__
+-#include "usb-compat.h"
+#include <linux/usb/usb_urb_compat.h>
+ #endif
+ 
+ static inline struct usb_hcd *musb_to_hcd(struct musb *musb)
+diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c
+index 8ac2f0a78a..85794356b0 100644
+--- a/drivers/usb/musb-new/musb_uboot.c
+++ b/drivers/usb/musb-new/musb_uboot.c
+@@ -8,10 +8,10 @@
+ #include <linux/errno.h>
+ #include <linux/usb/ch9.h>
+ #include <linux/usb/gadget.h>
+#include <linux/usb/usb_urb_compat.h>
+ 
+ #include <usb.h>
+ #include "linux-compat.h"
+-#include "usb-compat.h"
+ #include "musb_core.h"
+ #include "musb_host.h"
+ #include "musb_gadget.h"
+@@ -453,39 +453,3 @@ struct musb *musb_register(struct musb_hdrc_platform_data *plat, void *bdata,
+ 
+ 	return *musbp;
+ }
+-
+-#if CONFIG_IS_ENABLED(DM_USB)
+-struct usb_device *usb_dev_get_parent(struct usb_device *udev)
+-{
+-	struct udevice *parent = udev->dev->parent;
+-
+-	/*
+-	 * When called from usb-uclass.c: usb_scan_device() udev->dev points
+-	 * to the parent udevice, not the actual udevice belonging to the
+-	 * udev as the device is not instantiated yet.
+-	 *
+-	 * If dev is an usb-bus, then we are called from usb_scan_device() for
+-	 * an usb-device plugged directly into the root port, return NULL.
+-	 */
+-	if (device_get_uclass_id(udev->dev) == UCLASS_USB)
+-		return NULL;
+-
+-	/*
+-	 * If these 2 are not the same we are being called from
+-	 * usb_scan_device() and udev itself is the parent.
+-	 */
+-	if (dev_get_parent_priv(udev->dev) != udev)
+-		return udev;
+-
+-	/* We are being called normally, use the parent pointer */
+-	if (device_get_uclass_id(parent) == UCLASS_USB_HUB)
+-		return dev_get_parent_priv(parent);
+-
+-	return NULL;
+-}
+-#else
+-struct usb_device *usb_dev_get_parent(struct usb_device *udev)
+-{
+-	return udev->parent;
+-}
+-#endif
+diff --git a/drivers/usb/musb-new/musb_uboot.h b/drivers/usb/musb-new/musb_uboot.h
+index 18282efccc..6b162f03b1 100644
+--- a/drivers/usb/musb-new/musb_uboot.h
+++ b/drivers/usb/musb-new/musb_uboot.h
+@@ -8,8 +8,8 @@
+ #define __MUSB_UBOOT_H__
+ 
+ #include <usb.h>
+#include <linux/usb/usb_urb_compat.h>
+ #include "linux-compat.h"
+-#include "usb-compat.h"
+ #include "musb_core.h"
+ 
+ struct musb_host_data {
+diff --git a/drivers/usb/musb-new/usb-compat.h b/include/linux/usb/usb_urb_compat.h
+similarity index 57%
+rename from drivers/usb/musb-new/usb-compat.h
+rename to include/linux/usb/usb_urb_compat.h
+index 1c66c4fe36..438e70b56a 100644
+--- a/drivers/usb/musb-new/usb-compat.h
+++ b/include/linux/usb/usb_urb_compat.h
+@@ -1,16 +1,31 @@
+-#ifndef __USB_COMPAT_H__
+-#define __USB_COMPAT_H__
+#ifndef __USB_URB_COMPAT_H__
+#define __USB_URB_COMPAT_H__
+ 
+-#include "usb.h"
+#include <linux/compat.h>
+#include <usb.h>
+ 
+ struct udevice;
+struct urb;
+struct usb_hcd;
+
+
+struct usb_urb_ops {
+	int (*urb_enqueue)(struct usb_hcd *hcd, struct urb *urb,
+			   gfp_t mem_flags);
+	int (*urb_dequeue)(struct usb_hcd *hcd, struct urb *urb, int status);
+	int (*hub_control)(struct usb_hcd *hcd, struct usb_device *dev,
+			   unsigned long pipe, void *buffer, int len,
+			   struct devrequest *setup);
+	irqreturn_t (*isr)(int irq, void *priv);
+};
+ 
+ struct usb_hcd {
+ 	void *hcd_priv;
+	const struct usb_urb_ops *urb_ops;
+ };
+ 
+ struct usb_host_endpoint {
+-	struct usb_endpoint_descriptor		desc;
+	struct usb_endpoint_descriptor desc;
+ 	struct list_head urb_list;
+ 	void *hcpriv;
+ };
+@@ -23,8 +38,6 @@ struct usb_host_endpoint {
+ #define URB_SHORT_NOT_OK	0x0001	/* report short reads as errors */
+ #define URB_ZERO_PACKET		0x0040	/* Finish bulk OUT with short packet */
+ 
+-struct urb;
+-
+ typedef void (*usb_complete_t)(struct urb *);
+ 
+ struct urb {
+@@ -68,12 +81,27 @@ static inline int usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd,
+ 	return 0;
+ }
+ 
+-/**
+- * usb_dev_get_parent() - Get the parent of a USB device
+- *
+- * @udev: USB struct containing information about the device
+- * @return associated device for which udev == dev_get_parent_priv(dev)
+- */
+ struct usb_device *usb_dev_get_parent(struct usb_device *udev);
+ 
+int usb_urb_submit_control(struct usb_hcd *hcd, struct urb *urb,
+			   struct usb_host_endpoint *hep,
+			   struct usb_device *dev, unsigned long pipe,
+			   void *buffer, int len, struct devrequest *setup,
+			   int interval, enum usb_device_speed speed);
+
+int usb_urb_submit_bulk(struct usb_hcd *hcd, struct urb *urb,
+			struct usb_host_endpoint *hep, struct usb_device *dev,
+			unsigned long pipe, void *buffer, int len);
+
+int usb_urb_submit_irq(struct usb_hcd *hcd, struct urb *urb,
+		       struct usb_host_endpoint *hep, struct usb_device *dev,
+		       unsigned long pipe, void *buffer, int len, int interval);
+
+void usb_urb_fill(struct urb *urb, struct usb_host_endpoint *hep,
+		  struct usb_device *dev, int endpoint_type,
+		  unsigned long pipe, void *buffer, int len,
+		  struct devrequest *setup, int interval);
+
+int usb_urb_submit(struct usb_hcd *hcd, struct urb *urb);
+
+ #endif /* __USB_COMPAT_H__ */
+diff --git a/include/usb_defs.h b/include/usb_defs.h
+index 6dd2c997f9..ec00161710 100644
+--- a/include/usb_defs.h
+++ b/include/usb_defs.h
+@@ -81,6 +81,32 @@
+ #define EndpointOutRequest \
+ 	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+ 
+/* class requests from the USB 2.0 hub spec, table 11-15 */
+#define HUB_CLASS_REQ(dir, type, request) ((((dir) | (type)) << 8) | (request))
+/* GetBusState and SetHubDescriptor are optional, omitted */
+#define ClearHubFeature		HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_HUB, \
+					      USB_REQ_CLEAR_FEATURE)
+#define ClearPortFeature	HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \
+					      USB_REQ_CLEAR_FEATURE)
+#define GetHubDescriptor	HUB_CLASS_REQ(USB_DIR_IN, USB_RT_HUB, \
+					      USB_REQ_GET_DESCRIPTOR)
+#define GetHubStatus		HUB_CLASS_REQ(USB_DIR_IN, USB_RT_HUB, \
+					      USB_REQ_GET_STATUS)
+#define GetPortStatus		HUB_CLASS_REQ(USB_DIR_IN, USB_RT_PORT, \
+					      USB_REQ_GET_STATUS)
+#define SetHubFeature		HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_HUB, \
+					      USB_REQ_SET_FEATURE)
+#define SetPortFeature		HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \
+					      USB_REQ_SET_FEATURE)
+#define ClearTTBuffer		HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \
+					      HUB_CLEAR_TT_BUFFER)
+#define ResetTT			HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \
+					      HUB_RESET_TT)
+#define GetTTState		HUB_CLASS_REQ(USB_DIR_IN, USB_RT_PORT, \
+					      HUB_GET_TT_STATE)
+#define StopTT			HUB_CLASS_REQ(USB_DIR_OUT, USB_RT_PORT, \
+					      HUB_STOP_TT)
+
+ /* Descriptor types */
+ #define USB_DT_DEVICE        0x01
+ #define USB_DT_CONFIG        0x02
+@@ -289,10 +315,16 @@
+ #define USB_SS_PORT_STAT_C_CONFIG_ERROR	0x0080
+ 
+ /* wHubCharacteristics (masks) */
+#define HUB_CHAR_COMMON_OCPM        0x0000 /* All ports Over-Current reporting */
+#define HUB_CHAR_INDV_PORT_LPSM     0x0001 /* per-port power control */
+#define HUB_CHAR_NO_LPSM            0x0002 /* no power switching */
+ #define HUB_CHAR_LPSM               0x0003
+ #define HUB_CHAR_COMPOUND           0x0004
+#define HUB_CHAR_INDV_PORT_OCPM     0x0008 /* per-port Over-current reporting */
+#define HUB_CHAR_NO_OCPM            0x0010 /* No Over-current Protection support */
+ #define HUB_CHAR_OCPM               0x0018
+ #define HUB_CHAR_TTTT               0x0060 /* TT Think Time mask */
+#define HUB_CHAR_PORTIND            0x0080 /* per-port indicators (LEDs) */
+ 
+ /*
+  * Hub Status & Hub Change bit masks
+-- 
+2.33.0
+
@@ -0,0 +1,92 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From 663bfde59a56d65c031526f75f0e08126f02d845 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Tue, 27 Jul 2021 23:34:57 +0100
+Subject: [PATCH 05/16] corstone1000: enable isp1763 and usb stack
+
+MPS3 board have a ISP1763 usb controller, add the correspondent mmio
+area and enable it to be used for mass storage access for example.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ board/armltd/corstone1000/corstone1000.c |  8 ++++++++
+ configs/corstone1000_defconfig           | 19 +++++++++----------
+ 2 files changed, 17 insertions(+), 10 deletions(-)
+
+diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c
+index ab98fa87fb..a51f5ddfa0 100644
+--- a/board/armltd/corstone1000/corstone1000.c
+++ b/board/armltd/corstone1000/corstone1000.c
+@@ -46,6 +46,14 @@ static struct mm_region corstone1000_mem_map[] = {
+ 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ 			 PTE_BLOCK_NON_SHARE |
+ 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+        }, {
+                /* USB */
+                .virt = 0x40200000UL,
+                .phys = 0x40200000UL,
+                .size = 0x00100000UL,
+                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                         PTE_BLOCK_NON_SHARE |
+                         PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ 	}, {
+ 		/* OCVM */
+ 		.virt = 0x80000000UL,
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index 54c746d829..fed2b16c93 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -1,13 +1,12 @@
+ CONFIG_ARM=y
+-CONFIG_ARM64=y
+ CONFIG_TARGET_CORSTONE1000=y
+ CONFIG_SYS_TEXT_BASE=0x02100000
+ CONFIG_SYS_MALLOC_F_LEN=0x2000
+ CONFIG_NR_DRAM_BANKS=1
+ CONFIG_IDENT_STRING=" corstone1000 aarch64 "
+-CONFIG_BOOTDELAY=3
+-CONFIG_OF_CONTROL=y
+ CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3"
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+ CONFIG_USE_BOOTARGS=y
+ CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9"
+ # CONFIG_DISPLAY_CPUINFO is not set
+@@ -16,12 +15,11 @@ CONFIG_HUSH_PARSER=y
+ CONFIG_SYS_PROMPT="corstone1000# "
+ # CONFIG_CMD_CONSOLE is not set
+ CONFIG_CMD_BOOTZ=y
+-CONFIG_CMD_BOOTM=y
+ # CONFIG_CMD_XIMG is not set
+ # CONFIG_CMD_EDITENV is not set
+ # CONFIG_CMD_ENV_EXISTS is not set
+-# CONFIG_CMD_ARMFLASH=y
+ # CONFIG_CMD_LOADS is not set
+CONFIG_CMD_USB=y
+ # CONFIG_CMD_ITEST is not set
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_DHCP=y
+@@ -29,12 +27,13 @@ CONFIG_CMD_DHCP=y
+ CONFIG_CMD_MII=y
+ CONFIG_CMD_PING=y
+ CONFIG_CMD_CACHE=y
+-CONFIG_FIT=y
+-# CONFIG_CMD_MISC is not set
+ CONFIG_CMD_FAT=y
+-CONFIG_DM=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+ # CONFIG_MMC is not set
+-# CONFIG_MTD_NOR_FLASH=y
+ CONFIG_DM_ETH=y
+ CONFIG_DM_SERIAL=y
+-CONFIG_OF_LIBFDT=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_STORAGE=y
+-- 
+2.33.0
+
@@ -0,0 +1,240 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From 8244c266643d7fe77e360d2927adcd123a691dd1 Mon Sep 17 00:00:00 2001
+From: "Arpita S.K" <Arpita.S.K@arm.com>
+Date: Mon, 11 Oct 2021 11:41:25 +0530
+Subject: [PATCH 06/16] corstone1000: enable support for FVP
+
+Introduces a new device tree for the FVP.
+
+Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
+---
+ arch/arm/dts/Makefile             |   2 +
+ arch/arm/dts/corstone1000-fvp.dts |  28 ++++++
+ arch/arm/dts/corstone1000.dtsi    | 152 ++++++++++++++++++++++++++++++
+ configs/corstone1000_defconfig    |   1 -
+ 4 files changed, 182 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/dts/corstone1000-fvp.dts
+ create mode 100644 arch/arm/dts/corstone1000.dtsi
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 9fb38682e6..c70c20b9a5 100644
+--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
+@@ -1112,6 +1112,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
+ 
+ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+ 
+dtb-$(CONFIG_TARGET_CORSTONE1000) += $(DEVICE_TREE).dtb
+
+ targets += $(dtb-y)
+ 
+ # Add any required device tree compiler flags here
+diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
+new file mode 100644
+index 0000000000..2188ca5e0e
+--- /dev/null
+++ b/arch/arm/dts/corstone1000-fvp.dts
+@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+#include "corstone1000.dtsi"
+
+/ {
+       model = "corstone1000-fvp";
+
+       ethernet: eth@4010000 {
+               compatible = "smsc,lan91c111";
+               reg = <0x40100000 0x10000>;
+               phy-mode = "mii";
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_SPI 116 0xf04>;
+               reg-io-width = <2>;
+               smsc,irq-push-pull;
+       };
+
+};
+
+&refclk {
+       clock-frequency = <50000000>;
+};
+diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
+new file mode 100644
+index 0000000000..b863193fb6
+--- /dev/null
+++ b/arch/arm/dts/corstone1000.dtsi
+@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "arm,corstone1000";
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen { };
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0>;
+			next-level-cache = <&L2_0>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	gic: interrupt-controller@1c000000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg =	<0x1c010000 0x1000>,
+			<0x1c02f000 0x2000>,
+			<0x1c04f000 0x1000>,
+			<0x1c06f000 0x2000>;
+		interrupts = <1 9 0xf08>;
+	};
+
+	L2_0: l2-cache0 {
+		compatible = "cache";
+	};
+
+	refclk100mhz: refclk100mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "apb_pclk";
+	};
+
+	smbclk: refclk24mhzx2 {
+		/* Reference 24MHz clock x 2 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <48000000>;
+		clock-output-names = "smclk";
+	};
+
+	uartclk: uartclk {
+		/* UART clock - 50MHz */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+		clock-output-names = "uartclk";
+	};
+
+	serial0: uart@1a510000 {
+		compatible = "arm,pl011", "arm,primecell";
+		reg = <0x1a510000 0x1000>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 19 4>;
+		clocks = <&uartclk>, <&refclk100mhz>;
+		clock-names = "uartclk", "apb_pclk";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts =	<1 13 0xf08>,
+				<1 14 0xf08>,
+				<1 11 0xf08>,
+				<1 10 0xf08>;
+	};
+
+	refclk: refclk@1a220000 {
+		compatible = "arm,armv7-timer-mem";
+		reg = <0x1a220000  0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		frame@1a230000 {
+			frame-number = <0>;
+			interrupts = <0 2 0xf04>;
+			reg = <0x1a230000 0x1000>;
+		};
+	};
+
+	mbox_es0mhu0: mhu@1b000000 {
+		compatible = "arm,mhuv2","arm,primecell";
+		reg = <0x1b000000 0x1000>,
+		      <0x1b010000 0x1000>;
+		clocks = <&refclk100mhz>;
+		clock-names = "apb_pclk";
+		interrupts = <0 12 4>;
+		interrupt-names = "mhu_rx";
+		#mbox-cells = <1>;
+		mbox-name = "arm-es0-mhu0";
+	};
+
+	mbox_es0mhu1: mhu@1b020000 {
+		compatible = "arm,mhuv2","arm,primecell";
+		reg = <0x1b020000 0x1000>,
+		      <0x1b030000 0x1000>;
+		clocks = <&refclk100mhz>;
+		clock-names = "apb_pclk";
+		interrupts = <0 47 4>;
+		interrupt-names = "mhu_rx";
+		#mbox-cells = <1>;
+		mbox-name = "arm-es0-mhu1";
+	};
+
+	mbox_semhu1: mhu@1b820000 {
+		compatible = "arm,mhuv2","arm,primecell";
+		reg = <0x1b820000 0x1000>,
+		      <0x1b830000 0x1000>;
+		clocks = <&refclk100mhz>;
+		clock-names = "apb_pclk";
+		interrupts = <0 45 4>;
+		interrupt-names = "mhu_rx";
+		#mbox-cells = <1>;
+		mbox-name = "arm-se-mhu1";
+	};
+
+	client {
+		compatible = "arm,client";
+		mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>;
+		mbox-names = "es0mhu0", "es0mhu1", "semhu1";
+	};
+
+	extsys0: extsys@1A010310 {
+		compatible = "arm,extsys_ctrl";
+		reg = <0x1A010310 0x4>,
+		      <0x1A010314 0x4>;
+		reg-names = "rstreg", "streg";
+	};
+};
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index fed2b16c93..c7f291efb6 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x02100000
+ CONFIG_SYS_MALLOC_F_LEN=0x2000
+ CONFIG_NR_DRAM_BANKS=1
+ CONFIG_IDENT_STRING=" corstone1000 aarch64 "
+-CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3"
+ CONFIG_FIT=y
+ CONFIG_BOOTDELAY=3
+ CONFIG_USE_BOOTARGS=y
+-- 
+2.33.0
+
@@ -0,0 +1,34 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From b50c1457fcd05cddf633bff074fc5edecff22e7e Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Wed, 25 Aug 2021 16:50:40 +0100
+Subject: [PATCH 07/16] arm: corstone1000: sharing PSCI DTS node between FVP
+ and MPS3
+
+At this level of development PSCI is needed to initialize the SMCCC.
+
+SMCCC is needed by FF-A and it is relevant to the MPS3 and FVP.
+
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+---
+ arch/arm/dts/corstone1000.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
+index b863193fb6..da1725e01f 100644
+--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
+@@ -149,4 +149,8 @@
+ 		      <0x1A010314 0x4>;
+ 		reg-names = "rstreg", "streg";
+ 	};
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+ };
+-- 
+2.33.0
+
@@ -0,0 +1,32 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From 9a045bf04210bf9a00803fc47016e1af59d31e8f Mon Sep 17 00:00:00 2001
+From: "Arpita S.K" <Arpita.S.K@arm.com>
+Date: Mon, 11 Oct 2021 11:45:41 +0530
+Subject: [PATCH 08/16] arm: corstone1000: Emulated RTC Support
+
+This patch adds the options that should be
+enabled to turn on emulated RTC support.
+
+Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
+---
+ configs/corstone1000_defconfig | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index c7f291efb6..dbe3c9e3f3 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -36,3 +36,8 @@ CONFIG_USB=y
+ CONFIG_DM_USB=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_STORAGE=y
+CONFIG_DM_RTC=y
+CONFIG_CMD_RTC=y
+CONFIG_EFI_GET_TIME=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_RTC_EMULATION=y
+-- 
+2.33.0
+
@@ -0,0 +1,31 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From b720b166364407ceb05385f5e72cb238195622ad Mon Sep 17 00:00:00 2001
+From: Vishnu Banavath <vishnu.banavath@arm.com>
+Date: Wed, 1 Sep 2021 18:33:32 +0100
+Subject: [PATCH 09/16] arm: corstone1000: execute uboot from DDR
+
+Previously uboot was executing from CVM. With the addition of
+secure partitions in optee, uboot has been moved to DDR.
+
+Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
+---
+ configs/corstone1000_defconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index dbe3c9e3f3..af1c5ecd89 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -1,6 +1,6 @@
+ CONFIG_ARM=y
+ CONFIG_TARGET_CORSTONE1000=y
+-CONFIG_SYS_TEXT_BASE=0x02100000
+CONFIG_SYS_TEXT_BASE=0x80000000
+ CONFIG_SYS_MALLOC_F_LEN=0x2000
+ CONFIG_NR_DRAM_BANKS=1
+ CONFIG_IDENT_STRING=" corstone1000 aarch64 "
+-- 
+2.33.0
+
@@ -0,0 +1,177 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From 5278fb64beabeddd6c80229e5165f91ed1e95376 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Thu, 24 Jun 2021 09:25:00 +0100
+Subject: [PATCH 10/16] cmd: load: add load command for memory mapped
+
+cp.b is used a lot as a way to load binaries to memory and execute
+them, however we may need to integrate this with the efi subsystem to
+set it up as a bootdev.
+
+So, introduce a loadm command that will be consistent with the other
+loadX commands and will call the efi API's.
+
+ex: loadm $kernel_addr $kernel_addr_r $kernel_size
+
+with this a kernel with CONFIG_EFI_STUB enabled will be loaded and
+then subsequently booted with bootefi command.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ cmd/Kconfig                      |  6 ++++
+ cmd/bootefi.c                    | 12 ++++++++
+ cmd/load.c                       | 49 ++++++++++++++++++++++++++++++++
+ include/efi_loader.h             |  2 ++
+ lib/efi_loader/efi_device_path.c | 10 +++++++
+ 5 files changed, 79 insertions(+)
+
+diff --git a/cmd/Kconfig b/cmd/Kconfig
+index a9fb4eead2..56fa0ceade 100644
+--- a/cmd/Kconfig
+++ b/cmd/Kconfig
+@@ -1048,6 +1048,12 @@ config CMD_LOADB
+ 	help
+ 	  Load a binary file over serial line.
+ 
+config CMD_LOADM
+	bool "loadm"
+	default y
+	help
+	  Load a binary over memory mapped.
+
+ config CMD_LOADS
+ 	bool "loads"
+ 	default y
+diff --git a/cmd/bootefi.c b/cmd/bootefi.c
+index cba81ffe75..9e1b91c89e 100644
+--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
+@@ -34,6 +34,18 @@ static struct efi_device_path *bootefi_device_path;
+ static void *image_addr;
+ static size_t image_size;
+ 
+/**
+ * efi_get_image_parameters() - return image parameters
+ *
+ * @img_addr:		address of loaded image in memory
+ * @img_size:		size of loaded image
+ */
+void efi_get_image_parameters(void **img_addr, size_t *img_size)
+{
+	*img_addr = image_addr;
+	*img_size = image_size;
+}
+
+ /**
+  * efi_clear_bootdev() - clear boot device
+  */
+diff --git a/cmd/load.c b/cmd/load.c
+index b7894d7db0..4de197681c 100644
+--- a/cmd/load.c
+++ b/cmd/load.c
+@@ -1020,6 +1020,45 @@ static ulong load_serial_ymodem(ulong offset, int mode)
+ 
+ #endif
+ 
+#if defined(CONFIG_CMD_LOADM)
+static int do_load_memory_bin(struct cmd_tbl *cmdtp, int flag, int argc,
+			      char *const argv[])
+{
+	ulong	addr, dest, size;
+	void	*src, *dst;
+
+	if (argc != 4)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+	dest = simple_strtoul(argv[2], NULL, 16);
+
+	size = simple_strtoul(argv[3], NULL, 16);
+
+
+	if (!size) {
+		puts ("can not load zero bytes\n");
+		return 1;
+	}
+
+	src = map_sysmem(addr, size);
+	dst = map_sysmem(dest, size);
+
+	memcpy(dst, src, size);
+
+	unmap_sysmem(src);
+	unmap_sysmem(dst);
+
+	if (IS_ENABLED(CONFIG_CMD_BOOTEFI))
+		efi_set_bootdev("Mem", "", "", map_sysmem(dest, 0), size);
+
+	printf("loaded bin to memory: size: %lu\n", size);
+
+	return 0;
+}
+#endif
+
+ /* -------------------------------------------------------------------- */
+ 
+ #if defined(CONFIG_CMD_LOADS)
+@@ -1094,3 +1133,13 @@ U_BOOT_CMD(
+ );
+ 
+ #endif	/* CONFIG_CMD_LOADB */
+
+#if defined(CONFIG_CMD_LOADM)
+U_BOOT_CMD(
+	loadm, 4, 0,	do_load_memory_bin,
+	"load binary blob from two addresses",
+	"[src_addr] [dst_addr] [size]\n"
+	"     - load a binary blob from one memory location to other"
+	" from src_addr to dst_addr by size bytes"
+);
+#endif /* CONFIG_CMD_LOADM */
+diff --git a/include/efi_loader.h b/include/efi_loader.h
+index b81180cfda..fc4f1ec67a 100644
+--- a/include/efi_loader.h
+++ b/include/efi_loader.h
+@@ -485,6 +485,8 @@ void efi_save_gd(void);
+ void efi_restore_gd(void);
+ /* Call this to relocate the runtime section to an address space */
+ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map);
+/* Call this to get image parameters */
+void efi_get_image_parameters(void **img_addr, size_t *img_size);
+ /* Call this to set the current device name */
+ void efi_set_bootdev(const char *dev, const char *devnr, const char *path,
+ 		     void *buffer, size_t buffer_size);
+diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
+index 76c2f82fe6..a610b6ff0e 100644
+--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
+@@ -1170,6 +1170,8 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr,
+ {
+ 	struct blk_desc *desc = NULL;
+ 	struct disk_partition fs_partition;
+	size_t image_size;
+	void *image_addr;
+ 	int part = 0;
+ 	char *filename;
+ 	char *s;
+@@ -1185,6 +1187,14 @@ efi_status_t efi_dp_from_name(const char *dev, const char *devnr,
+ 	} else if (!strcmp(dev, "Uart")) {
+ 		if (device)
+ 			*device = efi_dp_from_uart();
+	} else if (!strcmp(dev, "Mem")) {
+
+		efi_get_image_parameters(&image_addr, &image_size);
+
+		if (device)
+			*device = efi_dp_from_mem(EFI_RESERVED_MEMORY_TYPE,
+						  (uintptr_t)image_addr,
+						  image_size);
+ 	} else {
+ 		part = blk_get_device_part_str(dev, devnr, &desc, &fs_partition,
+ 					       1);
+-- 
+2.33.0
+
@@ -0,0 +1,61 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From 283cae5b37eced831080a50d76006359662fb6bf Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Wed, 23 Jun 2021 00:45:38 +0100
+Subject: [PATCH 11/16] arm: corstone1000: enable boot using uefi
+
+In a way to prepare future use of uefi features, enable booting using
+the bootefi binary loading.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+Signed-off-by: Rui Miguel Silva <rui.silva@arm.com>
+---
+ configs/corstone1000_defconfig | 7 +++++++
+ include/configs/corstone1000.h | 6 +++---
+ 2 files changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index af1c5ecd89..aa664029fc 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -2,6 +2,7 @@ CONFIG_ARM=y
+ CONFIG_TARGET_CORSTONE1000=y
+ CONFIG_SYS_TEXT_BASE=0x80000000
+ CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_LOAD_ADDR=0x82100000
+ CONFIG_NR_DRAM_BANKS=1
+ CONFIG_IDENT_STRING=" corstone1000 aarch64 "
+ CONFIG_FIT=y
+@@ -14,6 +15,12 @@ CONFIG_HUSH_PARSER=y
+ CONFIG_SYS_PROMPT="corstone1000# "
+ # CONFIG_CMD_CONSOLE is not set
+ CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTM=y
+CONFIG_CMD_LOADM=y
+CONFIG_CMD_BOOTEFI=y
+CONFIG_EFI_LOADER=y
+CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
+CONFIG_CMD_BOOTEFI_HELLO=y
+ # CONFIG_CMD_XIMG is not set
+ # CONFIG_CMD_EDITENV is not set
+ # CONFIG_CMD_ENV_EXISTS is not set
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index 389ac45a58..5e22e075ad 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -70,7 +70,7 @@
+ 				"fdt_high=0xffffffff\0"
+ 
+ #define CONFIG_BOOTCOMMAND					\
+-				"echo Copying Kernel to memory ... ;" \
+-                                "cp.b $kernel_addr $kernel_addr_r 0xc00000;" \
+-                                "booti $kernel_addr_r - $fdtcontroladdr; "
+				"echo Loading Kernel to memory ... ;" \
+				"loadm $kernel_addr $kernel_addr_r 0xc00000;" \
+				"bootefi $kernel_addr_r $fdtcontroladdr;"
+ #endif
+-- 
+2.33.0
+
@@ -0,0 +1,32 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From e49597b8d9058d8c5b925339b0041fd7096c622d Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Tue, 14 Sep 2021 10:46:49 +0100
+Subject: [PATCH 12/16] arm: corstone1000: enable uefi secure boot
+
+To make it possible to have a secure way to execute UEFI images
+enable UEFI secure boot support and by inherit the
+cryptographic functionalities.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ configs/corstone1000_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index aa664029fc..a8651287ed 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -43,6 +43,7 @@ CONFIG_USB=y
+ CONFIG_DM_USB=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_STORAGE=y
+CONFIG_EFI_SECURE_BOOT=y
+ CONFIG_DM_RTC=y
+ CONFIG_CMD_RTC=y
+ CONFIG_EFI_GET_TIME=y
+-- 
+2.33.0
+
@@ -0,0 +1,47 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From de37d61d1414cb6408390412cf77d7a88f8964e1 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Tue, 14 Sep 2021 22:00:47 +0100
+Subject: [PATCH 13/16] arm: corstone1000: enable handlers for uefi variables
+
+Enable the setenv/printenv -e option to handle uefi
+variables and the efidebug command.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ configs/corstone1000_defconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index a8651287ed..b17e2df47b 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -24,6 +24,7 @@ CONFIG_CMD_BOOTEFI_HELLO=y
+ # CONFIG_CMD_XIMG is not set
+ # CONFIG_CMD_EDITENV is not set
+ # CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_NVEDIT_EFI=y
+ # CONFIG_CMD_LOADS is not set
+ CONFIG_CMD_USB=y
+ # CONFIG_CMD_ITEST is not set
+@@ -33,6 +34,7 @@ CONFIG_CMD_DHCP=y
+ CONFIG_CMD_MII=y
+ CONFIG_CMD_PING=y
+ CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+ CONFIG_CMD_FAT=y
+ CONFIG_OF_CONTROL=y
+ CONFIG_REGMAP=y
+@@ -43,6 +45,7 @@ CONFIG_USB=y
+ CONFIG_DM_USB=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_STORAGE=y
+# CONFIG_HEXDUMP is not set
+ CONFIG_EFI_SECURE_BOOT=y
+ CONFIG_DM_RTC=y
+ CONFIG_CMD_RTC=y
+-- 
+2.33.0
+
@@ -0,0 +1,36 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From fe0acf22a0c30f7d3eb1a8c66fb423b4146d35ab Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Tue, 14 Sep 2021 22:07:15 +0100
+Subject: [PATCH 14/16] arm: dipha: enable efi capsule options
+
+Enable the set of efi capsule config options to enable the
+variables.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ configs/corstone1000_defconfig | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index b17e2df47b..cfe80cf5f4 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -46,6 +46,12 @@ CONFIG_DM_USB=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_STORAGE=y
+ # CONFIG_HEXDUMP is not set
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+ CONFIG_EFI_SECURE_BOOT=y
+ CONFIG_DM_RTC=y
+ CONFIG_CMD_RTC=y
+-- 
+2.33.0
+
@@ -0,0 +1,64 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From a3b3ff8fc2d4e52748989aa61f155fc92a63261a Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Tue, 22 Jun 2021 11:35:10 +0100
+Subject: [PATCH 15/16] arm: dts: add initial devicetree corstone1000 mps3
+
+Corstone1000 is a platform enabled on MPS3 FPGA Arm board. It is a cortex-a35
+with with 8MB of CVM and 32MB of QSPI, with the peripherals USB,
+ethernet and others available on the MPS3 board.
+
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+---
+ arch/arm/dts/corstone1000-mps3.dts | 37 ++++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+ create mode 100644 arch/arm/dts/corstone1000-mps3.dts
+
+diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts
+new file mode 100644
+index 0000000000..d93915dbb7
+--- /dev/null
+++ b/arch/arm/dts/corstone1000-mps3.dts
+@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+#include "corstone1000.dtsi"
+
+/ {
+	model = "corstone1000-mps3";
+
+	ethernet: eth@4010000 {
+		compatible = "smsc,lan9220", "smsc,lan9115";
+		reg = <0x40100000 0x10000>;
+		phy-mode = "mii";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+		reg-io-width = <2>;
+		smsc,irq-push-pull;
+	};
+
+	usb: usb@40200000 {
+		compatible = "nxp,usb-isp1763";
+		reg = <0x40200000 0x100000>;
+		interrupts-parent = <&gic>;
+		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+		bus-width = <16>;
+		dr_mode = "host";
+	};
+
+};
+
+&refclk {
+	clock-frequency = <50000000>;
+};
+-- 
+2.33.0
+
@@ -0,0 +1,34 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arpita S.K <arpita.s.k@arm.com>
+
+From b5ec956659c3e419fd2e95431d9359db497e4afb Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Thu, 22 Jul 2021 18:11:33 +0100
+Subject: [PATCH 16/16] arm: corstone1000: adding PSCI device tree node
+
+At this level of development PSCI is needed to initialize the SMCCC.
+
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+---
+ arch/arm/dts/corstone1000-mps3.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts
+index d93915dbb7..a3726f1e1f 100644
+--- a/arch/arm/dts/corstone1000-mps3.dts
+++ b/arch/arm/dts/corstone1000-mps3.dts
+@@ -30,6 +30,11 @@
+ 		dr_mode = "host";
+ 	};
+ 
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+ };
+ 
+ &refclk {
+-- 
+2.33.0
+
@@ -0,0 +1,32 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+From 3ee38ef07bd82c843497dc4e69a4d4c5f21dbbf7 Mon Sep 17 00:00:00 2001
+From: Vishnu Banavath <vishnu.banavath@arm.com>
+Date: Tue, 26 Oct 2021 18:29:05 +0100
+Subject: [PATCH] arm: corstone1000: amend kernel bootargs with ip=dhcp
+ earlyprintk
+
+This change is to
+* pass ip=dhcp required for ethernet to get and ip
+* enable earlyprintk to print kernel logs before the actual
+kernel driver comes up
+
+Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index cfe80cf5f4..7574553e83 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -8,7 +8,7 @@ CONFIG_IDENT_STRING=" corstone1000 aarch64 "
+ CONFIG_FIT=y
+ CONFIG_BOOTDELAY=3
+ CONFIG_USE_BOOTARGS=y
+-CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9"
+CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
+ CONFIG_HUSH_PARSER=y
+-- 
+2.17.1
+
@@ -0,0 +1,344 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+From d65bce43228e85319f515e47f3490801fe02498b Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Tue, 16 Nov 2021 12:36:27 +0000
+Subject: [PATCH 2/5] arm_ffa: introducing armffa command
+
+A new armffa command is provided as an example of how to use
+the FF-A helper functions to communicate with secure world.
+
+The armffa command allows to query secure partitions data from
+the secure world and exchanging messages with the partitions.
+
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+---
+ MAINTAINERS  |   1 +
+ cmd/Kconfig  |  10 ++
+ cmd/Makefile |   2 +
+ cmd/armffa.c | 266 +++++++++++++++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 279 insertions(+)
+ create mode 100644 cmd/armffa.c
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 77b40f4689..ca4dd584e2 100644
+--- a/MAINTAINERS
+++ b/MAINTAINERS
+@@ -218,6 +218,7 @@ F:	include/configs/turris_*.h
+ ARM FF-A
+ M:	Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ S:	Maintained
+F:	cmd/armffa.c
+ F:	drivers/arm-ffa/
+ F:	include/arm_ffa.h
+ F:	include/arm_ffa_helper.h
+diff --git a/cmd/Kconfig b/cmd/Kconfig
+index 56fa0ceade..b7beedd883 100644
+--- a/cmd/Kconfig
+++ b/cmd/Kconfig
+@@ -785,6 +785,16 @@ endmenu
+ 
+ menu "Device access commands"
+ 
+config CMD_ARMFFA
+	bool "Arm FF-A test command"
+	depends on ARM_FFA_TRANSPORT
+	help
+	  Provides a test command for the Arm FF-A driver
+	  supported options:
+		- Listing the partition(s) info
+		- Sending a data pattern to the specified partition
+		- Displaying the arm_ffa device info
+
+ config CMD_ARMFLASH
+ 	#depends on FLASH_CFI_DRIVER
+ 	bool "armflash"
+diff --git a/cmd/Makefile b/cmd/Makefile
+index 9d10e07f0e..dcd25168ab 100644
+--- a/cmd/Makefile
+++ b/cmd/Makefile
+@@ -12,6 +12,8 @@ obj-y += panic.o
+ obj-y += version.o
+ 
+ # command
+
+obj-$(CONFIG_CMD_ARMFFA) += armffa.o
+ obj-$(CONFIG_CMD_ACPI) += acpi.o
+ obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o
+ obj-$(CONFIG_CMD_AES) += aes.o
+diff --git a/cmd/armffa.c b/cmd/armffa.c
+new file mode 100644
+index 0000000000..71a6ebb656
+--- /dev/null
+++ b/cmd/armffa.c
+@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 ARM Limited
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <arm_ffa_helper.h>
+#include <asm/io.h>
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <stdlib.h>
+
+/**
+ * do_ffa_get_singular_partition_info - implementation of the getpart subcommand
+ * @cmdtp:		Command Table
+ * @flag:		flags
+ * @argc:		number of arguments
+ * @argv:		arguments
+ *
+ * This function queries the secure partition information which the UUID is provided
+ * as an argument. The function uses the arm_ffa driver helper function
+ * to retrieve the data.
+ * The input UUID string is expected to be in big endian format.
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+static int do_ffa_get_singular_partition_info(struct cmd_tbl *cmdtp, int flag, int argc,
+					      char *const argv[])
+{
+	struct ffa_interface_data func_data = {0};
+	u32 count = 0;
+	int ret;
+	union ffa_partition_uuid service_uuid = {0};
+	struct ffa_partition_info *parts_info;
+	u32 info_idx;
+
+	if (argc != 1)
+		return -EINVAL;
+
+	if (ffa_uuid_str_to_bin(argv[0], (unsigned char *)&service_uuid)) {
+		ffa_err("Invalid UUID");
+		return -EINVAL;
+	}
+
+	/*
+	 * get from the driver the count of the SPs matching the UUID
+	 */
+	func_data.data0_size = sizeof(service_uuid);
+	func_data.data0 = &service_uuid;
+	func_data.data1_size = sizeof(count);
+	func_data.data1 = &count;
+
+	ret = ffa_helper_get_partitions_info(&func_data);
+	if (ret != FFA_ERR_STAT_SUCCESS) {
+		ffa_err("Failure in querying partitions count (error code: %d)", ret);
+		return ret;
+	}
+
+	if (!count) {
+		ffa_info("No secure partition found");
+		return ret;
+	}
+
+	/*
+	 * pre-allocate a buffer to be filled by the driver
+	 * with	 ffa_partition_info structs
+	 */
+
+	parts_info = calloc(count, sizeof(struct ffa_partition_info));
+	if (!parts_info)
+		return -EINVAL;
+
+	ffa_info("Pre-allocating %d partition(s) info structures", count);
+
+	func_data.data1_size = count * sizeof(struct ffa_partition_info);
+	func_data.data1 = parts_info;
+
+	/*
+	 * ask the driver to fill the buffer with the SPs info
+	 */
+	ret = ffa_helper_get_partitions_info(&func_data);
+	if (ret != FFA_ERR_STAT_SUCCESS) {
+		ffa_err("Failure in querying partition(s) info (error code: %d)", ret);
+		free(parts_info);
+		return ret;
+	}
+
+	/*
+	 * SPs found , show the partition information
+	 */
+	for (info_idx = 0; info_idx < count ; info_idx++) {
+		ffa_info("Partition: id = 0x%x , exec_ctxt 0x%x , properties 0x%x",
+			 parts_info[info_idx].id,
+			 parts_info[info_idx].exec_ctxt,
+			 parts_info[info_idx].properties);
+	}
+
+	free(parts_info);
+
+	return 0;
+}
+
+/**
+ * do_ffa_msg_send_direct_req - implementation of the ping subcommand
+ * @cmdtp:		Command Table
+ * @flag:		flags
+ * @argc:		number of arguments
+ * @argv:		arguments
+ *
+ * This function sends data to the secure partition which the ID is provided
+ * as an argument. The function uses the arm_ffa driver helper function
+ * to send data.
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+int  do_ffa_msg_send_direct_req(struct cmd_tbl *cmdtp, int flag, int argc,
+				char *const argv[])
+{
+	struct ffa_interface_data func_data = {0};
+	struct ffa_send_direct_data msg = {0};
+	u32 pattern = 0xaabbccd0;
+	u16 part_id;
+	int ret;
+
+	if (argc != 1)
+		return -EINVAL;
+
+	errno = 0;
+	part_id = strtoul(argv[0], NULL, 16);
+
+	if (errno) {
+		ffa_err("Invalid partition ID");
+		return -EINVAL;
+	}
+
+	/*
+	 * telling the driver which partition to use
+	 */
+	func_data.data0_size = sizeof(part_id);
+	func_data.data0 = &part_id;
+
+	/*
+	 * filling the message data
+	 */
+	msg.a3 = ++pattern;
+	msg.a4 = ++pattern;
+	msg.a5 = ++pattern;
+	msg.a6 = ++pattern;
+	msg.a7 = ++pattern;
+	func_data.data1_size = sizeof(msg);
+	func_data.data1 = &msg;
+
+	ret = ffa_helper_msg_send_direct_req(&func_data);
+	if (ret == FFA_ERR_STAT_SUCCESS) {
+		u8 cnt;
+
+		ffa_info("SP response:\n[LSB]");
+		for (cnt = 0;
+		     cnt < sizeof(struct ffa_send_direct_data) / sizeof(u32);
+		     cnt++)
+			ffa_info("0x%x", ((u32 *)&msg)[cnt]);
+	} else {
+		ffa_err("Sending direct request error (%d)", ret);
+	}
+
+	return ret;
+}
+
+/**
+ *do_ffa_dev_list - implementation of the devlist subcommand
+ * @cmdtp: [in]		Command Table
+ * @flag:		flags
+ * @argc:		number of arguments
+ * @argv:		arguments
+ *
+ * This function queries the devices belonging to the UCLASS_FFA
+ * class. Currently, one device is expected to show up: the arm_ffa device
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+int do_ffa_dev_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	struct udevice *dev = NULL;
+	int i, ret;
+
+	ffa_info("arm_ffa uclass entries:");
+
+	for (i = 0, ret = uclass_first_device(UCLASS_FFA, &dev);
+	     dev;
+	     ret = uclass_next_device(&dev), i++) {
+		if (ret)
+			break;
+
+		ffa_info("entry %d - instance %08x, ops %08x, plat %08x",
+			 i,
+			 (u32)map_to_sysmem(dev),
+			 (u32)map_to_sysmem(dev->driver->ops),
+			 (u32)map_to_sysmem(dev_get_plat(dev)));
+	}
+
+	return cmd_process_error(cmdtp, ret);
+}
+
+static struct cmd_tbl armffa_commands[] = {
+	U_BOOT_CMD_MKENT(getpart, 1, 1, do_ffa_get_singular_partition_info, "", ""),
+	U_BOOT_CMD_MKENT(ping, 1, 1, do_ffa_msg_send_direct_req, "", ""),
+	U_BOOT_CMD_MKENT(devlist, 0, 1, do_ffa_dev_list, "", ""),
+};
+
+/**
+ * do_armffa - the armffa command main function
+ * @cmdtp:	Command Table
+ * @flag:		flags
+ * @argc:		number of arguments
+ * @argv:		arguments
+ *
+ * This function identifies which armffa subcommand to run.
+ * Then, it makes sure the arm_ffa device is probed and
+ * ready for use.
+ * Then, it runs the subcommand.
+ *
+ * Return:
+ *
+ * CMD_RET_SUCCESS: on success, otherwise failure
+ */
+static int do_armffa(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	struct cmd_tbl *armffa_cmd;
+	int ret;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	armffa_cmd = find_cmd_tbl(argv[1], armffa_commands, ARRAY_SIZE(armffa_commands));
+
+	argc -= 2;
+	argv += 2;
+
+	if (!armffa_cmd || argc > armffa_cmd->maxargs)
+		return CMD_RET_USAGE;
+
+	ret = ffa_helper_init_device();
+	if (ret != FFA_ERR_STAT_SUCCESS)
+		return cmd_process_error(cmdtp, ret);
+
+	ret = armffa_cmd->cmd(armffa_cmd, flag, argc, argv);
+
+	return cmd_process_error(armffa_cmd, ret);
+}
+
+U_BOOT_CMD(armffa, 4, 1, do_armffa,
+	   "Arm FF-A operations test command",
+	   "getpart <partition UUID>\n"
+	   "	 - lists the partition(s) info\n"
+	   "ping <partition ID>\n"
+	   "	 - sends a data pattern to the specified partition\n"
+	   "devlist\n"
+	   "	 - displays the arm_ffa device info\n");
+-- 
+2.17.1
+
@@ -0,0 +1,134 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+From b77c6c2c8c0dff9a41e1dbb9a4e9c1ecac00c7f6 Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Tue, 16 Nov 2021 12:38:48 +0000
+Subject: [PATCH 3/5] arm_ffa: introducing test module for UCLASS_FFA
+
+This is the test module for the UCLASS_FFA class.
+
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+---
+ MAINTAINERS      |  1 +
+ test/dm/Makefile |  1 +
+ test/dm/ffa.c    | 56 ++++++++++++++++++++++++++++++++++++++++++++++++
+ test/dm/ffa.h    | 19 ++++++++++++++++
+ 4 files changed, 77 insertions(+)
+ create mode 100644 test/dm/ffa.c
+ create mode 100644 test/dm/ffa.h
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index ca4dd584e2..e73637e127 100644
+--- a/MAINTAINERS
+++ b/MAINTAINERS
+@@ -223,6 +223,7 @@ F:	drivers/arm-ffa/
+ F:	include/arm_ffa.h
+ F:	include/arm_ffa_helper.h
+ F:	lib/arm-ffa/
+F:	test/dm/ffa.c
+ 
+ ARM FREESCALE IMX
+ M:	Stefano Babic <sbabic@denx.de>
+diff --git a/test/dm/Makefile b/test/dm/Makefile
+index c9644617a1..c48f034584 100644
+--- a/test/dm/Makefile
+++ b/test/dm/Makefile
+@@ -74,6 +74,7 @@ obj-$(CONFIG_POWER_DOMAIN) += power-domain.o
+ obj-$(CONFIG_ACPI_PMC) += pmc.o
+ obj-$(CONFIG_DM_PMIC) += pmic.o
+ obj-$(CONFIG_DM_PWM) += pwm.o
+obj-$(CONFIG_ARM_FFA_TRANSPORT) += ffa.o
+ obj-$(CONFIG_QFW) += qfw.o
+ obj-$(CONFIG_RAM) += ram.o
+ obj-y += regmap.o
+diff --git a/test/dm/ffa.c b/test/dm/ffa.c
+new file mode 100644
+index 0000000000..b937cea57b
+--- /dev/null
+++ b/test/dm/ffa.c
+@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for UCLASS_FFA  class
+ *
+ * (C) Copyright 2021 ARM Limited
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+#include <arm_ffa_helper.h>
+#include "ffa.h"
+
+/* Basic test of 'armffa' command */
+static int dm_test_armffa_cmd(struct unit_test_state *uts)
+{
+	ut_assertok(ffa_helper_init_device());
+
+	ut_assertok(console_record_reset_enable());
+
+	/* armffa getpart <UUID> */
+	ut_assertok(run_command("armffa getpart " SE_PROXY_PARTITION_UUID, 0));
+	ut_assert_console_end();
+
+	/* armffa ping <ID> */
+	ut_assertok(run_command("armffa ping " SE_PROXY_PARTITION_ID, 0));
+	ut_assert_console_end();
+
+	/* armffa devlist */
+	ut_assertok(run_command("armffa devlist", 0));
+	ut_assert_console_end();
+
+	return 0;
+}
+
+DM_TEST(dm_test_armffa_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC);
+
+static int  test_ffa_msg_send_direct_req(void)
+{
+	char *const argv[1] = {SE_PROXY_PARTITION_ID}; /* Corstone1000 SE Proxy ID */
+
+	return do_ffa_msg_send_direct_req(NULL, 0, 1, argv);
+}
+
+/* Basic test of the FFA uclass */
+static int dm_test_ffa_uclass(struct unit_test_state *uts)
+{
+	ut_assertok(ffa_init_device());
+	ut_assertok(test_ffa_msg_send_direct_req());
+	return 0;
+}
+
+DM_TEST(dm_test_ffa_uclass, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+diff --git a/test/dm/ffa.h b/test/dm/ffa.h
+new file mode 100644
+index 0000000000..a0802bd692
+--- /dev/null
+++ b/test/dm/ffa.h
+@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 ARM Limited
+ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+ */
+
+#ifndef __TEST_DM_FFA_H
+#define __TEST_DM_FFA_H
+
+#define SE_PROXY_PARTITION_ID "0x8002"
+#define SE_PROXY_PARTITION_UUID "46bb39d1-b4d9-45b5-88ff-040027dab249"
+
+/**
+ * do_ffa_msg_send_direct_req - implementation of the ping subcommand
+ */
+int  do_ffa_msg_send_direct_req(struct cmd_tbl *cmdtp, int flag, int argc,
+				char *const argv[]);
+
+#endif /*__TEST_DM_FFA_H */
+-- 
+2.17.1
+
@@ -0,0 +1,383 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+From f84b0592d5456aee690164d195f3bfe592086a06 Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Wed, 13 Oct 2021 17:51:44 +0100
+Subject: [PATCH 4/5] arm_ffa: introducing MM communication with FF-A
+
+This commit allows to perform MM communication using FF-A transport.
+
+The MM SP (also called partition) can be StandAlonneMM or smm-gateway.
+Both partitions run in OP-TEE.
+
+When using the u-boot FF-A driver, StandAlonneMM and smm-gateway are
+supported.
+
+On EFI services such as GetVariable()/SetVariable(), the data
+is copied from the communication buffer to the MM shared buffer.
+
+Then, notifies the MM SP about data availability in the MM shared buffer.
+Communication with the MM SP is performed using FF-A transport.
+
+On such event, MM SP can read the data and updates the MM shared buffer
+with response data.
+
+The response data is copied back to the communication buffer.
+
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+---
+ lib/efi_loader/Kconfig            |  14 +-
+ lib/efi_loader/efi_variable_tee.c | 255 +++++++++++++++++++++++++++++-
+ 2 files changed, 263 insertions(+), 6 deletions(-)
+
+diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
+index 156b391521..120b656504 100644
+--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
+@@ -53,13 +53,23 @@ config EFI_VARIABLE_FILE_STORE
+ 	  stored as file /ubootefi.var on the EFI system partition.
+ 
+ config EFI_MM_COMM_TEE
+-	bool "UEFI variables storage service via OP-TEE"
+-	depends on OPTEE
+	bool "UEFI variables storage service via the trusted world"
+	depends on OPTEE || ARM_FFA_TRANSPORT
+ 	help
+	  The MM SP (also called partition) can be StandAlonneMM or smm-gateway.
+	  When using the u-boot OP-TEE driver, StandAlonneMM is supported.
+	  When using the u-boot FF-A  driver, StandAlonneMM and smm-gateway are supported.
+
+ 	  If OP-TEE is present and running StandAloneMM, dispatch all UEFI
+ 	  variable related operations to that. The application will verify,
+ 	  authenticate and store the variables on an RPMB.
+ 
+	  When ARM_FFA_TRANSPORT is used, dispatch all UEFI variable related
+	  operations to the MM SP running under Optee in the trusted world.
+	  A door bell mechanism is used to notify the SP when there is data in the shared
+	  MM buffer. The data is copied by u-boot to thea shared buffer before issuing
+	  the door bell event.
+
+ endchoice
+ 
+ config EFI_VARIABLES_PRESEED
+diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c
+index 51920bcb51..b363ec92bf 100644
+--- a/lib/efi_loader/efi_variable_tee.c
+++ b/lib/efi_loader/efi_variable_tee.c
+@@ -15,7 +15,28 @@
+ #include <malloc.h>
+ #include <mm_communication.h>
+ 
+#if (IS_ENABLED(CONFIG_OPTEE))
+ #define OPTEE_PAGE_SIZE BIT(12)
+#endif
+
+#if (IS_ENABLED(CONFIG_ARM_FFA_TRANSPORT))
+
+#include <arm_ffa_helper.h>
+#include <mapmem.h>
+
+/* MM return codes */
+#define MM_SUCCESS (0)
+
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 (0xC4000061)
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
+
+/* MM_SP_UUID_DATA defined by the platform */
+union ffa_partition_uuid mm_sp_svc_uuid = {.bytes = {MM_SP_UUID_DATA}};
+
+static u16 __efi_runtime_data mm_sp_id;
+
+#endif
+
+ extern struct efi_var_file __efi_runtime_data *efi_var_buf;
+ static efi_uintn_t max_buffer_size;	/* comm + var + func + data */
+ static efi_uintn_t max_payload_size;	/* func + data */
+@@ -25,6 +46,7 @@ struct mm_connection {
+ 	u32 session;
+ };
+ 
+#if (IS_ENABLED(CONFIG_OPTEE))
+ /**
+  * get_connection() - Retrieve OP-TEE session for a specific UUID.
+  *
+@@ -140,16 +162,229 @@ static efi_status_t optee_mm_communicate(void *comm_buf, ulong dsize)
+ 
+ 	return ret;
+ }
+#endif
+
+#if (IS_ENABLED(CONFIG_ARM_FFA_TRANSPORT))
+
+/**
+ * ffa_notify_mm_sp() - Announce there is data in the shared buffer
+ *
+ * Notifies the MM partition in the trusted world that
+ * data is available in the shared buffer.
+ * This is a blocking call during which trusted world has exclusive access
+ * to the MM shared buffer.
+ *
+ * Return:
+ *
+ * 0 on success
+ */
+static int __efi_runtime ffa_notify_mm_sp(void)
+{
+	struct ffa_interface_data func_data = {0};
+	struct ffa_send_direct_data msg = {0};
+	int ret;
+	u32 sp_event_complete;
+	int sp_event_ret;
+
+	func_data.data0_size = sizeof(mm_sp_id);
+	func_data.data0 = &mm_sp_id;
+
+	msg.a3 = FFA_SHARED_MM_BUFFER_ADDR;
+	msg.a4 = FFA_SHARED_MM_BUFFER_SIZE;
+	func_data.data1_size = sizeof(msg);
+	func_data.data1 = &msg;
+
+	ret = ffa_helper_msg_send_direct_req(&func_data);
+	if (ret != FFA_ERR_STAT_SUCCESS) {
+		log_err("EFI: Failure to notify the MM SP , FF-A  error (%d)\n", ret);
+		return ret;
+	}
+
+	sp_event_complete = msg.a3;
+	sp_event_ret = (int)msg.a4;
+
+	if (sp_event_complete == ARM_SVC_ID_SP_EVENT_COMPLETE && sp_event_ret == MM_SUCCESS)
+		return 0;
+
+	log_err("EFI: Failure to notify the MM SP (0x%x , %d)\n",
+		sp_event_complete,
+		sp_event_ret);
+
+	return -EACCES;
+}
+
+/**
+ * ffa_discover_mm_sp_id() - Query the MM partition ID
+ *
+ * Use the FF-A driver to get the MM partition ID.
+ * If multiple partitions are found, use the first one
+ *
+ * Return:
+ *
+ * 0 on success
+ */
+static int __efi_runtime ffa_discover_mm_sp_id(void)
+{
+	struct ffa_interface_data func_data = {0};
+	u32 count = 0;
+	int ret;
+	struct ffa_partition_info *parts_info;
+
+	/*
+	 * get from the driver the count of the SPs matching the UUID
+	 */
+	func_data.data0_size = sizeof(mm_sp_svc_uuid);
+	func_data.data0 = &mm_sp_svc_uuid;
+	func_data.data1_size = sizeof(count);
+	func_data.data1 = &count;
+
+	ret = ffa_helper_get_partitions_info(&func_data);
+	if (ret != FFA_ERR_STAT_SUCCESS) {
+		log_err("EFI: Failure in querying partitions count (error code: %d)\n", ret);
+		return ret;
+	}
+
+	if (!count) {
+		log_info("EFI: No MM partition found\n");
+		return ret;
+	}
+
+	/*
+	 * pre-allocate a buffer to be filled by the driver
+	 * with	 ffa_partition_info structs
+	 */
+
+	parts_info = calloc(count, sizeof(struct ffa_partition_info));
+	if (!parts_info)
+		return -EINVAL;
+
+	log_info("EFI: Pre-allocating %d partition(s) info structures\n", count);
+
+	func_data.data1_size = count *
+		sizeof(struct ffa_partition_info);
+	func_data.data1 = parts_info;
+
+	/*
+	 * ask the driver to fill the
+	 * buffer with the SPs info
+	 */
+	ret = ffa_helper_get_partitions_info(&func_data);
+	if (ret != FFA_ERR_STAT_SUCCESS) {
+		log_err("EFI: Failure in querying partition(s) info (error code: %d)\n", ret);
+		free(parts_info);
+		return ret;
+	}
+
+	/*
+	 * MM SPs found , use the first one
+	 */
+
+	mm_sp_id = parts_info[0].id;
+
+	log_info("EFI: MM partition ID 0x%x\n", mm_sp_id);
+
+	free(parts_info);
+
+	return 0;
+}
+
+/**
+ * ffa_mm_communicate() - Exchange EFI services data with  the MM partition using FF-A
+ * @comm_buf:		locally allocated communication buffer used for for rx/tx
+ * @dsize:				communication buffer size
+ *
+ * Issues a door bell event to notify the MM partition (SP) running in OP-TEE
+ * that there is data to read from the shared buffer.
+ * Communication with the MM SP is performed using FF-A transport.
+ * On the event, MM SP can read the data from the buffer and
+ * update the MM shared buffer with response data.
+ * The response data is copied back to the communication buffer.
+ *
+ * Return:
+ *
+ * EFI status code
+ */
+static efi_status_t __efi_runtime ffa_mm_communicate(void *comm_buf, ulong comm_buf_size)
+{
+	ulong tx_data_size;
+	int ffa_ret;
+	struct efi_mm_communicate_header *mm_hdr;
+	void *virt_shared_buf;
+
+	if (!comm_buf)
+		return EFI_INVALID_PARAMETER;
+
+	/* Discover MM partition ID */
+	if (!mm_sp_id && ffa_discover_mm_sp_id()  != FFA_ERR_STAT_SUCCESS) {
+		log_err("EFI: Failure to discover MM partition ID\n");
+		return EFI_UNSUPPORTED;
+	}
+
+	mm_hdr = (struct efi_mm_communicate_header *)comm_buf;
+	tx_data_size = mm_hdr->message_len + sizeof(efi_guid_t) + sizeof(size_t);
+
+	if (comm_buf_size != tx_data_size || tx_data_size > FFA_SHARED_MM_BUFFER_SIZE)
+		return EFI_INVALID_PARAMETER;
+
+	/* Copy the data to the shared buffer */
+
+	virt_shared_buf = (void *)map_sysmem((phys_addr_t)FFA_SHARED_MM_BUFFER_ADDR, 0);
+	efi_memcpy_runtime(virt_shared_buf, comm_buf, tx_data_size);
+
+	/* Announce there is data in the shared buffer */
+
+	ffa_ret = ffa_notify_mm_sp();
+	if (ffa_ret)
+		unmap_sysmem(virt_shared_buf);
+
+	switch (ffa_ret) {
+	case 0:
+	{
+		ulong rx_data_size;
+		/* Copy the MM SP response from the shared buffer to the communication buffer */
+		rx_data_size = ((struct efi_mm_communicate_header *)virt_shared_buf)->message_len +
+			sizeof(efi_guid_t) +
+			sizeof(size_t);
+
+		if (rx_data_size > comm_buf_size) {
+			unmap_sysmem(virt_shared_buf);
+			return EFI_OUT_OF_RESOURCES;
+		}
+
+		efi_memcpy_runtime(comm_buf, virt_shared_buf, rx_data_size);
+		unmap_sysmem(virt_shared_buf);
+
+		return EFI_SUCCESS;
+	}
+	case -EINVAL:
+		return EFI_DEVICE_ERROR;
+	case -EPERM:
+		return EFI_INVALID_PARAMETER;
+	case -EACCES:
+		return EFI_ACCESS_DENIED;
+	case -EBUSY:
+		return EFI_OUT_OF_RESOURCES;
+	default:
+		return EFI_ACCESS_DENIED;
+	}
+}
+#endif
+ 
+ /**
+- * mm_communicate() - Adjust the cmonnucation buffer to StandAlonneMM and send
+ * mm_communicate() - Adjust the communication buffer to the MM SP and send
+  * it to OP-TEE
+  *
+- * @comm_buf:		locally allocted communcation buffer
+ * @comm_buf:		locally allocted communication buffer
+  * @dsize:		buffer size
+ *
+ * The MM SP (also called partition) can be StandAlonneMM or smm-gateway.
+ * The comm_buf format is the same for both partitions.
+ * When using the u-boot OP-TEE driver, StandAlonneMM is supported.
+ * When using the u-boot FF-A  driver, StandAlonneMM and smm-gateway are supported.
+ *
+  * Return:		status code
+  */
+-static efi_status_t mm_communicate(u8 *comm_buf, efi_uintn_t dsize)
+static efi_status_t __efi_runtime mm_communicate(u8 *comm_buf, efi_uintn_t dsize)
+ {
+ 	efi_status_t ret;
+ 	struct efi_mm_communicate_header *mm_hdr;
+@@ -159,7 +394,11 @@ static efi_status_t mm_communicate(u8 *comm_buf, efi_uintn_t dsize)
+ 	mm_hdr = (struct efi_mm_communicate_header *)comm_buf;
+ 	var_hdr = (struct smm_variable_communicate_header *)mm_hdr->data;
+ 
+	#if (IS_ENABLED(CONFIG_OPTEE))
+ 	ret = optee_mm_communicate(comm_buf, dsize);
+	#elif (IS_ENABLED(CONFIG_ARM_FFA_TRANSPORT))
+	ret = ffa_mm_communicate(comm_buf, dsize);
+	#endif
+ 	if (ret != EFI_SUCCESS) {
+ 		log_err("%s failed!\n", __func__);
+ 		return ret;
+@@ -255,6 +494,8 @@ efi_status_t EFIAPI get_max_payload(efi_uintn_t *size)
+ 		goto out;
+ 	}
+ 	*size = var_payload->size;
+
+	#if (IS_ENABLED(CONFIG_OPTEE))
+ 	/*
+ 	 * Although the max payload is configurable on StMM, we only share a
+ 	 * single page from OP-TEE for the non-secure buffer used to communicate
+@@ -264,6 +505,12 @@ efi_status_t EFIAPI get_max_payload(efi_uintn_t *size)
+ 	if (*size > OPTEE_PAGE_SIZE)
+ 		*size = OPTEE_PAGE_SIZE - MM_COMMUNICATE_HEADER_SIZE  -
+ 			MM_VARIABLE_COMMUNICATE_SIZE;
+	#elif (IS_ENABLED(CONFIG_ARM_FFA_TRANSPORT))
+		if (*size > FFA_SHARED_MM_BUFFER_SIZE)
+			*size = FFA_SHARED_MM_BUFFER_SIZE - MM_COMMUNICATE_HEADER_SIZE  -
+				MM_VARIABLE_COMMUNICATE_SIZE;
+	#endif
+
+ 	/*
+ 	 * There seems to be a bug in EDK2 miscalculating the boundaries and
+ 	 * size checks, so deduct 2 more bytes to fulfill this requirement. Fix
+@@ -690,7 +937,7 @@ void efi_variables_boot_exit_notify(void)
+ 		ret = EFI_NOT_FOUND;
+ 
+ 	if (ret != EFI_SUCCESS)
+-		log_err("Unable to notify StMM for ExitBootServices\n");
+		log_err("Unable to notify the MM partition for ExitBootServices\n");
+ 	free(comm_buf);
+ 
+ 	/*
+-- 
+2.17.1
+
@@ -0,0 +1,112 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+From a0841a2072215b1912d95224de204c7a013650f0 Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Tue, 2 Nov 2021 16:44:39 +0000
+Subject: [PATCH 5/5] arm_ffa: corstone1000: enable FF-A and MM support
+
+This commit allows corstone1000 platform to perform
+MM communication between u-boot and the secure world
+using FF-A transport.
+
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+---
+ arch/arm/dts/corstone1000-fvp.dts  |  4 ++++
+ arch/arm/dts/corstone1000-mps3.dts |  4 ++++
+ arch/arm/dts/corstone1000.dtsi     |  7 +++++++
+ configs/corstone1000_defconfig     |  5 +++++
+ include/configs/corstone1000.h     | 14 ++++++++++++++
+ 5 files changed, 34 insertions(+)
+
+diff --git a/arch/arm/dts/corstone1000-fvp.dts b/arch/arm/dts/corstone1000-fvp.dts
+index 2188ca5e0e..92da15df4e 100644
+--- a/arch/arm/dts/corstone1000-fvp.dts
+++ b/arch/arm/dts/corstone1000-fvp.dts
+@@ -26,3 +26,7 @@
+ &refclk {
+        clock-frequency = <50000000>;
+ };
+
+&arm_ffa {
+	status = "okay";
+};
+diff --git a/arch/arm/dts/corstone1000-mps3.dts b/arch/arm/dts/corstone1000-mps3.dts
+index a3726f1e1f..6842395405 100644
+--- a/arch/arm/dts/corstone1000-mps3.dts
+++ b/arch/arm/dts/corstone1000-mps3.dts
+@@ -40,3 +40,7 @@
+ &refclk {
+ 	clock-frequency = <50000000>;
+ };
+
+&arm_ffa {
+	status = "okay";
+};
+diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
+index da1725e01f..97dfac9ae7 100644
+--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
+@@ -153,4 +153,11 @@
+ 		compatible = "arm,psci-1.0", "arm,psci-0.2";
+ 		method = "smc";
+ 	};
+
+	arm_ffa: arm_ffa {
+		compatible = "arm,ffa";
+		method = "smc";
+		status = "disabled";
+	};
+
+ };
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index 7574553e83..abd52af8fc 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -9,6 +9,7 @@ CONFIG_FIT=y
+ CONFIG_BOOTDELAY=3
+ CONFIG_USE_BOOTARGS=y
+ CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
+CONFIG_LOGLEVEL=7
+ # CONFIG_DISPLAY_CPUINFO is not set
+ # CONFIG_DISPLAY_BOARDINFO is not set
+ CONFIG_HUSH_PARSER=y
+@@ -45,6 +46,10 @@ CONFIG_USB=y
+ CONFIG_DM_USB=y
+ CONFIG_USB_ISP1760=y
+ CONFIG_USB_STORAGE=y
+CONFIG_ARM_FFA_TRANSPORT=y
+CONFIG_EFI_MM_COMM_TEE=y
+# CONFIG_OPTEE is not set
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
+ # CONFIG_HEXDUMP is not set
+ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+ CONFIG_EFI_CAPSULE_ON_DISK=y
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index 5e22e075ad..7b644fb52b 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -12,6 +12,20 @@
+ #ifndef __CORSTONE1000_H
+ #define __CORSTONE1000_H
+ 
+#include <linux/sizes.h>
+
+/* MM SP UUID binary data (little-endian format) */
+#define MM_SP_UUID_DATA	\
+	0xed, 0x32, 0xd5, 0x33,	\
+	0x99, 0xe6, 0x42, 0x09,	\
+	0x9c, 0xc0, 0x2d, 0x72,	\
+	0xcd, 0xd9, 0x98, 0xa7
+
+#define FFA_SHARED_MM_BUFFER_SIZE		SZ_4K /* 4 KB */
+
+/* shared buffer physical address used for communication between u-boot and the MM SP */
+#define FFA_SHARED_MM_BUFFER_ADDR		(0x023F8000)
+
+ #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x03f00000)
+ #define CONFIG_SKIP_LOWLEVEL_INIT
+ 
+-- 
+2.17.1
+
@@ -0,0 +1,419 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+From 666463acdd3dbf090952b8bc8b0f2508137804a4 Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Thu, 11 Nov 2021 16:27:59 +0000
+Subject: [PATCH] efi: corstone1000: introduce EFI capsule update
+
+This commit provides capsule update feature for Corstone1000.
+
+This feature is available before and after ExitBootServices().
+
+A platform specific capsule buffer is allocated. This buffer
+is physically contiguous and allocated at the start of the DDR
+memory after u-boot relocation to the end of DDR.
+
+The capsule buffer is shared between u-boot and the secure world.
+On UpdateCapsule() , capsule data is copied to the buffer
+and a buffer ready event is generated using FF-A transport.
+
+On ExitBootServices() a kernel started event is sent to the
+SE Proxy FW update service. This event is generated on each boot.
+
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+---
+ arch/arm/dts/corstone1000.dtsi |   4 +-
+ configs/corstone1000_defconfig |   3 +-
+ include/configs/corstone1000.h |  30 +++++---
+ include/efi_loader.h           |   4 +-
+ lib/efi_loader/efi_boottime.c  |  47 +++++++++++
+ lib/efi_loader/efi_capsule.c   | 137 ++++++++++++++++++++++++++++++++-
+ lib/efi_loader/efi_setup.c     |  15 ++++
+ 7 files changed, 224 insertions(+), 16 deletions(-)
+
+diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
+index 97dfac9ae7..0ea3a19698 100644
+--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
+@@ -26,9 +26,9 @@
+ 		};
+ 	};
+ 
+-	memory@80000000 {
+	memory@88200000 {
+ 		device_type = "memory";
+-		reg = <0x80000000 0x80000000>;
+		reg = <0x88200000 0x77e00000>;
+ 	};
+ 
+ 	gic: interrupt-controller@1c000000 {
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index 48ec37f641..c5eb9af101 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -53,7 +53,8 @@ CONFIG_EFI_MM_COMM_TEE=y
+ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+ CONFIG_EFI_CAPSULE_ON_DISK=y
+ CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y
+-CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+# CONFIG_EFI_CAPSULE_AUTHENTICATE is not set
+CONFIG_EFI_HAVE_CAPSULE_SUPPORT=y
+ CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+ CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+ CONFIG_EFI_SECURE_BOOT=y
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index 7b644fb52b..ce50bd5cc9 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -14,6 +14,24 @@
+ 
+ #include <linux/sizes.h>
+ 
+/* The SE Proxy partition ID*/
+#define CORSTONE1000_SEPROXY_PART_ID		(0x8002)
+
+/* Update service ID provided by  the SE Proxy secure partition*/
+#define CORSTONE1000_SEPROXY_UPDATE_SVC_ID	(0x4)
+
+/* Notification events used with SE Proxy update service */
+#define CORSTONE1000_BUFFER_READY_EVT	(0x1)
+#define CORSTONE1000_KERNEL_STARTED_EVT	(0x2)
+
+/* Size in 4KB pages of the EFI capsule buffer */
+#define CORSTONE1000_CAPSULE_BUFFER_SIZE		(8192) /* 32 MB */
+
+/* Capsule GUID */
+#define EFI_CORSTONE1000_CAPSULE_ID_GUID \
+	EFI_GUID(0x3a770ddc, 0x409b, 0x48b2, 0x81, 0x41, \
+		 0x93, 0xb7, 0xc6, 0x0b, 0x20, 0x9e)
+
+ /* MM SP UUID binary data (little-endian format) */
+ #define MM_SP_UUID_DATA	\
+ 	0xed, 0x32, 0xd5, 0x33,	\
+@@ -57,20 +75,14 @@
+ 
+ /* Physical Memory Map */
+ #define PHYS_SDRAM_1		(V2M_BASE)
+-#define PHYS_SDRAM_2		(V2M_QSPI)
+-
+-/* Top 16MB reserved for secure world use (maybe not needed) */
+-#define DRAM_SEC_SIZE		0x01000000
+-#define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
+#define PHYS_SDRAM_1_SIZE	0x80000000
+ 
+-#define PHYS_SDRAM_2_SIZE	0x02000000
+/* Default load address for the source command */
+#define CONFIG_SYS_LOAD_ADDR   (V2M_BASE + 0x10000000)
+ 
+ /* Size of malloc() pool */
+ #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (8 << 20))
+ 
+-/* Miscellaneous configurable options */
+-#define CONFIG_SYS_LOAD_ADDR	(V2M_BASE + 0x10000000)
+-
+ #define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+ 
+ /* Monitor Command Prompt */
+diff --git a/include/efi_loader.h b/include/efi_loader.h
+index 611aae64a9..ebee330c68 100644
+--- a/include/efi_loader.h
+++ b/include/efi_loader.h
+@@ -950,11 +950,11 @@ extern const struct efi_firmware_management_protocol efi_fmp_fit;
+ extern const struct efi_firmware_management_protocol efi_fmp_raw;
+ 
+ /* Capsule update */
+-efi_status_t EFIAPI efi_update_capsule(
+efi_status_t __efi_runtime EFIAPI efi_update_capsule(
+ 		struct efi_capsule_header **capsule_header_array,
+ 		efi_uintn_t capsule_count,
+ 		u64 scatter_gather_list);
+-efi_status_t EFIAPI efi_query_capsule_caps(
+efi_status_t __efi_runtime EFIAPI efi_query_capsule_caps(
+ 		struct efi_capsule_header **capsule_header_array,
+ 		efi_uintn_t capsule_count,
+ 		u64 *maximum_capsule_size,
+diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
+index 6f5f32b903..8175177a1c 100644
+--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
+@@ -2090,6 +2090,44 @@ static void efi_exit_caches(void)
+ #endif
+ }
+ 
+#if IS_ENABLED(CONFIG_TARGET_CORSTONE1000)
+/**
+ * efi_corstone1000_kernel_started_event - notifies SE Proxy FW update service
+ *
+ * This function notifies the SE Proxy update service that the kernel has already started
+ *
+ * Return:
+ *
+ * 0: on success, otherwise failure
+ */
+static int efi_corstone1000_kernel_started_event(void)
+{
+	struct ffa_interface_data func_data = {0};
+	struct ffa_send_direct_data msg = {0};
+	u16 part_id = CORSTONE1000_SEPROXY_PART_ID;
+
+	log_debug("[%s]\n", __func__);
+
+	/*
+	 * telling the driver which partition to use
+	 */
+	func_data.data0_size = sizeof(part_id);
+	func_data.data0 = &part_id;
+
+	/*
+	 * setting the kernel started  event arguments
+	 */
+	msg.a3 = CORSTONE1000_SEPROXY_UPDATE_SVC_ID;
+	msg.a5 = CORSTONE1000_KERNEL_STARTED_EVT;
+
+	func_data.data1_size = sizeof(msg);
+	func_data.data1 = &msg;
+
+	return ffa_helper_msg_send_direct_req(&func_data);
+}
+
+#endif
+
+ /**
+  * efi_exit_boot_services() - stop all boot services
+  * @image_handle: handle of the loaded image
+@@ -2195,6 +2233,15 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle,
+ 	/* Recalculate CRC32 */
+ 	efi_update_table_header_crc32(&systab.hdr);
+ 
+#if IS_ENABLED(CONFIG_TARGET_CORSTONE1000)
+	/* Notifying SE Proxy FW update service */
+	ffa_ret = efi_corstone1000_kernel_started_event();
+	if (ffa_ret)
+		debug("[efi_boottime][ERROR]: Failure to notify SE Proxy FW update service\n");
+	else
+		debug("[efi_boottime][INFO]: SE Proxy FW update service notified\n");
+#endif
+
+ 	/* Give the payload some time to boot */
+ 	efi_set_watchdog(0);
+ 	WATCHDOG_RESET();
+diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
+index b75e4bcba1..f180555faf 100644
+--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
+@@ -20,6 +20,14 @@
+ #include <crypto/pkcs7_parser.h>
+ #include <linux/err.h>
+ 
+#ifdef CONFIG_TARGET_CORSTONE1000
+#include <arm_ffa_helper.h>
+#include <cpu_func.h>
+
+void *__efi_runtime_data corstone1000_capsule_buf; /* capsule shared buffer virtual address */
+efi_guid_t corstone1000_capsule_guid = EFI_CORSTONE1000_CAPSULE_ID_GUID;
+#endif
+
+ const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID;
+ static const efi_guid_t efi_guid_firmware_management_capsule_id =
+ 		EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
+@@ -472,6 +480,89 @@ static efi_status_t efi_capsule_update_firmware(
+ }
+ #endif /* CONFIG_EFI_CAPSULE_FIRMWARE_MANAGEMENT */
+ 
+#if IS_ENABLED(CONFIG_TARGET_CORSTONE1000)
+
+/**
+ * efi_corstone1000_alloc_capsule_shared_buf - allocate capsule shared buffer
+ * @capsule_image_size:	The capsule data (header + payload)
+ *
+ * This function allocates the physically contiguous buffer shared between u-boot
+ * and the secure world. On UpdateCapsule() capsule data is copied to the buffer
+ * and a door bell event is generated.
+ * The buffer is allocated at the start of the DDR memory after u-boot has been relocated
+ * to the end of DDR.
+ *
+ * Return:
+ *
+ * 0: on success, otherwise failure
+ */
+efi_status_t efi_corstone1000_alloc_capsule_shared_buf(void)
+{
+	efi_status_t efi_ret;
+	u64 ram_base = CONFIG_SYS_SDRAM_BASE;
+
+	log_debug("[%s]\n", __func__);
+
+	efi_ret = efi_allocate_pages(EFI_ALLOCATE_ADDRESS,
+				     EFI_RUNTIME_SERVICES_DATA,
+				     CORSTONE1000_CAPSULE_BUFFER_SIZE,
+				     &ram_base);
+
+	if (efi_ret != EFI_SUCCESS) {
+		corstone1000_capsule_buf = NULL;
+		log_err("EFI: Corstone1000: Allocating capsule shared buffer error (%d)\n"
+			, (int)efi_ret);
+		return efi_ret;
+	}
+
+	log_info("EFI: Corstone1000: Capsule shared buffer at 0x%x , size %d pages\n"
+		, (unsigned int)ram_base,
+		CORSTONE1000_CAPSULE_BUFFER_SIZE);
+
+	corstone1000_capsule_buf = (void *)map_sysmem((phys_addr_t)ram_base, 0);
+
+	return EFI_SUCCESS;
+}
+
+/**
+ * efi_corstone1000_buffer_ready_event - issue door bell event
+ * @capsule_image_size:	The capsule data (header + payload)
+ *
+ * This function notifies the SE Proxy update service that capsule data is available
+ * in the capsule shared buffer.
+ *
+ * Return:
+ *
+ * 0: on success, otherwise failure
+ */
+static int __efi_runtime efi_corstone1000_buffer_ready_event(u32 capsule_image_size)
+{
+	struct ffa_interface_data func_data = {0};
+	struct ffa_send_direct_data msg = {0};
+	u16 part_id = CORSTONE1000_SEPROXY_PART_ID;
+
+	log_debug("[%s]\n", __func__);
+
+	/*
+	 * telling the driver which partition to use
+	 */
+	func_data.data0_size = sizeof(part_id);
+	func_data.data0 = &part_id;
+
+	/*
+	 * setting the buffer ready event arguments
+	 */
+	msg.a3 = CORSTONE1000_SEPROXY_UPDATE_SVC_ID;
+	msg.a4 = capsule_image_size;
+	msg.a5 = CORSTONE1000_BUFFER_READY_EVT;
+
+	func_data.data1_size = sizeof(msg);
+	func_data.data1 = &msg;
+
+	return ffa_helper_msg_send_direct_req(&func_data);
+}
+#endif
+
+ /**
+  * efi_update_capsule() - process information from operating system
+  * @capsule_header_array:	Array of virtual address pointers
+@@ -485,7 +576,7 @@ static efi_status_t efi_capsule_update_firmware(
+  *
+  * Return:			status code
+  */
+-efi_status_t EFIAPI efi_update_capsule(
+efi_status_t __efi_runtime EFIAPI efi_update_capsule(
+ 		struct efi_capsule_header **capsule_header_array,
+ 		efi_uintn_t capsule_count,
+ 		u64 scatter_gather_list)
+@@ -502,6 +593,13 @@ efi_status_t EFIAPI efi_update_capsule(
+ 		goto out;
+ 	}
+ 
+#if IS_ENABLED(CONFIG_TARGET_CORSTONE1000)
+		if (capsule_count != 1 || !corstone1000_capsule_buf) {
+			ret = EFI_INVALID_PARAMETER;
+			goto out;
+		}
+#endif
+
+ 	ret = EFI_SUCCESS;
+ 	for (i = 0, capsule = *capsule_header_array; i < capsule_count;
+ 	     i++, capsule = *(++capsule_header_array)) {
+@@ -514,6 +612,41 @@ efi_status_t EFIAPI efi_update_capsule(
+ 
+ 		log_debug("Capsule[%d] (guid:%pUl)\n",
+ 			  i, &capsule->capsule_guid);
+
+#if CONFIG_IS_ENABLED(TARGET_CORSTONE1000)
+
+		if (guidcmp(&corstone1000_capsule_guid, &capsule->capsule_guid)) {
+			ret = EFI_INVALID_PARAMETER;
+			log_err("Corstone1000: Invalid capsule GUID\n");
+			goto out;
+		}
+
+		if (efi_size_in_pages(capsule->capsule_image_size) >
+		    CORSTONE1000_CAPSULE_BUFFER_SIZE) {
+			log_err("Corstone1000: Capsule data size exceeds the shared buffer size\n");
+			ret = EFI_BUFFER_TOO_SMALL;
+			goto out;
+		}
+
+		/* copy the data to the contiguous buffer */
+		efi_memcpy_runtime(corstone1000_capsule_buf, capsule, capsule->capsule_image_size);
+
+		/* invalidate the data cache */
+		invalidate_dcache_all();
+
+		/* issue buffer ready event */
+		ret = efi_corstone1000_buffer_ready_event(capsule->capsule_image_size);
+		if (ret) {
+			log_err("EFI: Corstone1000: Buffer ready event error (%d)\n", (int)ret);
+			ret = EFI_DEVICE_ERROR;
+		} else {
+			ret = EFI_SUCCESS;
+		}
+
+		goto out;
+
+#endif
+
+ 		if (!guidcmp(&capsule->capsule_guid,
+ 			     &efi_guid_firmware_management_capsule_id)) {
+ 			ret  = efi_capsule_update_firmware(capsule);
+@@ -552,7 +685,7 @@ out:
+  *
+  * Return:			status code
+  */
+-efi_status_t EFIAPI efi_query_capsule_caps(
+efi_status_t __efi_runtime EFIAPI efi_query_capsule_caps(
+ 		struct efi_capsule_header **capsule_header_array,
+ 		efi_uintn_t capsule_count,
+ 		u64 *maximum_capsule_size,
+diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
+index a2338d74af..9e3399a28c 100644
+--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
+@@ -16,6 +16,13 @@
+ 
+ efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
+ 
+#if IS_ENABLED(CONFIG_TARGET_CORSTONE1000)
+/**
+ * efi_corstone1000_alloc_capsule_shared_buf - allocate capsule shared buffer
+ */
+extern efi_status_t efi_corstone1000_alloc_capsule_shared_buf(void);
+#endif
+
+ /*
+  * Allow unaligned memory access.
+  *
+@@ -128,6 +135,14 @@ static efi_status_t efi_init_capsule(void)
+ {
+ 	efi_status_t ret = EFI_SUCCESS;
+ 
+#if IS_ENABLED(CONFIG_TARGET_CORSTONE1000)
+	ret = efi_corstone1000_alloc_capsule_shared_buf();
+	if (ret != EFI_SUCCESS) {
+		printf("EFI: Corstone-1000: cannot allocate caspsule shared buffer\n");
+		return ret;
+	}
+#endif
+
+ 	if (IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_UPDATE)) {
+ 		ret = efi_set_variable_int(L"CapsuleMax",
+ 					   &efi_guid_capsule_report,
+-- 
+2.17.1
+
@@ -0,0 +1,34 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+
+From 1617ecbbf163c921468fee224c92a8f79b43e2fb Mon Sep 17 00:00:00 2001
+From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+Date: Thu, 11 Nov 2021 16:34:54 +0000
+Subject: [PATCH 7/7] corstone1000: adjust the environment and heap sizes
+
+env size set to 64 KB
+heap size 64 KB + 32 MB
+
+Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+---
+ include/configs/corstone1000.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index 7f8a8ee254..7d63dd4ad9 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -75,8 +75,9 @@
+ /* Default load address for the source command */
+ #define CONFIG_SYS_LOAD_ADDR   (V2M_BASE + 0x10000000)
+ 
+#define CONFIG_ENV_SECT_SIZE		SZ_64K
+ /* Size of malloc() pool */
+-#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (8 << 20))
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SECT_SIZE + SZ_32M)
+ 
+ #define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+ 
+-- 
+2.17.1
+
@@ -0,0 +1,38 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
+
+From 313b89315d93ace166e2312a8e09aa85f1beb747 Mon Sep 17 00:00:00 2001
+From: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
+Date: Wed, 17 Nov 2021 15:28:06 +0000
+Subject: [PATCH 06/10] corstone1000: Update FFA shared buffer address
+
+FFA shared buffer address changed to 0x02000000.
+
+The existing address 0x023F8000 is currently being used by
+Optee so the virtual address returned to the SMM gateway is 0x0000.
+So the buffer is moved to 0x02000000.
+
+Signed-off-by: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
+%% original patch: 0025-Update-FFA-shared-buffer-address.patch
+
+%% original patch: 0025-Update-FFA-shared-buffer-address.patch
+---
+ include/configs/corstone1000.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index 7f8c61ba93..0451121b79 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -42,7 +42,7 @@
+ #define FFA_SHARED_MM_BUFFER_SIZE		SZ_4K /* 4 KB */
+ 
+ /* shared buffer physical address used for communication between u-boot and the MM SP */
+-#define FFA_SHARED_MM_BUFFER_ADDR		(0x023F8000)
+#define FFA_SHARED_MM_BUFFER_ADDR		(0x02000000)
+ 
+ #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x03f00000)
+ #define CONFIG_SKIP_LOWLEVEL_INIT
+-- 
+2.17.1
+
@@ -0,0 +1,58 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
+
+From 524c865ae37f9cb9278988120e508c5314c2cd73 Mon Sep 17 00:00:00 2001
+From: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
+Date: Wed, 17 Nov 2021 15:28:53 +0000
+Subject: [PATCH 07/10] corstone1000: Disable set/get of NV variables
+
+This is a temporary change which uses only the volatile memory
+for get and set variable calls.
+
+The non volatile storage access is via openAmp in se proxy which is still not 
+integrated to the system. So when an efi_set_variable_int() call is made for
+NV variables, mm_commmunicate results in failure. This change will direct
+PlatformLang and OsIndications to volatile memory which would be a
+temporary solution.
+
+Signed-off-by: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
+%% original patch: 0026-Disable-set-get-of-NV-variables.patch
+
+%% original patch: 0026-Disable-set-get-of-NV-variables.patch
+---
+ lib/efi_loader/efi_setup.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
+index 9e3399a28c..fcf2eae9cd 100644
+--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
+@@ -83,7 +83,11 @@ static efi_status_t efi_init_platform_lang(void)
+ 
+ 	ret = efi_set_variable_int(L"PlatformLang",
+ 				   &efi_global_variable_guid,
+-				   EFI_VARIABLE_NON_VOLATILE |
+				   	/*
+					* This is a temporary change until NV memory is accessible 
+					* through OpenAmp. 
+					*/
+				   //EFI_VARIABLE_NON_VOLATILE | 
+ 				   EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ 				   EFI_VARIABLE_RUNTIME_ACCESS,
+ 				   1 + strlen(lang), lang, false);
+@@ -210,7 +214,11 @@ static efi_status_t efi_clear_os_indications(void)
+ 		os_indications &=
+ 			~EFI_OS_INDICATIONS_FILE_CAPSULE_DELIVERY_SUPPORTED;
+ 	ret = efi_set_variable_int(L"OsIndications", &efi_global_variable_guid,
+-				   EFI_VARIABLE_NON_VOLATILE |
+				   	/*
+					* This is a temporary change until NV memory is accessible 
+					* through OpenAmp. 
+					*/
+				   //EFI_VARIABLE_NON_VOLATILE |
+ 				   EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ 				   EFI_VARIABLE_RUNTIME_ACCESS,
+ 				   sizeof(os_indications), &os_indications,
+-- 
+2.17.1
+
@@ -0,0 +1,45 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
+
+From 5d53e40021d7fca594bb86307b0851a958047b6b Mon Sep 17 00:00:00 2001
+From: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
+Date: Thu, 18 Nov 2021 16:42:59 +0000
+Subject: [PATCH 08/10] corstone1000: Make sure shared buffer contents are not
+ cached
+
+After updating the shared buffer, it is required to flush the cache
+to ensure that the secure world sees expected the shared buffer
+contents.
+
+The MM communication shared buffer is configured in device region of optee
+which has cache disabled. So we need to invalidate the cache every time we
+update the buffer on uboot otherwise the secure world does not see the
+accurate values.
+
+Signed-off-by: Gowtham Suresh Kumar <gowtham.sureshkumar@arm.com>
+%% original patch: 0027-Make-sure-shared-buffer-contents-are-not-cached.patch
+
+%% original patch: 0027-Make-sure-shared-buffer-contents-are-not-cached.patch
+---
+ lib/efi_loader/efi_variable_tee.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c
+index b363ec92bf..9375aa6a63 100644
+--- a/lib/efi_loader/efi_variable_tee.c
+++ b/lib/efi_loader/efi_variable_tee.c
+@@ -331,6 +331,11 @@ static efi_status_t __efi_runtime ffa_mm_communicate(void *comm_buf, ulong comm_
+ 	virt_shared_buf = (void *)map_sysmem((phys_addr_t)FFA_SHARED_MM_BUFFER_ADDR, 0);
+ 	efi_memcpy_runtime(virt_shared_buf, comm_buf, tx_data_size);
+ 
+	/* The secure world has cache disabled for device region which we use for shared buffer
+	So, the secure world reads the data from DDR. Let's flush the cache so the DDR is
+	updated with the latest data */
+	invalidate_dcache_all();
+
+ 	/* Announce there is data in the shared buffer */
+ 
+ 	ffa_ret = ffa_notify_mm_sp();
+-- 
+2.17.1
+
@@ -0,0 +1,96 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Harry Moulton <harry.moulton@arm.com>
+
+From 224d5d7ca9359a1c383ee417d934d2a6dfca53df Mon Sep 17 00:00:00 2001
+From: Harry Moulton <harmou01@e123741.cambridge.arm.com>
+Date: Mon, 29 Nov 2021 13:13:17 +0000
+Subject: [PATCH] arm: corstone1000: fix unrecognized filesystem type
+ error.
+
+Fix the 'unrecognized filesystem type' error when attempting to boot
+from an EFI image on attached USB formated as GPT.
+
+Signed-off-by: Harry Moulton <harry.moulton@arm.com>
+---
+ common/usb_storage.c                |  3 +++
+ configs/corstone1000_defconfig      |  3 ++-
+ drivers/usb/isp1760/isp1760-uboot.c | 12 ++++++++++++
+ include/configs/corstone1000.h      |  1 +
+ 4 files changed, 18 insertions(+), 1 deletion(-)
+
+diff --git a/common/usb_storage.c b/common/usb_storage.c
+index 946c6b2b32..77b8b55010 100644
+--- a/common/usb_storage.c
+++ b/common/usb_storage.c
+@@ -769,6 +769,9 @@ static int usb_stor_BBB_transport(struct scsi_cmd *srb, struct us_data *us)
+ st:
+ 	retry = 0;
+ again:
+    if (srb->cmd[0] == SCSI_TST_U_RDY)
+        mdelay(100);
+
+ 	debug("STATUS phase\n");
+ 	result = usb_bulk_msg(us->pusb_dev, pipein, csw, UMASS_BBB_CSW_SIZE,
+ 				&actlen, USB_CNTL_TIMEOUT*5);
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index c5eb9af101..fe77bdc63f 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -20,6 +20,7 @@ CONFIG_CMD_BOOTM=y
+ CONFIG_CMD_LOADM=y
+ CONFIG_CMD_BOOTEFI=y
+ CONFIG_EFI_LOADER=y
+CONFIG_EFI_PARTITION=y
+ CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
+ CONFIG_CMD_BOOTEFI_HELLO=y
+ # CONFIG_CMD_XIMG is not set
+@@ -52,7 +53,7 @@ CONFIG_EFI_MM_COMM_TEE=y
+ # CONFIG_HEXDUMP is not set
+ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+ CONFIG_EFI_CAPSULE_ON_DISK=y
+-CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y
+# CONFIG_EFI_CAPSULE_ON_DISK_EARLY is not set
+ # CONFIG_EFI_CAPSULE_AUTHENTICATE is not set
+ CONFIG_EFI_HAVE_CAPSULE_SUPPORT=y
+ CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+diff --git a/drivers/usb/isp1760/isp1760-uboot.c b/drivers/usb/isp1760/isp1760-uboot.c
+index 9f2eaa75f3..cb03bc5d8c 100644
+--- a/drivers/usb/isp1760/isp1760-uboot.c
+++ b/drivers/usb/isp1760/isp1760-uboot.c
+@@ -56,9 +56,21 @@ static int isp1760_msg_submit_irq(struct udevice *dev, struct usb_device *udev,
+ 				  pipe, buffer, length, interval);
+ }
+ 
+static int isp1760_get_max_xfer_size(struct udevice *dev, size_t *size)
+{
+    struct isp1760_host_data *host = dev_get_priv(dev);
+    struct isp1760_hcd *priv = host->hcd.hcd_priv;
+    const struct isp1760_memory_layout *mem = priv->memory_layout;
+
+    *size = mem->blocks_size[ISP176x_BLOCK_NUM - 1];
+
+    return 0;
+}
+
+ struct dm_usb_ops isp1760_usb_ops = {
+ 	.control	= isp1760_msg_submit_control,
+ 	.bulk		= isp1760_msg_submit_bulk,
+ 	.interrupt	= isp1760_msg_submit_irq,
+    .get_max_xfer_size = isp1760_get_max_xfer_size,
+ };
+ 
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index 87682406d6..4c7993649d 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -91,6 +91,7 @@
+ #define CONFIG_SYS_MAXARGS		64	/* max command args */
+ 
+ #define CONFIG_EXTRA_ENV_SETTINGS					\
+                "usb_pgood_delay=250\0"         \
+ 				"fdt_addr_r=0x82000000\0"		\
+ 				"kernel_addr=0x08330000\0"		\
+ 				"kernel_addr_r=0x82100000\0"		\
+-- 
+2.17.1
+
@@ -0,0 +1,27 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+
+From 8b85cddde48f31266349277980a65d25dfae302e Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Wed, 17 Nov 2021 18:48:35 +0000
+Subject: [PATCH] corstone1000: set CONFIG_PSCI_RESET
+
+set CONFIG_PSCI_RESET to allow efi_reset_system API to use PSCI.
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+---
+ configs/corstone1000_defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index b59b75df3e..55f93b0a2c 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -64,3 +64,5 @@ CONFIG_CMD_RTC=y
+ CONFIG_EFI_GET_TIME=y
+ CONFIG_EFI_SET_TIME=y
+ CONFIG_RTC_EMULATION=y
+CONFIG_PSCI_RESET=y
+
+-- 
+2.25.1
+
@@ -0,0 +1,64 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
+
+From e51542907203c46bdbbd78aa1c76058204fd75f1 Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <Emekcan.Aras@arm.com>
+Date: Thu, 25 Nov 2021 16:54:57 +0000
+Subject: [PATCH] arm-bsp/u-boot: corstone1000: Implement autoboot
+ storage device selection
+
+This commit implements distro_bootcmd in config_bootcommand in u-boot.
+This command traverses all the USB devices connected to the board and
+finds a usb device that has bootable image to boot from it. If it cannot
+find a usb device with the bootable image, it will boot the system using
+the existing flash.
+
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+---
+ configs/corstone1000_defconfig |  2 +-
+ include/configs/corstone1000.h | 15 ++++++++++-----
+ 2 files changed, 11 insertions(+), 6 deletions(-)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index 10b7c3ea18..0b9ead461b 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -66,4 +66,4 @@ CONFIG_EFI_GET_TIME=y
+ CONFIG_EFI_SET_TIME=y
+ CONFIG_RTC_EMULATION=y
+ CONFIG_PSCI_RESET=y
+-
+CONFIG_DISTRO_DEFAULTS=y
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index b0932f9f33..d029059a81 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -85,15 +85,20 @@
+ #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+ #define CONFIG_SYS_MAXARGS		64	/* max command args */
+ 
+-#define CONFIG_EXTRA_ENV_SETTINGS					\
+#define BOOT_TARGET_DEVICES(func) \
+    func(USB, usb, 0)
+#include <config_distro_bootcmd.h>
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+                BOOTENV                         \
+                 "usb_pgood_delay=250\0"         \
+ 				"fdt_addr_r=0x82000000\0"		\
+ 				"kernel_addr=0x08330000\0"		\
+-				"kernel_addr_r=0x82100000\0"		\
+				"kernel_addr_r=0x88200000\0"	\
+ 				"fdt_high=0xffffffff\0"
+-
+-#define CONFIG_BOOTCOMMAND					\
+-				"echo Loading Kernel to memory ... ;" \
+#define CONFIG_BOOTCOMMAND					            \
+				"echo Loading Kernel to memory ... ;"   \
+ 				"loadm $kernel_addr $kernel_addr_r 0xc00000;" \
+                "usb start; usb reset;" \
+                "run distro_bootcmd;" \
+ 				"bootefi $kernel_addr_r $fdtcontroladdr;"
+ #endif
+-- 
+2.25.1
+
@@ -0,0 +1,47 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From 1e76c4b70c8539c56b4b9ae6b8fd415d811a1812 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Wed, 1 Dec 2021 19:04:59 +0000
+Subject: [PATCH] corstone1000: change base address of kernel in the flash
+
+More space in the flash is reserved up front for metadata
+parser and UEFI variables. That requires change in the flash
+base address of where images are present.
+
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ include/configs/corstone1000.h | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index bb3b099806..baa0720fb5 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -94,16 +94,16 @@
+     func(USB, usb, 0)
+ #include <config_distro_bootcmd.h>
+ #define CONFIG_EXTRA_ENV_SETTINGS				\
+-                BOOTENV                         \
+-                "usb_pgood_delay=250\0"         \
+				BOOTENV                         \
+				"usb_pgood_delay=250\0"         \
+ 				"fdt_addr_r=0x82000000\0"		\
+-				"kernel_addr=0x08330000\0"		\
+				"kernel_addr=0x083EE000\0"		\
+ 				"kernel_addr_r=0x88200000\0"	\
+ 				"fdt_high=0xffffffff\0"
+-#define CONFIG_BOOTCOMMAND					            \
+#define CONFIG_BOOTCOMMAND					\
+ 				"echo Loading Kernel to memory ... ;"   \
+ 				"loadm $kernel_addr $kernel_addr_r 0xc00000;" \
+-                "usb start; usb reset;" \
+-                "run distro_bootcmd;" \
+				"usb start; usb reset;" \
+				"run distro_bootcmd;" \
+ 				"bootefi $kernel_addr_r $fdtcontroladdr;"
+ #endif
+-- 
+2.17.1
+
@@ -0,0 +1,66 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+
+From abc455d29aa9c983c6af2fa75870a7ee95da2496 Mon Sep 17 00:00:00 2001
+From: Satish Kumar <satish.kumar01@arm.com>
+Date: Wed, 1 Dec 2021 19:17:57 +0000
+Subject: [PATCH] arm: corstone1000: identify which bank to load kernel from
+
+Secure enclave, based on the firmware update state of the
+system, decides the boot bank. In this commit, u-boot
+identifies the selected boot bank and loads the kernel
+from it.
+
+Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
+---
+ configs/corstone1000_defconfig |  2 +-
+ include/configs/corstone1000.h | 18 ++++++++++++++----
+ 2 files changed, 15 insertions(+), 5 deletions(-)
+
+diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
+index 0b9ead461b..3c00e13ceb 100644
+--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
+@@ -29,7 +29,7 @@ CONFIG_CMD_BOOTEFI_HELLO=y
+ CONFIG_CMD_NVEDIT_EFI=y
+ # CONFIG_CMD_LOADS is not set
+ CONFIG_CMD_USB=y
+-# CONFIG_CMD_ITEST is not set
+CONFIG_CMD_ITEST=y
+ # CONFIG_CMD_SETEXPR is not set
+ CONFIG_CMD_DHCP=y
+ # CONFIG_CMD_NFS is not set
+diff --git a/include/configs/corstone1000.h b/include/configs/corstone1000.h
+index baa0720fb5..7c6f66c891 100644
+--- a/include/configs/corstone1000.h
+++ b/include/configs/corstone1000.h
+@@ -97,12 +97,22 @@
+ 				BOOTENV                         \
+ 				"usb_pgood_delay=250\0"         \
+ 				"fdt_addr_r=0x82000000\0"		\
+-				"kernel_addr=0x083EE000\0"		\
+-				"kernel_addr_r=0x88200000\0"	\
+				"boot_bank_flag=0x08002000\0"		\
+				"kernel_addr_bank_0=0x083EE000\0"			\
+				"kernel_addr_bank_1=0x0936E000\0"			\
+				"retrieve_kernel_load_addr="				\
+					"if itest.l *${boot_bank_flag} == 0; then "	\
+					    "setenv kernel_addr $kernel_addr_bank_0;"	\
+					"else "						\
+					    "setenv kernel_addr $kernel_addr_bank_1;"	\
+					"fi;"						\
+					"\0"							\
+				"kernel_addr_r=0x88200000\0"				\
+ 				"fdt_high=0xffffffff\0"
+ #define CONFIG_BOOTCOMMAND					\
+-				"echo Loading Kernel to memory ... ;"   \
+-				"loadm $kernel_addr $kernel_addr_r 0xc00000;" \
+				"run retrieve_kernel_load_addr;" \
+				"echo Loading kernel from $kernel_addr to memory ... ;" \
+				"loadm $kernel_addr $kernel_addr_r 0xc00000;"		\
+ 				"usb start; usb reset;" \
+ 				"run distro_bootcmd;" \
+ 				"bootefi $kernel_addr_r $fdtcontroladdr;"
+-- 
+2.17.1
+
--- a/Show More
+++ b/Show More