update tags for Corstone-700 2020.02.10 release

Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>

arm/recipes-bsp/trusted-firmware-a/trusted-firmware-a.bb

@@ -13,7 +13,7 @@ TF-A_DEPENDS ?= ""
 DEPENDS += " dtc-native coreutils-native"
 DEPENDS += " ${TF-A_DEPENDS} "
 
-LIC_FILES_CHKSUM = "file://license.rst;md5=90153916317c204fade8b8df15739cde"
+LIC_FILES_CHKSUM = "file://license.rst;md5=1dd070c98a281d18d9eefd938729b031"
 
 FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
 

meta-corstone700/conf/layer.conf

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2019 Arm Limited
+#
+# corstone700 has a conf and classes directory, add to BBPATH
+BBPATH .= ":${LAYERDIR}"
+
+# corstone700 has a packages directory, add to BBFILES
+BBFILES += " \
+		${LAYERDIR}/recipes-*/*/*.bb \
+		${LAYERDIR}/recipes-*/*/*.bbappend"
+
+BBFILE_COLLECTIONS += "corstone700"
+BBFILE_PATTERN_corstone700 := "^${LAYERDIR}/"
+BBFILE_PRIORITY_corstone700 = "12"
+LAYERSERIES_COMPAT_corstone700 = "warrior"
+
+NAME_GCC_ARM_NONE_EABI 		= "gcc-arm-none-eabi"
+INSTALL_GCC_ARM_NONE_EABI 	= "${bindir}/${NAME_GCC_ARM_NONE_EABI}"
+TC_GCC_ARM_NONE_EABI		= "${STAGING_BINDIR_NATIVE}/${NAME_GCC_ARM_NONE_EABI}"
+TC_GCC_ARM_NONE_EABI_BIN 	= "${TC_GCC_ARM_NONE_EABI}/bin"
+
+LAYERDEPENDS_corstone700 = "arm"

meta-corstone700/conf/machine/corstone700.conf

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2019 Arm Limited
+#
+
+require conf/machine/include/arm-common-configuration.inc
+require conf/machine/include/cortex-a32.inc
+
+EXTRA_IMAGEDEPENDS_append = " test-app"
+
+CORE_IMAGE_EXTRA_INSTALL += "test-app"
+
+EXTRA_IMAGEDEPENDS_append = " boot-firmware external-system test-app"
+
+TF-A_PLATFORM = "corstone700"
+TF-A_EXTRA_OPTIONS += " \
+			RESET_TO_SP_MIN=1 \
+			ARM_LINUX_KERNEL_AS_BL33=1 \
+			PRELOADED_BL33_BASE=0x08300000 \
+			ARM_PRELOADED_DTB_BASE=0x80400000 \
+			ENABLE_STACK_PROTECTOR=strong \
+			ENABLE_PIE=1 \
+			"

meta-corstone700/recipes-bsp/boot-firmware/boot-firmware.bb

@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2019-2020 Arm Limited
+#
+
+SUMMARY = "Boot Processor firmware"
+DESCRIPTION = "Boot Processor firmware"
+DEPENDS += " coreutils-native gcc-arm-none-eabi-native trusted-firmware-a "
+LICENSE="BSD"
+LIC_FILES_CHKSUM = "file://license.md;md5=e44b2531cd6ffe9dece394dbe988d9a0"
+
+# Use Yocto-built python3 executable
+inherit python3native
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI = "gitsm://${USER}@git.linaro.org/landing-teams/working/arm/boot-firmware.git;protocol=https;branch=master"
+SRCREV = "CORSTONE-700-2020.02.10"
+S = "${WORKDIR}/git"
+B = "${WORKDIR}/build"
+
+COMPATIBLE_MACHINE = "(corstone700)"
+
+PLATFORM = "corstone-700"
+
+LDFLAGS[unexport] = "1"
+
+# the gcc-arm-none-eabi version does not support -fmacro-perfix-max, so make sure to setup
+DEBUG_PREFIX_MAP_pn-boot-firmware = "-fdebug-prefix-map=${WORKDIR}=/usr/src/debug/${PN}/${EXTENDPE}${PV}-${PR} \
+			-fdebug-prefix-map=${STAGING_DIR_HOST}= \
+			-fdebug-prefix-map=${STAGING_DIR_NATIVE}= \
+			"
+do_compile() {
+   export PATH=${TC_GCC_ARM_NONE_EABI_BIN}:$PATH
+   mkdir -p ${B}
+
+   oe_runmake -C ${S} BUILD_BASE=${B} \
+      BUILD_PLAT=${B}/${PLATFORM}/ \
+      PRODUCT=${PLATFORM} \
+      CROSS_COMPILE=arm-none-eabi- \
+      clean \
+      all
+
+   cp ${S}/build/product/${PLATFORM}/se_ramfw/release/bin/firmware.bin ${B}/se_ramfw.bin
+   cp ${S}/build/product/${PLATFORM}/se_romfw/release/bin/firmware.bin ${B}/se_romfw.bin
+
+    oe_runmake -C ${S}/tools/spitoc BUILD_BASE=${B} \
+       BUILD_PLAT=${B}/${PLATFORM}/ \
+       all
+
+    cp ${S}/tools/spitoc/spitoc ${B}/spitoc
+}
+
+do_install() {
+	install -D -p -m 0644 ${B}/se_ramfw.bin ${DEPLOY_DIR_IMAGE}/se_ramfw.bin
+	install -D -p -m 0644 ${B}/se_romfw.bin ${DEPLOY_DIR_IMAGE}/se_romfw.bin
+        ${B}/spitoc --seram ${DEPLOY_DIR_IMAGE}/se_ramfw.bin --offset 1  --fip ${DEPLOY_DIR_IMAGE}/${TF-A_PLATFORM}.fip --offset  33 --out ${DEPLOY_DIR_IMAGE}/spitoc.bin
+}

meta-corstone700/recipes-bsp/boot-firmware/boot-firmware/license.md

@@ -0,0 +1,39 @@
+License
+=======
+
+Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+-  Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+-  Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+-  Neither the name of Arm nor the names of its contributors may be used to
+   endorse or promote products derived from this software without specific prior
+   written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+---
+
+__Note:__
+Individual files contain the following tag instead of the full license text.
+
+    SPDX-License-Identifier:    BSD-3-Clause
+
+This enables machine processing of license information based on the SPDX
+License Identifiers that are available here: http://spdx.org/licenses/

meta-corstone700/recipes-bsp/external-system/external-system.bb

@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2019-2020 Arm Limited
+#
+
+SUMMARY = "External system Cortex-M3 Firmware"
+DESCRIPTION = "External system Firmware"
+HOMEPAGE = "https://gerrit.oss.arm.com/#/admin/projects/EP/src/ExternalSystem"
+DEPENDS += " coreutils-native gcc-arm-none-eabi-native"
+LICENSE="BSD"
+LIC_FILES_CHKSUM = "file://license.md;md5=e44b2531cd6ffe9dece394dbe988d9a0"
+
+# Use Yocto-built python3 executable
+inherit python3native
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI = "gitsm://${USER}@git.linaro.org/landing-teams/working/arm/external-system.git;protocol=https;branch=master"
+SRCREV = "CORSTONE-700-2020.02.10"
+S = "${WORKDIR}/git"
+B = "${WORKDIR}/build"
+
+COMPATIBLE_MACHINE = "(corstone700)"
+
+PLATFORM = "corstone-700"
+
+LDFLAGS[unexport] = "1"
+
+DEBUG_PREFIX_MAP_pn-external-system = "-fdebug-prefix-map=${WORKDIR}=/usr/src/debug/${PN}/${EXTENDPE}${PV}-${PR} \
+                        -fdebug-prefix-map=${STAGING_DIR_HOST}= \
+                        -fdebug-prefix-map=${STAGING_DIR_NATIVE}= \
+                        "
+
+
+do_compile() {
+    export PATH=${TC_GCC_ARM_NONE_EABI_BIN}:$PATH
+    mkdir -p ${B}
+    oe_runmake -C ${S} BUILD_BASE=${B} \
+        BUILD_PLAT=${B}/${PLATFORM}/ \
+        PRODUCT=${PLATFORM} \
+        CROSS_COMPILE=arm-none-eabi- \
+        clean \
+        all
+    cp ${S}/build/product/${PLATFORM}/firmware/release/bin/firmware.bin ${B}/es_flashfw.bin
+}
+
+do_install() {
+    install -D -p -m 0644 ${B}/es_flashfw.bin ${DEPLOY_DIR_IMAGE}/es_flashfw.bin
+}

meta-corstone700/recipes-bsp/trusted-firmware-a/trusted-firmware-a.bbappend

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2019-2020 Arm Limited
+#
+
+LIC_FILES_CHKSUM_corstone700 = "file://license.rst;md5=c709b197e22b81ede21109dbffd5f363"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI_corstone700 = "git://${USER}@git.linaro.org/landing-teams/working/arm/arm-tf.git;protocol=https;branch=iota"
+SRCREV = "CORSTONE-700-2020.02.10"

meta-corstone700/recipes-kernel/linux/linux-arm.bbappend

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2019-2020 Arm Limited
+#
+
+SUMMARY = "Linux Kernel provided and supported by Arm/Linaro for Cortex-A32"
+
+KERNEL_IMAGETYPE = "xipImage"
+
+KBUILD_DEFCONFIG = "corstone700_defconfig"
+
+SRC_URI = "git://${USER}@git.linaro.org/landing-teams/working/arm/kernel-release.git;protocol=https;branch=iota"
+SRCREV = "CORSTONE-700-2020.02.10"

meta-corstone700/recipes-test/test-app/test-app.bb

@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2019-2020 Arm Limited
+#
+
+SUMMARY = "CORSTONE700 Host Test App"
+DESCRIPTION = "CORSTONE700 Host Test App"
+DEPENDS += " coreutils-native "
+LICENSE="BSD"
+LIC_FILES_CHKSUM = "file://license.md;md5=e44b2531cd6ffe9dece394dbe988d9a0"
+
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+
+SRC_URI = "git://${USER}@git.linaro.org/landing-teams/working/arm/test-apps.git;protocol=https;branch=master"
+SRCREV = "CORSTONE-700-2020.02.10"
+
+S = "${WORKDIR}/git"
+B = "${WORKDIR}/build"
+
+COMPATIBLE_MACHINE = "(corstone700)"
+
+PLATFORM = "corstone700"
+
+LDFLAGS[unexport] = "1"
+
+do_compile() {
+	mkdir -p ${B}
+	${CC} ${S}/test-app.c -o ${S}/test-app --static
+	cp ${S}/test-app ${B}/test-app
+}
+
+do_install() {
+	install -d ${D}/${bindir}/
+	install -m 0755 ${B}/test-app ${D}${bindir}/test-app
+}
+
+FILES_${PN} += "${bindir}/test-app"

meta-corstone700/wic/iota-tiny-image.corstone700.wks

@@ -0,0 +1,13 @@
+# Partition for corstone700
+part --source rawcopy --sourceparams="file=spitoc.bin" --no-table --align 1 --fixed-size 1k
+
+part --source rawcopy --sourceparams="file=se_ramfw.bin" --no-table --align 1 --fixed-size 32k
+
+# Rawcopy of the FIP binary
+part --source rawcopy --sourceparams="file=corstone700.fip" --no-table --align 1 --fixed-size 991k
+
+# Rawcopy of the rootfs
+part --source rawcopy --sourceparams="file=${IMGDEPLOYDIR}/iota-tiny-image-corstone700.cramfs-xip" --no-table --fixed-size 2
+
+# Rawcopy of the kernel binary
+part --source rawcopy --sourceparams="file=xipImage" --no-table --fixed-size 3

meta-designstart/recipes-bsp/trusted-firmware-a/trusted-firmware-a.bbappend

@@ -5,7 +5,4 @@
 
 FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
 
-SRC_URI += "\
-            file://0001-plat-arm-a5ds-move-dtb-to-a-new-address.patch \
-	    "
-SRCREV = "ed01e0c407a1794faf8ff8173183a50419bbd2ae"
+SRCREV = "5d3ee0764b03567bf3501edf47d67d72daff0cb3"

meta-designstart/recipes-bsp/trusted-firmware-a/trusted-firmware-a/0001-plat-arm-a5ds-move-dtb-to-a-new-address.patch

@@ -1,31 +0,0 @@
-From d3cadbc6f1060020960dc05af0465db919bbbe2b Mon Sep 17 00:00:00 2001
-From: Rui Miguel Silva <rui.silva@linaro.org>
-Date: Fri, 30 Aug 2019 13:38:44 +0100
-Subject: [PATCH] plat/arm: a5ds: move dtb to a new address
-
-When Using bigger kernel images (>8.4MB compressed zImage) and at
-decompress and final location init stage of kernel start makes it
-override dtb at this address, to avoid this move the dtb a little
-higher in address related.
-
-Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
----
- plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
-index 9ab2d9656600..c616ff772237 100644
---- a/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
-+++ b/plat/arm/board/a5ds/fdts/a5ds_tb_fw_config.dts
-@@ -10,7 +10,7 @@
- 	/* Platform Config */
- 	plat_arm_bl2 {
- 		compatible = "arm,tb_fw";
--		hw_config_addr = <0x0 0x82000000>;
-+		hw_config_addr = <0x0 0x83000000>;
- 		hw_config_max_size = <0x01000000>;
- 		/* Disable authentication for development */
- 		disable_auth = <0x0>;
--- 
-2.22.1
-

meta-designstart/recipes-bsp/u-boot/u-boot/0001-a5ds_target_support.patch

@@ -1,7 +1,7 @@
-From e634679d854b1603452d0f71a2fa9936e026fb35 Mon Sep 17 00:00:00 2001
+From 92f65bc0131b54b579252f262e4bfc4c8f1d64c2 Mon Sep 17 00:00:00 2001
 From: Rui Miguel Silva <rui.silva@linaro.org>
 Date: Wed, 14 Aug 2019 09:49:08 +0100
-Subject: [PATCH 3/3] a5ds: add support for target designstart A5
+Subject: a5ds: add support for target designstart A5
 
 Give support, based on vexpress for now, to designstart platform with
 Cortex-A5 chip. Create config and setup boot commands and tweak memory
@@ -9,14 +9,16 @@ map related with this platform.
 
 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
 
+%% original patch: 0001-a5ds-add-support-for-target-designstart-A5.patch
+
 %% original patch: 0001-a5ds-add-support-for-target-designstart-A5.patch
 ---
  arch/arm/Kconfig                       |  5 +++
  board/armltd/vexpress64/Kconfig        |  2 +-
- configs/vexpress_aemv8a_a5ds_defconfig | 37 ++++++++++++++++++++++
- include/configs/vexpress_aemv8a.h      | 43 ++++++++++++++++++++++----
- 4 files changed, 80 insertions(+), 7 deletions(-)
- create mode 100644 configs/vexpress_aemv8a_a5ds_defconfig
+ configs/vexpress_aemv8a_a5ds_defconfig | 37 ++++++++++++++++++
+ include/configs/vexpress_aemv8a.h      | 53 ++++++++++++++++++++++----
+ 4 files changed, 89 insertions(+), 8 deletions(-)
+ create mode 100755 configs/vexpress_aemv8a_a5ds_defconfig
 
 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
 index 0a6ee962d5..e26b3fc37d 100644
@@ -45,8 +47,8 @@ index f6930aee47..3a6c972d0a 100644
  config SYS_BOARD
  	default "vexpress64"
 diff --git a/configs/vexpress_aemv8a_a5ds_defconfig b/configs/vexpress_aemv8a_a5ds_defconfig
-new file mode 100644
-index 0000000000..00b80824d8
+new file mode 100755
+index 0000000000..59c9868318
 --- /dev/null
 +++ b/configs/vexpress_aemv8a_a5ds_defconfig
 @@ -0,0 +1,37 @@
@@ -85,19 +87,22 @@ index 0000000000..00b80824d8
 +CONFIG_OF_LIBFDT=y
 +CONFIG_DEBUG_UART=y
 +CONFIG_DEBUG_UART_PL011=y
-+CONFIG_DEBUG_UART_BASE=0x1A510000
-+CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_DEBUG_UART_BASE=0x1A200000
++CONFIG_DEBUG_UART_CLOCK=7500000
 diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
-index 4de9914128..1bc478ca2a 100644
+index 4de9914128..e7b2e0f2fa 100644
 --- a/include/configs/vexpress_aemv8a.h
 +++ b/include/configs/vexpress_aemv8a.h
-@@ -23,13 +23,19 @@
+@@ -22,14 +22,22 @@
+ #else
  #define HIGH_ADDR			"0xffffffff"
  #define BOOT_TYPE			"bootz"
- #define CONFIG_SYS_HZ_CLOCK		24000000
 +#ifdef CONFIG_TARGET_DESIGNSTART_A5
++#define CONFIG_SYS_HZ_CLOCK		7500000
++#define CONFIG_SYS_HZ			1000
 +#define CONFIG_SYS_MMIO_TIMER
 +#else
+ #define CONFIG_SYS_HZ_CLOCK		24000000
  #define CONFIG_SYS_ARCH_TIMER
 +#endif
  #define CONFIG_SKIP_LOWLEVEL_INIT
@@ -112,7 +117,7 @@ index 4de9914128..1bc478ca2a 100644
  /* ATF loads u-boot here for BASE_FVP model */
  #define CONFIG_SYS_TEXT_BASE		0x88000000
  #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
-@@ -66,6 +72,9 @@
+@@ -66,6 +74,9 @@
  	defined(CONFIG_TARGET_VEXPRESS64_JUNO_AARCH32)
  #define V2M_UART0			0x7ff80000
  #define V2M_UART1			0x7ff70000
@@ -122,7 +127,19 @@ index 4de9914128..1bc478ca2a 100644
  #else /* Not Juno */
  #define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
  #define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
-@@ -121,7 +130,7 @@
+@@ -93,7 +104,11 @@
+ #define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)
+ 
+ /* Generic Timer Definitions */
++#ifdef CONFIG_TARGET_DESIGNSTART_A5
++#define COUNTER_FREQUENCY		CONFIG_SYS_HZ_CLOCK
++#else
+ #define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
++#endif
+ 
+ /* Generic Interrupt Controller Definitions */
+ #ifdef CONFIG_GICV3
+@@ -121,7 +136,7 @@
  #define CONFIG_SMC911X			1
  #define CONFIG_SMC911X_32_BIT		1
  #define CONFIG_SMC911X_BASE		(0x018000000)
@@ -131,7 +148,16 @@ index 4de9914128..1bc478ca2a 100644
  /* The Vexpress64 simulators use SMSC91C111 */
  #define CONFIG_SMC91111			1
  #define CONFIG_SMC91111_BASE		(0x01A000000)
-@@ -222,19 +231,26 @@
+@@ -134,6 +149,8 @@
+ #if defined(CONFIG_TARGET_VEXPRESS64_JUNO) || \
+ 	defined(CONFIG_TARGET_VEXPRESS64_JUNO_AARCH32)
+ #define CONFIG_PL011_CLOCK		7273800
++#elif defined(CONFIG_TARGET_DESIGNSTART_A5)
++#define CONFIG_PL011_CLOCK		7500000
+ #else
+ #define CONFIG_PL011_CLOCK		24000000
+ #endif
+@@ -222,19 +239,26 @@
  				"setenv bootargs ${bootargs} ${bootargs_sky2}; "\
  				BOOT_TYPE " ${kernel_addr} ${initrd_param} ${fdt_addr}"
  
@@ -143,7 +169,8 @@ index 4de9914128..1bc478ca2a 100644
 +	defined(CONFIG_TARGET_DESIGNSTART_A5)
  #define CONFIG_EXTRA_ENV_SETTINGS	\
  				"kernel_name=Image\0"		\
- 				"kernel_addr=0x80080000\0"	\
+-				"kernel_addr=0x80080000\0"	\
++				"kernel_addr=0x80F00000\0"	\
  				"initrd_name=ramdisk.img\0"	\
  				"initrd_addr=0x84000000\0"	\
  				"fdt_name=devtree.dtb\0"	\
@@ -162,7 +189,7 @@ index 4de9914128..1bc478ca2a 100644
  #define CONFIG_BOOTARGS		"console=ttyAMA0 earlycon=pl011,"\
  				"0x1c090000 debug user_debug=31 "\
  				"systemd.log_target=null "\
-@@ -242,7 +258,14 @@
+@@ -242,7 +266,14 @@
  				"root=/dev/vda2 rw "\
  				"rootwait "\
  				"loglevel=9"
@@ -170,14 +197,14 @@ index 4de9914128..1bc478ca2a 100644
  
 +#if defined(CONFIG_TARGET_DESIGNSTART_A5)
 +#define CONFIG_BOOTCOMMAND	"echo copy to RAM...; " \
-+				"cp.b 0x08100000 $kernel_addr 0xB00000; " \
-+				"cp.b 0x08D00000 $initrd_addr 0x500000; " \
++				"cp.b 0x80100000 $kernel_addr 0xB00000; " \
++				"cp.b 0x80D00000 $initrd_addr 0x500000; " \
 +				BOOT_TYPE " $kernel_addr $initrd_addr $fdt_addr"
 +#else
  #define CONFIG_BOOTCOMMAND	"if smhload ${fdt_name} ${fdt_addr}; then "\
  				"  if smhload ${initrd_name} ${initrd_addr} "\
  				"  initrd_end; then " \
-@@ -263,6 +286,7 @@
+@@ -263,6 +294,7 @@
  				"with contents of DRAM; " \
  				BOOT_TYPE " $kernel_addr $initrd_addr $fdt_addr"
  #endif
@@ -185,12 +212,12 @@ index 4de9914128..1bc478ca2a 100644
  
  /* Monitor Command Prompt */
  #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
-@@ -282,6 +306,13 @@
+@@ -282,6 +314,13 @@
  /* in the Juno firmware. */
  #define CONFIG_ENV_ADDR			0x0BFC0000
  #define CONFIG_ENV_SECT_SIZE		0x00010000
 +#elif defined(CONFIG_TARGET_DESIGNSTART_A5)
-+#define CONFIG_SYS_FLASH_BASE		0x08000000
++#define CONFIG_SYS_FLASH_BASE		0x80000000
 +/* 256 x 256KiB sectors */
 +#define CONFIG_SYS_MAX_FLASH_SECT	256
 +/* Store environment at top of flash */

meta-designstart/recipes-bsp/u-boot/u-boot/0001-armv7-rename-sp804-timer-to-mmio-timer.patch

@@ -1,93 +0,0 @@
-From 381d3916beffa61b253317b671f48f87964c0ec3 Mon Sep 17 00:00:00 2001
-From: Rui Miguel Silva <rui.silva@linaro.org>
-Date: Wed, 14 Aug 2019 09:20:42 +0100
-Subject: [PATCH 2/3] armv7: rename sp804 timer to mmio timer
-
-Rename the wrongly init named mmio timer and fix the use of it on a
-Cortex-A5 system that does not have arch_timer.
-
-Signed-off-by: Usama Arif <usama.arif@arm.com>
-Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
-
-%% original patch: 0001-armv7-rename-sp804-timer-to-mmio-timer.patch
----
- arch/arm/cpu/armv7/Makefile                    |  6 +-----
- .../cpu/armv7/{sp804_timer.c => mmio_timer.c}  | 18 ++++++++++--------
- scripts/config_whitelist.txt                   |  1 +
- 3 files changed, 12 insertions(+), 13 deletions(-)
- rename arch/arm/cpu/armv7/{sp804_timer.c => mmio_timer.c} (71%)
-
-diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
-index 288d14732e..97727a0dbb 100644
---- a/arch/arm/cpu/armv7/Makefile
-+++ b/arch/arm/cpu/armv7/Makefile
-@@ -23,12 +23,8 @@ obj-$(CONFIG_ARMV7_PSCI)	+= psci.o psci-common.o
- obj-$(CONFIG_IPROC) += iproc-common/
- obj-$(CONFIG_KONA) += kona-common/
- 
--SUPPORT_ARCH_TIMER    ?= yes
--ifeq ($(SUPPORT_ARCH_TIMER),no)
--obj-y += sp804_timer.o
--else
- obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
--endif
-+obj-$(CONFIG_SYS_MMIO_TIMER) += mmio_timer.o
- 
- ifneq (,$(filter s5pc1xx exynos,$(SOC)))
- obj-y += s5p-common/
-diff --git a/arch/arm/cpu/armv7/sp804_timer.c b/arch/arm/cpu/armv7/mmio_timer.c
-similarity index 71%
-rename from arch/arm/cpu/armv7/sp804_timer.c
-rename to arch/arm/cpu/armv7/mmio_timer.c
-index 9c1ecf3fa0..862587644f 100644
---- a/arch/arm/cpu/armv7/sp804_timer.c
-+++ b/arch/arm/cpu/armv7/mmio_timer.c
-@@ -11,23 +11,25 @@
- 
- DECLARE_GLOBAL_DATA_PTR;
- 
--#define SP804_TIMER0_BASE  UL(0x1C110000)
--#define SP804_TIMER1_VALUE_OFFSET UL(0x004)
-+#define CNTCTLBASE UL(0x1a020000)
-+#define CNTREADBASE UL(0x1a030000)
- 
--int timer_init(void)
-+static inline uint32_t mmio_read32(uintptr_t addr)
- {
--	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
--	return 0;
-+	return *(volatile uint32_t*)addr;
- }
- 
--static inline uint32_t mmio_read_32(uintptr_t addr)
-+int timer_init(void)
- {
--	return *(volatile uint32_t*)addr;
-+	gd->arch.timer_rate_hz = mmio_read32(CNTCTLBASE);
-+
-+	return 0;
- }
- 
- unsigned long long get_ticks(void)
- {
--	return UINT_MAX - mmio_read_32(SP804_TIMER0_BASE + SP804_TIMER1_VALUE_OFFSET);
-+	return ((mmio_read32(CNTCTLBASE + 0x4) << 32) |
-+		mmio_read32(CNTREADBASE));
- }
- 
- ulong get_timer(ulong base)
-diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
-index 95f27b6ead..e82e53cea3 100644
---- a/scripts/config_whitelist.txt
-+++ b/scripts/config_whitelist.txt
-@@ -3923,6 +3923,7 @@ CONFIG_SYS_MMC_U_BOOT_DST
- CONFIG_SYS_MMC_U_BOOT_OFFS
- CONFIG_SYS_MMC_U_BOOT_SIZE
- CONFIG_SYS_MMC_U_BOOT_START
-+CONFIG_SYS_MMIO_TIMER
- CONFIG_SYS_MONITOR_
- CONFIG_SYS_MONITOR_BASE
- CONFIG_SYS_MONITOR_BASE_EARLY
--- 
-2.17.1
-

meta-designstart/recipes-bsp/u-boot/u-boot/0001-rename_sp804_timer_to_mmio_timer.patch

@@ -0,0 +1,187 @@
+From 9705e83c7eb77aa8d257546f3cebcf3ca924d001 Mon Sep 17 00:00:00 2001
+From: Rui Miguel Silva <rui.silva@linaro.org>
+Date: Wed, 14 Aug 2019 09:20:42 +0100
+Subject: armv7: rename sp804 timer to mmio timer
+
+Rename the wrongly init named mmio timer and fix the use of it on a
+Cortex-A5 system that does not have arch_timer.
+
+Signed-off-by: Usama Arif <usama.arif@arm.com>
+Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
+
+%% original patch: 0001-armv7-rename-sp804-timer-to-mmio-timer.patch
+
+%% original patch: 0001-armv7-rename-sp804-timer-to-mmio-timer.patch
+---
+ arch/arm/cpu/armv7/Makefile      |  6 +--
+ arch/arm/cpu/armv7/mmio_timer.c  | 65 ++++++++++++++++++++++++++++++++
+ arch/arm/cpu/armv7/sp804_timer.c | 54 --------------------------
+ scripts/config_whitelist.txt     |  1 +
+ 4 files changed, 67 insertions(+), 59 deletions(-)
+ create mode 100755 arch/arm/cpu/armv7/mmio_timer.c
+ delete mode 100644 arch/arm/cpu/armv7/sp804_timer.c
+
+diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
+index 288d14732e..97727a0dbb 100644
+--- a/arch/arm/cpu/armv7/Makefile
++++ b/arch/arm/cpu/armv7/Makefile
+@@ -23,12 +23,8 @@ obj-$(CONFIG_ARMV7_PSCI)	+= psci.o psci-common.o
+ obj-$(CONFIG_IPROC) += iproc-common/
+ obj-$(CONFIG_KONA) += kona-common/
+ 
+-SUPPORT_ARCH_TIMER    ?= yes
+-ifeq ($(SUPPORT_ARCH_TIMER),no)
+-obj-y += sp804_timer.o
+-else
+ obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
+-endif
++obj-$(CONFIG_SYS_MMIO_TIMER) += mmio_timer.o
+ 
+ ifneq (,$(filter s5pc1xx exynos,$(SOC)))
+ obj-y += s5p-common/
+diff --git a/arch/arm/cpu/armv7/mmio_timer.c b/arch/arm/cpu/armv7/mmio_timer.c
+new file mode 100755
+index 0000000000..e38dc660c5
+--- /dev/null
++++ b/arch/arm/cpu/armv7/mmio_timer.c
+@@ -0,0 +1,65 @@
++/*
++ * Copyright (c) 2019, Arm Limited. All rights reserved.
++ *
++ * SPDX-License-Identifier:     GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <div64.h>
++#include <bootstage.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define CNTCTLBASE  UL(0x1a020000)
++#define CNTREADBASE UL(0x1a030000)
++#define CNTEN       UL(0x1)
++#define CNTFCREQ    UL(0x100)
++
++static inline uint32_t mmio_read32(uintptr_t addr)
++{
++	return *(volatile uint32_t*)addr;
++}
++
++static inline void mmio_write32(uintptr_t addr, uint32_t data)
++{
++	*(volatile uint32_t*)addr = data;
++}
++
++int timer_init(void)
++{
++	gd->arch.timer_rate_hz = COUNTER_FREQUENCY/CONFIG_SYS_HZ;
++	mmio_write32(CNTCTLBASE + 0x20, COUNTER_FREQUENCY);
++	// Enable counter and enter the number of entries in freq mode table
++	mmio_write32(CNTCTLBASE, CNTFCREQ|CNTEN);
++	return 0;
++}
++
++unsigned long long get_ticks(void)
++{
++	return ((mmio_read32(CNTREADBASE + 0x4) << 32) |
++		mmio_read32(CNTREADBASE));
++}
++
++ulong get_timer(ulong base)
++{
++	return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
++}
++
++void __udelay(unsigned long usec)
++{
++	unsigned long endtick;
++
++	endtick = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
++			1000UL);
++
++	endtick += get_ticks();
++
++	while (get_ticks() < endtick)
++		;
++}
++
++ulong get_tbclk(void)
++{
++	return gd->arch.timer_rate_hz;
++}
+diff --git a/arch/arm/cpu/armv7/sp804_timer.c b/arch/arm/cpu/armv7/sp804_timer.c
+deleted file mode 100644
+index 9c1ecf3fa0..0000000000
+--- a/arch/arm/cpu/armv7/sp804_timer.c
++++ /dev/null
+@@ -1,54 +0,0 @@
+-/*
+- * Copyright (c) 2019, Arm Limited. All rights reserved.
+- *
+- * SPDX-License-Identifier:     GPL-2.0+
+- */
+-
+-#include <common.h>
+-#include <asm/io.h>
+-#include <div64.h>
+-#include <bootstage.h>
+-
+-DECLARE_GLOBAL_DATA_PTR;
+-
+-#define SP804_TIMER0_BASE  UL(0x1C110000)
+-#define SP804_TIMER1_VALUE_OFFSET UL(0x004)
+-
+-int timer_init(void)
+-{
+-	gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
+-	return 0;
+-}
+-
+-static inline uint32_t mmio_read_32(uintptr_t addr)
+-{
+-	return *(volatile uint32_t*)addr;
+-}
+-
+-unsigned long long get_ticks(void)
+-{
+-	return UINT_MAX - mmio_read_32(SP804_TIMER0_BASE + SP804_TIMER1_VALUE_OFFSET);
+-}
+-
+-ulong get_timer(ulong base)
+-{
+-	return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base;
+-}
+-
+-void __udelay(unsigned long usec)
+-{
+-	unsigned long endtime;
+-
+-	endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
+-			1000UL);
+-
+-	endtime += get_ticks();
+-
+-	while (get_ticks() < endtime)
+-		;
+-}
+-
+-ulong get_tbclk(void)
+-{
+-	return gd->arch.timer_rate_hz;
+-}
+diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
+index 95f27b6ead..e82e53cea3 100644
+--- a/scripts/config_whitelist.txt
++++ b/scripts/config_whitelist.txt
+@@ -3923,6 +3923,7 @@ CONFIG_SYS_MMC_U_BOOT_DST
+ CONFIG_SYS_MMC_U_BOOT_OFFS
+ CONFIG_SYS_MMC_U_BOOT_SIZE
+ CONFIG_SYS_MMC_U_BOOT_START
++CONFIG_SYS_MMIO_TIMER
+ CONFIG_SYS_MONITOR_
+ CONFIG_SYS_MONITOR_BASE
+ CONFIG_SYS_MONITOR_BASE_EARLY
+-- 
+2.17.1
+

meta-designstart/recipes-bsp/u-boot/u-boot_%.bbappend

@@ -9,6 +9,6 @@ UBOOT_MACHINE = "vexpress_aemv8a_a5ds_defconfig"
 
 SRC_URI += "\
 	file://0001-skip-creating-libfdt-for-python-for-yocto-build.patch \
-	file://0001-armv7-rename-sp804-timer-to-mmio-timer.patch \
-	file://0001-a5ds-add-support-for-target-designstart-A5.patch \
+	file://0001-rename_sp804_timer_to_mmio_timer.patch \
+	file://0001-a5ds_target_support.patch \
 	"

meta-iota/recipes-core/images/iota-tiny-image.bb

@@ -12,7 +12,10 @@ LICENSE = "MIT"
 
 IMAGE_LINGUAS = " "
 IMAGE_FEATURES += "debug-tweaks"
-IMAGE_FSTYPES += " wic"
+
+IMAGE_CLASSES += "cramfs-xip"
+IMAGE_FSTYPES += " cramfs-xip wic"
+
 DEPENDS += "u-boot-mkimage-native"
 
 inherit core-image