arm-bsp/n1sdp: Enable OP-TEE cache in N1SDP

This change enables N1SDP cache to improve performance by removing this patch: HACK-disable-instruction-cache-and-data-cache.patch Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
arm-bsp/n1sdp: Move OP-TEE to DDR4
2026-07-18 16:37:08 +00:00 · 2023-10-19 21:14:39 -05:00 · 2023-10-19 21:14:39 -05:00 · 2023-10-19 21:14:39 -05:00 · 2023-10-16 09:28:49 -04:00 · 2023-10-06 09:23:53 -04:00
24 changed files with 234 additions and 109 deletions
@@ -6,10 +6,6 @@ This repository contains the Arm layers for OpenEmbedded.

  This layer contains general recipes for the Arm architecture, such as firmware, FVPs, and Arm-specific integration.

-* meta-arm-autonomy
-
-  This layer is the distribution for a reference stack for autonomous systems.
-
 * meta-arm-bsp

  This layer contains machines for Arm reference platforms, for example FVP Base, N1SDP, and Juno.
@@ -6,4 +6,3 @@ header:
 repos:
  meta-virtualization:
    url: git://git.yoctoproject.org/meta-virtualization
-    refspec: master
@@ -0,0 +1,42 @@
+From 2d305094f8f500362079e9e7637d46129bf980e4 Mon Sep 17 00:00:00 2001
+From: Adam Johnston <adam.johnston@arm.com>
+Date: Tue, 25 Jul 2023 16:05:51 +0000
+Subject: [PATCH] n1sdp: Reserve OP-TEE memory from NWd
+
+The physical memory which is used to run OP-TEE on the N1SDP is known
+to the secure world via TOS_FW_CONFIG, but it may not be known to the
+normal world.
+
+As a precaution, explicitly reserve this memory via NT_FW_CONFIG to
+prevent the normal world from using it. This is not required on most
+platforms as the Trusted OS is run from secure RAM.
+
+Upstream-Status: Pending (not yet submitted to upstream)
+Signed-off-by: Adam Johnston <adam.johnston@arm.com>
+Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
+---
+ plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts b/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts
+index da5e04ddb6..b7e2d4e86f 100644
+--- a/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts
+++ b/plat/arm/board/n1sdp/fdts/n1sdp_nt_fw_config.dts
+@@ -20,4 +20,16 @@
+ 		local-ddr-size = <0x0>;
+ 		remote-ddr-size = <0x0>;
+ 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		optee@0xDE000000 {
+			compatible = "removed-dma-pool";
+			reg = <0x0 0xDE000000 0x0 0x02000000>;
+			no-map;
+		};
+	};
+ };
+\ No newline at end of file
@@ -0,0 +1,30 @@
+From 15dab90c3cb8e7677c4f953c2269e8ee1afa01b0 Mon Oct 2 13:45:43 2023
+From: Mariam Elshakfy <mariam.elshakfy@arm.com>
+Date: Mon, 2 Oct 2023 13:45:43 +0000
+Subject: [PATCH] Modify BL32 Location to DDR4
+
+Since OP-TEE start address is changed to run
+from DDR4, this patch changes BL32 entrypoint
+to the correct one.
+
+Upstream-Status: Pending (not yet submitted to upstream)
+Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
+---
+ plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts b/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts
+index ed870803c..797dfe3a4 100644
+--- a/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts
+++ b/plat/arm/board/n1sdp/fdts/n1sdp_optee_spmc_manifest.dts
+@@ -22,8 +22,8 @@
+ 		maj_ver = <0x1>;
+ 		min_ver = <0x0>;
+ 		exec_state = <0x0>;
+-		load_address = <0x0 0x08000000>;
+-		entrypoint = <0x0 0x08000000>;
+		load_address = <0x0 0xDE000000>;
+		entrypoint = <0x0 0xDE000000>;
+ 		binary_size = <0x2000000>;
+ 	};
+ 
@@ -0,0 +1,28 @@
+From 9a1d11b9fbadf740c73aee6dca4fd0370b38e4a8 Tue Oct 3 13:49:13 2023
+From: Mariam Elshakfy <mariam.elshakfy@arm.com>
+Date: Tue, 3 Oct 2023 13:49:13 +0000
+Subject: [PATCH] Modify SPMC Base to DDR4
+
+Since OP-TEE start address is changed to run
+from DDR4, this patch changes SPMC base to 
+the correct one.
+
+Upstream-Status: Pending (not yet submitted to upstream)
+Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
+---
+ plat/arm/board/n1sdp/include/platform_def.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
+index b3799a7b2..b12c61b61 100644
+--- a/plat/arm/board/n1sdp/include/platform_def.h
+++ b/plat/arm/board/n1sdp/include/platform_def.h
+@@ -118,7 +118,7 @@
+ 
+ #define PLAT_ARM_MAX_BL31_SIZE		UL(0x40000)
+ 
+-#define PLAT_ARM_SPMC_BASE		U(0x08000000)
+#define PLAT_ARM_SPMC_BASE		U(0xDE000000)
+ #define PLAT_ARM_SPMC_SIZE		UL(0x02000000)  /* 32 MB */
+ 
+ 
@@ -37,6 +37,7 @@ EXTRA_OEMAKE:append = " \
                        NR_OF_IMAGES_IN_FW_BANK=4 \
                        COT=tbbr \
                        ARM_ROTPK_LOCATION=devel_rsa  \
+                        ERRATA_A35_855472=1 \
                        ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
                        BL32=${RECIPE_SYSROOT}/lib/firmware/tee-pager_v2.bin \
                        LOG_LEVEL=50 \
@@ -9,6 +9,14 @@ TFA_MBEDTLS        = "1"
 TFA_UBOOT          = "0"
 TFA_UEFI           = "1"

+FILESEXTRAPATHS:prepend := "${THISDIR}/files/n1sdp:"
+
+SRC_URI:append = " \ 
+    file://0001-Reserve-OP-TEE-memory-from-nwd.patch \
+    file://0002-Modify-BL32-Location-to-DDR4.patch \
+    file://0003-Modify-SPMC-Base-to-DDR4.patch \
+    "
+
 TFA_ROT_KEY= "plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem"

 # Enabling Secure-EL1 Payload Dispatcher (SPD)
@@ -0,0 +1,29 @@
+From ef97f7083279565dab45a550139935d741f159a9 Mon Sep 17 00:00:00 2001
+From: Emekcan Aras <emekcan.aras@arm.com>
+Date: Fri, 29 Sep 2023 09:57:19 +0100
+Subject: [PATCH] platform: corstone1000: Increase ITS max asset size
+
+Increases the max asset size for ITS to enable parsec services & tests
+
+Upstream-Status: Pending
+Signed-off-by: Emekcan Aras <emekcan.aras@arm.com>
+Signed-off-by: Vikas Katariya <vikas.katariya@arm.com>
+---
+ platform/ext/target/arm/corstone1000/config_tfm_target.h | 5 +++++
+ 1 files changed, 5 insertions(+)
+
+diff --git a/platform/ext/target/arm/corstone1000/config_tfm_target.h b/platform/ext/target/arm/corstone1000/config_tfm_target.h
+index e968366639..3f6e8477e5 100644
+--- a/platform/ext/target/arm/corstone1000/config_tfm_target.h
+++ b/platform/ext/target/arm/corstone1000/config_tfm_target.h
+@@ -24,4 +24,9 @@
+ #undef PS_NUM_ASSETS
+ #define PS_NUM_ASSETS        20
+
+/* The maximum size of asset to be stored in the Internal Trusted Storage area. */
+#undef ITS_MAX_ASSET_SIZE
+#define ITS_MAX_ASSET_SIZE        2048
+
+
+ #endif /* __CONFIG_TFM_TARGET_H__ */
+-- 
@@ -52,6 +52,7 @@ SRC_URI:append:corstone1000 = " \
    file://0014-Platform-Corstone1000-Increase-BL2_DATA_SIZE.patch              \
    file://0015-Platform-Corstone1000-Calculate-the-new-CRC32-value-.patch      \
    file://corstone1000/rwx.patch                                               \
+    file://0016-platform-corstone1000-increase-ITS-max-asset-size.patch         \
    "

 # TF-M ships patches for external dependencies that needs to be applied
@@ -23,6 +23,7 @@ SRC_URI:append = "\
    file://0007-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch;patchdir=edk2-platforms \
    file://0008-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch;patchdir=edk2-platforms \
    file://0009-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch;patchdir=edk2-platforms \
+    file://0010-Platform-ARM-N1Sdp-Reserve-OP-TEE-Region-from-UEFI.patch;patchdir=edk2-platforms \
 "

 do_deploy:append() {
@@ -0,0 +1,65 @@
+From 235fabb2269a86e016bab2886b9129c77f0fea71 Wed Oct 11 16:18:22 2023
+From: Mariam Elshakfy <mariam.elshakfy@arm.com>
+Date: Wed Oct 11 16:18:22 2023 +0000
+
+Subject: [PATCH] Platform/ARM/N1Sdp: Reserve OP-TEE Region from UEFI
+
+To enable cache on N1SDP, OP-TEE has to be moved
+to run from DDR4 memory. Since this memory is
+known to application side, it must be reserved
+
+Upstream-Status: Pending (not yet submitted to upstream)
+Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
+
+diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+index 78f309c3aa..dc82d5bd87 100644
+--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+@@ -62,6 +62,9 @@
+ 
+   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ 
+  gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemoryBase
+  gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemorySize
+
+ [Guids]
+   gArmNeoverseN1SocPlatformInfoDescriptorGuid
+   gEfiHobListGuid          ## CONSUMES  ## SystemTable
+diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+index 8bb9407490..d8ad0f975c 100644
+--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+@@ -150,6 +150,19 @@ ArmPlatformGetVirtualMemoryMap (
+     EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+     EFI_RESOURCE_ATTRIBUTE_TESTED;
+ 
+  // Reserved OP-TEE region
+  BuildResourceDescriptorHob (
+      EFI_RESOURCE_SYSTEM_MEMORY,
+      ResourceAttributes,
+      PcdGet64 (PcdOpteeMemoryBase),
+      PcdGet64 (PcdOpteeMemorySize)
+    );
+  BuildMemoryAllocationHob (
+    PcdGet64 (PcdOpteeMemoryBase),
+    PcdGet64 (PcdOpteeMemorySize),
+    EfiReservedMemoryType
+  );
+
+   BuildResourceDescriptorHob (
+     EFI_RESOURCE_SYSTEM_MEMORY,
+     ResourceAttributes,
+diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+index 9e257ebde0..b400b94fd5 100644
+--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+@@ -86,5 +86,9 @@
+   gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
+   gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
+ 
+  # Base Address of OP-TEE
+  gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemoryBase|0xDE000000|UINT64|0x00000052
+  gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemorySize|0x02000000|UINT64|0x00000053
+
+ [Ppis]
+   gNtFwConfigDtInfoPpiGuid =  { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } }
@@ -49,8 +49,8 @@ index 00000000..06b4975a
 +CFG_CORE_HEAP_SIZE = 0x32000 # 200kb
 +
 +CFG_TEE_CORE_NB_CORE = 4
-+CFG_TZDRAM_START ?= 0x08000000
-+CFG_TZDRAM_SIZE  ?= 0x02008000
+CFG_TZDRAM_START ?= 0xDE000000
+CFG_TZDRAM_SIZE  ?= 0x02000000
 +
 +CFG_SHMEM_START  ?= 0x83000000
 +CFG_SHMEM_SIZE   ?= 0x00210000
@@ -1,46 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-
-From 0c3ce4c09cd7d2ff4cd2e62acab899dd88dc9514 Mon Sep 17 00:00:00 2001
-From: Vishnu Banavath <vishnu.banavath@arm.com>
-Date: Wed, 20 Jul 2022 16:45:59 +0100
-Subject: [PATCH] HACK: disable instruction cache and data cache.
-
-For some reason, n1sdp fails to boot with instruction cache and
-data cache enabled. This is a temporary change to disable I cache
-and D cache until a proper fix is found.
-
-Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
-
-%% original patch: 0003-HACK-disable-instruction-cache-and-data-cache.patch
-
-diff --git a/core/arch/arm/kernel/entry_a64.S b/core/arch/arm/kernel/entry_a64.S
-index 875b6e69..594d6928 100644
--- a/core/arch/arm/kernel/entry_a64.S
-+++ b/core/arch/arm/kernel/entry_a64.S
-@@ -52,7 +52,7 @@
- 
- 	.macro set_sctlr_el1
- 		mrs	x0, sctlr_el1
-		orr	x0, x0, #SCTLR_I
-+		bic	x0, x0, #SCTLR_I
- 		orr	x0, x0, #SCTLR_SA
- 		orr	x0, x0, #SCTLR_SPAN
- #if defined(CFG_CORE_RWDATA_NOEXEC)
-@@ -490,11 +490,11 @@ LOCAL_FUNC enable_mmu , : , .identity_map
- 	isb
- 
- 	/* Enable I and D cache */
-	mrs	x1, sctlr_el1
-+	/* mrs	x1, sctlr_el1
- 	orr	x1, x1, #SCTLR_I
- 	orr	x1, x1, #SCTLR_C
- 	msr	sctlr_el1, x1
-	isb
-+	isb */
- 
- 	/* Adjust stack pointers and return address */
- 	msr	spsel, #1
-- 
-2.17.1
-
@@ -8,10 +8,9 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/files/optee-os/n1sdp:"
 SRC_URI:append = " \
    file://0001-core-arm-add-MPIDR-affinity-shift-and-mask-for-32-bi.patch \
    file://0002-plat-n1sdp-add-N1SDP-platform-support.patch \
-    file://0003-HACK-disable-instruction-cache-and-data-cache.patch \
-    file://0004-Handle-logging-syscall.patch \
-    file://0005-plat-n1sdp-register-DRAM1-to-optee-os.patch \
-    file://0006-plat-n1sdp-add-external-device-tree-base-and-size.patch \
+    file://0003-Handle-logging-syscall.patch \
+    file://0004-plat-n1sdp-register-DRAM1-to-optee-os.patch \
+    file://0005-plat-n1sdp-add-external-device-tree-base-and-size.patch \
    "

 EXTRA_OEMAKE += " CFG_TEE_CORE_LOG_LEVEL=4"
@@ -1,45 +0,0 @@
-From 891eeb87cddb0d52bc9eac39afcca5027a660be6 Mon Sep 17 00:00:00 2001
-From: Jon Mason <jdmason@kudzu.us>
-Date: Fri, 3 Feb 2023 05:21:07 -0500
-Subject: [PATCH 2/2] Revert "arm64: defconfig: Add Nuvoton NPCM family
- support"
-
-This reverts commit 45472f1e5348c7b755b4912f2f529ec81cea044b
-
-Signed-off-by: Jon Mason <jon.mason@arm.com>
-Upstream-Status: Inappropriate
---
- arch/arm64/configs/defconfig | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
-index 70919b241469..4f09b80a1b96 100644
--- a/arch/arm64/configs/defconfig
-+++ b/arch/arm64/configs/defconfig
-@@ -51,7 +51,6 @@ CONFIG_ARCH_MESON=y
- CONFIG_ARCH_MVEBU=y
- CONFIG_ARCH_NXP=y
- CONFIG_ARCH_MXC=y
-CONFIG_ARCH_NPCM=y
- CONFIG_ARCH_QCOM=y
- CONFIG_ARCH_RENESAS=y
- CONFIG_ARCH_ROCKCHIP=y
-@@ -637,7 +636,6 @@ CONFIG_UNIPHIER_WATCHDOG=y
- CONFIG_PM8916_WATCHDOG=m
- CONFIG_BCM2835_WDT=y
- CONFIG_BCM7038_WDT=m
-CONFIG_NPCM7XX_WATCHDOG=y
- CONFIG_MFD_ALTERA_SYSMGR=y
- CONFIG_MFD_BD9571MWV=y
- CONFIG_MFD_AXP20X_I2C=y
-@@ -1049,7 +1047,6 @@ CONFIG_COMMON_CLK_FSL_SAI=y
- CONFIG_COMMON_CLK_S2MPS11=y
- CONFIG_COMMON_CLK_PWM=y
- CONFIG_COMMON_CLK_VC5=y
-CONFIG_COMMON_CLK_NPCM8XX=y
- CONFIG_COMMON_CLK_BD718XX=m
- CONFIG_CLK_RASPBERRYPI=m
- CONFIG_CLK_IMX8MM=y
-- 
-2.30.2
-
@@ -0,0 +1,4 @@
+# These configurations have a dependency on !PREEMPT_RT. Set them to `n` to
+# avoid complain when do_kernel_configcheck.
+CONFIG_LEDS_TRIGGER_CPU=n
+CONFIG_TRANSPARENT_HUGEPAGE=n
@@ -0,0 +1,7 @@
+define KMACHINE generic-arm64
+define KTYPE preempt-rt
+define KARCH arm64
+
+kconf hardware generic-arm64-preempt-rt-tweaks.cfg
+include ktypes/preempt-rt/preempt-rt.scc
+include features/bluetooth/bluetooth.scc
@@ -1,11 +1,5 @@
 ARMFILESPATHS := "${THISDIR}/files:"

-FILESEXTRAPATHS:prepend:aarch64 = "${ARMFILESPATHS}"
-SRC_URI:append:aarch64 = " \
-    file://0001-Revert-arm64-defconfig-Enable-Tegra-MGBE-driver.patch \
-    file://0002-Revert-arm64-defconfig-Add-Nuvoton-NPCM-family-suppo.patch \
-    "
-
 COMPATIBLE_MACHINE:generic-arm64 = "generic-arm64"
 FILESEXTRAPATHS:prepend:generic-arm64 = "${ARMFILESPATHS}"
 SRC_URI:append:generic-arm64 = " \
@@ -0,0 +1,5 @@
+
+FILESEXTRAPATHS:prepend:aarch64 = "${ARMFILESPATHS}"
+SRC_URI:append:aarch64 = " \
+    file://0001-Revert-arm64-defconfig-Enable-Tegra-MGBE-driver.patch \
+    "
@@ -0,0 +1,5 @@
+
+FILESEXTRAPATHS:prepend:aarch64 = "${ARMFILESPATHS}"
+SRC_URI:append:aarch64 = " \
+    file://0001-Revert-arm64-defconfig-Enable-Tegra-MGBE-driver.patch \
+    "
@@ -12,7 +12,7 @@ SRC_URI:append = "\
 "

 #Latest on 2023 April 28
-SRCREV="08b3d39471f4914186bd23793dc920e83b0e3197"
+SRCREV_trusted-services = "08b3d39471f4914186bd23793dc920e83b0e3197"
 LIC_FILES_CHKSUM = "file://${S}/license.rst;md5=ea160bac7f690a069c608516b17997f4"

 S = "${WORKDIR}/git/trusted-services"
@@ -58,6 +58,8 @@ SRC_URI += "git://github.com/OpenAMP/open-amp.git;name=openamp;protocol=https;br
 SRCREV_openamp = "347397decaa43372fc4d00f965640ebde042966d"
 LIC_FILES_CHKSUM += "file://../openamp/LICENSE.md;md5=a8d8cf662ef6bf9936a1e1413585ecbf"

+SRCREV_FORMAT = "trusted-services_dtc_mbedtls_nanopb_qcbor_tcose_cpputest_libmetal_openamp"
+
 # TS ships patches for external dependencies that needs to be applied
 apply_ts_patches() {
    ( cd ${WORKDIR}/git/qcbor;    git stash; git branch -f bf_am; git am ${S}/external/qcbor/*.patch; git reset bf_am )
Author	SHA1	Message	Date
Mariam Elshakfy	9bcc166bd5	arm-bsp/n1sdp: Enable OP-TEE cache in N1SDP This change enables N1SDP cache to improve performance by removing this patch: HACK-disable-instruction-cache-and-data-cache.patch Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>	2023-10-19 21:14:39 -05:00
Mariam Elshakfy	0e35e4b951	arm-bsp/n1sdp: Move OP-TEE to DDR4 Since the original location of OP-TEE in DDR3 observes a HW issue when cache is enabled, this change moves OP-TEE to run from DDR4. Patches are added to TF-A to reflect that change and the used region is also reserved in UEFI (EDK2) to protect against allocations by UEFI applications. OP-TEE size is modified for consistency across all patches to be 32 MB (0x02000000) instead of (0x02008000). Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>	2023-10-19 21:14:39 -05:00
Jon Mason	bbe2d63100	arm/linux-yocto: remove defconfig patch Mikko Rapeli upstreamed the patch for the Nuvoton defconfig issue and it has been pulled back the 6.1 kernel. So, it is no longer needed here. Signed-off-by: Jon Mason <jon.mason@arm.com>	2023-10-19 21:14:39 -05:00
Vikas Katariya	2b57548b36	arm-bsp/corstone1000: Fix RSA key generation issue This support is for Cassini distro using Corstone-1000 platform. When running parsec test, it reports an error `PSA_ERROR_DATA_INVALID (-153)`. This is related to `ITS_MAX_ASSET_SIZE` configuration which is been set to 512 on the secure enclave (TF-M), which defines the max asset size and it overflows when running the parsec tests. The key is generated, but when it is asked to store via `psa_its_set` it returns `PSA_ERROR_INVALID_ARGUMENT (-135)`, which then propagates to `PSA_ERROR_DATA_INVALID (-153)` Increasing the `ITS_MAX_ASSET_SIZE` to 2048 solves this issue. Signed-off-by: Vikas Katariya <vikas.katariya@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2023-10-16 09:28:49 -04:00
Jon Mason	c6380674f5	arm/trusted-services: add SRCREV_FORMAT SRCREV_FORMAT is now required. Add that to address the build breakage. Signed-off-by: Jon Mason <jon.mason@arm.com>	2023-10-06 09:23:53 -04:00
Jon Mason	6e199b354e	README: remove reference to meta-arm-autonomy Signed-off-by: Jon Mason <jon.mason@arm.com>	2023-10-01 16:01:33 -04:00
Abdellatif El Khlifi	7c67197694	arm-bsp/trusted-firmware-a: corstone1000: enable ERRATA_A35_855472 enable errata 855472 for Cortex-A35 in Corstone-1000 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2023-09-29 11:35:27 -04:00
Robbie Cao	85b0e80e7d	arm/recipes-kernel: Add preempt-rt support for generic-arm64 Add kernel configuration necessary to build an image with preempt-rt support for generic-arm64. And tweak kernel configuration for preempt-rt kernel. Signed-off-by: Robbie Cao <robbie.cao@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2023-08-14 10:26:48 -04:00
Jon Mason	821fa15a73	arm/linux-yocto: move 6.1 patches to a unique bbappend Move the 3 patches only needed by the 6.1 kernel into a unique bbappend The defconfig changes cannot be moved into a config fragment because they only exist in the defconfig file (because the patches that integrated their functionality into the kernel were not merged). Signed-off-by: Jon Mason <jon.mason@arm.com>	2023-08-14 10:25:36 -04:00
Jon Mason	18edb7bcff	CI: remove master refspec for meta-virtualization yml file Signed-off-by: Jon Mason <jon.mason@arm.com>	2023-08-14 09:54:23 -04:00
Adam Johnston	10c355b9c7	arm-bsp/trusted-firmware-a: Reserve OP-TEE memory from NWd on N1SDP The physical memory which is used to run OP-TEE on the N1SDP is known to the secure world via TOS_FW_CONFIG, but it may not be known to the normal world. As a precaution, explicitly reserve this memory via NT_FW_CONFIG to prevent the normal world from using it. This is not required on most platforms as the Trusted OS is run from secure RAM. Signed-off-by: Adam Johnston <adam.johnston@arm.com> Signed-off-by: Jon Mason <jon.mason@arm.com>	2023-07-27 09:44:10 -04:00