Revert "arm-bsp/tc0: Enable verified u-boot"

This reverts commit 29cee51f84.
Revert "arm-bsp/u-boot: update SHA for tc0"
2026-07-18 16:37:08 +00:00 · 2021-04-22 23:27:47 +01:00 · 2021-04-22 23:24:10 +01:00 · 2021-04-22 23:23:34 +01:00 · 2021-04-22 23:23:13 +01:00 · 2021-04-22 23:22:02 +01:00
50 changed files with 19532 additions and 489 deletions
@@ -29,8 +29,8 @@ FIT_GENERATE_KEYS = "1"
 PREFERRED_PROVIDER_virtual/trusted-firmware-a ?= "trusted-firmware-a"
 PREFERRED_VERSION_trusted-firmware-a ?= "2.4%"

-PREFERRED_PROVIDER_virtual/kernel ?= "linux-arm64-ack"
 PREFERRED_VERSION_linux-arm64-ack ?= "5.4"
+PREFERRED_PROVIDER_virtual/kernel ?= "linux-arm64-ack"

 # Cannot use the default zImage on arm64
 KERNEL_IMAGETYPE = "Image"
@@ -1,324 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
-
-From cb329ce33874abd8b69988c3dc63fd323a3413be Mon Sep 17 00:00:00 2001
-From: Max Shvetsov <maksims.svecovs@arm.com>
-Date: Thu, 27 Aug 2020 12:37:57 +0100
-Subject: [PATCH 1/4] FF-A: Register secondary core entry point at SPMC init.
-
-When the primary physical core boots the SPMC registers its secondary physical
-core entry points to the SPMD. All Secure Partition are then initialized on
-their primary Execution Contexts. A Secure Partition calls PSCI_CPU_ON from its
-first EC (trapped to the SPMC) passing entry point addresses of secondary ECs.
-ECs are turned "on" in their SPMC internal states, although they do not run yet
-(the service call does not reach the EL3 PSCI layer). Later, when the NWd
-(Hypervisor or OS Kernel) boots, it calls PSCI_CPU_ON for waking up physical
-cores down to EL3. The PSCI layer calls into SPMD PM hooks, then the SPMD calls
-into the SPMC by an exception return to the registered secondary entry point.
-The target secondary core then reaches Hafnium vcpu_main.
-
-Change-Id: I2bd42ea54e1a7feebff20e878345ec196ff352e9
-Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
-Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
---
- inc/hf/arch/init.h                          |   7 ++
- src/arch/aarch64/hypervisor/psci_handler.c  | 131 +++++++++++++++++---
- src/arch/aarch64/inc/hf/arch/spmd_helpers.h |  15 +++
- src/cpu.c                                   |   7 ++
- src/init.c                                  |   2 +
- 5 files changed, 143 insertions(+), 19 deletions(-)
- create mode 100644 src/arch/aarch64/inc/hf/arch/spmd_helpers.h
-
-diff --git a/inc/hf/arch/init.h b/inc/hf/arch/init.h
-index 5205e4e..ef0e48f 100644
--- a/inc/hf/arch/init.h
-+++ b/inc/hf/arch/init.h
-@@ -8,6 +8,8 @@
- 
- #pragma once
- 
-+#include "hf/boot_params.h"
-+
- /**
-  * Performs arch specific boot time initialization.
-  *
-@@ -15,3 +17,8 @@
-  * possible.
-  */
- void arch_one_time_init(void);
-+
-+/**
-+ * Sets up secondary cores.
-+ */
-+void arch_psci_secondary_core_init(const struct boot_params *params);
-diff --git a/src/arch/aarch64/hypervisor/psci_handler.c b/src/arch/aarch64/hypervisor/psci_handler.c
-index f89a00b..bdcc1d3 100644
--- a/src/arch/aarch64/hypervisor/psci_handler.c
-+++ b/src/arch/aarch64/hypervisor/psci_handler.c
-@@ -11,9 +11,11 @@
- #include <stdint.h>
- 
- #include "hf/arch/plat/psci.h"
-+#include "hf/arch/spmd_helpers.h"
- #include "hf/arch/types.h"
- 
- #include "hf/api.h"
-+#include "hf/boot_params.h"
- #include "hf/cpu.h"
- #include "hf/dlog.h"
- #include "hf/ffa.h"
-@@ -24,9 +26,32 @@
- #include "smc.h"
- 
- static uint32_t el3_psci_version;
-+static ffa_vm_id_t physical_ffa_id;
- 
- void cpu_entry(struct cpu *c);
- 
-+#if SECURE_WORLD == 1
-+
-+static void set_ffa_id(void)
-+{
-+	struct ffa_value res =
-+		smc_ffa_call((struct ffa_value){.func = FFA_ID_GET_32});
-+
-+	if (res.func != FFA_SUCCESS_32) {
-+		dlog_error("%s Failed to get it's own FF-A ID.\n", __func__);
-+		physical_ffa_id = HF_INVALID_VM_ID;
-+		return;
-+	}
-+	physical_ffa_id = res.arg2 & 0xFFFF;
-+}
-+
-+#endif
-+
-+ffa_vm_id_t get_ffa_id(void)
-+{
-+	return physical_ffa_id;
-+}
-+
- /* Performs arch specific boot time initialisation. */
- void arch_one_time_init(void)
- {
-@@ -53,9 +78,79 @@ void arch_one_time_init(void)
- 	}
- #else
- 	el3_psci_version = PSCI_VERSION_1_1;
-+
-+	set_ffa_id();
- #endif
- }
- 
-+/**
-+ * Register secondary physical core entry points to the SPMD.
-+ */
-+void arch_psci_secondary_core_init(const struct boot_params *params)
-+{
-+#if SECURE_WORLD == 1
-+	struct ffa_value res;
-+
-+	for (uint32_t count = 0; count < params->cpu_count; count++) {
-+		uint32_t id = params->cpu_ids[count];
-+		struct cpu *cpu = cpu_find(id);
-+		const ffa_vm_id_t ffa_id = get_ffa_id();
-+
-+		res = smc_ffa_call((struct ffa_value){
-+			.func = FFA_MSG_SEND_DIRECT_REQ_32,
-+			.arg1 = (ffa_id << 16) | SPMD_ID,
-+			.arg3 = SPMD_DIRECT_MSG_SET_ENTRY_POINT,
-+			.arg4 = params->cpu_ids[count],
-+			.arg5 = (uintreg_t)&cpu_entry,
-+			.arg6 = (uintreg_t)cpu});
-+
-+		if (res.func != FFA_SUCCESS_32) {
-+			dlog_warning(
-+				"%s Failed to initialize secondary core ID: "
-+				"%u\n",
-+				__func__, id);
-+		}
-+
-+		dlog_verbose("SPMD EP register returned %#x\n", res.func);
-+	}
-+#endif
-+}
-+
-+/**
-+ * Convert a PSCI CPU / affinity ID for a secondary VM to the corresponding vCPU
-+ * index.
-+ */
-+ffa_vcpu_index_t vcpu_id_to_index(cpu_id_t vcpu_id)
-+{
-+	/* For now we use indices as IDs for the purposes of PSCI. */
-+	return vcpu_id;
-+}
-+
-+#if SECURE_WORLD == 1
-+/**
-+ * Use vcpu_on only as a way to initialize entry point without
-+ * an intent to power up vcpu.
-+ */
-+static uintreg_t ffa_register_entrypoint(cpu_id_t id, struct vm *vm,
-+					 uintreg_t entrypoint, uintreg_t param)
-+{
-+	ffa_vcpu_index_t target_vcpu_index = vcpu_id_to_index(id);
-+
-+	if (target_vcpu_index >= vm->vcpu_count) {
-+		return PSCI_ERROR_INVALID_PARAMETERS;
-+	}
-+
-+	struct vcpu *target_vcpu = vm_get_vcpu(vm, target_vcpu_index);
-+	struct vcpu_locked locked_target_vcpu = vcpu_lock(target_vcpu);
-+
-+	vcpu_on(locked_target_vcpu, ipa_init(entrypoint), param);
-+
-+	vcpu_unlock(&locked_target_vcpu);
-+
-+	return PSCI_RETURN_SUCCESS;
-+}
-+#endif
-+
- /**
-  * Handles PSCI requests received via HVC or SMC instructions from the primary
-  * VM.
-@@ -180,7 +275,8 @@ bool psci_primary_vm_handler(struct vcpu *vcpu, uint32_t func, uintreg_t arg0,
- 		panic("CPU off failed");
- 		break;
- 
-	case PSCI_CPU_ON:
-+	case PSCI_CPU_ON: {
-+#if SECURE_WORLD == 0
- 		c = cpu_find(arg0);
- 		if (!c) {
- 			*ret = PSCI_ERROR_INVALID_PARAMETERS;
-@@ -208,7 +304,12 @@ bool psci_primary_vm_handler(struct vcpu *vcpu, uint32_t func, uintreg_t arg0,
- 		if (*ret != PSCI_RETURN_SUCCESS) {
- 			cpu_off(c);
- 		}
-+#else
-+		*ret = ffa_register_entrypoint((cpu_id_t)arg0, vcpu->vm, arg1,
-+					       arg2);
-+#endif
- 		break;
-+	}
- 
- 	case PSCI_MIGRATE:
- 	case PSCI_MIGRATE_INFO_TYPE:
-@@ -234,16 +335,6 @@ bool psci_primary_vm_handler(struct vcpu *vcpu, uint32_t func, uintreg_t arg0,
- 	return true;
- }
- 
-/**
- * Convert a PSCI CPU / affinity ID for a secondary VM to the corresponding vCPU
- * index.
- */
-ffa_vcpu_index_t vcpu_id_to_index(cpu_id_t vcpu_id)
-{
-	/* For now we use indices as IDs for the purposes of PSCI. */
-	return vcpu_id;
-}
-
- /**
-  * Handles PSCI requests received via HVC or SMC instructions from a secondary
-  * VM.
-@@ -337,22 +428,23 @@ bool psci_secondary_vm_handler(struct vcpu *vcpu, uint32_t func, uintreg_t arg0,
- 	case PSCI_CPU_ON: {
- 		/* Parameter names as per PSCI specification. */
- 		cpu_id_t target_cpu = arg0;
-		ipaddr_t entry_point_address = ipa_init(arg1);
- 		uint64_t context_id = arg2;
-		ffa_vcpu_index_t target_vcpu_index =
-			vcpu_id_to_index(target_cpu);
- 		struct vm *vm = vcpu->vm;
-		struct vcpu *target_vcpu;
- 
-+#if SECURE_WORLD == 1
-+		*ret = ffa_register_entrypoint((cpu_id_t)target_cpu, vm, arg1,
-+					       context_id);
-+#else
-+		ffa_vcpu_index_t target_vcpu_index =
-+			vcpu_id_to_index(target_cpu);
- 		if (target_vcpu_index >= vm->vcpu_count) {
- 			*ret = PSCI_ERROR_INVALID_PARAMETERS;
- 			break;
- 		}
-+		struct vcpu *target_vcpu = vm_get_vcpu(vm, target_vcpu_index);
- 
-		target_vcpu = vm_get_vcpu(vm, target_vcpu_index);
-
-		if (vcpu_secondary_reset_and_start(
-			    target_vcpu, entry_point_address, context_id)) {
-+		if (vcpu_secondary_reset_and_start(target_vcpu, ipa_init(arg1),
-+						   context_id)) {
- 			/*
- 			 * Tell the scheduler that it can start running the new
- 			 * vCPU now.
-@@ -362,6 +454,7 @@ bool psci_secondary_vm_handler(struct vcpu *vcpu, uint32_t func, uintreg_t arg0,
- 		} else {
- 			*ret = PSCI_ERROR_ALREADY_ON;
- 		}
-+#endif
- 
- 		break;
- 	}
-diff --git a/src/arch/aarch64/inc/hf/arch/spmd_helpers.h b/src/arch/aarch64/inc/hf/arch/spmd_helpers.h
-new file mode 100644
-index 0000000..6e11c36
--- /dev/null
-+++ b/src/arch/aarch64/inc/hf/arch/spmd_helpers.h
-@@ -0,0 +1,15 @@
-+/*
-+ * Copyright 2020 The Hafnium Authors.
-+ *
-+ * Use of this source code is governed by a BSD-style
-+ * license that can be found in the LICENSE file or at
-+ * https://opensource.org/licenses/BSD-3-Clause.
-+ */
-+
-+#define SPMD_ID 0xFFFF
-+#define SPMD_DIRECT_MSG_SET_ENTRY_POINT 1
-+
-+/**
-+ * Get SPMC ID stored in the manifest.
-+ */
-+ffa_vm_id_t get_ffa_id(void);
-diff --git a/src/cpu.c b/src/cpu.c
-index 0a3fc6f..42a17fa 100644
--- a/src/cpu.c
-+++ b/src/cpu.c
-@@ -138,6 +138,8 @@ bool cpu_on(struct cpu *c, ipaddr_t entry, uintreg_t arg)
- 	c->is_on = true;
- 	sl_unlock(&c->lock);
- 
-+#if SECURE_WORLD == 0
-+
- 	if (!prev) {
- 		struct vm *vm = vm_find(HF_PRIMARY_VM_ID);
- 		struct vcpu *vcpu = vm_get_vcpu(vm, cpu_index(c));
-@@ -148,6 +150,11 @@ bool cpu_on(struct cpu *c, ipaddr_t entry, uintreg_t arg)
- 		vcpu_unlock(&vcpu_locked);
- 	}
- 
-+#else
-+	(void)entry;
-+	(void)arg;
-+#endif
-+
- 	return prev;
- }
- 
-diff --git a/src/init.c b/src/init.c
-index a5b48ab..0121213 100644
--- a/src/init.c
-+++ b/src/init.c
-@@ -146,6 +146,8 @@ void one_time_init(void)
- 
- 	cpu_module_init(params.cpu_ids, params.cpu_count);
- 
-+	arch_psci_secondary_core_init(&params);
-+
- 	/* Load all VMs. */
- 	update.reserved_ranges_count = 0;
- 	if (!load_vms(mm_stage1_locked, &manifest, &cpio, &params, &update,
-- 
-2.26.2
-
@@ -0,0 +1,256 @@
+From 7a8b0d634b23e77bb6c84f1b34c5cc031aa8c105 Mon Sep 17 00:00:00 2001
+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Date: Mon, 12 Apr 2021 10:08:29 +0100
+Subject: [PATCH 1/3] Revert "FFA: Set and verify allocator of memory handle"
+
+This reverts commit 917d2f2dc46b20625156e9067329e04c7fec587d.
+Reverting this commit enables memory sharing between SPs
+
+Upstream-Status: Inappropriate [will not be submitted as its only required for ACK 5.4]
+---
+ inc/hf/arch/ffa_memory_handle.h               | 25 ----------------
+ inc/vmapi/hf/ffa.h                            | 14 ++++-----
+ src/api.c                                     |  4 +--
+ src/arch/aarch64/hypervisor/BUILD.gn          |  1 -
+ .../aarch64/hypervisor/ffa_memory_handle.c    | 29 -------------------
+ src/arch/fake/hypervisor/BUILD.gn             |  1 -
+ src/arch/fake/hypervisor/ffa_memory_handle.c  | 20 -------------
+ src/ffa_memory.c                              | 19 ++++--------
+ 8 files changed, 14 insertions(+), 99 deletions(-)
+ delete mode 100644 inc/hf/arch/ffa_memory_handle.h
+ delete mode 100644 src/arch/aarch64/hypervisor/ffa_memory_handle.c
+ delete mode 100644 src/arch/fake/hypervisor/ffa_memory_handle.c
+
+diff --git a/inc/hf/arch/ffa_memory_handle.h b/inc/hf/arch/ffa_memory_handle.h
+deleted file mode 100644
+index 9eba5d4..0000000
+--- a/inc/hf/arch/ffa_memory_handle.h
+++ /dev/null
+@@ -1,25 +0,0 @@
+-/*
+- * Copyright 2021 The Hafnium Authors.
+- *
+- * Use of this source code is governed by a BSD-style
+- * license that can be found in the LICENSE file or at
+- * https://opensource.org/licenses/BSD-3-Clause.
+- */
+-
+-#ifndef FFA_MEMORY_HANDLE_H
+-#define FFA_MEMORY_HANDLE_H
+-
+-#include "hf/ffa.h"
+-
+-/**
+- * Encodes memory handle according to section 5.10.2 of the FF-A v1.0 spec.
+- */
+-ffa_memory_handle_t ffa_memory_handle_make(uint64_t index);
+-
+-/**
+- * Checks whether given handle was allocated by current world, according to
+- * handle encoding rules.
+- */
+-bool ffa_memory_handle_allocated_by_current_world(ffa_memory_handle_t handle);
+-
+-#endif
+diff --git a/inc/vmapi/hf/ffa.h b/inc/vmapi/hf/ffa.h
+index a79f2eb..a948930 100644
+--- a/inc/vmapi/hf/ffa.h
+++ b/inc/vmapi/hf/ffa.h
+@@ -189,23 +189,21 @@ ATTR_FUNCTION_SET(memory_shareability, ffa_memory_attributes_t,
+ ATTR_FUNCTION_GET(memory_shareability, ffa_memory_attributes_t,
+ 		  FFA_MEMORY_SHAREABILITY_OFFSET, FFA_MEMORY_SHAREABILITY_MASK)
+ 
+-/**
+- * A globally-unique ID assigned by the hypervisor for a region of memory being
+- * sent between VMs.
+- */
+-typedef uint64_t ffa_memory_handle_t;
+-
+ #define FFA_MEMORY_HANDLE_ALLOCATOR_MASK \
+ 	((ffa_memory_handle_t)(UINT64_C(1) << 63))
+ #define FFA_MEMORY_HANDLE_ALLOCATOR_HYPERVISOR \
+ 	((ffa_memory_handle_t)(UINT64_C(1) << 63))
+-
+-#define FFA_MEMORY_HANDLE_ALLOCATOR_SPMC (UINT64_C(0) << 63)
+ #define FFA_MEMORY_HANDLE_INVALID (~UINT64_C(0))
+ 
+ /** The ID of a VM. These are assigned sequentially starting with an offset. */
+ typedef uint16_t ffa_vm_id_t;
+ 
+/**
+ * A globally-unique ID assigned by the hypervisor for a region of memory being
+ * sent between VMs.
+ */
+typedef uint64_t ffa_memory_handle_t;
+
+ /**
+  * A count of VMs. This has the same range as the VM IDs but we give it a
+  * different name to make the different semantics clear.
+diff --git a/src/api.c b/src/api.c
+index fa5c9b7..16626b6 100644
+--- a/src/api.c
+++ b/src/api.c
+@@ -9,7 +9,6 @@
+ #include "hf/api.h"
+ 
+ #include "hf/arch/cpu.h"
+-#include "hf/arch/ffa_memory_handle.h"
+ #include "hf/arch/mm.h"
+ #include "hf/arch/other_world.h"
+ #include "hf/arch/timer.h"
+@@ -2158,7 +2157,8 @@ struct ffa_value api_ffa_mem_reclaim(ffa_memory_handle_t handle,
+ 	struct vm *to = current->vm;
+ 	struct ffa_value ret;
+ 
+-	if (ffa_memory_handle_allocated_by_current_world(handle)) {
+	if ((handle & FFA_MEMORY_HANDLE_ALLOCATOR_MASK) ==
+	    FFA_MEMORY_HANDLE_ALLOCATOR_HYPERVISOR) {
+ 		struct vm_locked to_locked = vm_lock(to);
+ 
+ 		ret = ffa_memory_reclaim(to_locked, handle, flags,
+diff --git a/src/arch/aarch64/hypervisor/BUILD.gn b/src/arch/aarch64/hypervisor/BUILD.gn
+index 8f57598..0f9c15e 100644
+--- a/src/arch/aarch64/hypervisor/BUILD.gn
+++ b/src/arch/aarch64/hypervisor/BUILD.gn
+@@ -17,7 +17,6 @@ offset_size_header("offsets") {
+ source_set("other_world") {
+   public_configs = [ "//src/arch/aarch64:config" ]
+   sources = [
+-    "ffa_memory_handle.c",
+     "other_world.c",
+   ]
+   deps = [
+diff --git a/src/arch/aarch64/hypervisor/ffa_memory_handle.c b/src/arch/aarch64/hypervisor/ffa_memory_handle.c
+deleted file mode 100644
+index 647186d..0000000
+--- a/src/arch/aarch64/hypervisor/ffa_memory_handle.c
+++ /dev/null
+@@ -1,29 +0,0 @@
+-/*
+- * Copyright 2021 The Hafnium Authors.
+- *
+- * Use of this source code is governed by a BSD-style
+- * license that can be found in the LICENSE file or at
+- * https://opensource.org/licenses/BSD-3-Clause.
+- */
+-
+-#include "hf/arch/ffa_memory_handle.h"
+-
+-ffa_memory_handle_t ffa_memory_handle_make(uint64_t index)
+-{
+-#if SECURE_WORLD == 1
+-	return (index & ~FFA_MEMORY_HANDLE_ALLOCATOR_MASK) |
+-	       FFA_MEMORY_HANDLE_ALLOCATOR_SPMC;
+-#else
+-	return index | FFA_MEMORY_HANDLE_ALLOCATOR_HYPERVISOR;
+-#endif
+-}
+-
+-bool ffa_memory_handle_allocated_by_current_world(ffa_memory_handle_t handle)
+-{
+-	return (handle & FFA_MEMORY_HANDLE_ALLOCATOR_MASK) ==
+-#if SECURE_WORLD == 1
+-	       FFA_MEMORY_HANDLE_ALLOCATOR_SPMC;
+-#else
+-	       FFA_MEMORY_HANDLE_ALLOCATOR_HYPERVISOR;
+-#endif
+-}
+diff --git a/src/arch/fake/hypervisor/BUILD.gn b/src/arch/fake/hypervisor/BUILD.gn
+index 8f28802..97a82f6 100644
+--- a/src/arch/fake/hypervisor/BUILD.gn
+++ b/src/arch/fake/hypervisor/BUILD.gn
+@@ -16,7 +16,6 @@ source_set("hypervisor") {
+ 
+ source_set("other_world") {
+   sources = [
+-    "ffa_memory_handle.c",
+     "other_world.c",
+   ]
+ }
+diff --git a/src/arch/fake/hypervisor/ffa_memory_handle.c b/src/arch/fake/hypervisor/ffa_memory_handle.c
+deleted file mode 100644
+index 9091295..0000000
+--- a/src/arch/fake/hypervisor/ffa_memory_handle.c
+++ /dev/null
+@@ -1,20 +0,0 @@
+-/*
+- * Copyright 2021 The Hafnium Authors.
+- *
+- * Use of this source code is governed by a BSD-style
+- * license that can be found in the LICENSE file or at
+- * https://opensource.org/licenses/BSD-3-Clause.
+- */
+-
+-#include "hf/arch/ffa_memory_handle.h"
+-
+-ffa_memory_handle_t ffa_memory_handle_make(uint64_t index)
+-{
+-	return index;
+-}
+-
+-bool ffa_memory_handle_allocated_by_current_world(ffa_memory_handle_t handle)
+-{
+-	(void)handle;
+-	return true;
+-}
+diff --git a/src/ffa_memory.c b/src/ffa_memory.c
+index 8b28191..00ec68c 100644
+--- a/src/ffa_memory.c
+++ b/src/ffa_memory.c
+@@ -8,7 +8,6 @@
+ 
+ #include "hf/ffa_memory.h"
+ 
+-#include "hf/arch/ffa_memory_handle.h"
+ #include "hf/arch/other_world.h"
+ 
+ #include "hf/api.h"
+@@ -121,14 +120,6 @@ static struct ffa_memory_share_state share_states[MAX_MEM_SHARES];
+ alignas(PAGE_SIZE) static uint8_t
+ 	tee_retrieve_buffer[HF_MAILBOX_SIZE * MAX_FRAGMENTS];
+ 
+-/**
+- * Extracts the index from a memory handle allocated by Hafnium's current world.
+- */
+-uint64_t ffa_memory_handle_get_index(ffa_memory_handle_t handle)
+-{
+-	return handle & ~FFA_MEMORY_HANDLE_ALLOCATOR_MASK;
+-}
+-
+ /**
+  * Initialises the next available `struct ffa_memory_share_state` and sets
+  * `share_state_ret` to a pointer to it. If `handle` is
+@@ -159,7 +150,8 @@ static bool allocate_share_state(
+ 
+ 			if (handle == FFA_MEMORY_HANDLE_INVALID) {
+ 				memory_region->handle =
+-					ffa_memory_handle_make(i);
+					i |
+					FFA_MEMORY_HANDLE_ALLOCATOR_HYPERVISOR;
+ 			} else {
+ 				memory_region->handle = handle;
+ 			}
+@@ -213,7 +205,7 @@ static bool get_share_state(struct share_states_locked share_states,
+ 			    struct ffa_memory_share_state **share_state_ret)
+ {
+ 	struct ffa_memory_share_state *share_state;
+-	uint64_t index;
+	uint32_t index;
+ 
+ 	CHECK(share_states.share_states != NULL);
+ 	CHECK(share_state_ret != NULL);
+@@ -222,8 +214,9 @@ static bool get_share_state(struct share_states_locked share_states,
+ 	 * First look for a share_state allocated by us, in which case the
+ 	 * handle is based on the index.
+ 	 */
+-	if (ffa_memory_handle_allocated_by_current_world(handle)) {
+-		index = ffa_memory_handle_get_index(handle);
+	if ((handle & FFA_MEMORY_HANDLE_ALLOCATOR_MASK) ==
+	    FFA_MEMORY_HANDLE_ALLOCATOR_HYPERVISOR) {
+		index = handle & ~FFA_MEMORY_HANDLE_ALLOCATOR_MASK;
+ 		if (index < MAX_MEM_SHARES) {
+ 			share_state = &share_states.share_states[index];
+ 			if (share_state->share_func != 0) {
+-- 
+2.29.2
+
@@ -1,65 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
-
-From 8422e2a5d6b2094f9f451a2d818a593cba29af84 Mon Sep 17 00:00:00 2001
-From: Max Shvetsov <maksims.svecovs@arm.com>
-Date: Thu, 27 Aug 2020 12:39:50 +0100
-Subject: [PATCH 2/4] FF-A: Cold boot and wake up from suspend.
-
-WIP: Currently there is zero entry-point passed with no arguments, This
-will be reworked once a proper way to pass this information will be
-defined.
-
-Change-Id: Ic6050af16d4081ca31729744995fbb999b170e11
-Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
---
- src/main.c | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
-diff --git a/src/main.c b/src/main.c
-index 5f30aac..7b7264f 100644
--- a/src/main.c
-+++ b/src/main.c
-@@ -7,6 +7,7 @@
-  */
- 
- #include "hf/cpu.h"
-+#include "hf/dlog.h"
- #include "hf/vm.h"
- 
- /**
-@@ -16,9 +17,31 @@
- struct vcpu *cpu_main(struct cpu *c)
- {
- 	struct vcpu *vcpu;
-+
- #if SECURE_WORLD == 1
- 	struct vm *first_boot = vm_get_first_boot();
- 
-+	if (c->is_on == false) {
-+		/*
-+		 * This is the PSCI warm reset path (svc_cpu_on_finish
-+		 * handler relayed by SPMD). Notice currenty the "first_boot"
-+		 * VM is resumed on any CPU on event.
-+		 */
-+		(void)cpu_on(c, ipa_init(0UL), 0UL);
-+		dlog_verbose("%s: cpu mpidr 0x%x on\n", __func__, c->id);
-+	}
-+
-+	/*
-+	 * If `vm_get_first_boot` returns a valid vm, the first partition to
-+	 * execute is in accordance to the boot-order field of the partition's
-+	 * manifest.
-+	 * Else, no partition has been configured with the "boot-order" field
-+	 * in its manifest, and primary vm should be booted.
-+	 */
-+	if (!first_boot) {
-+		first_boot = vm_find(HF_PRIMARY_VM_ID);
-+	}
-+
- 	vcpu = vm_get_vcpu(first_boot, cpu_index(c));
- #else
- 	vcpu = vm_get_vcpu(vm_find(HF_PRIMARY_VM_ID), cpu_index(c));
-- 
-2.26.2
-
@@ -0,0 +1,99 @@
+From f080a6ae839b48188131648363c9e050f496f205 Mon Sep 17 00:00:00 2001
+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Date: Mon, 12 Apr 2021 10:22:26 +0100
+Subject: [PATCH 3/3] FF-A: Fix to fetch proper vCPU index for UP SP
+
+When switching the context between SPs, fetch the vCPU index using
+api_vm_get_vcpu() helper routine. This routine gets the vCPU at index 0
+for UP SP.
+
+Rename function api_ffa_msg_send_direct_get_receiver_vcpu() to
+api_vm_get_vcpu() as it is used both in direct message request
+and response.
+
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Change-Id: I45a60427f8c2d1b5058443536d972495728ee0c2
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ src/api.c | 44 +++++++++++++++++++++-----------------------
+ 1 file changed, 21 insertions(+), 23 deletions(-)
+
+diff --git a/src/api.c b/src/api.c
+index 16626b6..4c8034e 100644
+--- a/src/api.c
+++ b/src/api.c
+@@ -63,6 +63,25 @@ void api_init(struct mpool *ppool)
+ 	mpool_init_from(&api_page_pool, ppool);
+ }
+ 
+/**
+ * Get target VM vCPU.
+ * If VM is UP then return first vCPU.
+ * If VM is MP then return vCPU whose index matches current CPU index.
+ */
+static struct vcpu *api_vm_get_vcpu(struct vm *vm, struct vcpu *current)
+{
+	ffa_vcpu_index_t current_cpu_index = cpu_index(current->cpu);
+	struct vcpu *vcpu = NULL;
+
+	if (vm->vcpu_count == 1) {
+		vcpu = vm_get_vcpu(vm, 0);
+	} else if (current_cpu_index < vm->vcpu_count) {
+		vcpu = vm_get_vcpu(vm, current_cpu_index);
+	}
+
+	return vcpu;
+}
+
+ /**
+  * Switches the physical CPU back to the corresponding vCPU of the VM whose ID
+  * is given as argument of the function.
+@@ -80,7 +99,7 @@ static struct vcpu *api_switch_to_vm(struct vcpu *current,
+ 				     ffa_vm_id_t to_id)
+ {
+ 	struct vm *to_vm = vm_find(to_id);
+-	struct vcpu *next = vm_get_vcpu(to_vm, cpu_index(current->cpu));
+	struct vcpu *next = api_vm_get_vcpu(to_vm, current);
+ 
+ 	CHECK(next != NULL);
+ 
+@@ -1630,26 +1649,6 @@ struct ffa_value api_ffa_features(uint32_t function_id)
+ 	}
+ }
+ 
+-/**
+- * Get target VM vCPU for direct messaging request.
+- * If VM is UP then return first vCPU.
+- * If VM is MP then return vCPU whose index matches current CPU index.
+- */
+-static struct vcpu *api_ffa_msg_send_direct_get_receiver_vcpu(
+-	struct vm *vm, struct vcpu *current)
+-{
+-	ffa_vcpu_index_t current_cpu_index = cpu_index(current->cpu);
+-	struct vcpu *vcpu = NULL;
+-
+-	if (vm->vcpu_count == 1) {
+-		vcpu = vm_get_vcpu(vm, 0);
+-	} else if (current_cpu_index < vm->vcpu_count) {
+-		vcpu = vm_get_vcpu(vm, current_cpu_index);
+-	}
+-
+-	return vcpu;
+-}
+-
+ /**
+  * FF-A specification states that x2/w2 Must Be Zero for direct messaging
+  * interfaces.
+@@ -1733,8 +1732,7 @@ struct ffa_value api_ffa_msg_send_direct_req(ffa_vm_id_t sender_vm_id,
+ 	 * number of PEs in the system. It further states that MP partitions
+ 	 * accepting direct request messages cannot migrate.
+ 	 */
+-	receiver_vcpu =
+-		api_ffa_msg_send_direct_get_receiver_vcpu(receiver_vm, current);
+	receiver_vcpu = api_vm_get_vcpu(receiver_vm, current);
+ 	if (receiver_vcpu == NULL) {
+ 		return ffa_error(FFA_INVALID_PARAMETERS);
+ 	}
+-- 
+2.29.2
+
@@ -1,87 +0,0 @@
-Upstream-Status: Pending [Not submitted to upstream yet]
-Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
-
-From 66d7628fea54dd7a25d25a13eb4f732c0a3428d0 Mon Sep 17 00:00:00 2001
-From: Max Shvetsov <maksims.svecovs@arm.com>
-Date: Fri, 18 Sep 2020 13:52:20 +0100
-Subject: [PATCH 3/4] FF-A: Respond to PSCI_CPU_OFF from SPMD.
-
-At run-time when a PSCI call is made from NWd, the corresponding SPMD PM
-hooks gets called and is eventually routed to the SPMC.  This change
-implements a generic "SPMD handler" processing PM events that may be
-conveyed from SPMD to SPMC such as core suspend, core off.
-
-Change-Id: Id288e26d9fbb8328acc71f5cf68c39e095a0e3da
-Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
---
- src/arch/aarch64/hypervisor/handler.c | 40 ++++++++++++++++++++++++++-
- 1 file changed, 39 insertions(+), 1 deletion(-)
-
-diff --git a/src/arch/aarch64/hypervisor/handler.c b/src/arch/aarch64/hypervisor/handler.c
-index c10f77e..95d6a18 100644
--- a/src/arch/aarch64/hypervisor/handler.c
-+++ b/src/arch/aarch64/hypervisor/handler.c
-@@ -13,6 +13,7 @@
- #include "hf/arch/mmu.h"
- #include "hf/arch/other_world.h"
- #include "hf/arch/plat/smc.h"
-+#include "hf/arch/spmd_helpers.h"
- 
- #include "hf/api.h"
- #include "hf/check.h"
-@@ -478,6 +479,41 @@ static bool ffa_handler(struct ffa_value *args, struct vcpu *current,
- 
- #if SECURE_WORLD == 1
- 
-+/**
-+ * Returns true if the message is sent directly from SPMD to SPMC.
-+ */
-+static bool is_spmd_message(const uint64_t arg)
-+{
-+	return (((arg & 0xFFFF) == get_ffa_id()) &&
-+		(((arg >> 16) & 0xFFFF) == SPMD_ID));
-+}
-+
-+/**
-+ * Handle special direct messages from SPMD to SPMC. For now related to power
-+ * management only.
-+ */
-+static bool spmd_handler(struct ffa_value *ret)
-+{
-+	if (!is_spmd_message(ret->arg1)) {
-+		return false;
-+	}
-+
-+	dlog_verbose("%s Handling direct PSCI calls from SPMD\n", __func__);
-+
-+	switch (ret->arg3) {
-+	case PSCI_CPU_OFF:
-+		ret->func = FFA_MSG_SEND_DIRECT_RESP_32;
-+		ret->arg1 = (get_ffa_id() << 16) | SPMD_ID;
-+		ret->arg2 = 0U;
-+		break;
-+	default:
-+		dlog_verbose("Following message not handled %#x\n", ret->arg3);
-+		return false;
-+	}
-+
-+	return true;
-+}
-+
- /**
-  * Called to switch to the other world and handle FF-A calls from it. Returns
-  * when it is ready to run a secure partition again.
-@@ -510,7 +546,9 @@ static void other_world_switch_loop(struct vcpu *other_world_vcpu,
- 		 * the result of the call back to EL3 unless the API handler
- 		 * sets *next to something different.
- 		 */
-		if (!ffa_handler(&other_world_args, other_world_vcpu, next)) {
-+
-+		if (!spmd_handler(&other_world_args) &&
-+		    !ffa_handler(&other_world_args, other_world_vcpu, next)) {
- 			other_world_args.func = SMCCC_ERROR_UNKNOWN;
- 		}
- 	}
-- 
-2.26.2
-
@@ -0,0 +1,32 @@
+From fd177558a1da73fa7e10f8b2997864bb76d66dc8 Mon Sep 17 00:00:00 2001
+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Date: Thu, 15 Apr 2021 10:46:33 +0100
+Subject: [PATCH] tc0: Add Theodul DSU support and GICR changes
+
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Change-Id: I4a9b7e4350410fdacccd8c12ff03a61b7e64e98b
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ project/reference/BUILD.gn | 4 ++--
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/project/reference/BUILD.gn b/project/reference/BUILD.gn
+index 5596009..ffcaab7 100644
+--- a/project/reference/BUILD.gn
+++ b/project/reference/BUILD.gn
+@@ -160,9 +160,9 @@ aarch64_toolchains("secure_tc0") {
+   iommu = "//src/iommu:absent"
+   gic_version = 3
+   gicd_base_address = "0x30000000"
+-  gicr_base_address = "0x30140000"
+-  heap_pages = 60
+-  max_cpus = 4
+  gicr_base_address = "0x30080000"
+  heap_pages = 80
+  max_cpus = 8
+   max_vms = 16
+   toolchain_args = {
+     plat_psci = "//src/arch/aarch64/plat/psci:spmc"
+-- 
+2.29.2
+
@@ -1,15 +1,15 @@
 # TC0 specific configuration

-# Intermediate SHA with 2.4 baseline version
-SRCREV = "ee68c5494dea5c5a59aa02af46b35ab3d949672e"
+# Intermediate SHA with 2.4 baseline version, required for OP-TEE SEL1 support
+SRCREV = "2904b2c5361f06d35c324f37d2e71e3278d351a7"
 PV = "2.4+git${SRCPV}"

 FILESEXTRAPATHS_prepend_tc0 := "${THISDIR}/files/tc0:"

 SRC_URI_append = " \
-    file://0001-FF-A-Register-secondary-core-entry-point-at-SPMC-ini.patch \
-    file://0002-FF-A-Cold-boot-and-wake-up-from-suspend.patch \
-    file://0003-FF-A-Respond-to-PSCI_CPU_OFF-from-SPMD.patch \
+    file://0001-Revert-FFA-Set-and-verify-allocator-of-memory-handle.patch \
+    file://0002-FF-A-Fix-to-fetch-proper-vCPU-index-for-UP-SP.patch \
+    file://0003-tc0-Theodul-GICR-changes.patch \
    "

 COMPATIBLE_MACHINE = "tc0"
@@ -0,0 +1,817 @@
+From 6be977b3196b555cdee0758a380102264410f651 Mon Sep 17 00:00:00 2001
+From: Usama Arif <usama.arif@arm.com>
+Date: Sun, 31 Jan 2021 22:13:07 +0000
+Subject: [PATCH 1/2] product/tc0: add clock and dvfs support for all cores.
+
+This patch corrects the OPPs of cores 0-3 (klein cores)
+and adds the right OPPs for matterhorn cores.
+
+Signed-off-by: Usama Arif <usama.arif@arm.com>
+Change-Id: I1070d71c29ca2d06f9945708c135fa812b172003
+
+Upstream-Status: Backport [https://github.com/ARM-software/SCP-firmware/commit/a550dd1042ecc1e6191ea2636b67d370ee865024]
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+---
+ product/tc0/include/clock_soc.h           |  15 +++-
+ product/tc0/include/scp_soc_mmap.h        |   4 +
+ product/tc0/include/tc0_timer.h           |   3 +-
+ product/tc0/scp_ramfw/config_clock.c      |  18 +++-
+ product/tc0/scp_ramfw/config_css_clock.c  | 105 +++++++++++++++++++---
+ product/tc0/scp_ramfw/config_dvfs.c       |  62 +++++++++++--
+ product/tc0/scp_ramfw/config_mock_psu.c   |  16 +++-
+ product/tc0/scp_ramfw/config_pik_clock.c  |  77 +++++++++++++---
+ product/tc0/scp_ramfw/config_psu.c        |  11 ++-
+ product/tc0/scp_ramfw/config_scmi_perf.c  |   1 +
+ product/tc0/scp_ramfw/config_system_pll.c |  19 +++-
+ product/tc0/scp_romfw/config_clock.c      |   6 +-
+ product/tc0/scp_romfw/config_css_clock.c  |  40 ++++-----
+ product/tc0/scp_romfw/config_pik_clock.c  |  20 ++---
+ product/tc0/scp_romfw/config_system_pll.c |   6 +-
+ 15 files changed, 327 insertions(+), 76 deletions(-)
+
+diff --git a/product/tc0/include/clock_soc.h b/product/tc0/include/clock_soc.h
+index 3e05bbab..2c2805c0 100644
+--- a/product/tc0/include/clock_soc.h
+++ b/product/tc0/include/clock_soc.h
+@@ -17,7 +17,8 @@
+  * PLL clock indexes.
+  */
+ enum clock_pll_idx {
+-    CLOCK_PLL_IDX_CPU0,
+    CLOCK_PLL_IDX_CPU_KLEIN,
+    CLOCK_PLL_IDX_CPU_MATTERHORN,
+     CLOCK_PLL_IDX_SYS,
+     CLOCK_PLL_IDX_INTERCONNECT,
+     CLOCK_PLL_IDX_DPU,
+@@ -30,11 +31,15 @@ enum clock_pll_idx {
+  * PIK clock indexes.
+  */
+ enum clock_pik_idx {
+    CLOCK_PIK_IDX_INTERCONNECT,
+     CLOCK_PIK_IDX_CLUS0_CPU0,
+     CLOCK_PIK_IDX_CLUS0_CPU1,
+     CLOCK_PIK_IDX_CLUS0_CPU2,
+     CLOCK_PIK_IDX_CLUS0_CPU3,
+-    CLOCK_PIK_IDX_INTERCONNECT,
+    CLOCK_PIK_IDX_CLUS0_CPU4,
+    CLOCK_PIK_IDX_CLUS0_CPU5,
+    CLOCK_PIK_IDX_CLUS0_CPU6,
+    CLOCK_PIK_IDX_CLUS0_CPU7,
+     CLOCK_PIK_IDX_SCP,
+     CLOCK_PIK_IDX_GIC,
+     CLOCK_PIK_IDX_PCLKSCP,
+@@ -48,7 +53,8 @@ enum clock_pik_idx {
+  * CSS clock indexes.
+  */
+ enum clock_css_idx {
+-    CLOCK_CSS_IDX_CPU_GROUP0,
+    CLOCK_CSS_IDX_CPU_GROUP_KLEIN,
+    CLOCK_CSS_IDX_CPU_GROUP_MATTERHORN,
+     CLOCK_CSS_IDX_DPU,
+     CLOCK_CSS_IDX_COUNT
+ };
+@@ -58,7 +64,8 @@ enum clock_css_idx {
+  */
+ enum clock_idx {
+     CLOCK_IDX_INTERCONNECT,
+-    CLOCK_IDX_CPU_GROUP0,
+    CLOCK_IDX_CPU_GROUP_KLEIN,
+    CLOCK_IDX_CPU_GROUP_MATTERHORN,
+     CLOCK_IDX_DPU,
+     CLOCK_IDX_PIXEL_0,
+     CLOCK_IDX_PIXEL_1,
+diff --git a/product/tc0/include/scp_soc_mmap.h b/product/tc0/include/scp_soc_mmap.h
+index 14f8a8d5..774bbc29 100644
+--- a/product/tc0/include/scp_soc_mmap.h
+++ b/product/tc0/include/scp_soc_mmap.h
+@@ -22,5 +22,9 @@
+ #define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104)
+ #define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108)
+ #define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C)
+#define SCP_PLL_CPU4 (SCP_PLL_BASE + 0x00000110)
+#define SCP_PLL_CPU5 (SCP_PLL_BASE + 0x00000114)
+#define SCP_PLL_CPU6 (SCP_PLL_BASE + 0x00000118)
+#define SCP_PLL_CPU7 (SCP_PLL_BASE + 0x0000011C)
+ 
+ #endif /* SCP_SOC_MMAP_H */
+diff --git a/product/tc0/include/tc0_timer.h b/product/tc0/include/tc0_timer.h
+index 03d6893c..6f4bf06c 100644
+--- a/product/tc0/include/tc0_timer.h
+++ b/product/tc0/include/tc0_timer.h
+@@ -9,7 +9,8 @@
+ #define CONFIG_TIMER_H
+ 
+ enum config_timer_refclk_sub_element_idx {
+-    CONFIG_TIMER_DVFS_CPU,
+    CONFIG_TIMER_DVFS_CPU_KLEIN,
+    CONFIG_TIMER_DVFS_CPU_MATTERHORN,
+     CONFIG_TIMER_SUB_ELEMENT_IDX_COUNT,
+ };
+ 
+diff --git a/product/tc0/scp_ramfw/config_clock.c b/product/tc0/scp_ramfw/config_clock.c
+index db545119..98863a01 100644
+--- a/product/tc0/scp_ramfw/config_clock.c
+++ b/product/tc0/scp_ramfw/config_clock.c
+@@ -32,13 +32,25 @@ static const struct fwk_element clock_dev_desc_table[] = {
+                     MOD_PIK_CLOCK_API_TYPE_CLOCK),
+             }),
+         },
+-    [CLOCK_IDX_CPU_GROUP0] =
+    [CLOCK_IDX_CPU_GROUP_KLEIN] =
+         {
+-            .name = "CPU_GROUP0",
+            .name = "CPU_GROUP_KLEIN",
+             .data = &((struct mod_clock_dev_config){
+                 .driver_id = FWK_ID_ELEMENT_INIT(
+                     FWK_MODULE_IDX_CSS_CLOCK,
+-                    CLOCK_CSS_IDX_CPU_GROUP0),
+                    CLOCK_CSS_IDX_CPU_GROUP_KLEIN),
+                .api_id = FWK_ID_API_INIT(
+                    FWK_MODULE_IDX_CSS_CLOCK,
+                    MOD_CSS_CLOCK_API_TYPE_CLOCK),
+            }),
+        },
+    [CLOCK_IDX_CPU_GROUP_MATTERHORN] =
+        {
+            .name = "CPU_GROUP_MATTERHORN",
+            .data = &((struct mod_clock_dev_config){
+                .driver_id = FWK_ID_ELEMENT_INIT(
+                    FWK_MODULE_IDX_CSS_CLOCK,
+                    CLOCK_CSS_IDX_CPU_GROUP_MATTERHORN),
+                 .api_id = FWK_ID_API_INIT(
+                     FWK_MODULE_IDX_CSS_CLOCK,
+                     MOD_CSS_CLOCK_API_TYPE_CLOCK),
+diff --git a/product/tc0/scp_ramfw/config_css_clock.c b/product/tc0/scp_ramfw/config_css_clock.c
+index 1ad285ae..14a23d63 100644
+--- a/product/tc0/scp_ramfw/config_css_clock.c
+++ b/product/tc0/scp_ramfw/config_css_clock.c
+@@ -17,7 +17,60 @@
+ #include <fwk_module.h>
+ #include <fwk_module_idx.h>
+ 
+-static const struct mod_css_clock_rate rate_table_cpu_group[] = {
+static const struct mod_css_clock_rate rate_table_cpu_group_klein[] = {
+    {
+        /* Super Underdrive */
+        .rate = 768 * FWK_MHZ,
+        .pll_rate = 768 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Underdrive */
+        .rate = 1153 * FWK_MHZ,
+        .pll_rate = 1153 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Nominal */
+        .rate = 1537 * FWK_MHZ,
+        .pll_rate = 1537 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Overdrive */
+        .rate = 1844 * FWK_MHZ,
+        .pll_rate = 1844 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+    {
+        /* Super Overdrive */
+        .rate = 2152 * FWK_MHZ,
+        .pll_rate = 2152 * FWK_MHZ,
+        .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .clock_div = 1,
+        .clock_mod_numerator = 1,
+        .clock_mod_denominator = 1,
+    },
+};
+
+static const struct mod_css_clock_rate rate_table_cpu_group_matterhorn[] = {
+     {
+         /* Super Underdrive */
+         .rate = 946 * FWK_MHZ,
+@@ -70,39 +123,71 @@ static const struct mod_css_clock_rate rate_table_cpu_group[] = {
+     },
+ };
+ 
+-static const fwk_id_t member_table_cpu_group_0[] = {
+static const fwk_id_t member_table_cpu_group_klein[] = {
+     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0),
+     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1),
+     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2),
+     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU3),
+ };
+ 
+static const fwk_id_t member_table_cpu_group_matterhorn[] = {
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU4),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU5),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU6),
+    FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU7),
+};
+
+
+ static const fwk_id_t member_table_dpu[] = {
+     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_DPU),
+ };
+ 
+ static const struct fwk_element css_clock_element_table[] = {
+-    [CLOCK_CSS_IDX_CPU_GROUP0] =
+    [CLOCK_CSS_IDX_CPU_GROUP_KLEIN] =
+        {
+            .name = "CPU_GROUP_KLEIN",
+            .data = &((struct mod_css_clock_dev_config){
+                .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
+                .rate_table = rate_table_cpu_group_klein,
+                .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+                .clock_switching_source =
+                    MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
+                .pll_id = FWK_ID_ELEMENT_INIT(
+                    FWK_MODULE_IDX_SYSTEM_PLL,
+                    CLOCK_PLL_IDX_CPU_KLEIN),
+                .pll_api_id = FWK_ID_API_INIT(
+                    FWK_MODULE_IDX_SYSTEM_PLL,
+                    MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
+                .member_table = member_table_cpu_group_klein,
+                .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_klein),
+                .member_api_id = FWK_ID_API_INIT(
+                    FWK_MODULE_IDX_PIK_CLOCK,
+                    MOD_PIK_CLOCK_API_TYPE_CSS),
+                .initial_rate = 1537 * FWK_MHZ,
+                .modulation_supported = true,
+            }),
+        },
+    [CLOCK_CSS_IDX_CPU_GROUP_MATTERHORN] =
+         {
+-            .name = "CPU_GROUP_0",
+            .name = "CPU_GROUP_MATTERHORN",
+             .data = &((struct mod_css_clock_dev_config){
+                 .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
+-                .rate_table = rate_table_cpu_group,
+-                .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+                .rate_table = rate_table_cpu_group_matterhorn,
+                .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn),
+                 .clock_switching_source =
+                     MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
+                 .pll_id = FWK_ID_ELEMENT_INIT(
+                     FWK_MODULE_IDX_SYSTEM_PLL,
+-                    CLOCK_PLL_IDX_CPU0),
+                    CLOCK_PLL_IDX_CPU_MATTERHORN),
+                 .pll_api_id = FWK_ID_API_INIT(
+                     FWK_MODULE_IDX_SYSTEM_PLL,
+                     MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
+-                .member_table = member_table_cpu_group_0,
+-                .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0),
+                .member_table = member_table_cpu_group_matterhorn,
+                .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_matterhorn),
+                 .member_api_id = FWK_ID_API_INIT(
+                     FWK_MODULE_IDX_PIK_CLOCK,
+                     MOD_PIK_CLOCK_API_TYPE_CSS),
+-                .initial_rate = 2271 * FWK_MHZ,
+                .initial_rate = 1893 * FWK_MHZ,
+                 .modulation_supported = true,
+             }),
+         },
+diff --git a/product/tc0/scp_ramfw/config_dvfs.c b/product/tc0/scp_ramfw/config_dvfs.c
+index a0b59b2b..4b952ef8 100644
+--- a/product/tc0/scp_ramfw/config_dvfs.c
+++ b/product/tc0/scp_ramfw/config_dvfs.c
+@@ -16,7 +16,35 @@
+ #include <fwk_module.h>
+ #include <fwk_module_idx.h>
+ 
+-static struct mod_dvfs_opp opps[] = { {
+static struct mod_dvfs_opp opps_klein[] = { {
+                                          .level = 768 * 1000000UL,
+                                          .frequency = 768 * FWK_KHZ,
+                                          .voltage = 550,
+                                      },
+                                      {
+                                          .level = 1153 * 1000000UL,
+                                          .frequency = 1153 * FWK_KHZ,
+                                          .voltage = 650,
+                                      },
+                                      {
+                                          .level = 1537 * 1000000UL,
+                                          .frequency = 1537 * FWK_KHZ,
+                                          .voltage = 750,
+                                      },
+                                      {
+                                          .level = 1844 * 1000000UL,
+                                          .frequency = 1844 * FWK_KHZ,
+                                          .voltage = 850,
+                                      },
+                                      {
+                                          .level = 2152 * 1000000UL,
+                                          .frequency = 2152 * FWK_KHZ,
+                                          .voltage = 950,
+                                      },
+                                      { 0 } };
+
+
+static struct mod_dvfs_opp opps_matterhorn[] = { {
+                                           .level = 946 * 1000000UL,
+                                           .frequency = 946 * FWK_KHZ,
+                                           .voltage = 550,
+@@ -43,11 +71,26 @@ static struct mod_dvfs_opp opps[] = { {
+                                       },
+                                       { 0 } };
+ 
+-static const struct mod_dvfs_domain_config cpu_group = {
+static const struct mod_dvfs_domain_config cpu_group_klein = {
+     .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 0),
+-    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP0),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_KLEIN),
+    .alarm_id =
+        FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0, CONFIG_TIMER_DVFS_CPU_KLEIN),
+    .notification_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SCMI_PERF),
+    .updates_api_id = FWK_ID_API_INIT(
+        FWK_MODULE_IDX_SCMI_PERF,
+        MOD_SCMI_PERF_DVFS_UPDATE_API),
+    .retry_ms = 1,
+    .latency = 1200,
+    .sustained_idx = 2,
+    .opps = opps_klein,
+};
+
+static const struct mod_dvfs_domain_config cpu_group_matterhorn = {
+    .psu_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PSU, 1),
+    .clock_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_CPU_GROUP_MATTERHORN),
+     .alarm_id =
+-        FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0, CONFIG_TIMER_DVFS_CPU),
+        FWK_ID_SUB_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0, CONFIG_TIMER_DVFS_CPU_MATTERHORN),
+     .notification_id = FWK_ID_MODULE_INIT(FWK_MODULE_IDX_SCMI_PERF),
+     .updates_api_id = FWK_ID_API_INIT(
+         FWK_MODULE_IDX_SCMI_PERF,
+@@ -55,13 +98,18 @@ static const struct mod_dvfs_domain_config cpu_group = {
+     .retry_ms = 1,
+     .latency = 1200,
+     .sustained_idx = 2,
+-    .opps = opps,
+    .opps = opps_matterhorn,
+ };
+ 
+ static const struct fwk_element element_table[] = { [0] =
+                                                         {
+-                                                            .name = "CPU_GROUP",
+-                                                            .data = &cpu_group,
+                                                            .name = "CPU_GROUP_KLEIN",
+                                                            .data = &cpu_group_klein,
+                                                        },
+                                                    [1] =
+                                                        {
+                                                            .name = "CPU_GROUP_MATTERHORN",
+                                                            .data = &cpu_group_matterhorn,
+                                                         },
+                                                     { 0 } };
+ 
+diff --git a/product/tc0/scp_ramfw/config_mock_psu.c b/product/tc0/scp_ramfw/config_mock_psu.c
+index 1f9411ca..2d3742f2 100644
+--- a/product/tc0/scp_ramfw/config_mock_psu.c
+++ b/product/tc0/scp_ramfw/config_mock_psu.c
+@@ -12,7 +12,21 @@
+ 
+ static const struct fwk_element element_table[] = {
+     {
+-        .name = "DVFS_GROUP0",
+        .name = "DVFS_GROUP_KLEIN",
+        .data =
+            &(const struct mod_mock_psu_element_cfg){
+                .async_alarm_id = FWK_ID_NONE_INIT,
+                .async_alarm_api_id = FWK_ID_NONE_INIT,
+
+                .async_response_id = FWK_ID_NONE_INIT,
+                .async_response_api_id = FWK_ID_NONE_INIT,
+
+                .default_enabled = true,
+                .default_voltage = 550,
+            },
+    },
+    {
+        .name = "DVFS_GROUP_MATTERHORN",
+         .data =
+             &(const struct mod_mock_psu_element_cfg){
+                 .async_alarm_id = FWK_ID_NONE_INIT,
+diff --git a/product/tc0/scp_ramfw/config_pik_clock.c b/product/tc0/scp_ramfw/config_pik_clock.c
+index d2c03865..38837a91 100644
+--- a/product/tc0/scp_ramfw/config_pik_clock.c
+++ b/product/tc0/scp_ramfw/config_pik_clock.c
+@@ -21,9 +21,18 @@
+ /*
+  * Rate lookup tables
+  */
+-static struct mod_pik_clock_rate rate_table_cpu_group[] = {
+static struct mod_pik_clock_rate rate_table_cpu_group_klein[] = {
+     {
+-        .rate = 1750 * FWK_MHZ,
+        .rate = 1537 * FWK_MHZ,
+        .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+        .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+        .divider = 1, /* Rate adjusted via CPU PLL */
+    },
+};
+
+static struct mod_pik_clock_rate rate_table_cpu_group_matterhorn[] = {
+    {
+        .rate = 1893 * FWK_MHZ,
+         .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+         .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+         .divider = 1, /* Rate adjusted via CPU PLL */
+@@ -103,8 +112,8 @@ static const struct fwk_element pik_clock_element_table[] = {
+             .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].CTRL,
+             .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].DIV,
+             .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].MOD,
+-            .rate_table = rate_table_cpu_group,
+-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+            .rate_table = rate_table_cpu_group_klein,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+         }),
+     },
+     [CLOCK_PIK_IDX_CLUS0_CPU1] = {
+@@ -115,8 +124,8 @@ static const struct fwk_element pik_clock_element_table[] = {
+             .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].CTRL,
+             .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].DIV,
+             .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].MOD,
+-            .rate_table = rate_table_cpu_group,
+-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+            .rate_table = rate_table_cpu_group_klein,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+         }),
+     },
+     [CLOCK_PIK_IDX_CLUS0_CPU2] = {
+@@ -127,8 +136,8 @@ static const struct fwk_element pik_clock_element_table[] = {
+             .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].CTRL,
+             .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].DIV,
+             .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].MOD,
+-            .rate_table = rate_table_cpu_group,
+-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+            .rate_table = rate_table_cpu_group_klein,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+         }),
+     },
+     [CLOCK_PIK_IDX_CLUS0_CPU3] = {
+@@ -139,8 +148,56 @@ static const struct fwk_element pik_clock_element_table[] = {
+             .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].CTRL,
+             .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].DIV,
+             .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].MOD,
+-            .rate_table = rate_table_cpu_group,
+-            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+            .rate_table = rate_table_cpu_group_klein,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU4] = {
+        .name = "CLUS0_CPU4",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[4].CTRL,
+            .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[4].DIV,
+            .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[4].MOD,
+            .rate_table = rate_table_cpu_group_matterhorn,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU5] = {
+        .name = "CLUS0_CPU5",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[5].CTRL,
+            .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[5].DIV,
+            .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[5].MOD,
+            .rate_table = rate_table_cpu_group_matterhorn,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU6] = {
+        .name = "CLUS0_CPU6",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[6].CTRL,
+            .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[6].DIV,
+            .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[6].MOD,
+            .rate_table = rate_table_cpu_group_matterhorn,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn),
+        }),
+    },
+    [CLOCK_PIK_IDX_CLUS0_CPU7] = {
+        .name = "CLUS0_CPU7",
+        .data = &((struct mod_pik_clock_dev_config) {
+            .type = MOD_PIK_CLOCK_TYPE_CLUSTER,
+            .is_group_member = true,
+            .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[7].CTRL,
+            .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[7].DIV,
+            .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[7].MOD,
+            .rate_table = rate_table_cpu_group_matterhorn,
+            .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_matterhorn),
+         }),
+     },
+     [CLOCK_PIK_IDX_INTERCONNECT] = {
+diff --git a/product/tc0/scp_ramfw/config_psu.c b/product/tc0/scp_ramfw/config_psu.c
+index 8e3bcb5a..3bf0f7fd 100644
+--- a/product/tc0/scp_ramfw/config_psu.c
+++ b/product/tc0/scp_ramfw/config_psu.c
+@@ -14,7 +14,7 @@
+ 
+ static const struct fwk_element element_table[] = {
+     {
+-        .name = "DVFS_GROUP0",
+        .name = "DVFS_GROUP_KLEIN",
+         .data =
+             &(const struct mod_psu_element_cfg){
+                 .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, 0),
+@@ -22,6 +22,15 @@ static const struct fwk_element element_table[] = {
+                     FWK_MODULE_IDX_MOCK_PSU,
+                     MOD_MOCK_PSU_API_IDX_DRIVER) },
+     },
+    {
+        .name = "DVFS_GROUP_MATTERHORN",
+        .data =
+            &(const struct mod_psu_element_cfg){
+                .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MOCK_PSU, 1),
+                .driver_api_id = FWK_ID_API_INIT(
+                    FWK_MODULE_IDX_MOCK_PSU,
+                    MOD_MOCK_PSU_API_IDX_DRIVER) },
+    },
+     { 0 }
+ };
+ 
+diff --git a/product/tc0/scp_ramfw/config_scmi_perf.c b/product/tc0/scp_ramfw/config_scmi_perf.c
+index f2be2253..6ef6146b 100644
+--- a/product/tc0/scp_ramfw/config_scmi_perf.c
+++ b/product/tc0/scp_ramfw/config_scmi_perf.c
+@@ -15,6 +15,7 @@
+ 
+ static const struct mod_scmi_perf_domain_config domains[] = {
+     [0] = {},
+    [1] = {},
+ };
+ 
+ const struct fwk_module_config config_scmi_perf = {
+diff --git a/product/tc0/scp_ramfw/config_system_pll.c b/product/tc0/scp_ramfw/config_system_pll.c
+index b55dd642..37578855 100644
+--- a/product/tc0/scp_ramfw/config_system_pll.c
+++ b/product/tc0/scp_ramfw/config_system_pll.c
+@@ -18,14 +18,27 @@
+ 
+ static const struct fwk_element system_pll_element_table[] =
+     {
+-        [CLOCK_PLL_IDX_CPU0] =
+        [CLOCK_PLL_IDX_CPU_KLEIN] =
+             {
+-                .name = "CPU_PLL_0",
+                .name = "CPU_PLL_KLEIN",
+                 .data = &((struct mod_system_pll_dev_config){
+                     .control_reg = (void *)SCP_PLL_CPU0,
+                     .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+                     .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0),
+-                    .initial_rate = 1750 * FWK_MHZ,
+                    .initial_rate = 1537 * FWK_MHZ,
+                    .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+                    .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+                    .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+                }),
+            },
+        [CLOCK_PLL_IDX_CPU_MATTERHORN] =
+            {
+                .name = "CPU_PLL_MATTERHORN",
+                .data = &((struct mod_system_pll_dev_config){
+                    .control_reg = (void *)SCP_PLL_CPU4,
+                    .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+                    .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0),
+                    .initial_rate = 1893 * FWK_MHZ,
+                     .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+                     .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+                     .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+diff --git a/product/tc0/scp_romfw/config_clock.c b/product/tc0/scp_romfw/config_clock.c
+index f43b61b0..96806211 100644
+--- a/product/tc0/scp_romfw/config_clock.c
+++ b/product/tc0/scp_romfw/config_clock.c
+@@ -35,13 +35,13 @@ static const struct fwk_element clock_dev_desc_table[] = {
+ 
+             }),
+         },
+-    [CLOCK_IDX_CPU_GROUP0] =
+    [CLOCK_IDX_CPU_GROUP_KLEIN] =
+         {
+-            .name = "CPU_GROUP0",
+            .name = "CPU_GROUP_KLEIN",
+             .data = &((struct mod_clock_dev_config){
+                 .driver_id = FWK_ID_ELEMENT_INIT(
+                     FWK_MODULE_IDX_CSS_CLOCK,
+-                    CLOCK_CSS_IDX_CPU_GROUP0),
+                    CLOCK_CSS_IDX_CPU_GROUP_KLEIN),
+                 .api_id = FWK_ID_API_INIT(
+                     FWK_MODULE_IDX_CSS_CLOCK,
+                     MOD_CSS_CLOCK_API_TYPE_CLOCK),
+diff --git a/product/tc0/scp_romfw/config_css_clock.c b/product/tc0/scp_romfw/config_css_clock.c
+index fcb9bbbb..ca284ee7 100644
+--- a/product/tc0/scp_romfw/config_css_clock.c
+++ b/product/tc0/scp_romfw/config_css_clock.c
+@@ -17,11 +17,11 @@
+ #include <fwk_module.h>
+ #include <fwk_module_idx.h>
+ 
+-static const struct mod_css_clock_rate rate_table_cpu_group[] = {
+static const struct mod_css_clock_rate rate_table_cpu_group_klein[] = {
+     {
+         /* Super Underdrive */
+-        .rate = 946 * FWK_MHZ,
+-        .pll_rate = 946 * FWK_MHZ,
+        .rate = 768 * FWK_MHZ,
+        .pll_rate = 768 * FWK_MHZ,
+         .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+         .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+         .clock_div = 1,
+@@ -30,8 +30,8 @@ static const struct mod_css_clock_rate rate_table_cpu_group[] = {
+     },
+     {
+         /* Underdrive */
+-        .rate = 1419 * FWK_MHZ,
+-        .pll_rate = 1419 * FWK_MHZ,
+        .rate = 1153 * FWK_MHZ,
+        .pll_rate = 1153 * FWK_MHZ,
+         .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+         .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+         .clock_div = 1,
+@@ -40,8 +40,8 @@ static const struct mod_css_clock_rate rate_table_cpu_group[] = {
+     },
+     {
+         /* Nominal */
+-        .rate = 1893 * FWK_MHZ,
+-        .pll_rate = 1893 * FWK_MHZ,
+        .rate = 1537 * FWK_MHZ,
+        .pll_rate = 1537 * FWK_MHZ,
+         .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+         .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+         .clock_div = 1,
+@@ -50,8 +50,8 @@ static const struct mod_css_clock_rate rate_table_cpu_group[] = {
+     },
+     {
+         /* Overdrive */
+-        .rate = 2271 * FWK_MHZ,
+-        .pll_rate = 2271 * FWK_MHZ,
+        .rate = 1844 * FWK_MHZ,
+        .pll_rate = 1844 * FWK_MHZ,
+         .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+         .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+         .clock_div = 1,
+@@ -60,8 +60,8 @@ static const struct mod_css_clock_rate rate_table_cpu_group[] = {
+     },
+     {
+         /* Super Overdrive */
+-        .rate = 2650 * FWK_MHZ,
+-        .pll_rate = 2650 * FWK_MHZ,
+        .rate = 2152 * FWK_MHZ,
+        .pll_rate = 2152 * FWK_MHZ,
+         .clock_source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+         .clock_div_type = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+         .clock_div = 1,
+@@ -70,7 +70,7 @@ static const struct mod_css_clock_rate rate_table_cpu_group[] = {
+     },
+ };
+ 
+-static const fwk_id_t member_table_cpu_group_0[] = {
+static const fwk_id_t member_table_cpu_group_klein[] = {
+     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU0),
+     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU1),
+     FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK, CLOCK_PIK_IDX_CLUS0_CPU2),
+@@ -78,27 +78,27 @@ static const fwk_id_t member_table_cpu_group_0[] = {
+ };
+ 
+ static const struct fwk_element css_clock_element_table[] = {
+-    [CLOCK_CSS_IDX_CPU_GROUP0] =
+    [CLOCK_CSS_IDX_CPU_GROUP_KLEIN] =
+         {
+-            .name = "CPU_GROUP_0",
+            .name = "CPU_GROUP_KLEIN",
+             .data = &((struct mod_css_clock_dev_config){
+                 .clock_type = MOD_CSS_CLOCK_TYPE_INDEXED,
+-                .rate_table = rate_table_cpu_group,
+-                .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+                .rate_table = rate_table_cpu_group_klein,
+                .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+                 .clock_switching_source =
+                     MOD_PIK_CLOCK_CLUSCLK_SOURCE_SYSREFCLK,
+                 .pll_id = FWK_ID_ELEMENT_INIT(
+                     FWK_MODULE_IDX_SYSTEM_PLL,
+-                    CLOCK_PLL_IDX_CPU0),
+                    CLOCK_PLL_IDX_CPU_KLEIN),
+                 .pll_api_id = FWK_ID_API_INIT(
+                     FWK_MODULE_IDX_SYSTEM_PLL,
+                     MOD_SYSTEM_PLL_API_TYPE_DEFAULT),
+-                .member_table = member_table_cpu_group_0,
+-                .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_0),
+                .member_table = member_table_cpu_group_klein,
+                .member_count = FWK_ARRAY_SIZE(member_table_cpu_group_klein),
+                 .member_api_id = FWK_ID_API_INIT(
+                     FWK_MODULE_IDX_PIK_CLOCK,
+                     MOD_PIK_CLOCK_API_TYPE_CSS),
+-                .initial_rate = 2271 * FWK_MHZ,
+                .initial_rate = 1537 * FWK_MHZ,
+                 .modulation_supported = true,
+             }),
+         },
+diff --git a/product/tc0/scp_romfw/config_pik_clock.c b/product/tc0/scp_romfw/config_pik_clock.c
+index ba7c3ddc..2c883084 100644
+--- a/product/tc0/scp_romfw/config_pik_clock.c
+++ b/product/tc0/scp_romfw/config_pik_clock.c
+@@ -19,9 +19,9 @@
+ /*
+  * Rate lookup tables
+  */
+-static struct mod_pik_clock_rate rate_table_cpu_group[] = {
+static struct mod_pik_clock_rate rate_table_cpu_group_klein[] = {
+     {
+-        .rate = 1750 * FWK_MHZ,
+        .rate = 1537 * FWK_MHZ,
+         .source = MOD_PIK_CLOCK_CLUSCLK_SOURCE_PLL0,
+         .divider_reg = MOD_PIK_CLOCK_MSCLOCK_DIVIDER_DIV_EXT,
+         .divider = 1, /* Rate adjusted via CPU PLL */
+@@ -94,8 +94,8 @@ static const struct fwk_element
+                         .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].CTRL,
+                         .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].DIV,
+                         .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].MOD,
+-                        .rate_table = rate_table_cpu_group,
+-                        .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+                        .rate_table = rate_table_cpu_group_klein,
+                        .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+                     }),
+                 },
+             [CLOCK_PIK_IDX_CLUS0_CPU1] =
+@@ -107,8 +107,8 @@ static const struct fwk_element
+                         .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].CTRL,
+                         .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].DIV,
+                         .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[1].MOD,
+-                        .rate_table = rate_table_cpu_group,
+-                        .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+                        .rate_table = rate_table_cpu_group_klein,
+                        .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+                     }),
+                 },
+             [CLOCK_PIK_IDX_CLUS0_CPU2] =
+@@ -120,8 +120,8 @@ static const struct fwk_element
+                         .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].CTRL,
+                         .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].DIV,
+                         .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[2].MOD,
+-                        .rate_table = rate_table_cpu_group,
+-                        .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+                        .rate_table = rate_table_cpu_group_klein,
+                        .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+                     }),
+                 },
+             [CLOCK_PIK_IDX_CLUS0_CPU3] =
+@@ -133,8 +133,8 @@ static const struct fwk_element
+                         .control_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].CTRL,
+                         .divext_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].DIV,
+                         .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[3].MOD,
+-                        .rate_table = rate_table_cpu_group,
+-                        .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group),
+                        .rate_table = rate_table_cpu_group_klein,
+                        .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group_klein),
+                     }),
+                 },
+             [CLOCK_PIK_IDX_INTERCONNECT] =
+diff --git a/product/tc0/scp_romfw/config_system_pll.c b/product/tc0/scp_romfw/config_system_pll.c
+index e6b578ff..8440f126 100644
+--- a/product/tc0/scp_romfw/config_system_pll.c
+++ b/product/tc0/scp_romfw/config_system_pll.c
+@@ -17,14 +17,14 @@
+ #include <fwk_module.h>
+ 
+ static const struct fwk_element system_pll_element_table[] = {
+-    [CLOCK_PLL_IDX_CPU0] =
+    [CLOCK_PLL_IDX_CPU_KLEIN] =
+         {
+-            .name = "CPU_PLL_0",
+            .name = "CPU_PLL_KLEIN",
+             .data = &((struct mod_system_pll_dev_config){
+                 .control_reg = (void *)SCP_PLL_CPU0,
+                 .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+                 .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0),
+-                .initial_rate = 1750 * FWK_MHZ,
+                .initial_rate = 1537 * FWK_MHZ,
+                 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+                 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+                 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+-- 
+2.29.2
+
@@ -0,0 +1,125 @@
+From 492c5d094b5c9aaeffe076265840056a2b9d57ac Mon Sep 17 00:00:00 2001
+From: Usama Arif <usama.arif@arm.com>
+Date: Tue, 23 Feb 2021 15:06:46 +0000
+Subject: [PATCH 2/2] module/cmn_booker: amend CFGM base address
+
+The CFGM base address calculation depends on the number of ports
+per XP.
+
+Signed-off-by: Usama Arif <usama.arif@arm.com>
+Change-Id: Iabb9e76b86ee80b345857deb86e9acd4cec5988c
+
+Upstream-Status: Backport [https://github.com/ARM-software/SCP-firmware/commit/5abe1656f27216f633b3fc29e20ff64340f47bfe]
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+---
+ module/cmn_booker/include/mod_cmn_booker.h |  7 +++++++
+ module/cmn_booker/src/cmn_booker.c         | 18 +++++++++++++++---
+ module/cmn_booker/src/cmn_booker.h         |  5 +++--
+ module/cmn_booker/src/mod_cmn_booker.c     |  2 +-
+ product/tc0/scp_romfw/config_cmn_booker.c  |  1 +
+ 5 files changed, 27 insertions(+), 6 deletions(-)
+
+diff --git a/module/cmn_booker/include/mod_cmn_booker.h b/module/cmn_booker/include/mod_cmn_booker.h
+index 5d395521..a172b336 100644
+--- a/module/cmn_booker/include/mod_cmn_booker.h
+++ b/module/cmn_booker/include/mod_cmn_booker.h
+@@ -127,6 +127,13 @@ struct mod_cmn_booker_config {
+      *      to a CAL port, node id of HN-F will be a odd number).
+      */
+     bool hnf_cal_mode;
+
+    /*! \
+     * \brief Number of device ports per XP
+     * \details The calculation for CFGM base address depends on the number of
+     *      ports per cross point
+     */
+    unsigned int ports_per_xp;
+ };
+ 
+ /*!
+diff --git a/module/cmn_booker/src/cmn_booker.c b/module/cmn_booker/src/cmn_booker.c
+index d6e90964..277415ef 100644
+--- a/module/cmn_booker/src/cmn_booker.c
+++ b/module/cmn_booker/src/cmn_booker.c
+@@ -196,7 +196,7 @@ unsigned int get_node_pos_y(void *node_base)
+ 
+ struct cmn_booker_cfgm_reg *get_root_node(uintptr_t base,
+     unsigned int hnd_node_id, unsigned int mesh_size_x,
+-    unsigned int mesh_size_y)
+    unsigned int mesh_size_y, unsigned int ports_per_xp)
+ {
+     unsigned int node_pos_x;
+     unsigned int node_pos_y;
+@@ -217,11 +217,23 @@ struct cmn_booker_cfgm_reg *get_root_node(uintptr_t base,
+     node_port = (hnd_node_id >> CMN_BOOKER_NODE_ID_PORT_POS) &
+                 CMN_BOOKER_NODE_ID_PORT_MASK;
+ 
+    /* Calculate node address offset */
+    if(ports_per_xp > 4)
+    {
+        // Single XP configuration, upto 6 device ports allowed
+        offset = ((node_port & 0x3) << CMN_BOOKER_ROOT_NODE_OFFSET_PORT_POS);
+    } else if(ports_per_xp > 2)
+    {
+        // XPs which have more than 2 device ports
+        offset = (((node_port)>>1) << CMN_BOOKER_ROOT_NODE_OFFSET_PORT_POS);
+    }else
+    {
+        offset = (node_port << CMN_BOOKER_ROOT_NODE_OFFSET_PORT_POS);
+    }
+     /* Calculate node address offset */
+     offset = (node_pos_y << CMN_BOOKER_ROOT_NODE_OFFSET_Y_POS) |
+              (node_pos_x << (CMN_BOOKER_ROOT_NODE_OFFSET_Y_POS +
+-                             encoding_bits)) |
+-             (node_port << CMN_BOOKER_ROOT_NODE_OFFSET_PORT_POS);
+                             encoding_bits)) | offset;
+ 
+     return (struct cmn_booker_cfgm_reg *)(base + offset);
+ }
+diff --git a/module/cmn_booker/src/cmn_booker.h b/module/cmn_booker/src/cmn_booker.h
+index 9a89f173..b0d59804 100644
+--- a/module/cmn_booker/src/cmn_booker.h
+++ b/module/cmn_booker/src/cmn_booker.h
+@@ -417,12 +417,13 @@ unsigned int get_node_pos_y(void *node_base);
+  * \param base CMN BOOKER peripheral base address
+  * \param hnd_node_id HN-D node identifier containing the global configuration
+  * \param mesh_size_x Size of the mesh along the x-axis
+- * \param mesh_size_y Size of the mesh along the x-axis
+ * \param mesh_size_y Size of the mesh along the y-axis
+ * \param mesh_size_y Device ports per XP
+  *
+  * \return Pointer to the root node descriptor
+  */
+ struct cmn_booker_cfgm_reg *get_root_node(uintptr_t base,
+     unsigned int hnd_node_id, unsigned int mesh_size_x,
+-    unsigned int mesh_size_y);
+    unsigned int mesh_size_y, unsigned int ports_per_xp);
+ 
+ #endif /* CMN_BOOKER_H */
+diff --git a/module/cmn_booker/src/mod_cmn_booker.c b/module/cmn_booker/src/mod_cmn_booker.c
+index cbff273e..09fc8884 100644
+--- a/module/cmn_booker/src/mod_cmn_booker.c
+++ b/module/cmn_booker/src/mod_cmn_booker.c
+@@ -536,7 +536,7 @@ static int cmn_booker_init(fwk_id_t module_id, unsigned int element_count,
+         return FWK_E_DATA;
+ 
+     ctx->root = get_root_node(config->base, config->hnd_node_id,
+-        config->mesh_size_x, config->mesh_size_y);
+        config->mesh_size_x, config->mesh_size_y, config->ports_per_xp);
+ 
+     ctx->config = config;
+ 
+diff --git a/product/tc0/scp_romfw/config_cmn_booker.c b/product/tc0/scp_romfw/config_cmn_booker.c
+index a076d8d7..d13138b2 100644
+--- a/product/tc0/scp_romfw/config_cmn_booker.c
+++ b/product/tc0/scp_romfw/config_cmn_booker.c
+@@ -116,5 +116,6 @@ const struct fwk_module_config config_cmn_booker = {
+         .clock_id =
+             FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CLOCK, CLOCK_IDX_INTERCONNECT),
+         .hnf_cal_mode = false,
+        .ports_per_xp = 4,
+     }),
+ };
+-- 
+2.29.2
+
@@ -1,5 +1,16 @@
 # TC0 specific SCP configuration

+# Intermediate SHA with 2.7 baseline version, required for Theodul DSU
+SRCREV = "a841e17b9a11784cddd96f3becdd7e4c54cfb44b"
+PV = "2.7+git${SRCPV}"
+
+FILESEXTRAPATHS_prepend_tc0 := "${THISDIR}/files/tc0:"
+
+SRC_URI_append = " \
+    file://0001-product-tc0-add-clock-and-dvfs-support-for-all-cores.patch \
+    file://0002-module-cmn_booker-amend-CFGM-base-address.patch \
+    "
+
 COMPATIBLE_MACHINE = "tc0"

 SCP_PLATFORM = "tc0"
@@ -0,0 +1,199 @@
+From bda42d4e1c56022692b60447279d5321f872aa2b Mon Sep 17 00:00:00 2001
+From: Davidson K <davidson.kumaresan@arm.com>
+Date: Wed, 10 Mar 2021 12:07:15 +0530
+Subject: [PATCH 1/2] product/tc0: Add support for Trusted Services Secure
+ Partitions
+
+This patch adds support for the crypto and secure storage secure
+partitions for the Total Compute platform.  These secure partitions
+have to be managed by Hafnium executing at S-EL2
+
+Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
+Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ Makefile                                      |   4 +
+ docs/plat/arm/arm-build-options.rst           |   4 +
+ .../fdts/tc0_spmc_ts_optee_sp_manifest.dts    | 118 ++++++++++++++++++
+ plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts  |  10 ++
+ 4 files changed, 136 insertions(+)
+ create mode 100644 plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts
+
+diff --git a/Makefile b/Makefile
+index b6c8b210c..d85c52bb4 100644
+--- a/Makefile
+++ b/Makefile
+@@ -514,6 +514,10 @@ ifneq (${SPD},none)
+         ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp)
+             DTC_CPPFLAGS	+=	-DOPTEE_SP_FW_CONFIG
+         endif
+
+        ifeq ($(findstring ts_optee_sp,$(ARM_SPMC_MANIFEST_DTS)),ts_optee_sp)
+            DTC_CPPFLAGS	+=	-DTS_SP_FW_CONFIG
+        endif
+     else
+         # All other SPDs in spd directory
+         SPD_DIR := spd
+diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
+index a1d231357..32cf19291 100644
+--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
+@@ -98,6 +98,10 @@ Arm Platform Build Options
+    device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest
+    file name contains pattern optee_sp.
+ 
+ -  ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and
+   secure-storage) as SP in tb_fw_config device tree. This flag is defined only
+   when ``ARM_SPMC_MANIFEST_DTS`` manifest file name contains pattern ts_optee_sp.
+
+ For a better understanding of these options, the Arm development platform memory
+ map is explained in the :ref:`Firmware Design`.
+ 
+diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts
+new file mode 100644
+index 000000000..ac91db238
+--- /dev/null
+++ b/plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts
+@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+/ {
+	compatible = "arm,ffa-core-manifest-1.0";
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	attribute {
+		spmc_id = <0x8000>;
+		maj_ver = <0x1>;
+		min_ver = <0x0>;
+		exec_state = <0x0>;
+		load_address = <0x0 0xfd000000>;
+		entrypoint = <0x0 0xfd000000>;
+		binary_size = <0x80000>;
+	};
+
+	hypervisor {
+		compatible = "hafnium,hafnium";
+		vm1 {
+			is_ffa_partition;
+			debug_name = "op-tee";
+			load_address = <0xfd280000>;
+			vcpu_count = <8>;
+			mem_size = <0x1980000>; /* 25MB TZC DRAM */
+		};
+		vm2 {
+			is_ffa_partition;
+			debug_name = "secure-storage";
+			load_address = <0xfee00000>;
+			vcpu_count = <1>;
+			mem_size = <0x200000>; /* 2MB TZC DRAM */
+		};
+		vm3 {
+			is_ffa_partition;
+			debug_name = "crypto";
+			load_address = <0xfec00000>;
+			vcpu_count = <1>;
+			mem_size = <0x200000>; /* 2MB TZC DRAM */
+		};
+	};
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		CPU0:cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		/*
+		 * SPMC (Hafnium) requires secondary cpu nodes are declared in
+		 * descending order
+		 */
+		CPU7:cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x700>;
+			enable-method = "psci";
+		};
+
+		CPU6:cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x600>;
+			enable-method = "psci";
+		};
+
+		CPU5:cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x500>;
+			enable-method = "psci";
+		};
+
+		CPU4:cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x400>;
+			enable-method = "psci";
+		};
+
+		CPU3:cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+		};
+
+		CPU2:cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+		};
+
+		CPU1:cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+		};
+	};
+
+	/* 32MB of TC0_TZC_DRAM1_BASE */
+	memory@fd000000 {
+		device_type = "memory";
+		reg = <0x0 0xfd000000 0x2000000>;
+	};
+};
+diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
+index de5f95d5e..82c6ccb27 100644
+--- a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
+++ b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
+@@ -27,6 +27,16 @@
+ 
+ 	secure-partitions {
+ 		compatible = "arm,sp";
+#if TS_SP_FW_CONFIG
+		secure-storage {
+		       uuid = <0xdc1eef48 0x4ccfb17a 0xcfdf8bac 0x141b71f7>;
+		       load-address = <0xfee00000>;
+		};
+		crypto {
+		       uuid = <0xd9df52d5 0x4bb216a2 0x6dd2a49a 0xc0e8843b>;
+		       load-address = <0xfec00000>;
+		};
+#endif
+ #if OPTEE_SP_FW_CONFIG
+ 		op-tee {
+ 		       uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
+-- 
+2.29.2
+
@@ -0,0 +1,59 @@
+From bc31cd2454854ab44aa9861b98f13848c2b474aa Mon Sep 17 00:00:00 2001
+From: Usama Arif <usama.arif@arm.com>
+Date: Tue, 30 Mar 2021 16:39:19 +0100
+Subject: [PATCH 2/2] tc0: update GICR base address
+
+The number of ITS have changed from 4 to 1, resulting
+in GICR base address change.
+
+Signed-off-by: Usama Arif <usama.arif@arm.com>
+Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ fdts/tc0.dts                              | 4 ++--
+ plat/arm/board/tc0/include/platform_def.h | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/fdts/tc0.dts b/fdts/tc0.dts
+index 2d7611cf2..382860d9d 100644
+--- a/fdts/tc0.dts
+++ b/fdts/tc0.dts
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -236,7 +236,7 @@
+ 		ranges;
+ 		interrupt-controller;
+ 		reg = <0x0 0x30000000 0 0x10000>, /* GICD */
+-		      <0x0 0x30140000 0 0x200000>; /* GICR */
+		      <0x0 0x30080000 0 0x200000>; /* GICR */
+ 		interrupts = <0x1 0x9 0x4>;
+ 	};
+ 
+diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h
+index 30b5ab716..b169d7720 100644
+--- a/plat/arm/board/tc0/include/platform_def.h
+++ b/plat/arm/board/tc0/include/platform_def.h
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -220,7 +220,7 @@
+ /* GIC related constants */
+ #define PLAT_ARM_GICD_BASE		UL(0x30000000)
+ #define PLAT_ARM_GICC_BASE		UL(0x2C000000)
+-#define PLAT_ARM_GICR_BASE		UL(0x30140000)
+#define PLAT_ARM_GICR_BASE		UL(0x30080000)
+ 
+ /*
+  * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
+-- 
+2.29.2
+
@@ -0,0 +1,16 @@
+{
+	"secure-storage" : {
+		"image": "secure-storage.bin",
+		"pm": "secure-storage.dts"
+	},
+
+	"crypto" : {
+		"image": "crypto-sp.bin",
+		"pm": "crypto.dts"
+	},
+
+	"op-tee" : {
+		"image": "tee-pager_v2.bin",
+		"pm": "optee_manifest.dts"
+	}
+}
@@ -1,9 +1,17 @@
 # TC0 specific TFA configuration

-# Intermediate SHA with 2.4 baseline version, required for OP-TEE SP
-SRCREV_tfa = "b153ce0391012e9228b807815a65fa0dc514cf77"
+# Intermediate SHA with 2.4 baseline version, required for Theodul DSU
+# --- This SRC_URI will be removed once below SRCREV_tfa gets merged to TF-A master
+SRC_URI = "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https;branch=integration;name=tfa"
+SRCREV_tfa = "8078b5c5a0c2a47710df96412d88df53486e2b29"
 PV = "2.4+git${SRCPV}"

+FILESEXTRAPATHS_prepend_tc0 := "${THISDIR}/files/tc0:"
+
+SRC_URI_append = " \
+    file://0001-product-tc0-Add-support-for-Trusted-Services-Secure-.patch \
+    file://0002-tc0-update-GICR-base-address.patch \
+    "
 DEPENDS += "scp-firmware"

 COMPATIBLE_MACHINE = "tc0"
@@ -18,12 +26,24 @@ TFA_DEBUG = "1"
 TFA_SPD = "spmd"
 TFA_SPMD_SPM_AT_SEL2 = "1"

-# Set optee as SP. Set spmc manifest and sp layout file to optee
-DEPENDS += "optee-os"
+# Set optee, crypto-sp and secure-storage as the SP.
+# Set spmc manifest and sp layout file to match.
+DEPENDS += "optee-os crypto-sp secure-storage"
+SRC_URI_append = " file://sp_layout.json;subdir=sp_layout"

-TFA_SP_LAYOUT_FILE = "${RECIPE_SYSROOT}/lib/firmware/sp_layout.json"
-TFA_ARM_SPMC_MANIFEST_DTS = "plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts"
+TFA_SP_LAYOUT_FILE = "${WORKDIR}/sp_layout/sp_layout.json"
+TFA_ARM_SPMC_MANIFEST_DTS = "plat/arm/board/tc0/fdts/tc0_spmc_ts_optee_sp_manifest.dts"

 EXTRA_OEMAKE += "SCP_BL2=${RECIPE_SYSROOT}/firmware/scp_ramfw.bin"
 EXTRA_OEMAKE += "TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 ARM_ROTPK_LOCATION=devel_rsa \
                     ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem"
+
+do_compile_prepend() {
+    cp -t ${WORKDIR}/sp_layout \
+        ${RECIPE_SYSROOT}/${nonarch_base_libdir}/firmware/tee-pager_v2.bin \
+        ${RECIPE_SYSROOT}/${nonarch_base_libdir}/firmware/optee_manifest.dts \
+        ${RECIPE_SYSROOT}/firmware/secure-storage.bin \
+        ${RECIPE_SYSROOT}/firmware/secure-storage.dts \
+        ${RECIPE_SYSROOT}/firmware/crypto-sp.bin \
+        ${RECIPE_SYSROOT}/firmware/crypto.dts
+}
@@ -0,0 +1,307 @@
+From 854c5d7b8a010d47da38735f15a31d0b7d10ae3c Mon Sep 17 00:00:00 2001
+From: Usama Arif <usama.arif@arm.com>
+Date: Fri, 3 Jul 2020 10:26:56 +0100
+Subject: [PATCH] Add support for Total Compute
+
+This includes basic platform patch support and boots
+kernel and ramdisk that have been sideloaded in DRAM.
+
+Change-Id: I2e35a1d983efd1d27572f671cad5a9fe4ad68ee6
+Signed-off-by: Usama Arif <usama.arif@arm.com>
+Upstream-Status: Pending
+---
+ arch/arm/Kconfig                         |  9 +++
+ board/armltd/totalcompute/Kconfig        | 12 ++++
+ board/armltd/totalcompute/MAINTAINERS    |  6 ++
+ board/armltd/totalcompute/Makefile       |  6 ++
+ board/armltd/totalcompute/totalcompute.c | 74 +++++++++++++++++++++++
+ configs/total_compute_defconfig          | 39 ++++++++++++
+ include/configs/total_compute.h          | 77 ++++++++++++++++++++++++
+ 7 files changed, 223 insertions(+)
+ create mode 100644 board/armltd/totalcompute/Kconfig
+ create mode 100644 board/armltd/totalcompute/MAINTAINERS
+ create mode 100644 board/armltd/totalcompute/Makefile
+ create mode 100644 board/armltd/totalcompute/totalcompute.c
+ create mode 100644 configs/total_compute_defconfig
+ create mode 100644 include/configs/total_compute.h
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 36c9c2fecd0..b423b7655b6 100644
+--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
+@@ -635,6 +635,14 @@ config TARGET_VEXPRESS_CA15_TC2
+ 	select CPU_V7_HAS_VIRT
+ 	select PL011_SERIAL
+ 
+config TARGET_TOTAL_COMPUTE
+	bool "Support Total Compute Platform"
+	select ARM64
+	select PL01X_SERIAL
+	select DM
+	select DM_SERIAL
+	select DM_ETH
+
+ config ARCH_BCMSTB
+ 	bool "Broadcom BCM7XXX family"
+ 	select CPU_V7A
+@@ -1774,6 +1782,7 @@ source "arch/arm/cpu/armv8/Kconfig"
+ 
+ source "arch/arm/mach-imx/Kconfig"
+ 
+source "board/armltd/totalcompute/Kconfig"
+ source "board/bosch/shc/Kconfig"
+ source "board/bosch/guardian/Kconfig"
+ source "board/CarMediaLab/flea3/Kconfig"
+diff --git a/board/armltd/totalcompute/Kconfig b/board/armltd/totalcompute/Kconfig
+new file mode 100644
+index 00000000000..8bd8c30a6b5
+--- /dev/null
+++ b/board/armltd/totalcompute/Kconfig
+@@ -0,0 +1,12 @@
+if TARGET_TOTAL_COMPUTE
+
+config SYS_BOARD
+	default "totalcompute"
+
+config SYS_VENDOR
+	default "armltd"
+
+config SYS_CONFIG_NAME
+	default "total_compute"
+
+endif
+diff --git a/board/armltd/totalcompute/MAINTAINERS b/board/armltd/totalcompute/MAINTAINERS
+new file mode 100644
+index 00000000000..bb09a90a309
+--- /dev/null
+++ b/board/armltd/totalcompute/MAINTAINERS
+@@ -0,0 +1,6 @@
+TOTAL_COMPUTE BOARD
+M:	Usama Arif <usama.arif@arm.com>
+S:	Maintained
+F:	board/armltd/totalcompute/
+F:	include/configs/total_compute.h
+F:	configs/total_compute_defconfig
+diff --git a/board/armltd/totalcompute/Makefile b/board/armltd/totalcompute/Makefile
+new file mode 100644
+index 00000000000..4c40afef723
+--- /dev/null
+++ b/board/armltd/totalcompute/Makefile
+@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020 ARM Limited
+# Usama Arif <usama.arif@arm.com>
+
+obj-y	:= totalcompute.o
+diff --git a/board/armltd/totalcompute/totalcompute.c b/board/armltd/totalcompute/totalcompute.c
+new file mode 100644
+index 00000000000..21247e4ef0f
+--- /dev/null
+++ b/board/armltd/totalcompute/totalcompute.c
+@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 ARM Limited
+ * Usama Arif <usama.arif@arm.com>
+ */
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pl01x_serial_platdata serial_platdata = {
+	.base = UART0_BASE,
+	.type = TYPE_PL011,
+	.clock = CONFIG_PL011_CLOCK,
+};
+
+U_BOOT_DEVICE(total_compute_serials) = {
+	.name = "serial_pl01x",
+	.platdata = &serial_platdata,
+};
+
+static struct mm_region total_compute_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0xff80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = total_compute_mem_map;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_1_SIZE;
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig
+new file mode 100644
+index 00000000000..31d97dddc21
+--- /dev/null
+++ b/configs/total_compute_defconfig
+@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_TARGET_TOTAL_COMPUTE=y
+CONFIG_SYS_TEXT_BASE=0xe0000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute video=640x480-32@60 root=/dev/vda2 ip=dhcp androidboot.selinux=permissive"
+# CONFIG_USE_BOOTCOMMAND is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="TOTAL_COMPUTE# "
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xff000000
+CONFIG_CMD_ARMFLASH=y
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEVICE=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_OF_LIBFDT=y
+diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h
+new file mode 100644
+index 00000000000..54086205db6
+--- /dev/null
+++ b/include/configs/total_compute.h
+@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Total Compute. Parts were derived from other ARM
+ * configurations.
+ * (C) Copyright 2020 ARM Limited
+ * Usama Arif <usama.arif@arm.com>
+ */
+
+#ifndef __TOTAL_COMPUTE_H
+#define __TOTAL_COMPUTE_H
+
+#define CONFIG_REMAKE_ELF
+
+/* Link Definitions */
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+#define CONFIG_ENV_SIZE	0x10000
+
+
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+
+#define UART0_BASE			0x7ff80000
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
+
+/* Generic Interrupt Controller Definitions */
+
+#define GICD_BASE			(0x2C010000)
+#define GICC_BASE			(0x2C02f000)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_CLOCK		7372800
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR		0x90000000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1			0x80000000
+/* Top 32MB reserved for secure world use */
+#define DRAM_SEC_SIZE		0x02000000
+#define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+/* Enable memtest */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+				"kernel_addr_r=0x80080000\0"	\
+				"initrd_addr_r=0x88000000\0"	\
+				"fdt_addr_r=0x83000000\0"	\
+				"fdt_high=0xffffffffffffffff\0"	\
+				"initrd_high=0xffffffffffffffff\0"
+
+#define CONFIG_BOOTCOMMAND	"booti ${kernel_addr_r} ${initrd_addr_r} ${fdt_addr_r}"
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_SYS_FLASH_BASE		0x0C000000
+/* 256 x 256KiB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
+#define FLASH_MAX_SECTOR_SIZE		0x00040000
+
+#endif /* __TOTAL_COMPUTE_H */
+-- 
+2.17.1
+
@@ -81,6 +81,10 @@ SRC_URI_append_tc0 = " \
    file://0011-tee-optee-Add-support-for-session-login-client-UUID-.patch \
    file://0012-driver-optee-Support-for-ffa-transport.patch \
    file://0013-tee-optee-fix-mem-handle-removal-in-ffa_shm_unregist.patch \
+    file://0014-arm64-Add-support-for-asymmetric-AArch32-EL0-configu.patch \
+    file://0015-arm64-smp-Prevent-hotplugging-the-last-AArch32-able-.patch \
+    file://0016-drivers-buf-Add-userspace-ff-a-driver-buf-and-add-to.patch \
+    file://0017-drivers-ffa-modify-FFA-ABIs-with-supported-conventio.patch \
    "

 #
@@ -0,0 +1,462 @@
+Upstream-Status: Backport [http://www.linux-arm.org/git?p=linux-power.git;a=commit;h=ce7d6e205568b7949ff26f2b3c65dc4db1c15b96]
+Signed-off-by: Usama Arif <usama.arif@arm.com>
+
+From 0316669bc2a0e1279427b7a3ed01313b70544756 Mon Sep 17 00:00:00 2001
+From: Catalin Marinas <catalin.marinas@arm.com>
+Date: Thu, 20 Jun 2019 17:59:25 +0100
+Subject: [PATCH 1/2] arm64: Add support for asymmetric AArch32 EL0
+ configurations
+
+There is a non-negligible chance that we may see asymmetric big.LITTLE
+configurations where only the LITTLE CPUs have AArch32 support at EL0.
+While Linux currently handles such configurations by not allowing
+AArch32 tasks, there is a strong marketing push to investigate the
+possibility of allowing compat applications. This patch is aimed to
+facilitate internal testing and NOT FOR UPSTREAM.
+
+When the CONFIG_ASYMMETRIC_AARCH32 option is enabled (EXPERT), the type
+of the ARM64_HAS_32BIT_EL0 capability becomes WEAK_LOCAL_CPU_FEATURE.
+The kernel will now return true for system_supports_32bit_el0() and
+32-bit tasks will be migrated to the capable CPUs during
+do_notify_resume(). If the last CPU supporting 32-bit is offlined, the
+kernel will SIGKILL any scheduled 32-bit tasks (the alternative is to
+prevent offlining through a new .cpu_disable feature entry).
+
+In addition to the relaxation of the ARM64_HAS_32BIT_EL0 capability,
+this patch factors out the 32-bit cpuinfo and features setting into
+separate functions: __cpuinfo_store_cpu_32bit(),
+init_cpu_32bit_features(). The cpuinfo of the booting CPU
+(boot_cpu_data) is now updated on the first 32-bit capable CPU even if
+it is a secondary one. The ID_AA64PFR0_EL0_64BIT_ONLY feature is relaxed
+to FTR_NONSTRICT and FTR_HIGHER_SAFE when the asymmetric AArch32 support
+is enabled. The compat_elf_hwcaps are only verified for the
+AArch32-capable CPUs to still allow hotplugging AArch64-only CPUs.
+
+Cc: Suzuki K Poulose <Suzuki.Poulose@arm.com>
+Cc: Morten Rasmussen <Morten.Rasmussen@arm.com>
+Cc: Valentin Schneider <valentin.schneider@arm.com>
+Cc: Qais Yousef <qais.yousef@arm.com>
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Qais Yousef <qais.yousef@arm.com>
+---
+ arch/arm64/Kconfig                   | 13 ++++++
+ arch/arm64/include/asm/cpu.h         |  2 +
+ arch/arm64/include/asm/cpufeature.h  |  3 ++
+ arch/arm64/include/asm/thread_info.h |  5 ++-
+ arch/arm64/kernel/cpufeature.c       | 64 ++++++++++++++++++----------
+ arch/arm64/kernel/cpuinfo.c          | 61 +++++++++++++++++---------
+ arch/arm64/kernel/process.c          | 17 ++++++++
+ arch/arm64/kernel/signal.c           | 30 ++++++++++++-
+ 8 files changed, 150 insertions(+), 45 deletions(-)
+
+diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
+index 71d23b5d10d4..068e9e9ffc40 100644
+--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
+@@ -1680,6 +1680,19 @@ config DMI
+ 
+ endmenu
+ 
+config ASYMMETRIC_AARCH32
+	bool "Allow support for asymmetric AArch32 support"
+	depends on COMPAT && EXPERT && !KVM
+	help
+	  Enable this option to allow support for asymmetric AArch32 EL0
+	  CPU configurations. Once the AArch32 EL0 support is detected
+	  on a CPU, the feature is made available to user space to allow
+	  the execution of 32-bit (compat) applications by migrating
+	  them to the capable CPUs. Offlining such CPUs leads to 32-bit
+	  applications being killed.
+
+	  If unsure say N.
+
+ config SYSVIPC_COMPAT
+ 	def_bool y
+ 	depends on COMPAT && SYSVIPC
+diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
+index d72d995b7e25..39dbf5827070 100644
+--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
+@@ -15,6 +15,7 @@
+ struct cpuinfo_arm64 {
+ 	struct cpu	cpu;
+ 	struct kobject	kobj;
+	bool		aarch32_valid;
+ 	u32		reg_ctr;
+ 	u32		reg_cntfrq;
+ 	u32		reg_dczid;
+@@ -60,6 +61,7 @@ void cpuinfo_store_cpu(void);
+ void __init cpuinfo_store_boot_cpu(void);
+ 
+ void __init init_cpu_features(struct cpuinfo_arm64 *info);
+void init_cpu_32bit_features(struct cpuinfo_arm64 *info);
+ void update_cpu_features(int cpu, struct cpuinfo_arm64 *info,
+ 				 struct cpuinfo_arm64 *boot);
+ 
+diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
+index 9cde5d2e768f..d00d673d423b 100644
+--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
+@@ -17,6 +17,7 @@
+ #ifndef __ASSEMBLY__
+ 
+ #include <linux/bug.h>
+#include <linux/cpumask.h>
+ #include <linux/jump_label.h>
+ #include <linux/kernel.h>
+ 
+@@ -370,6 +371,8 @@ cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
+ 	return false;
+ }
+ 
+extern cpumask_t aarch32_el0_mask;
+
+ extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
+ extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
+ extern struct static_key_false arm64_const_caps_ready;
+diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h
+index 8c73764b9ed2..54a4c912a7ab 100644
+--- a/arch/arm64/include/asm/thread_info.h
+++ b/arch/arm64/include/asm/thread_info.h
+@@ -66,6 +66,7 @@ void arch_release_task_struct(struct task_struct *tsk);
+ #define TIF_FOREIGN_FPSTATE	3	/* CPU's FP state is not current's */
+ #define TIF_UPROBE		4	/* uprobe breakpoint or singlestep */
+ #define TIF_FSCHECK		5	/* Check FS is USER_DS on return */
+#define TIF_SET_32BIT_AFFINITY	6	/* set thread affinity for asymmetric AArch32 */
+ #define TIF_NOHZ		7
+ #define TIF_SYSCALL_TRACE	8	/* syscall trace active */
+ #define TIF_SYSCALL_AUDIT	9	/* syscall auditing */
+@@ -95,11 +96,13 @@ void arch_release_task_struct(struct task_struct *tsk);
+ #define _TIF_UPROBE		(1 << TIF_UPROBE)
+ #define _TIF_FSCHECK		(1 << TIF_FSCHECK)
+ #define _TIF_32BIT		(1 << TIF_32BIT)
+#define _TIF_SET_32BIT_AFFINITY	(1 << TIF_SET_32BIT_AFFINITY)
+ #define _TIF_SVE		(1 << TIF_SVE)
+ 
+ #define _TIF_WORK_MASK		(_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
+ 				 _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE | \
+-				 _TIF_UPROBE | _TIF_FSCHECK)
+				 _TIF_UPROBE | _TIF_FSCHECK | \
+				 _TIF_SET_32BIT_AFFINITY)
+ 
+ #define _TIF_SYSCALL_WORK	(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
+ 				 _TIF_SYSCALL_TRACEPOINT | _TIF_SECCOMP | \
+diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
+index da92693b202c..c0d656cfe5b8 100644
+--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
+@@ -8,7 +8,6 @@
+ #define pr_fmt(fmt) "CPU features: " fmt
+ 
+ #include <linux/bsearch.h>
+-#include <linux/cpumask.h>
+ #include <linux/crash_dump.h>
+ #include <linux/sort.h>
+ #include <linux/stop_machine.h>
+@@ -164,7 +163,11 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
+ 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
+ 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
+ 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
+#ifndef CONFIG_ASYMMETRIC_AARCH32
+ 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
+#else
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_HIGHER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
+#endif
+ 	ARM64_FTR_END,
+ };
+ 
+@@ -509,7 +512,7 @@ static void __init sort_ftr_regs(void)
+  * Any bits that are not covered by an arm64_ftr_bits entry are considered
+  * RES0 for the system-wide value, and must strictly match.
+  */
+-static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
+static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
+ {
+ 	u64 val = 0;
+ 	u64 strict_mask = ~0x0ULL;
+@@ -590,25 +593,6 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
+ 	init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
+ 	init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
+ 
+-	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
+-		init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
+-		init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
+-		init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
+-		init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
+-		init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
+-		init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
+-		init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
+-		init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
+-		init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
+-		init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
+-		init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
+-		init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
+-		init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
+-		init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
+-		init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
+-		init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
+-	}
+-
+ 	if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
+ 		init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
+ 		sve_init_vq_map();
+@@ -627,6 +611,26 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
+ 	setup_boot_cpu_capabilities();
+ }
+ 
+void init_cpu_32bit_features(struct cpuinfo_arm64 *info)
+{
+	init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
+	init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
+	init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
+	init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
+	init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
+	init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
+	init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
+	init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
+	init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
+	init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
+	init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
+	init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
+	init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
+	init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
+	init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
+	init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
+}
+
+ static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
+ {
+ 	const struct arm64_ftr_bits *ftrp;
+@@ -1264,6 +1268,16 @@ static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
+ }
+ #endif
+ 
+#ifdef CONFIG_ASYMMETRIC_AARCH32
+cpumask_t aarch32_el0_mask;
+
+static void cpu_enable_aarch32_el0(struct arm64_cpu_capabilities const *cap)
+{
+	if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU))
+		cpumask_set_cpu(smp_processor_id(), &aarch32_el0_mask);
+}
+#endif
+
+ static const struct arm64_cpu_capabilities arm64_features[] = {
+ 	{
+ 		.desc = "GIC system register CPU interface",
+@@ -1340,7 +1354,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
+ 	{
+ 		.desc = "32-bit EL0 Support",
+ 		.capability = ARM64_HAS_32BIT_EL0,
+#ifndef CONFIG_ASYMMETRIC_AARCH32
+ 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
+#else
+		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
+		.cpu_enable = cpu_enable_aarch32_el0,
+#endif
+ 		.matches = has_cpuid_feature,
+ 		.sys_reg = SYS_ID_AA64PFR0_EL1,
+ 		.sign = FTR_UNSIGNED,
+@@ -1983,7 +2002,8 @@ static void verify_local_cpu_capabilities(void)
+ 
+ 	verify_local_elf_hwcaps(arm64_elf_hwcaps);
+ 
+-	if (system_supports_32bit_el0())
+	if (system_supports_32bit_el0() &&
+	    this_cpu_has_cap(ARM64_HAS_32BIT_EL0))
+ 		verify_local_elf_hwcaps(compat_elf_hwcaps);
+ 
+ 	if (system_supports_sve())
+diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
+index 05933c065732..bda37687bb66 100644
+--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
+@@ -351,27 +351,6 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
+ 	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
+ 	info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
+ 
+-	/* Update the 32bit ID registers only if AArch32 is implemented */
+-	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
+-		info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
+-		info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
+-		info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
+-		info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
+-		info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
+-		info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
+-		info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
+-		info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
+-		info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
+-		info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
+-		info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
+-		info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
+-		info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
+-
+-		info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
+-		info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
+-		info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
+-	}
+-
+ 	if (IS_ENABLED(CONFIG_ARM64_SVE) &&
+ 	    id_aa64pfr0_sve(info->reg_id_aa64pfr0))
+ 		info->reg_zcr = read_zcr_features();
+@@ -379,10 +358,46 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
+ 	cpuinfo_detect_icache_policy(info);
+ }
+ 
+static void __cpuinfo_store_cpu_32bit(struct cpuinfo_arm64 *info)
+{
+	info->aarch32_valid = true;
+
+	info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
+	info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
+	info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
+	info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
+	info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
+	info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
+	info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
+	info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
+	info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
+	info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
+	info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
+	info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
+	info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
+
+	info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
+	info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
+	info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
+}
+
+ void cpuinfo_store_cpu(void)
+ {
+ 	struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
+ 	__cpuinfo_store_cpu(info);
+	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
+		__cpuinfo_store_cpu_32bit(info);
+	/*
+	 * With asymmetric AArch32 support, populate the boot CPU information
+	 * on the first 32-bit capable secondary CPU if the primary one
+	 * skipped this step.
+	 */
+	if (IS_ENABLED(CONFIG_ASYMMETRIC_AARCH32) &&
+	    !boot_cpu_data.aarch32_valid &&
+	    id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
+		__cpuinfo_store_cpu_32bit(&boot_cpu_data);
+		init_cpu_32bit_features(&boot_cpu_data);
+	}
+ 	update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
+ }
+ 
+@@ -390,9 +405,13 @@ void __init cpuinfo_store_boot_cpu(void)
+ {
+ 	struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
+ 	__cpuinfo_store_cpu(info);
+	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
+		__cpuinfo_store_cpu_32bit(info);
+ 
+ 	boot_cpu_data = *info;
+ 	init_cpu_features(&boot_cpu_data);
+	if (id_aa64pfr0_32bit_el0(boot_cpu_data.reg_id_aa64pfr0))
+		init_cpu_32bit_features(&boot_cpu_data);
+ }
+ 
+ device_initcall(cpuinfo_regs_init);
+diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
+index cc1d8b1025b1..35f0c93699ce 100644
+--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
+@@ -494,6 +494,15 @@ static void entry_task_switch(struct task_struct *next)
+ 	__this_cpu_write(__entry_task, next);
+ }
+ 
+static void aarch32_thread_switch(struct task_struct *next)
+{
+	struct thread_info *ti = task_thread_info(next);
+
+	if (IS_ENABLED(CONFIG_ASYMMETRIC_AARCH32) && is_compat_thread(ti) &&
+	    !cpumask_test_cpu(smp_processor_id(), &aarch32_el0_mask))
+		set_ti_thread_flag(ti, TIF_SET_32BIT_AFFINITY);
+}
+
+ /*
+  * Thread switching.
+  */
+@@ -511,6 +520,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev,
+ 	ptrauth_thread_switch(next);
+ 	ssbs_thread_switch(next);
+ 	scs_overflow_check(next);
+	aarch32_thread_switch(next);
+ 
+ 	/*
+ 	 * Complete any pending TLB or cache maintenance on this CPU in case
+@@ -569,6 +579,13 @@ void arch_setup_new_exec(void)
+ 	current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0;
+ 
+ 	ptrauth_thread_init_user(current);
+
+	/*
+	 * If exec'ing a 32-bit task, force the asymmetric 32-bit feature
+	 * check as the task may not go through a switch_to() call.
+	 */
+	if (IS_ENABLED(CONFIG_ASYMMETRIC_AARCH32) && is_compat_task())
+		set_thread_flag(TIF_SET_32BIT_AFFINITY);
+ }
+ 
+ #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
+diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
+index dd2cdc0d5be2..d8cdd3211d68 100644
+--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
+@@ -8,6 +8,7 @@
+ 
+ #include <linux/cache.h>
+ #include <linux/compat.h>
+#include <linux/cpumask.h>
+ #include <linux/errno.h>
+ #include <linux/kernel.h>
+ #include <linux/signal.h>
+@@ -896,6 +897,29 @@ static void do_signal(struct pt_regs *regs)
+ 	restore_saved_sigmask();
+ }
+ 
+static void set_32bit_cpus_allowed(void)
+{
+	int ret;
+
+	/*
+	 * Try to honour as best as possible whatever affinity request this
+	 * task has. If it spans no compatible CPU, disregard it entirely.
+	 */
+	if (cpumask_intersects(current->cpus_ptr, &aarch32_el0_mask)) {
+		cpumask_t cpus_allowed;
+
+		cpumask_and(&cpus_allowed, current->cpus_ptr, &aarch32_el0_mask);
+		ret = set_cpus_allowed_ptr(current, &cpus_allowed);
+	} else {
+		ret = set_cpus_allowed_ptr(current, &aarch32_el0_mask);
+	}
+
+	if (ret) {
+		pr_warn_once("No CPUs capable of running 32-bit tasks\n");
+		force_sig(SIGKILL);
+	}
+}
+
+ asmlinkage void do_notify_resume(struct pt_regs *regs,
+ 				 unsigned long thread_flags)
+ {
+@@ -910,7 +934,11 @@ asmlinkage void do_notify_resume(struct pt_regs *regs,
+ 		/* Check valid user FS if needed */
+ 		addr_limit_user_check();
+ 
+-		if (thread_flags & _TIF_NEED_RESCHED) {
+		if (IS_ENABLED(CONFIG_ASYMMETRIC_AARCH32) &&
+		    thread_flags & _TIF_SET_32BIT_AFFINITY) {
+			clear_thread_flag(TIF_SET_32BIT_AFFINITY);
+			set_32bit_cpus_allowed();
+		} else if (thread_flags & _TIF_NEED_RESCHED) {
+ 			/* Unmask Debug and SError for the next task */
+ 			local_daif_restore(DAIF_PROCCTX_NOIRQ);
+ 
+-- 
+2.29.2
+
@@ -0,0 +1,89 @@
+Upstream-Status: Backport [http://www.linux-arm.org/git?p=linux-power.git;a=commit;h=e6b567c1cc07dd1690e5d34b6a93ab9819ab2eeb]
+Signed-off-by: Usama Arif <usama.arif@arm.com>
+
+From d6acb605de7d40c295ada9b1f4c8336e4db71ae4 Mon Sep 17 00:00:00 2001
+From: Valentin Schneider <valentin.schneider@arm.com>
+Date: Thu, 5 Sep 2019 17:53:19 +0100
+Subject: [PATCH 2/2] arm64: smp: Prevent hotplugging the last AArch32-able CPU
+
+EL0 AArch32 tasks are now sigkilled when they can't run on any
+compatible CPU, either because there aren't any left (hotplug) or
+because they aren't allowed to run on those left (task affinity).
+
+However, it has been deemed valuable to prevent the loss of
+functionality resulting in offlining the last AArch32-compatible CPU.
+
+Add arch-specific hook in _cpu_down() that allows checking whether we
+can offline a cpu or not and use that hook to veto offlining the last
+AArch32 CPU.
+
+Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>
+Signed-off-by: Qais Yousef <qais.yousef@arm.com>
+---
+ arch/arm64/kernel/smp.c | 22 ++++++++++++++++++++++
+ kernel/cpu.c            |  9 +++++++++
+ 2 files changed, 31 insertions(+)
+
+diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
+index 038ce6263d1c..c8ab4ee29f32 100644
+--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
+@@ -85,6 +85,28 @@ static inline int op_cpu_kill(unsigned int cpu)
+ }
+ #endif
+ 
+bool arch_allows_cpu_disable(int cpu, int tasks_frozen,
+			     enum cpuhp_state target)
+{
+	/*
+	 * Don't let the last AArch32-compatible CPU go down unless the request
+	 * is related to suspend (!tasks_frozen) then allow it to be offlined
+	 * or we'll break suspend-to-ram functionality.
+	 */
+	if (IS_ENABLED(CONFIG_ASYMMETRIC_AARCH32) &&
+	    !cpumask_empty(&aarch32_el0_mask) &&
+	    !tasks_frozen) {
+		cpumask_t online;
+
+		cpumask_and(&online, &aarch32_el0_mask, cpu_online_mask);
+
+		if (cpumask_weight(&online) == 1)
+			return false;
+	}
+
+	return true;
+}
+
+ 
+ /*
+  * Boot a secondary CPU, and assign it the specified idle task.
+diff --git a/kernel/cpu.c b/kernel/cpu.c
+index 261b5098f81c..4fae9b61f442 100644
+--- a/kernel/cpu.c
+++ b/kernel/cpu.c
+@@ -134,6 +134,12 @@ static struct cpuhp_step *cpuhp_get_step(enum cpuhp_state state)
+ 	return cpuhp_hp_states + state;
+ }
+ 
+bool __weak arch_allows_cpu_disable(int cpu, int tasks_frozen,
+				    enum cpuhp_state target)
+{
+	return true;
+}
+
+ /**
+  * cpuhp_invoke_callback _ Invoke the callbacks for a given state
+  * @cpu:	The cpu for which the callback should be invoked
+@@ -985,6 +991,9 @@ static int __ref _cpu_down(unsigned int cpu, int tasks_frozen,
+ 	if (!cpu_present(cpu))
+ 		return -EINVAL;
+ 
+	if (!arch_allows_cpu_disable(cpu, tasks_frozen, target))
+		return -EBUSY;
+
+ 	cpus_write_lock();
+ 
+ 	cpuhp_tasks_frozen = tasks_frozen;
+-- 
+2.29.2
+
@@ -0,0 +1,357 @@
+From 1d85316ed0571300c12216c9cafb634db6fe4a8a Mon Sep 17 00:00:00 2001
+From: Ben Horgan <ben.horgan@arm.com>
+Date: Tue, 16 Mar 2021 16:08:54 +0000
+Subject: [PATCH 1/2] drivers: buf: Add userspace ff-a driver (buf) and add to
+ build
+
+This is an earlier revision of:
+https://gitlab.arm.com/linux-arm/linux-trusted-services/
+
+Change-Id: Iffa92583826285d616aef8d32f3a3326ec4f1f96
+Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+Upstream-Status: Backport [https://git.gitlab.arm.com/linux-arm/linux-trusted-services/-/commit/4696c6f92e991072052d7ef8297db6fa4695994a]
+---
+ drivers/Makefile         |   3 +
+ drivers/buf/Makefile     |   3 +
+ drivers/buf/buf_common.h |  45 +++++++
+ drivers/buf/buf_driver.c | 254 +++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 305 insertions(+)
+ create mode 100644 drivers/buf/Makefile
+ create mode 100644 drivers/buf/buf_common.h
+ create mode 100644 drivers/buf/buf_driver.c
+
+diff --git a/drivers/Makefile b/drivers/Makefile
+index aaef17cc6512..67cb5965ab94 100644
+--- a/drivers/Makefile
+++ b/drivers/Makefile
+@@ -186,3 +186,6 @@ obj-$(CONFIG_SIOX)		+= siox/
+ obj-$(CONFIG_GNSS)		+= gnss/
+ obj-$(CONFIG_INTERCONNECT)	+= interconnect/
+ obj-$(CONFIG_COUNTER)		+= counter/
+
+# FF-A debugfs userspace driver
+obj-y				+= buf/
+diff --git a/drivers/buf/Makefile b/drivers/buf/Makefile
+new file mode 100644
+index 000000000000..d42b20734770
+--- /dev/null
+++ b/drivers/buf/Makefile
+@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y := buf_driver.o
+diff --git a/drivers/buf/buf_common.h b/drivers/buf/buf_common.h
+new file mode 100644
+index 000000000000..397b234bad30
+--- /dev/null
+++ b/drivers/buf/buf_common.h
+@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021, Arm Limited
+ */
+
+#ifndef __BUF_COMMON_H
+#define __BUF_COMMON_H
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#include <uapi/asm-generic/ioctl.h>
+#else
+#include <stdint.h>
+#include <sys/ioctl.h>
+#endif
+
+struct buf_descr {
+	uint8_t *buf;
+	size_t length;
+};
+
+struct msg_args {
+	uint16_t dst_id;
+	uint32_t args[5];
+};
+
+struct endpoint_id {
+	uint32_t uuid_0;
+	uint32_t uuid_1;
+	uint32_t uuid_2;
+	uint32_t uuid_3;
+	uint16_t id;
+};
+
+#define IOCTL_TYPE	0xf0
+
+#define GET_PART_ID	_IOWR(IOCTL_TYPE, 0x00, struct endpoint_id)
+#define SEND_SYNC_MSG	_IOWR(IOCTL_TYPE, 0x01, struct msg_args)
+
+#define SHARE_INIT	_IOR(IOCTL_TYPE, 0x10, unsigned long)
+#define SHARE_DEINIT	_IO(IOCTL_TYPE, 0x11)
+#define SHARE_READ	_IOW(IOCTL_TYPE, 0x12, struct buf_descr)
+#define SHARE_WRITE	_IOW(IOCTL_TYPE, 0x13, struct buf_descr)
+
+#endif /* __BUF_COMMON_H */
+diff --git a/drivers/buf/buf_driver.c b/drivers/buf/buf_driver.c
+new file mode 100644
+index 000000000000..2403709c3757
+--- /dev/null
+++ b/drivers/buf/buf_driver.c
+@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Thin layer to expose FF-A operations towards user space
+ *
+ * The FF-A driver operations are currently not accessible from user space. This
+ * module creates a debugfs interface to expose them. This is only a temporary
+ * workaround, not intended to be merged.
+ *
+ * Copyright (c) 2020-2021, Arm Limited
+ */
+
+#include <asm/uaccess.h>
+#include <linux/arm_ffa.h>
+#include <linux/arm-smcccv1_2.h>
+#include <linux/debugfs.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/scatterlist.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <uapi/linux/stat.h>
+
+#include "buf_common.h"
+
+static struct dentry *debugfs_file = NULL;
+static struct ffa_ops *ops = NULL;
+static const ffa_sp_id_t spm_id = 0x8001;
+
+static void *mem_region = NULL;
+static size_t mem_size = 4096;
+struct page **pages;
+static struct sg_table sgt;
+static ffa_mem_handle_t handle;
+static struct endpoint_id sp_id;
+static struct ffa_mem_region_attributes attrs[1] = { 0 };
+
+static int get_part_id(struct endpoint_id *sp_id)
+{
+	int n;
+	struct ffa_partition_info *sp_infos = NULL;
+
+	n = ops->partition_info_get(sp_id->uuid_0, sp_id->uuid_1, sp_id->uuid_2,
+				    sp_id->uuid_3, &sp_infos);
+
+	if (n >= 1) {
+		if (n > 1) {
+			pr_warn("Multiple SP with same UUID");
+		}
+		sp_id->id = sp_infos->id;
+		kfree(sp_infos);
+		return 0;
+	}
+	else {
+		pr_err("Partition info get failed");
+		return -1;
+	}
+}
+
+static int send_sync_msg(struct msg_args *args)
+{
+	struct arm_smcccv1_2_return resp;
+
+	resp = ops->sync_msg_send(args->dst_id, args->args[0], args->args[1],
+				 args->args[2], args->args[3], args->args[4]);
+
+	if (resp.arg0) {
+		pr_err("FFA response: 0x%llx", resp.arg0);
+		return -1;
+	}
+
+	/* TODO: sort out argument widths */
+	args->args[0] = (uint32_t)resp.arg3;
+	args->args[1] = (uint32_t)resp.arg4;
+	args->args[2] = (uint32_t)resp.arg5;
+	args->args[3] = (uint32_t)resp.arg6;
+	args->args[4] = (uint32_t)resp.arg7;
+
+	return 0;
+}
+
+static int init_share(void)
+{
+	int ret;
+
+	mem_region = kzalloc(mem_size, GFP_KERNEL);
+	if (IS_ERR_OR_NULL(mem_region)) {
+		pr_err("Out of memory");
+		return -ENOMEM;
+	}
+
+	pages = kzalloc(1 * sizeof(void *), GFP_KERNEL);
+	if (IS_ERR_OR_NULL(pages)) {
+		kfree(mem_region);
+		pr_err("Out of memory");
+		return -ENOMEM;
+	}
+
+	pages[0] = virt_to_page(mem_region);
+
+	sg_alloc_table_from_pages(&sgt, pages, 1, 0, 4096, GFP_KERNEL);
+
+	attrs[0].receiver = sp_id.id;
+	attrs[0].attrs = FFA_MEM_RW;
+
+	ret = ops->mem_share(0, 0, attrs, 1, sgt.sgl, sgt.nents, &handle, true);
+	if (ret) {
+		pr_err("Mem share failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int close_share(void)
+{
+	int ret;
+
+	ret = ops->mem_reclaim(handle, FFA_KEEP_MEMORY);
+	if (ret) {
+		pr_err("Mem reclaim failed");
+	}
+
+	kfree(mem_region);
+
+	return ret;
+}
+
+static int read_buf(struct buf_descr descr)
+{
+	if (descr.length > 4096) {
+		return -ENOMEM;
+	}
+
+	if(copy_to_user(descr.buf, mem_region, descr.length)) {
+		pr_err("Copy to user failed");
+		return -1;
+	}
+
+	return 0;
+}
+
+static int write_buf(struct buf_descr descr)
+{
+	if (descr.length > 4096) {
+		return -ENOMEM;
+	}
+
+	if(copy_from_user(mem_region, descr.buf, descr.length)) {
+		pr_err("Copy from user failed");
+		return -1;
+	}
+
+	return 0;
+}
+
+static long ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
+{
+	int ret = 0;
+	void __user *uarg = (void __user *)arg;
+	struct buf_descr descr;
+	struct msg_args args;
+
+	switch (cmd) {
+	case GET_PART_ID:
+		if(copy_from_user(&sp_id, uarg, sizeof(struct endpoint_id))) {
+			pr_err("Copy from user failed");
+			return -1;
+		}
+		ret = get_part_id(&sp_id);
+		if(copy_to_user(uarg, &sp_id, sizeof(struct endpoint_id))) {
+			pr_err("Copy to user failed");
+			return -1;
+		}
+		break;
+	case SEND_SYNC_MSG:
+		if(copy_from_user(&args, uarg, sizeof(struct msg_args))) {
+			pr_err("Copy from user failed");
+			return -1;
+		}
+		ret = send_sync_msg(&args);
+		if(copy_to_user(uarg, &args, sizeof(struct msg_args))) {
+			pr_err("Copy to user failed");
+			return -1;
+		}
+		break;
+	case SHARE_INIT:
+		ret = init_share();
+		if(copy_to_user(uarg, &handle, sizeof(unsigned long))) {
+			pr_err("Copy to user failed");
+			return -1;
+		}
+		break;
+	case SHARE_DEINIT:
+		ret = close_share();
+		break;
+	case SHARE_READ:
+		if(copy_from_user(&descr, uarg, sizeof(struct buf_descr))) {
+			pr_err("Copy from user failed");
+			return -1;
+		}
+		ret = read_buf(descr);
+		break;
+	case SHARE_WRITE:
+		if(copy_from_user(&descr, uarg, sizeof(struct buf_descr))) {
+			pr_err("Copy from user failed");
+			return -1;
+		}
+		ret = write_buf(descr);
+		break;
+	default:
+		pr_warn("Unknown command: %d", cmd);
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static const struct file_operations fops = {
+	.unlocked_ioctl = ioctl,
+};
+
+static int mod_init(void)
+{
+	ops = get_ffa_ops();
+
+	if (IS_ERR_OR_NULL(ops)) {
+		pr_err("Cannot get FFA ops");
+		return -1;
+	}
+
+	debugfs_file = debugfs_create_file("buf", S_IRUSR | S_IWUSR, NULL, NULL, &fops);
+
+	if (IS_ERR_OR_NULL(debugfs_file)) {
+		pr_err("Cannot create debugfs file");
+		return -1;
+	}
+
+	return 0;
+}
+
+static void mod_exit(void)
+{
+	debugfs_remove_recursive(debugfs_file);
+}
+
+module_init(mod_init)
+module_exit(mod_exit)
+MODULE_LICENSE("GPL");
+-- 
+2.29.2
+
@@ -0,0 +1,87 @@
+From e4bc772637c8aaf4dc6fa64c6d3e3df237ee5e3d Mon Sep 17 00:00:00 2001
+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Date: Mon, 12 Apr 2021 10:44:13 +0100
+Subject: [PATCH 2/2] drivers/ffa: modify FFA ABIs with supported convention
+
+SPMC (hafnium) only supports 64-bit variant of FFA_RXTX_MAP and
+32-bit variant of FFA_MEM_SHARE.
+
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Change-Id: I2fbddb7b9bf061b529d4e1f2e93172b1aab73492
+Upstream-Status: Inappropriate [will not be submitted as its only required for ACK 5.4]
+---
+ drivers/firmware/ffa/arm_ffa.c | 8 ++++----
+ include/linux/arm_ffa.h        | 4 +++-
+ 2 files changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/firmware/ffa/arm_ffa.c b/drivers/firmware/ffa/arm_ffa.c
+index 21838f8c4632..0524deac1ce7 100644
+--- a/drivers/firmware/ffa/arm_ffa.c
+++ b/drivers/firmware/ffa/arm_ffa.c
+@@ -7,7 +7,7 @@
+  * residing on other Secure Partitions or Virtual Machines managed by any FFA
+  * compliant firmware framework.
+  *
+- * Copyright (C) 2019, 2020 Arm Ltd.
+ * Copyright (C) 2019 - 2021 Arm Ltd.
+  */
+ #define DEBUG
+ 
+@@ -171,7 +171,7 @@ static int ffa_share_init_frag(phys_addr_t buffer, u32 buffer_size,
+ 	struct arm_smcccv1_2_return smccc_return;
+ 
+ 	smccc_return =
+-		arm_ffa_smccc(FFA_MEM_SHARE_64, total_len, fragment_len, buffer,
+		arm_ffa_smccc(FFA_MEM_SHARE_32, total_len, fragment_len, buffer,
+ 		buffer_size, 0, 0, 0);
+ 
+ 	while (smccc_return.arg0 != FFA_SUCCESS_32) {
+@@ -649,7 +649,7 @@ static int ffa_rxtx_map(uintptr_t tx_page, uintptr_t rx_page)
+ {
+ 	struct arm_smcccv1_2_return map_return;
+ 
+-	map_return = arm_ffa_smccc(FFA_RXTX_MAP_32, tx_page,
+	map_return = arm_ffa_smccc(FFA_RXTX_MAP_64, tx_page,
+ 					 rx_page, 1, 0, 0, 0, 0);
+ 
+ 	if (map_return.arg0 == FFA_ERROR_32) {
+@@ -716,7 +716,7 @@ static int ffa_probe(struct platform_device *pdev)
+ 	/* Initialize VM ID. */
+ 	ret = ffa_id_get(&vm_id);
+ 	if (ret) {
+-		pr_warn("%s: failed to obtain own FFA endpoint ID\n", __func__);
+		pr_err("%s: failed to obtain own FFA endpoint ID\n", __func__);
+ 		return ret;
+ 	}
+ 
+diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h
+index d3c80b7f9e07..9a8b32e2c846 100644
+--- a/include/linux/arm_ffa.h
+++ b/include/linux/arm_ffa.h
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0 */
+ /*
+- * Copyright (C) 2019, 2020 Arm Ltd.
+ * Copyright (C) 2019 - 2021 Arm Ltd.
+  */
+ 
+ #ifndef __LINUX_ARM_FFA_H
+@@ -13,6 +13,7 @@
+ #define FFA_FEATURES_32              0x84000064
+ #define FFA_RX_RELEASE_32            0x84000065
+ #define FFA_RXTX_MAP_32              0x84000066
+#define FFA_RXTX_MAP_64              0xc4000066
+ 
+ #define FFA_PARTITION_INFO_GET_32    0x84000068
+ #define FFA_ID_GET_32                0x84000069
+@@ -25,6 +26,7 @@
+ #define FFA_MEM_OP_PAUSE_32          0x84000078
+ #define FFA_MEM_OP_RESUME_32         0x84000079
+ 
+#define FFA_MEM_SHARE_32             0x84000073
+ #define FFA_MEM_SHARE_64             0xC4000073
+ 
+ #define FFA_MEM_FRAG_RX_32			  0x8400007A
+-- 
+2.29.2
+
@@ -2,6 +2,7 @@ CONFIG_POSIX_MQUEUE=y
 CONFIG_AUDIT=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ASYMMETRIC_AARCH32=y
 CONFIG_PREEMPT=y
 CONFIG_IRQ_TIME_ACCOUNTING=y
 CONFIG_BSD_PROCESS_ACCT=y
@@ -116,7 +117,6 @@ CONFIG_ACPI_APEI_PCIEAER=y
 CONFIG_ACPI_APEI_MEMORY_FAILURE=y
 CONFIG_ACPI_APEI_EINJ=y
 CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=y
 CONFIG_ARM64_CRYPTO=y
 CONFIG_CRYPTO_SHA1_ARM64_CE=y
 CONFIG_CRYPTO_SHA2_ARM64_CE=y
@@ -0,0 +1,93 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+
+From 3563e39d66404ff2415d29c4018757a85cd0ad97 Mon Sep 17 00:00:00 2001
+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Date: Wed, 13 Jan 2021 13:49:54 +0000
+Subject: [PATCH 1/3] plat-totalcompute: add Theodul DSU support
+
+- Change CPU count from 4 to 8
+- Set heap size to 128K
+- In debug print, change EMSG to DMSG
+
+Change-Id: Ic426f5e08ac4e7ce1be37333486c75a3228e3415
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+---
+ core/arch/arm/mm/mobj_ffa.c                        |  2 +-
+ core/arch/arm/plat-totalcompute/conf.mk            |  4 +++-
+ core/arch/arm/plat-totalcompute/optee_manifest.dts |  2 +-
+ core/arch/arm/plat-totalcompute/tc0_spmc_pm.c      | 10 +++++++++-
+ 4 files changed, 14 insertions(+), 4 deletions(-)
+
+diff --git a/core/arch/arm/mm/mobj_ffa.c b/core/arch/arm/mm/mobj_ffa.c
+index 8e334f04..500404c3 100644
+--- a/core/arch/arm/mm/mobj_ffa.c
+++ b/core/arch/arm/mm/mobj_ffa.c
+@@ -381,7 +381,7 @@ struct mobj *mobj_ffa_get_by_cookie(uint64_t cookie,
+ 		if (mf)
+ 			DMSG("cookie %#"PRIx64" resurrecting", cookie);
+ 		if (!mf) {
+-			EMSG("Populating mobj from rx buffer\n");
+			DMSG("Populating mobj from rx:  %#"PRIx64"", cookie);
+ 			mf = thread_spmc_populate_mobj_from_rx(cookie);
+ 		}
+ #endif
+diff --git a/core/arch/arm/plat-totalcompute/conf.mk b/core/arch/arm/plat-totalcompute/conf.mk
+index d330eb92..c35437aa 100644
+--- a/core/arch/arm/plat-totalcompute/conf.mk
+++ b/core/arch/arm/plat-totalcompute/conf.mk
+@@ -22,7 +22,9 @@ platform-aflags-debug-info = -gdwarf-2
+ endif
+ 
+ ifeq ($(PLATFORM_FLAVOR),tc0)
+-CFG_TEE_CORE_NB_CORE = 4
+CFG_TEE_CORE_NB_CORE = 8
+
+CFG_CORE_HEAP_SIZE ?= 131072
+ 
+ ifeq ($(CFG_CORE_SEL1_SPMC),y)
+ CFG_TZDRAM_START ?= 0xfd000000
+diff --git a/core/arch/arm/plat-totalcompute/optee_manifest.dts b/core/arch/arm/plat-totalcompute/optee_manifest.dts
+index 4e60cbe1..60cb5957 100644
+--- a/core/arch/arm/plat-totalcompute/optee_manifest.dts
+++ b/core/arch/arm/plat-totalcompute/optee_manifest.dts
+@@ -18,7 +18,7 @@
+ 	ffa-version = <0x00010000>; /* 31:16 - Major, 15:0 - Minor */
+ 	uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
+ 	id = <1>;
+-	execution-ctx-count = <4>;
+	execution-ctx-count = <8>;
+ 	exception-level = <2>; /* S-EL1 */
+ 	execution-state = <0>; /* AARCH64 */
+ 	load-address = <0xfd280000>;
+diff --git a/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c b/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c
+index 8e59a8cc..3fb32823 100644
+--- a/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c
+++ b/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c
+@@ -17,7 +17,11 @@ static const uint64_t core_clus_aff_array[] = {
+ 	0x0000,		/* Cluster 0 Cpu 0 */
+ 	0x0001,		/* Cluster 0 Cpu 1 */
+ 	0x0002,		/* Cluster 0 Cpu 2 */
+-	0x0003		/* Cluster 0 Cpu 3 */
+	0x0003,		/* Cluster 0 Cpu 3 */
+	0x0004,		/* Cluster 0 Cpu 4 */
+	0x0005,		/* Cluster 0 Cpu 5 */
+	0x0006,		/* Cluster 0 Cpu 6 */
+	0x0007		/* Cluster 0 Cpu 7 */
+ };
+ 
+ void ffa_secondary_cpu_boot_req(vaddr_t secondary_ep, uint64_t cookie)
+@@ -38,6 +42,10 @@ void ffa_secondary_cpu_boot_req(vaddr_t secondary_ep, uint64_t cookie)
+ 		/* Create an mpidr from core_clus_aff_array */
+ 		a1 |= core_clus_aff_array[cnt] << aff_shift;
+ 
+		/* Ignore current cpu */
+		if (a1 == mpidr)
+			continue;
+
+ 		/* Invoke the PSCI_CPU_ON_SMC64 function */
+ 		ret = thread_smc(PSCI_CPU_ON_SMC64, a1, secondary_ep, cookie);
+ 
+-- 
+2.29.2
+
@@ -0,0 +1,47 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+
+From fd325f731da694057a2738411faa2ccbeea71778 Mon Sep 17 00:00:00 2001
+From: Olivier Deprez <olivier.deprez@arm.com>
+Date: Thu, 3 Dec 2020 22:29:37 +0100
+Subject: [PATCH 2/3] WIP OP-TEE SP declare device regions in manifest
+
+Secure Partitions must declare peripherals they access such
+that the SPMC maps IO regions in SP's Stage-2 translation
+regime. OP-TEE currently directly accesses the GIC Distributor
+and the UART0 peripheral hence declare those device regions in
+OP-TEE's manifest.
+
+Change-Id: I1fda46e5cf17153dfaf499042dceff325729d041
+Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
+---
+ .../arch/arm/plat-totalcompute/optee_manifest.dts | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/core/arch/arm/plat-totalcompute/optee_manifest.dts b/core/arch/arm/plat-totalcompute/optee_manifest.dts
+index 60cb5957..cdc28d98 100644
+--- a/core/arch/arm/plat-totalcompute/optee_manifest.dts
+++ b/core/arch/arm/plat-totalcompute/optee_manifest.dts
+@@ -30,4 +30,19 @@
+ 
+ 	/* Boot protocol */
+ 	gp-register-num = <0x0>;
+
+	device-regions {
+		compatible = "arm,ffa-manifest-device-regions";
+		uart0 {
+			base-address = <0x00000000 0x7ff70000>;
+			pages-count = <1>;
+			attributes = <0x3>; /* read-write */
+		};
+
+		gicd {
+			base-address = <0x00000000 0x30000000>;
+			pages-count = <16>;
+			attributes = <0x3>; /* read-write */
+		};
+	};
+ };
+-- 
+2.29.2
+
@@ -0,0 +1,173 @@
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+
+From 85110aaf32b6d3b19fdca301f7a07a4683825802 Mon Sep 17 00:00:00 2001
+From: Olivier Deprez <olivier.deprez@arm.com>
+Date: Thu, 3 Dec 2020 17:33:09 +0100
+Subject: [PATCH 3/3] WIP OP-TEE SP use CNTVCT in place of CNTVCT
+
+The SPMC forbids access to the physical counter and Secure Partitions
+shall rather access the virtual counter (for which virtual offset is
+set to 0). More information at [1].
+
+[1] https://lists.trustedfirmware.org/pipermail/hafnium/2020-December/000092.html
+
+Change-Id: Ifab083921fa12154cafc31bd80ce91fa8da0db82
+Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
+---
+ core/arch/arm/include/arm64.h              | 2 +-
+ core/arch/arm/include/kernel/delay.h       | 4 ++--
+ core/arch/arm/kernel/arm32_sysreg.txt      | 2 +-
+ core/arch/arm/kernel/tee_time_arm_cntpct.c | 4 ++--
+ core/kernel/tee_ta_manager.c               | 4 ++--
+ lib/libutee/arch/arm/arm32_user_sysreg.txt | 2 +-
+ lib/libutee/include/arm64_user_sysreg.h    | 2 +-
+ lib/libutils/ext/ftrace/ftrace.c           | 6 +++---
+ 8 files changed, 13 insertions(+), 13 deletions(-)
+
+diff --git a/core/arch/arm/include/arm64.h b/core/arch/arm/include/arm64.h
+index 40a6b113..46c5431f 100644
+--- a/core/arch/arm/include/arm64.h
+++ b/core/arch/arm/include/arm64.h
+@@ -322,7 +322,7 @@ DEFINE_U32_REG_READ_FUNC(sctlr_el1)
+ 
+ /* ARM Generic timer functions */
+ DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0)
+-DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0)
+DEFINE_REG_READ_FUNC_(cntvct, uint64_t, cntvct_el0)
+ DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1)
+ DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1)
+ DEFINE_REG_READ_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1)
+diff --git a/core/arch/arm/include/kernel/delay.h b/core/arch/arm/include/kernel/delay.h
+index 00510059..34629ba2 100644
+--- a/core/arch/arm/include/kernel/delay.h
+++ b/core/arch/arm/include/kernel/delay.h
+@@ -44,12 +44,12 @@ static inline uint64_t arm_cnt_us2cnt(uint32_t us)
+ 
+ static inline uint64_t timeout_init_us(uint32_t us)
+ {
+-	return read_cntpct() + arm_cnt_us2cnt(us);
+	return read_cntvct() + arm_cnt_us2cnt(us);
+ }
+ 
+ static inline bool timeout_elapsed(uint64_t expire)
+ {
+-	return read_cntpct() > expire;
+	return read_cntvct() > expire;
+ }
+ 
+ #endif
+diff --git a/core/arch/arm/kernel/arm32_sysreg.txt b/core/arch/arm/kernel/arm32_sysreg.txt
+index b69ebcb4..155773f8 100644
+--- a/core/arch/arm/kernel/arm32_sysreg.txt
+++ b/core/arch/arm/kernel/arm32_sysreg.txt
+@@ -117,7 +117,7 @@ VBAR  c12 0 c0 0 RW Vector Base Address Register
+ 
+ @ B8.2 Generic Timer registers summary
+ CNTFRQ    c14 0 c0  0 RW Counter Frequency register
+-CNTPCT    -   0 c14 - RO Physical Count register
+CNTVCT    -   1 c14 - RO Physical Count register
+ CNTKCTL   c14 0 c1  0 RW Timer PL1 Control register
+ CNTP_TVAL c14 0 c2  0 RW PL1 Physical TimerValue register
+ CNTP_CTL  c14 0 c2  1 RW PL1 Physical Timer Control register
+diff --git a/core/arch/arm/kernel/tee_time_arm_cntpct.c b/core/arch/arm/kernel/tee_time_arm_cntpct.c
+index 3c41e4c2..04e673d9 100644
+--- a/core/arch/arm/kernel/tee_time_arm_cntpct.c
+++ b/core/arch/arm/kernel/tee_time_arm_cntpct.c
+@@ -16,7 +16,7 @@
+ 
+ static TEE_Result arm_cntpct_get_sys_time(TEE_Time *time)
+ {
+-	uint64_t cntpct = read_cntpct();
+	uint64_t cntpct = read_cntvct();
+ 	uint32_t cntfrq = read_cntfrq();
+ 
+ 	time->seconds = cntpct / cntfrq;
+@@ -49,7 +49,7 @@ REGISTER_TIME_SOURCE(arm_cntpct_time_source)
+ 
+ void plat_prng_add_jitter_entropy(enum crypto_rng_src sid, unsigned int *pnum)
+ {
+-	uint64_t tsc = read_cntpct();
+	uint64_t tsc = read_cntvct();
+ 	int bytes = 0, n;
+ 	static uint8_t first, bits;
+ 	static uint16_t acc;
+diff --git a/core/kernel/tee_ta_manager.c b/core/kernel/tee_ta_manager.c
+index 46632ce7..4153fbd8 100644
+--- a/core/kernel/tee_ta_manager.c
+++ b/core/kernel/tee_ta_manager.c
+@@ -923,7 +923,7 @@ static void gprof_update_session_utime(bool suspend, struct ts_session *s,
+ static void tee_ta_update_session_utime(bool suspend)
+ {
+ 	struct ts_session *s = ts_get_current_session();
+-	uint64_t now = read_cntpct();
+	uint64_t now = read_cntvct();
+ 
+ 	gprof_update_session_utime(suspend, s, now);
+ }
+@@ -947,7 +947,7 @@ static void ftrace_update_times(bool suspend)
+ 	uint64_t now = 0;
+ 	uint32_t i = 0;
+ 
+-	now = read_cntpct();
+	now = read_cntvct();
+ 
+ 	fbuf = s->fbuf;
+ 	if (!fbuf)
+diff --git a/lib/libutee/arch/arm/arm32_user_sysreg.txt b/lib/libutee/arch/arm/arm32_user_sysreg.txt
+index 8baefd10..13e28f20 100644
+--- a/lib/libutee/arch/arm/arm32_user_sysreg.txt
+++ b/lib/libutee/arch/arm/arm32_user_sysreg.txt
+@@ -10,4 +10,4 @@
+ 
+ @ B8.2 Generic Timer registers summary
+ CNTFRQ    c14 0 c0  0 RW Counter Frequency register
+-CNTPCT    -   0 c14 - RO Physical Count register
+CNTVCT    -   1 c14 - RO Physical Count register
+diff --git a/lib/libutee/include/arm64_user_sysreg.h b/lib/libutee/include/arm64_user_sysreg.h
+index db4ee188..722a08c9 100644
+--- a/lib/libutee/include/arm64_user_sysreg.h
+++ b/lib/libutee/include/arm64_user_sysreg.h
+@@ -31,7 +31,7 @@ static inline __noprof void write_##reg(type val)		\
+ 
+ /* ARM Generic timer functions */
+ DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0)
+-DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0)
+DEFINE_REG_READ_FUNC_(cntvct, uint64_t, cntvct_el0)
+ DEFINE_REG_READ_FUNC_(tpidr_el0, uint64_t, tpidr_el0)
+ DEFINE_REG_WRITE_FUNC_(tpidr_el0, uint64_t, tpidr_el0)
+ 
+diff --git a/lib/libutils/ext/ftrace/ftrace.c b/lib/libutils/ext/ftrace/ftrace.c
+index 101aa594..637cbd19 100644
+--- a/lib/libutils/ext/ftrace/ftrace.c
+++ b/lib/libutils/ext/ftrace/ftrace.c
+@@ -165,7 +165,7 @@ void __noprof ftrace_enter(unsigned long pc, unsigned long *lr)
+ 
+ 	if (fbuf->ret_idx < FTRACE_RETFUNC_DEPTH) {
+ 		fbuf->ret_stack[fbuf->ret_idx] = *lr;
+-		fbuf->begin_time[fbuf->ret_idx] = read_cntpct();
+		fbuf->begin_time[fbuf->ret_idx] = read_cntvct();
+ 		fbuf->ret_idx++;
+ 	} else {
+ 		/*
+@@ -269,7 +269,7 @@ unsigned long __noprof ftrace_return(void)
+ 		dur_loc = curr_buf - (fbuf->ret_idx +
+ 				      (2 * sizeof(unsigned long)) + 11);
+ 		ftrace_duration(dur_loc, fbuf->begin_time[fbuf->ret_idx],
+-				read_cntpct());
+				read_cntvct());
+ 	} else {
+ 		bool full = false;
+ 
+@@ -297,7 +297,7 @@ unsigned long __noprof ftrace_return(void)
+ 			dur_loc = curr_buf - fbuf->ret_idx - 6;
+ 			ftrace_duration(dur_loc,
+ 					fbuf->begin_time[fbuf->ret_idx],
+-					read_cntpct());
+					read_cntvct());
+ 		}
+ 	}
+ 
+-- 
+2.29.2
+
@@ -0,0 +1,155 @@
+From 5d903d035e376e3b4c411e4f8947f6508ef577d9 Mon Sep 17 00:00:00 2001
+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Date: Mon, 12 Apr 2021 15:42:29 +0100
+Subject: [PATCH 1/2] core: Add FFA_SECONDARY_EP_REGISTER support
+
+Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Change-Id: I806b07b815278512abaecc7c77b29a0d395e3d35
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ core/arch/arm/include/ffa.h                   |  3 +-
+ core/arch/arm/include/kernel/boot.h           |  3 +-
+ core/arch/arm/kernel/entry_a64.S              |  3 +-
+ core/arch/arm/plat-totalcompute/tc0_spmc_pm.c | 55 ++++---------------
+ 4 files changed, 17 insertions(+), 47 deletions(-)
+
+diff --git a/core/arch/arm/include/ffa.h b/core/arch/arm/include/ffa.h
+index 6c78dacc..f5480c00 100644
+--- a/core/arch/arm/include/ffa.h
+++ b/core/arch/arm/include/ffa.h
+@@ -1,7 +1,7 @@
+ /* SPDX-License-Identifier: BSD-3-Clause */
+ /*
+  * Copyright (c) 2020, Linaro Limited
+- * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
+  */
+ 
+ #ifndef __FFA_H
+@@ -68,6 +68,7 @@
+ #define FFA_MEM_RECLAIM			U(0x84000077)
+ #define FFA_MEM_FRAG_RX			U(0x8400007A)
+ #define FFA_MEM_FRAG_TX			U(0x8400007B)
+#define FFA_SECONDARY_EP_REGISTER_64	U(0xC4000084)
+ 
+ /* Special value for traffic targeted to the Hypervisor or SPM */
+ #define FFA_TARGET_INFO_MBZ		U(0x0)
+diff --git a/core/arch/arm/include/kernel/boot.h b/core/arch/arm/include/kernel/boot.h
+index 278d514f..30eb1596 100644
+--- a/core/arch/arm/include/kernel/boot.h
+++ b/core/arch/arm/include/kernel/boot.h
+@@ -1,6 +1,7 @@
+ /* SPDX-License-Identifier: BSD-2-Clause */
+ /*
+  * Copyright (c) 2015-2020, Linaro Limited
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+  */
+ #ifndef __KERNEL_BOOT_H
+ #define __KERNEL_BOOT_H
+@@ -86,6 +87,6 @@ void *get_external_dt(void);
+ 
+ unsigned long get_aslr_seed(void *fdt);
+ 
+-void ffa_secondary_cpu_boot_req(vaddr_t secondary_ep, uint64_t cookie);
+void ffa_secondary_cpu_ep_register(vaddr_t secondary_ep);
+ 
+ #endif /* __KERNEL_BOOT_H */
+diff --git a/core/arch/arm/kernel/entry_a64.S b/core/arch/arm/kernel/entry_a64.S
+index 9ae6b32e..7d7b8aaf 100644
+--- a/core/arch/arm/kernel/entry_a64.S
+++ b/core/arch/arm/kernel/entry_a64.S
+@@ -1,6 +1,7 @@
+ /* SPDX-License-Identifier: BSD-2-Clause */
+ /*
+  * Copyright (c) 2015, Linaro Limited
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+  */
+ 
+ #include <platform_config.h>
+@@ -239,7 +240,7 @@ clear_nex_bss:
+ 	 */
+ 	ldr	x1, boot_mmu_config + CORE_MMU_CONFIG_LOAD_OFFSET
+ 	sub	x0, x0, x1
+-	bl	ffa_secondary_cpu_boot_req
+	bl	ffa_secondary_cpu_ep_register
+ 	b	thread_ffa_msg_wait
+ #else
+ 	/*
+diff --git a/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c b/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c
+index 3fb32823..f31324b9 100644
+--- a/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c
+++ b/core/arch/arm/plat-totalcompute/tc0_spmc_pm.c
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: BSD-2-Clause
+ /*
+- * Copyright (c) 2020, Arm Limited
+ * Copyright (c) 2020 - 2021, Arm Limited
+  */
+ 
+ #include <arm.h>
+@@ -8,51 +8,18 @@
+ #include <ffa.h>
+ #include <sm/psci.h>
+ 
+-/*
+- * Lookup table of core and cluster affinities on the TC0. In the absence of a
+- * DT that provides the same information, this table is used to initialise
+- * OP-TEE on secondary cores.
+- */
+-static const uint64_t core_clus_aff_array[] = {
+-	0x0000,		/* Cluster 0 Cpu 0 */
+-	0x0001,		/* Cluster 0 Cpu 1 */
+-	0x0002,		/* Cluster 0 Cpu 2 */
+-	0x0003,		/* Cluster 0 Cpu 3 */
+-	0x0004,		/* Cluster 0 Cpu 4 */
+-	0x0005,		/* Cluster 0 Cpu 5 */
+-	0x0006,		/* Cluster 0 Cpu 6 */
+-	0x0007		/* Cluster 0 Cpu 7 */
+-};
+-
+-void ffa_secondary_cpu_boot_req(vaddr_t secondary_ep, uint64_t cookie)
+void ffa_secondary_cpu_ep_register(vaddr_t secondary_ep)
+ {
+-	unsigned long mpidr = read_mpidr();
+-	unsigned int aff_shift = 0;
+-	unsigned long a1 = 0;
+-	unsigned int cnt = 0;
+-	int32_t ret = 0;
+-
+-	if (mpidr & MPIDR_MT_MASK)
+-		aff_shift = MPIDR_CLUSTER_SHIFT;
+	unsigned int ret = 0;
+ 
+-	for (cnt = 0; cnt < ARRAY_SIZE(core_clus_aff_array); cnt++) {
+-		/* Clear out the affinity fields until level 2 */
+-		a1 = mpidr & ~(unsigned long)MPIDR_AARCH32_AFF_MASK;
+	/* Invoke FFA_SECONDARY_EP_REGISTER_64 to the SPMC */
+	ret = thread_smc(FFA_SECONDARY_EP_REGISTER_64, secondary_ep, 0, 0);
+ 
+-		/* Create an mpidr from core_clus_aff_array */
+-		a1 |= core_clus_aff_array[cnt] << aff_shift;
+-
+-		/* Ignore current cpu */
+-		if (a1 == mpidr)
+-			continue;
+-
+-		/* Invoke the PSCI_CPU_ON_SMC64 function */
+-		ret = thread_smc(PSCI_CPU_ON_SMC64, a1, secondary_ep, cookie);
+-
+-		if (ret != PSCI_RET_SUCCESS)
+-			EMSG("PSCI_CPU_ON op on mpidr 0x%lx failed %"PRId32,
+-			     a1, ret);
+-		else
+-			DMSG("PSCI_CPU_ON op on mpidr 0x%lx done", a1);
+	if (ret != FFA_SUCCESS_32) {
+		EMSG("FFA_SECONDARY_EP_REGISTER_64 ret %"PRId32, ret);
+	} else {
+		DMSG("FFA_SECONDARY_EP_REGISTER_64 done");
+ 	}
+
+	return;
+ }
+-- 
+2.29.2
+
@@ -0,0 +1,79 @@
+From 6b7edfa39991079fc735a2afcba23454ae0205ed Mon Sep 17 00:00:00 2001
+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Date: Mon, 12 Apr 2021 15:29:13 +0100
+Subject: [PATCH 2/2] core: arm: modify FFA ABIs with supported convention
+
+Use FFA_MEM_RETRIEVE_REQ_32 as SPMC at SEL2 (hafnium) only supports 32-bit variant
+Fix warnings in thread_spmc.c
+
+Change-Id: Ia3d206d24f7f12dca9332b40f45934e132a37f99
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Upstream-Status: Pending [Not submitted to upstream yet]
+---
+ core/arch/arm/kernel/thread_spmc.c | 13 ++++++++-----
+ 1 file changed, 8 insertions(+), 5 deletions(-)
+
+diff --git a/core/arch/arm/kernel/thread_spmc.c b/core/arch/arm/kernel/thread_spmc.c
+index 872221d6..f8a05412 100644
+--- a/core/arch/arm/kernel/thread_spmc.c
+++ b/core/arch/arm/kernel/thread_spmc.c
+@@ -1,7 +1,7 @@
+ // SPDX-License-Identifier: BSD-2-Clause
+ /*
+  * Copyright (c) 2020, Linaro Limited.
+- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019 - 2021, Arm Limited. All rights reserved.
+  */
+ 
+ #include <assert.h>
+@@ -128,8 +128,10 @@ static unsigned int rxtx_size;
+ static unsigned int rxtx_spinlock;
+ static bool tx_buf_is_mine;
+ 
+#ifdef CFG_CORE_SEL1_SPMC
+ static SLIST_HEAD(mem_frag_state_head, mem_frag_state) frag_state_head =
+ 	SLIST_HEAD_INITIALIZER(&frag_state_head);
+#endif
+ 
+ static uint32_t swap_src_dst(uint32_t src_dst)
+ {
+@@ -387,7 +389,8 @@ static void handle_partition_info_get(struct thread_smc_args *args)
+ 
+ 	cpu_spin_lock(&rxtx_spinlock);
+ 	if (rxtx_size && tx_buf_is_mine) {
+-		struct ffa_partition_info *fpi = tx_buf;
+		struct ffa_partition_info *fpi =
+			(struct ffa_partition_info *)tx_buf;
+ 
+ 		fpi->id = my_sp_id;
+ 		fpi->execution_context = CFG_TEE_CORE_NB_CORE;
+@@ -874,7 +877,7 @@ void thread_spmc_msg_recv(struct thread_smc_args *args)
+ 	case FFA_FEATURES:
+ 		handle_features(args);
+ 		break;
+-#if CFG_CORE_SEL1_SPMC
+#ifdef CFG_CORE_SEL1_SPMC
+ #ifdef ARM64
+ 	case FFA_RXTX_MAP_64:
+ #endif
+@@ -901,7 +904,7 @@ void thread_spmc_msg_recv(struct thread_smc_args *args)
+ 		else
+ 			handle_blocking_call(args);
+ 		break;
+-#if CFG_CORE_SEL1_SPMC
+#ifdef CFG_CORE_SEL1_SPMC
+ #ifdef ARM64
+ 	case FFA_MEM_SHARE_64:
+ #endif
+@@ -1266,7 +1269,7 @@ static struct mem_transaction_descr *spmc_retrieve_req(uint64_t cookie)
+ 	uint64_t size = sizeof(*retrieve_region) +
+ 		1 * sizeof(struct mem_access_descr);
+ 	struct thread_smc_args args = {
+-		.a0 = FFA_MEM_RETRIEVE_REQ_64,
+		.a0 = FFA_MEM_RETRIEVE_REQ_32,
+ 		.a1 =   size,  	// Total Length
+ 		.a2 =	size,	// Frag Length == Total length
+ 		.a3 =	0,				// Address, Using TX -> MBZ
+-- 
+2.29.2
+
@@ -22,6 +22,11 @@ SRC_URI_append = " \
    file://0006-plat-totalcompute-Add-support-for-S-EL2-SPMC.patch \
    file://0007-plat-totalcompute-add-optee-manifest-file-and-sp-lay.patch \
    file://0008-plat-totalcompute-define-tzdram-start-address-for-S-.patch \
+    file://0009-plat-totalcompute-add-Theodul-DSU-support.patch \
+    file://0010-WIP-OP-TEE-SP-declare-device-regions-in-manifest.patch \
+    file://0011-WIP-OP-TEE-SP-use-CNTVCT-in-place-of-CNTVCT.patch \
+    file://0012-core-Add-FFA_SECONDARY_EP_REGISTER-support.patch \
+    file://0013-core-arm-modify-FFA-ABIs-with-supported-convention.patch \
    "

 COMPATIBLE_MACHINE = "tc0"
@@ -0,0 +1,14 @@
+SUMMARY = "crypto-sp secure partition"
+
+require sp.inc
+
+TS_DEPLOYMENT = "${S}/deployments/crypto/shim/"
+
+do_install () {
+    install -d -m 755 ${D}/firmware
+    install -m 0644 "${B}/crypto-sp.bin" "${D}/firmware/crypto-sp.bin"
+    install -m 0644 "${S}/deployments/crypto/shim/crypto.dts" \
+        "${D}/firmware/crypto.dts"
+}
+
+FILES_${PN} = "/firmware/crypto-sp.bin /firmware/crypto.dts"
@@ -0,0 +1,41 @@
+From 5930446f09ab1df10ca70f47a3d1bb21a010effe Mon Sep 17 00:00:00 2001
+From: Davidson K <davidson.kumaresan@arm.com>
+Date: Fri, 5 Feb 2021 12:29:37 +0530
+Subject: [PATCH 02/13] Change instruction access permissions of shared memory
+
+According to the FFA spec (Section 5.11.3 - Instruction Access Permissions Usage)
+the instruction access permission of the memory that has to be shared should be
+set as "Not specified and must be ignored" by the Lender in an invocation of
+FFA_MEM_SHARE or FFA_MEM_LEND ABIs.
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
+Change-Id: I6d84c46da8c648f93673afd7cf06a88cd4de139e
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ components/rpc/ffarpc/caller/sp/ffarpc_caller.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/components/rpc/ffarpc/caller/sp/ffarpc_caller.c b/components/rpc/ffarpc/caller/sp/ffarpc_caller.c
+index 9d98512..269cbd4 100644
+--- a/components/rpc/ffarpc/caller/sp/ffarpc_caller.c
+++ b/components/rpc/ffarpc/caller/sp/ffarpc_caller.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -211,7 +211,7 @@ int ffarpc_caller_open(struct ffarpc_caller *s, uint16_t call_ep_id)
+ 	desc.mem_region_attr.normal_memory.shareability = sp_shareability_inner_shareable;
+ 
+ 	acc_desc.data_access = sp_data_access_read_write;
+-	acc_desc.instruction_access = sp_instruction_access_not_executable;
+	acc_desc.instruction_access = sp_instruction_access_not_specified;
+ 	acc_desc.receiver_id = call_ep_id;
+ 
+ 	region.address = shared_buffer;
+-- 
+2.29.2
+
@@ -0,0 +1,39 @@
+From 6109a46678f147b6b617edf3805738f2f41b0f19 Mon Sep 17 00:00:00 2001
+From: Davidson K <davidson.kumaresan@arm.com>
+Date: Fri, 5 Feb 2021 18:27:05 +0530
+Subject: [PATCH 03/13] Set in_region_count to 0 during memory retrieve
+
+in_region_count will be used during the lend, donate and share memory
+transactions and it is not needed for the retrieve request.
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
+Change-Id: Id9f805aa7b9e16878a1114f71cd465dc97cc5dfd
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ components/rpc/ffarpc/endpoint/ffarpc_call_ep.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/components/rpc/ffarpc/endpoint/ffarpc_call_ep.c b/components/rpc/ffarpc/endpoint/ffarpc_call_ep.c
+index bb40cf3..8109345 100644
+--- a/components/rpc/ffarpc/endpoint/ffarpc_call_ep.c
+++ b/components/rpc/ffarpc/endpoint/ffarpc_call_ep.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -43,7 +43,7 @@ static void init_shmem_buf(struct ffa_call_ep *call_ep, uint16_t source_id,
+ 	struct sp_memory_descriptor desc = { };
+ 	struct sp_memory_access_descriptor acc_desc = { };
+ 	struct sp_memory_region region = { };
+-	uint32_t in_region_count = 1;
+	uint32_t in_region_count = 0;
+ 	uint32_t out_region_count = 1;
+ 	uint64_t handle = 0;
+ 	rpc_status_t rpc_status = TS_RPC_ERROR_INTERNAL;
+-- 
+2.29.2
+
@@ -0,0 +1,44 @@
+From de8c7b4ba36606067f68799f63b1a6a7de2c1a70 Mon Sep 17 00:00:00 2001
+From: Davidson K <davidson.kumaresan@arm.com>
+Date: Fri, 19 Feb 2021 11:34:26 +0530
+Subject: [PATCH 04/13] Release rx buffer after memory retrieve request
+
+After the RX buffer is consumed by the SP, the ownership has to be
+transferred to the SPM so that SPM can own it as a producer and write
+to it whenever needed.
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
+Change-Id: Ib058e1ef8a4f5286d1618394de2a74c3b7431476
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ components/rpc/ffarpc/endpoint/ffarpc_call_ep.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/components/rpc/ffarpc/endpoint/ffarpc_call_ep.c b/components/rpc/ffarpc/endpoint/ffarpc_call_ep.c
+index 8109345..f65398b 100644
+--- a/components/rpc/ffarpc/endpoint/ffarpc_call_ep.c
+++ b/components/rpc/ffarpc/endpoint/ffarpc_call_ep.c
+@@ -40,6 +40,7 @@ static void init_shmem_buf(struct ffa_call_ep *call_ep, uint16_t source_id,
+ 			   const uint32_t *req_args, uint32_t *resp_args)
+ {
+ 	sp_result sp_res = SP_RESULT_INTERNAL_ERROR;
+	ffa_result ffa_res;
+ 	struct sp_memory_descriptor desc = { };
+ 	struct sp_memory_access_descriptor acc_desc = { };
+ 	struct sp_memory_region region = { };
+@@ -68,6 +69,11 @@ static void init_shmem_buf(struct ffa_call_ep *call_ep, uint16_t source_id,
+ 		EMSG("memory retrieve error: %d", sp_res);
+ 	}
+ 
+	ffa_res = ffa_rx_release();
+	if (ffa_res != FFA_OK) {
+		EMSG("ffa_rx_release(): error %"PRId32, ffa_res);
+	}
+
+ 	set_mgmt_resp_args(resp_args, req_args[FFA_CALL_ARGS_OPCODE], rpc_status);
+ }
+ 
+-- 
+2.29.2
+
@@ -0,0 +1,364 @@
+From dfd02cb62a2dad931bb81ff7eeed0a116ccc50be Mon Sep 17 00:00:00 2001
+From: Davidson K <davidson.kumaresan@arm.com>
+Date: Tue, 9 Mar 2021 17:53:03 +0530
+Subject: [PATCH 05/13] crypto-sp: Create a new deployment with the shim
+ environment
+
+The shim environment provides support for the trusted service to
+run as secure partition at S-EL0 and a shim layer at S-EL1 with
+Hafnium as SPMC running at S-EL2.
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
+Change-Id: Id3fdf50470e4b9df7388c00e445f75b7bc8362d8
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ deployments/crypto/shim/CMakeLists.txt | 121 +++++++++++++++++++++++++
+ deployments/crypto/shim/crypto.dts     |  32 +++++++
+ deployments/crypto/shim/crypto_sp.c    | 117 ++++++++++++++++++++++++
+ deployments/crypto/shim/crypto_sp.h    |  18 ++++
+ deployments/crypto/shim/sp_def.h       |  16 ++++
+ 5 files changed, 304 insertions(+)
+ create mode 100644 deployments/crypto/shim/CMakeLists.txt
+ create mode 100644 deployments/crypto/shim/crypto.dts
+ create mode 100644 deployments/crypto/shim/crypto_sp.c
+ create mode 100644 deployments/crypto/shim/crypto_sp.h
+ create mode 100644 deployments/crypto/shim/sp_def.h
+
+diff --git a/deployments/crypto/shim/CMakeLists.txt b/deployments/crypto/shim/CMakeLists.txt
+new file mode 100644
+index 0000000..65cc215
+--- /dev/null
+++ b/deployments/crypto/shim/CMakeLists.txt
+@@ -0,0 +1,121 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+cmake_minimum_required(VERSION 3.16)
+include(../../deployment.cmake REQUIRED)
+
+#-------------------------------------------------------------------------------
+#  The CMakeLists.txt for building the crypto deployment with the shim layer
+#
+#  Builds the Crypto service provider for running in an SEL0 secure partition
+#  with the shim layer in SEL1 hosted by Hafnium in the role of SPM.
+#-------------------------------------------------------------------------------
+include(${TS_ROOT}/environments/shim/env.cmake)
+project(trusted-services LANGUAGES C ASM)
+add_executable(crypto-sp)
+target_include_directories(crypto-sp PRIVATE "${TOP_LEVEL_INCLUDE_DIRS}")
+set(SP_UUID "d9df52d5-16a2-4bb2-9aa4-d26d3b84e8c0")
+
+
+add_components(TARGET "crypto-sp"
+	BASE_DIR ${TS_ROOT}
+	COMPONENTS
+		"components/messaging/ffa/libsp"
+		"components/rpc/ffarpc/endpoint"
+		"components/rpc/ffarpc/caller/sp"
+		"components/rpc/common/caller"
+		"components/rpc/common/interface"
+		"components/rpc/dummy"
+		"components/service/common"
+		"components/service/common/serializer/protobuf"
+		"components/service/common/provider"
+		"components/service/crypto/provider/mbedcrypto"
+		"components/service/crypto/provider/mbedcrypto/entropy_source/mock"
+		"components/service/crypto/provider/serializer/protobuf"
+		"components/service/secure_storage/client/psa"
+		"protocols/rpc/common/packed-c"
+		"protocols/service/secure_storage/packed-c"
+		"protocols/service/crypto/protobuf"
+		"environments/shim"
+)
+
+target_sources(crypto-sp PRIVATE
+	crypto_sp.c
+)
+
+######################################################## Build protobuf files
+include(../../../external/nanopb/nanopb.cmake)
+target_link_libraries(crypto-sp PRIVATE nanopb::protobuf-nanopb-static)
+protobuf_generate_all(TGT "crypto-sp" NAMESPACE "protobuf" BASE_DIR "${TS_ROOT}/protocols")
+
+################################################################# mbedcrypto
+include(../../../external/mbed-crypto/mbedcrypto.cmake)
+target_link_libraries(crypto-sp PRIVATE mbedcrypto)
+
+if(CMAKE_CROSSCOMPILING)
+	target_link_libraries(crypto-sp PRIVATE stdc++ gcc m)
+endif()
+
+#################################################################
+
+target_compile_definitions(crypto-sp PRIVATE
+	ARM64=1
+	LOG_LEVEL=30
+	CRYPTO=1
+)
+
+target_include_directories(crypto-sp PRIVATE
+	${TS_ROOT}/deployments/crypto/shim
+)
+
+if(CMAKE_C_COMPILER_ID STREQUAL "GNU")
+	target_compile_options(crypto-sp PRIVATE
+		-fdiagnostics-show-option
+		-fpic
+		-gdwarf-2
+		-mstrict-align
+		-O0
+		-std=gnu99
+		-ffreestanding
+		-mgeneral-regs-only
+	)
+
+	# Options for GCC that control linking
+	target_link_options(crypto-sp PRIVATE
+		-fno-lto
+		-nostdlib
+		-pie
+		-zmax-page-size=4096
+	)
+	# Options directly for LD, these are not understood by GCC
+	target_link_options(crypto-sp PRIVATE
+		-Wl,--as-needed
+		-Wl,--sort-section=alignment
+		-T${CMAKE_BINARY_DIR}/crypto-sp.ld
+		-Wl,-Map=crypto.map
+	)
+endif()
+
+compiler_generate_stripped_elf(TARGET crypto-sp NAME "${SP_UUID}.stripped.elf" RES STRIPPED_ELF)
+compiler_generate_binary_output(TARGET crypto-sp RES STRIPPED_ELF)
+
+######################################## install
+if (CMAKE_INSTALL_PREFIX_INITIALIZED_TO_DEFAULT)
+	set(CMAKE_INSTALL_PREFIX ${CMAKE_BINARY_DIR}/install CACHE PATH "location to install build output to." FORCE)
+endif()
+#TODO: api headers
+install(TARGETS crypto-sp
+			PUBLIC_HEADER DESTINATION ${TS_ENV}/include
+			RUNTIME DESTINATION ${TS_ENV}/bin
+		)
+install(FILES ${STRIPPED_ELF} DESTINATION ${TS_ENV}/bin)
+
+get_property(_PROTO_FILES TARGET crypto-sp PROPERTY PROTOBUF_FILES)
+install(FILES ${_PROTO_FILES} DESTINATION ${TS_ENV}/lib/protobuf)
+
+
+set(EXPORT_SP_NAME "crypto")
+set(EXPORT_SP_UUID ${SP_UUID})
+diff --git a/deployments/crypto/shim/crypto.dts b/deployments/crypto/shim/crypto.dts
+new file mode 100644
+index 0000000..23bd7a2
+--- /dev/null
+++ b/deployments/crypto/shim/crypto.dts
+@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is a Partition Manifest (PM) for Crypto Trusted Service 
+ * Secure Partition (SP).
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "arm,ffa-manifest-1.0";
+
+	/* Properties */
+	description = "crypto";
+	ffa-version = <0x00010000>; /* 31:16 - Major, 15:0 - Minor */
+	uuid = <0xd9df52d5 0x4bb216a2 0x6dd2a49a 0xc0e8843b>;
+	id = <3>;
+	execution-ctx-count = <1>;
+	exception-level = <2>; /* S-EL1 */
+	execution-state = <0>; /* AARCH64 */
+	load-address = <0xfec00000>;
+	entrypoint-offset = <0x00001000>;
+	xlat-granule = <0>; /* 4KiB */
+	boot-order = <0>;
+	messaging-method = <0>; /* Direct messaging only */
+	run-time-model = <1>; /* Run to completion */
+
+	/* Boot protocol */
+	gp-register-num = <0x0>;
+};
+diff --git a/deployments/crypto/shim/crypto_sp.c b/deployments/crypto/shim/crypto_sp.c
+new file mode 100644
+index 0000000..8b3eba5
+--- /dev/null
+++ b/deployments/crypto/shim/crypto_sp.c
+@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ */
+
+#include <rpc/ffarpc/caller/sp/ffarpc_caller.h>
+#include <rpc/ffarpc/endpoint/ffarpc_call_ep.h>
+#include <rpc/dummy/dummy_caller.h>
+#include <service/secure_storage/client/psa/its/its_client.h>
+#include <service/crypto/provider/mbedcrypto/crypto_provider.h>
+#include <protocols/rpc/common/packed-c/status.h>
+#include <ffa_api.h>
+#include <sp_api.h>
+#include <sp_def.h>
+#include <sp_rxtx.h>
+#include <trace.h>
+#include <malloc.h>
+
+
+#define SP_STORAGE_UUID_BYTES \
+	{ 0x48, 0xef, 0x1e, 0xdc, 0x7a, 0xb1, 0xcf, 0x4c, \
+	  0xac, 0x8b, 0xdf, 0xcf, 0xf7, 0x71, 0x1b, 0x14, }
+
+uint16_t own_id = 0; /* !!Needs refactoring as parameter to ffarpc_caller_init */
+static const uint8_t storage_uuid[] = SP_STORAGE_UUID_BYTES;
+
+
+static int sp_init(uint16_t *own_sp_id);
+
+uint8_t sp_heap[SP_HEAP_SIZE] __aligned(16);
+
+void __noreturn sp_main(struct ffa_init_info *init_info)
+{
+	struct mbed_crypto_provider crypto_provider;
+	struct ffa_call_ep ffarpc_call_ep;
+	struct call_ep *crypto_ep;
+	struct ffarpc_caller ffarpc_caller;
+	struct dummy_caller dummy_caller;
+	struct rpc_caller *storage_caller;
+	struct ffa_direct_msg req_msg;
+	uint16_t storage_sp_ids[1];
+
+	/* Beginning of the boot phase */
+	(void) init_info;
+
+	if (sp_init(&own_id) != 0) goto fatal_error;
+
+	/* Establish RPC session with secure storage SP */
+	storage_caller = ffarpc_caller_init(&ffarpc_caller);
+
+	if (!ffarpc_caller_discover(storage_uuid, storage_sp_ids, sizeof(storage_sp_ids)/sizeof(storage_sp_ids[0])) ||
+		ffarpc_caller_open(&ffarpc_caller, storage_sp_ids[0])) {
+		/*
+		 * Failed to establish session.  To allow the crypto service
+		 * to still be initialized, albeit with no persistent storage,
+		 * initialise a dummy_caller that will safely
+		 * handle rpc requests but will report an error.
+		 */
+		storage_caller = dummy_caller_init(&dummy_caller,
+                                TS_RPC_CALL_ACCEPTED, PSA_ERROR_STORAGE_FAILURE);
+	}
+
+	/* Initialize the crypto service */
+	crypto_ep = mbed_crypto_provider_init(&crypto_provider, storage_caller);
+	ffa_call_ep_init(&ffarpc_call_ep, crypto_ep);
+
+	malloc_add_pool(sp_heap, SP_HEAP_SIZE);
+
+	/* End of boot phase */
+	ffa_msg_wait(&req_msg);
+
+	while (1) {
+		if (req_msg.function_id == FFA_MSG_SEND_DIRECT_REQ_32) {
+
+			struct ffa_direct_msg resp_msg;
+
+			ffa_call_ep_receive(&ffarpc_call_ep, &req_msg, &resp_msg);
+
+			ffa_msg_send_direct_resp(req_msg.destination_id,
+					req_msg.source_id, resp_msg.args[0], resp_msg.args[1],
+					resp_msg.args[2], resp_msg.args[3], resp_msg.args[4],
+					&req_msg);
+		} else {
+			EMSG("Received unexpected request");
+			break;
+		}
+	}
+
+fatal_error:
+	/* SP is not viable */
+	EMSG("Crypto SP error");
+	while (1) {}
+}
+
+void sp_interrupt_handler(uint32_t interrupt_id)
+{
+	(void)interrupt_id;
+}
+
+static int sp_init(uint16_t *own_sp_id)
+{
+	int status = -1;
+	sp_result sp_res;
+	static uint8_t tx_buffer[4096] __aligned(4096);
+	static uint8_t rx_buffer[4096] __aligned(4096);
+
+	sp_res = sp_rxtx_buffer_map(tx_buffer, rx_buffer, sizeof(rx_buffer));
+	if (sp_res == SP_RESULT_OK) {
+		ffa_result ffa_res;
+		ffa_res = ffa_id_get(own_sp_id);
+		if (ffa_res == FFA_OK) {
+			status = 0;
+		}
+	}
+
+	return status;
+}
+diff --git a/deployments/crypto/shim/crypto_sp.h b/deployments/crypto/shim/crypto_sp.h
+new file mode 100644
+index 0000000..e3ee0c6
+--- /dev/null
+++ b/deployments/crypto/shim/crypto_sp.h
+@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CRYPTO_SP_H
+#define CRYPTO_SP_H
+
+#define CRYPTO_SP_UUID \
+	 {0xd9df52d5, 0x16a2, 0x4bb2, \
+                {0x9a, 0xa4, 0xd2, 0x6d, 0x3b, 0x84, 0xe8, 0xc0}}
+
+#define CRYPTO_SP_UUID_BYTES \
+	{0xd9, 0xdf, 0x52, 0xd5, 0x16, 0xa2, 0x4b, 0xb2, \
+    0x9a, 0xa4, 0xd2, 0x6d, 0x3b, 0x84, 0xe8, 0xc0}
+
+#endif /* CRYPTO_SP_H */
+diff --git a/deployments/crypto/shim/sp_def.h b/deployments/crypto/shim/sp_def.h
+new file mode 100644
+index 0000000..c4eff67
+--- /dev/null
+++ b/deployments/crypto/shim/sp_def.h
+@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SP_DEF_H
+#define SP_DEF_H
+
+/* Memory reserved for stacks */
+#define SP_STACKS_SIZE			(32 * 1024)
+
+/* Memory for heap */
+#define SP_HEAP_SIZE                   (480 * 1024)
+
+#endif /* SP_DEF_H */
+-- 
+2.29.2
+
@@ -0,0 +1,268 @@
+From 47bd3e42cc7e33cd2f41c98112ed159b23149023 Mon Sep 17 00:00:00 2001
+From: Davidson K <davidson.kumaresan@arm.com>
+Date: Tue, 9 Mar 2021 18:01:05 +0530
+Subject: [PATCH 06/13] secure-storage: Create a new deployment with the shim
+ environment
+
+The shim environment provides support for the trusted service to
+run as secure partition at S-EL0 and a shim layer at S-EL1 with
+Hafnium as SPMC running at S-EL2.
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
+Change-Id: I6fd23a100b5b1ab8d80742ee2f3a81bfb7595a51
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ .../secure-storage/shim/CMakeLists.txt        | 93 +++++++++++++++++++
+ .../secure-storage/shim/secure-storage.dts    | 33 +++++++
+ deployments/secure-storage/shim/sp.c          | 74 +++++++++++++++
+ deployments/secure-storage/shim/sp_def.h      | 16 ++++
+ 4 files changed, 216 insertions(+)
+ create mode 100644 deployments/secure-storage/shim/CMakeLists.txt
+ create mode 100644 deployments/secure-storage/shim/secure-storage.dts
+ create mode 100644 deployments/secure-storage/shim/sp.c
+ create mode 100644 deployments/secure-storage/shim/sp_def.h
+
+diff --git a/deployments/secure-storage/shim/CMakeLists.txt b/deployments/secure-storage/shim/CMakeLists.txt
+new file mode 100644
+index 0000000..bcc3486
+--- /dev/null
+++ b/deployments/secure-storage/shim/CMakeLists.txt
+@@ -0,0 +1,93 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+cmake_minimum_required(VERSION 3.16)
+include(../../deployment.cmake REQUIRED)
+
+#-------------------------------------------------------------------------------
+#  The CMakeLists.txt for building the secure-storage deployment for hafnium
+#
+#  Builds the secure storage service provider for running in an SEL0 secure
+#  partition with the shim layer in SEL1 hosted by Hafnium in the role of SPM.
+#-------------------------------------------------------------------------------
+include(${TS_ROOT}/environments/shim/env.cmake)
+project(trusted-services LANGUAGES C ASM)
+add_executable(secure-storage)
+target_include_directories(secure-storage PRIVATE "${TOP_LEVEL_INCLUDE_DIRS}")
+set(SP_UUID "dc1eef48-b17a-4ccf-ac8b-dfcff7711b14")
+
+add_components(TARGET "secure-storage"
+	BASE_DIR ${TS_ROOT}
+	COMPONENTS
+		components/messaging/ffa/libsp
+		components/rpc/ffarpc/endpoint
+		components/rpc/common/interface
+		components/service/common/provider
+		components/service/secure_storage/provider/secure_flash_store
+		components/service/secure_storage/provider/secure_flash_store/flash_fs
+		components/service/secure_storage/provider/secure_flash_store/flash
+		protocols/rpc/common/packed-c
+		protocols/service/secure_storage/packed-c
+		environments/shim
+)
+
+target_sources(secure-storage PRIVATE
+	sp.c
+)
+
+target_compile_definitions(secure-storage PRIVATE
+	ARM64=1
+	LOG_LEVEL=30
+	SECURE_STORAGE=1
+)
+
+target_include_directories(secure-storage PRIVATE
+	${TS_ROOT}/deployments/secure-storage/shim
+)
+
+if(CMAKE_C_COMPILER_ID STREQUAL "GNU")
+	target_compile_options(secure-storage PRIVATE
+		-fdiagnostics-show-option
+		-fpic
+		-gdwarf-2
+		-mstrict-align
+		-O0
+		-std=gnu99
+                -ffreestanding
+                -mgeneral-regs-only
+	)
+
+	# Options for GCC that control linking
+	target_link_options(secure-storage PRIVATE
+		-fno-lto
+		-nostdlib
+		-pie
+		-zmax-page-size=4096
+	)
+	# Options directly for LD, these are not understood by GCC
+	target_link_options(secure-storage PRIVATE
+		-Wl,--as-needed
+		-Wl,--sort-section=alignment
+		-T${CMAKE_BINARY_DIR}/secure-storage.ld
+		-Wl,-Map=secure-storage.map
+	)
+endif()
+
+compiler_generate_stripped_elf(TARGET secure-storage NAME "${SP_UUID}.stripped.elf" RES STRIPPED_ELF)
+compiler_generate_binary_output(TARGET secure-storage RES STRIPPED_ELF)
+
+######################################## install
+if (CMAKE_INSTALL_PREFIX_INITIALIZED_TO_DEFAULT)
+	set(CMAKE_INSTALL_PREFIX ${CMAKE_BINARY_DIR}/install CACHE PATH "location to install build output to." FORCE)
+endif()
+install(TARGETS secure-storage
+			PUBLIC_HEADER DESTINATION ${TS_ENV}/include
+			RUNTIME DESTINATION ${TS_ENV}/bin
+		)
+install(FILES ${STRIPPED_ELF} DESTINATION ${TS_ENV}/bin)
+
+set(EXPORT_SP_NAME "secure-storage")
+set(EXPORT_SP_UUID ${SP_UUID})
+diff --git a/deployments/secure-storage/shim/secure-storage.dts b/deployments/secure-storage/shim/secure-storage.dts
+new file mode 100644
+index 0000000..5df3153
+--- /dev/null
+++ b/deployments/secure-storage/shim/secure-storage.dts
+@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is a Partition Manifest (PM) for the secure-storage
+ * Secure Partition (SP)
+ */
+
+
+/dts-v1/;
+
+/ {
+	compatible = "arm,ffa-manifest-1.0";
+
+	/* Properties */
+	description = "secure-storage";
+	ffa-version = <0x00010000>; /* 31:16 - Major, 15:0 - Minor */
+	uuid = <0xdc1eef48 0x4ccfb17a 0xcfdf8bac 0x141b71f7>;
+	id = <2>;
+	execution-ctx-count = <1>;
+	exception-level = <2>; /* S-EL1 */
+	execution-state = <0>; /* AARCH64 */
+	load-address = <0xfee00000>;
+	entrypoint-offset = <0x00001000>;
+	xlat-granule = <0>; /* 4KiB */
+	boot-order = <0>;
+	messaging-method = <0>; /* Direct messaging only */
+	run-time-model = <1>; /* Run to completion */
+
+	/* Boot protocol */
+	gp-register-num = <0x0>;
+};
+diff --git a/deployments/secure-storage/shim/sp.c b/deployments/secure-storage/shim/sp.c
+new file mode 100644
+index 0000000..2baec88
+--- /dev/null
+++ b/deployments/secure-storage/shim/sp.c
+@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <ffa_api.h>
+#include <components/rpc/common/endpoint/call_ep.h>
+#include <components/rpc/ffarpc/endpoint/ffarpc_call_ep.h>
+#include <components/service/secure_storage/provider/secure_flash_store/sfs_provider.h>
+#include <components/service/common/provider/service_provider.h>
+#include <sp_api.h>
+#include <sp_def.h>
+#include <stdlib.h>
+#include <sp_rxtx.h>
+#include <trace.h>
+#include <malloc.h>
+
+uint16_t own_id = 0;
+static uint8_t tx_buffer[4096] __aligned(4096);
+static uint8_t rx_buffer[4096] __aligned(4096);
+
+uint8_t sp_heap[SP_HEAP_SIZE] __aligned(16);
+
+void sp_main(struct ffa_init_info *init_info)
+{
+	ffa_result ffa_res;
+	sp_result sp_res;
+	struct call_ep *sfs_ep;
+	struct ffa_call_ep ffa_call_ep;
+	struct ffa_direct_msg req_msg;
+	struct sfs_provider sfs_provider;
+
+	/* Beginning of boot phase */
+	(void) init_info;
+
+	malloc_add_pool(sp_heap, SP_HEAP_SIZE);
+
+	ffa_res = ffa_id_get(&own_id);
+	if (ffa_res != FFA_OK) {
+		EMSG("id get error: %d", ffa_res);
+	}
+
+	sp_res = sp_rxtx_buffer_map(tx_buffer, rx_buffer, sizeof(rx_buffer));
+	if (sp_res != SP_RESULT_OK) {
+		EMSG("rxtx map error: %d", sp_res);
+	}
+
+	sfs_ep = sfs_provider_init(&sfs_provider);
+	ffa_call_ep_init(&ffa_call_ep, sfs_ep);
+
+	/* End of boot phase */
+	ffa_msg_wait(&req_msg);
+
+	while (1) {
+		if (req_msg.function_id == FFA_MSG_SEND_DIRECT_REQ_32) {
+			struct ffa_direct_msg resp_msg;
+			ffa_call_ep_receive(&ffa_call_ep, &req_msg, &resp_msg);
+
+			ffa_msg_send_direct_resp(req_msg.destination_id,
+					req_msg.source_id, resp_msg.args[0], resp_msg.args[1],
+					resp_msg.args[2], resp_msg.args[3], resp_msg.args[4],
+					&req_msg);
+		} else {
+			EMSG("Received unexpected request");
+			break;
+		}
+	}
+}
+
+void sp_interrupt_handler(uint32_t interrupt_id)
+{
+	(void)interrupt_id;
+}
+diff --git a/deployments/secure-storage/shim/sp_def.h b/deployments/secure-storage/shim/sp_def.h
+new file mode 100644
+index 0000000..aaf045d
+--- /dev/null
+++ b/deployments/secure-storage/shim/sp_def.h
+@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SP_DEF_H
+#define SP_DEF_H
+
+/* Memory reserved for stacks */
+#define SP_STACKS_SIZE			ULL(0xa000)
+
+/* Memory for heap */
+#define SP_HEAP_SIZE                   (300 * 1024)
+
+#endif /* SP_DEF_H */
+-- 
+2.29.2
+
@@ -0,0 +1,30 @@
+From ab7c90b324371e8c0b49fb45b833d521eca3c06d Mon Sep 17 00:00:00 2001
+From: Ben Horgan <ben.horgan@arm.com>
+Date: Thu, 8 Apr 2021 09:49:13 +0000
+Subject: [PATCH 07/13] crypto: shim: Don't link against unrequired libraries
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Change-Id: Ia1b5476d8a8d1ede0023092ddd86f079db4beb7d
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ deployments/crypto/shim/CMakeLists.txt | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/deployments/crypto/shim/CMakeLists.txt b/deployments/crypto/shim/CMakeLists.txt
+index 65cc215..b401d25 100644
+--- a/deployments/crypto/shim/CMakeLists.txt
+++ b/deployments/crypto/shim/CMakeLists.txt
+@@ -55,10 +55,6 @@ protobuf_generate_all(TGT "crypto-sp" NAMESPACE "protobuf" BASE_DIR "${TS_ROOT}/
+ include(../../../external/mbed-crypto/mbedcrypto.cmake)
+ target_link_libraries(crypto-sp PRIVATE mbedcrypto)
+ 
+-if(CMAKE_CROSSCOMPILING)
+-	target_link_libraries(crypto-sp PRIVATE stdc++ gcc m)
+-endif()
+-
+ #################################################################
+ 
+ target_compile_definitions(crypto-sp PRIVATE
+-- 
+2.29.2
+
@@ -0,0 +1,34 @@
+From 611050d667ee7e4da0bed578b1a033315bc45ff4 Mon Sep 17 00:00:00 2001
+From: Ben Horgan <ben.horgan@arm.com>
+Date: Thu, 8 Apr 2021 09:51:25 +0000
+Subject: [PATCH 08/13] libts: arm-linux: Add version to libts.so
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Change-Id: I6164b05ef49553a39252717d5622dc958ad65be4
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ deployments/libts/arm-linux/CMakeLists.txt | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/deployments/libts/arm-linux/CMakeLists.txt b/deployments/libts/arm-linux/CMakeLists.txt
+index ab512d6..a87ed48 100644
+--- a/deployments/libts/arm-linux/CMakeLists.txt
+++ b/deployments/libts/arm-linux/CMakeLists.txt
+@@ -1,5 +1,5 @@
+ #-------------------------------------------------------------------------------
+-# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+@@ -45,4 +45,5 @@ include(../libts.cmake REQUIRED)
+ #
+ #-------------------------------------------------------------------------------
+ env_set_link_options(TGT ts)
+-target_link_libraries(ts PRIVATE gcc)
+\ No newline at end of file
+set_target_properties(ts PROPERTIES VERSION 1.0.0 SOVERSION 1)
+target_link_libraries(ts PRIVATE gcc)
+-- 
+2.29.2
+
@@ -0,0 +1,81 @@
+From 6eb38e38bc50655b659494b3ca4e53dc727f6c53 Mon Sep 17 00:00:00 2001
+From: Ben Horgan <ben.horgan@arm.com>
+Date: Thu, 8 Apr 2021 10:00:37 +0000
+Subject: [PATCH 09/13] libts: Add option to use installed libts
+
+Allows using libts as dependency of trusted service tests in yocto
+Set LIBTS_USE_INSTALLED to use installed libts. The default is
+unchanged.
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Change-Id: Ied743afc80a490238361feea64a37faadacd8dda
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ deployments/ts-demo/ts-demo.cmake                 | 14 ++++++++++++--
+ deployments/ts-service-test/ts-service-test.cmake | 15 +++++++++++++--
+ 2 files changed, 25 insertions(+), 4 deletions(-)
+
+diff --git a/deployments/ts-demo/ts-demo.cmake b/deployments/ts-demo/ts-demo.cmake
+index 4c85a40..f968612 100644
+--- a/deployments/ts-demo/ts-demo.cmake
+++ b/deployments/ts-demo/ts-demo.cmake
+@@ -1,5 +1,5 @@
+ #-------------------------------------------------------------------------------
+-# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+@@ -16,7 +16,17 @@
+ #  libts will be imported for the enviroment in which service tests are
+ #  deployed.
+ #-------------------------------------------------------------------------------
+-include(${TS_ROOT}/deployments/libts/libts-import.cmake)
+
+if (NOT LIBTS_USE_INSTALLED)
+	include(${TS_ROOT}/deployments/libts/libts-import.cmake)
+else()
+	find_library(libts_lib ts REQUIRED)
+	find_path(libts_inc rpc_status.h REQUIRED)
+	add_library(libts SHARED IMPORTED)
+	set_property(TARGET libts PROPERTY INTERFACE_INCLUDE_DIRECTORIES "${libts_inc}")
+	set_property(TARGET libts PROPERTY IMPORTED_LOCATION "${libts_lib}")
+endif()
+
+ target_link_libraries(ts-demo PRIVATE libts)
+ 
+ #-------------------------------------------------------------------------------
+diff --git a/deployments/ts-service-test/ts-service-test.cmake b/deployments/ts-service-test/ts-service-test.cmake
+index 1593188..5f78b36 100644
+--- a/deployments/ts-service-test/ts-service-test.cmake
+++ b/deployments/ts-service-test/ts-service-test.cmake
+@@ -1,5 +1,5 @@
+ #-------------------------------------------------------------------------------
+-# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+@@ -16,7 +16,18 @@
+ #  libts will be imported for the enviroment in which service tests are
+ #  deployed.
+ #-------------------------------------------------------------------------------
+-include(${TS_ROOT}/deployments/libts/libts-import.cmake)
+
+if (NOT LIBTS_USE_INSTALLED)
+	include(${TS_ROOT}/deployments/libts/libts-import.cmake)
+else()
+	find_library(libts_lib ts REQUIRED)
+	message("benhor01: ${libts_lib}")
+	find_path(libts_inc rpc_status.h REQUIRED)
+	add_library(libts SHARED IMPORTED)
+	set_property(TARGET libts PROPERTY INTERFACE_INCLUDE_DIRECTORIES "${libts_inc}")
+	set_property(TARGET libts PROPERTY IMPORTED_LOCATION "${libts_lib}")
+endif()
+
+ target_link_libraries(ts-service-test PRIVATE libts)
+ 
+ #-------------------------------------------------------------------------------
+-- 
+2.29.2
+
@@ -0,0 +1,599 @@
+From 10b56be594b945c70af428116ae734660d8e11bb Mon Sep 17 00:00:00 2001
+From: Ben Horgan <ben.horgan@arm.com>
+Date: Thu, 8 Apr 2021 10:07:13 +0000
+Subject: [PATCH 10/13] external: Add option to use local source or installed
+ libs
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Change-Id: I6bd466af8518a928f402f0d6474e607092c7340a
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ external/CppUTest/CppUTest.cmake      | 138 +++++++++---------
+ external/mbed-crypto/mbedcrypto.cmake | 131 ++++++++++-------
+ external/nanopb/nanopb.cmake          | 200 +++++++++++++++-----------
+ 3 files changed, 264 insertions(+), 205 deletions(-)
+
+diff --git a/external/CppUTest/CppUTest.cmake b/external/CppUTest/CppUTest.cmake
+index c18f3e3..9b65ae5 100644
+--- a/external/CppUTest/CppUTest.cmake
+++ b/external/CppUTest/CppUTest.cmake
+@@ -1,44 +1,47 @@
+ #-------------------------------------------------------------------------------
+-# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+ #-------------------------------------------------------------------------------
+ 
+-set(CPPUTEST_URL "https://github.com/cpputest/cpputest.git" CACHE STRING "CppUTest repository URL")
+-set(CPPUTEST_REFSPEC "v3.8" CACHE STRING "CppUTest git refspec")
+-set(CPPUTEST_INSTALL_PATH ${CMAKE_CURRENT_BINARY_DIR}/CppUTest_install CACHE PATH "CppUTest installation directory")
+ 
+-include(FetchContent)
+if (NOT CPPUTEST_USE_INSTALLED)
+ 
+-# Checking git
+-find_program(GIT_COMMAND "git")
+-if (NOT GIT_COMMAND)
+-	message(FATAL_ERROR "Please install git")
+-endif()
+	set(CPPUTEST_URL "https://github.com/cpputest/cpputest.git" CACHE STRING "CppUTest repository URL")
+	set(CPPUTEST_REFSPEC "v3.8" CACHE STRING "CppUTest git refspec")
+	set(CPPUTEST_INSTALL_PATH ${CMAKE_CURRENT_BINARY_DIR}/CppUTest_install CACHE PATH "CppUTest installation directory")
+
+	include(FetchContent)
+
+	# Checking git
+	find_program(GIT_COMMAND "git")
+	if (NOT GIT_COMMAND)
+		message(FATAL_ERROR "Please install git")
+	endif()
+ 
+-# Fetching CppUTest
+-FetchContent_Declare(
+-	cpputest
+-	GIT_REPOSITORY ${CPPUTEST_URL}
+-	GIT_TAG ${CPPUTEST_REFSPEC}
+-	GIT_SHALLOW TRUE
+-	PATCH_COMMAND git stash
+	# Fetching CppUTest
+	FetchContent_Declare(
+		cpputest
+		GIT_REPOSITORY ${CPPUTEST_URL}
+		GIT_TAG ${CPPUTEST_REFSPEC}
+		GIT_SHALLOW TRUE
+		PATCH_COMMAND git stash
+ 		COMMAND git apply ${CMAKE_CURRENT_LIST_DIR}/cpputest-cmake-fix.patch
+-)
+		)
+ 
+-# FetchContent_GetProperties exports cpputest_SOURCE_DIR and cpputest_BINARY_DIR variables
+-FetchContent_GetProperties(cpputest)
+-if(NOT cpputest_POPULATED)
+-	message(STATUS "Fetching CppUTest")
+-	FetchContent_Populate(cpputest)
+-endif()
+	# FetchContent_GetProperties exports cpputest_SOURCE_DIR and cpputest_BINARY_DIR variables
+	FetchContent_GetProperties(cpputest)
+	if(NOT cpputest_POPULATED)
+		message(STATUS "Fetching CppUTest")
+		FetchContent_Populate(cpputest)
+	endif()
+ 
+-# Build and install CppUTest configuration time. This makes us able to use CppUTest as a CMake package.
+-# Memory leak detection is turned off to avoid conflict with memcheck.
+-if(NOT CMAKE_CROSSCOMPILING)
+-	execute_process(COMMAND
+-		${CMAKE_COMMAND}
+	# Build and install CppUTest configuration time. This makes us able to use CppUTest as a CMake package.
+	# Memory leak detection is turned off to avoid conflict with memcheck.
+	if(NOT CMAKE_CROSSCOMPILING)
+		execute_process(COMMAND
+			${CMAKE_COMMAND}
+ 			-DMEMORY_LEAK_DETECTION=OFF
+ 			-DLONGLONG=ON
+ 			-DC++11=ON
+@@ -48,47 +51,54 @@ if(NOT CMAKE_CROSSCOMPILING)
+ 			${cpputest_SOURCE_DIR}
+ 		WORKING_DIRECTORY
+ 			${cpputest_BINARY_DIR}
+-			RESULT_VARIABLE
+-				_exec_error
+-	)
+-else()
+		RESULT_VARIABLE
+			_exec_error
+			)
+	else()
+		execute_process(COMMAND
+			${CMAKE_COMMAND}
+			-DMEMORY_LEAK_DETECTION=OFF
+			-DLONGLONG=ON
+			-DC++11=ON
+			-DCMAKE_INSTALL_PREFIX=${CPPUTEST_INSTALL_PATH}
+			-DCMAKE_TOOLCHAIN_FILE=${TS_EXTERNAL_LIB_TOOLCHAIN_FILE}
+			-DTESTS=OFF
+			-DEXTENSIONS=OFF
+			-DHAVE_FORK=OFF
+			-DCPP_PLATFORM=armcc
+			-DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY
+			-G${CMAKE_GENERATOR}
+			${cpputest_SOURCE_DIR}
+		WORKING_DIRECTORY
+			${cpputest_BINARY_DIR}
+		RESULT_VARIABLE
+			_exec_error
+			)
+	endif()
+	if (NOT _exec_error EQUAL 0)
+		message(FATAL_ERROR "Configuriong CppUTest build failed.")
+	endif()
+ 	execute_process(COMMAND
+-	${CMAKE_COMMAND}
+-		-DMEMORY_LEAK_DETECTION=OFF
+-		-DLONGLONG=ON
+-		-DC++11=ON
+-		-DCMAKE_INSTALL_PREFIX=${CPPUTEST_INSTALL_PATH}
+-		-DCMAKE_TOOLCHAIN_FILE=${TS_EXTERNAL_LIB_TOOLCHAIN_FILE}
+-		-DTESTS=OFF
+-		-DEXTENSIONS=OFF
+-		-DHAVE_FORK=OFF
+-		-DCPP_PLATFORM=armcc
+-		-DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY
+-		-G${CMAKE_GENERATOR}
+-		${cpputest_SOURCE_DIR}
+-	WORKING_DIRECTORY
+-		${cpputest_BINARY_DIR}
+-	RESULT_VARIABLE
+-		_exec_error
+-	)
+-endif()
+-if (NOT _exec_error EQUAL 0)
+-	message(FATAL_ERROR "Configuriong CppUTest build failed.")
+-endif()
+-execute_process(COMMAND
+-	${CMAKE_COMMAND}
+		${CMAKE_COMMAND}
+ 		--build ${cpputest_BINARY_DIR}
+ 		-- install -j8
+-	RESULT_VARIABLE
+		RESULT_VARIABLE
+ 		_exec_error
+-	)
+-if (NOT _exec_error EQUAL 0)
+-	message(FATAL_ERROR "Building CppUTest failed.")
+		)
+	if (NOT _exec_error EQUAL 0)
+		message(FATAL_ERROR "Building CppUTest failed.")
+	endif()
+
+	# Finding CppUTest package. CMake will check [package name]_DIR variable.
+	set(CppUTest_DIR ${CPPUTEST_INSTALL_PATH}/lib/CppUTest/cmake CACHE PATH "CppUTest package location" FORCE)
+	find_package(CppUTest CONFIG REQUIRED NO_DEFAULT_PATH PATHS ${CppUTest_DIR})
+
+else()
+
+	find_package(CppUTest REQUIRED)
+
+ endif()
+ 
+-# Finding CppUTest package. CMake will check [package name]_DIR variable.
+-set(CppUTest_DIR ${CPPUTEST_INSTALL_PATH}/lib/CppUTest/cmake CACHE PATH "CppUTest package location" FORCE)
+-find_package(CppUTest CONFIG REQUIRED NO_DEFAULT_PATH PATHS ${CppUTest_DIR})
+ # CppUTest package files do not set include path properties on the targets.
+ # Fix this here.
+ foreach(_cpputest_target IN LISTS CppUTest_LIBRARIES)
+diff --git a/external/mbed-crypto/mbedcrypto.cmake b/external/mbed-crypto/mbedcrypto.cmake
+index bf00588..f681e74 100644
+--- a/external/mbed-crypto/mbedcrypto.cmake
+++ b/external/mbed-crypto/mbedcrypto.cmake
+@@ -1,46 +1,59 @@
+ #-------------------------------------------------------------------------------
+-# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+ #-------------------------------------------------------------------------------
+ 
+-set(MBEDCRYPTO_URL "https://github.com/ARMmbed/mbed-crypto.git" CACHE STRING "mbedcrypto repository URL")
+-set(MBEDCRYPTO_REFSPEC "mbedcrypto-3.1.0" CACHE STRING "mbedcrypto git refspec")
+-set(MBEDCRYPTO_INSTALL_PATH "${CMAKE_CURRENT_BINARY_DIR}/mbedcrypto_install" CACHE PATH "mbedcrypto installation directory")
+-set(MBEDCRYPTO_PACKAGE_PATH "${MBEDCRYPTO_INSTALL_PATH}/lib/mbedcrypto/cmake" CACHE PATH "mbedcrypto CMake package directory")
+if(NOT MBEDCRYPTO_USE_INSTALLED)
+ 
+-include(FetchContent)
+	include(FetchContent)
+ 
+-# Checking git
+-find_program(GIT_COMMAND "git")
+-if (NOT GIT_COMMAND)
+-	message(FATAL_ERROR "Please install git")
+-endif()
+	if (NOT MBEDCRYPTO_SOURCE_PATH)
+ 
+-# Fetching mbedcrypto
+-FetchContent_Declare(
+-	mbedcrypto
+-	GIT_REPOSITORY ${MBEDCRYPTO_URL}
+-	GIT_TAG ${MBEDCRYPTO_REFSPEC}
+-	GIT_SHALLOW TRUE
+-)
+-
+-# FetchContent_GetProperties exports mbedcrypto_SOURCE_DIR and mbedcrypto_BINARY_DIR variables
+-FetchContent_GetProperties(mbedcrypto)
+-if(NOT mbedcrypto_POPULATED)
+-	message(STATUS "Fetching mbedcrypto")
+-	FetchContent_Populate(mbedcrypto)
+-endif()
+		set(MBEDCRYPTO_URL "https://github.com/ARMmbed/mbed-crypto.git" CACHE STRING "mbedcrypto repository URL")
+		set(MBEDCRYPTO_REFSPEC "mbedcrypto-3.1.0" CACHE STRING "mbedcrypto git refspec")
+ 
+-# Convert the include path list to a string. Needed to make parameter passing to
+-# mbedcrypto build work fine.
+-string(REPLACE ";" "\\;" MBEDCRYPTO_EXTRA_INCLUDES "${MBEDCRYPTO_EXTRA_INCLUDES}")
+		# Checking git
+		find_program(GIT_COMMAND "git")
+		if (NOT GIT_COMMAND)
+			message(FATAL_ERROR "Please install git")
+		endif()
+ 
+-#Configure the library
+-if(NOT CMAKE_CROSSCOMPILING)
+-	execute_process(COMMAND
+-		${CMAKE_COMMAND}
+		# Fetching mbedcrypto
+		FetchContent_Declare(
+			mbedcrypto
+			GIT_REPOSITORY ${MBEDCRYPTO_URL}
+			GIT_TAG ${MBEDCRYPTO_REFSPEC}
+			GIT_SHALLOW TRUE
+			)
+
+	else()
+
+		FetchContent_Declare(
+			mbedcrypto
+			SOURCE_DIR ${MBEDCRYPTO_SOURCE_PATH}
+			)
+
+	endif()
+
+	# FetchContent_GetProperties exports mbedcrypto_SOURCE_DIR and mbedcrypto_BINARY_DIR variables
+	FetchContent_GetProperties(mbedcrypto)
+
+	if(NOT mbedcrypto_POPULATED)
+		message(STATUS "Fetching mbedcrypto")
+		FetchContent_Populate(mbedcrypto)
+	endif()
+
+	set(MBEDCRYPTO_INSTALL_PATH "${CMAKE_CURRENT_BINARY_DIR}/mbedcrypto_install" CACHE PATH "mbedcrypto installation directory")
+	set(MBEDCRYPTO_PACKAGE_PATH "${MBEDCRYPTO_INSTALL_PATH}/lib/mbedcrypto/cmake" CACHE PATH "mbedcrypto CMake package directory")
+	# Convert the include path list to a string. Needed to make parameter passing to
+	# mbedcrypto build work fine.
+	string(REPLACE ";" "\\;" MBEDCRYPTO_EXTRA_INCLUDES "${MBEDCRYPTO_EXTRA_INCLUDES}")
+	#Configure the library
+	if(NOT CMAKE_CROSSCOMPILING)
+		execute_process(COMMAND
+			${CMAKE_COMMAND}
+ 			-DENABLE_PROGRAMS=OFF
+ 			-DENABLE_TESTING=OFF
+ 			-DCMAKE_INSTALL_PREFIX=${MBEDCRYPTO_INSTALL_PATH}
+@@ -49,12 +62,12 @@ if(NOT CMAKE_CROSSCOMPILING)
+ 			-Dthirdparty_inc=${MBEDCRYPTO_EXTRA_INCLUDES}
+ 			-GUnix\ Makefiles
+ 			${mbedcrypto_SOURCE_DIR}
+-		WORKING_DIRECTORY
+			WORKING_DIRECTORY
+ 			${mbedcrypto_BINARY_DIR}
+-		)
+-else()
+-	execute_process(COMMAND
+-		${CMAKE_COMMAND}
+			)
+	else()
+		execute_process(COMMAND
+			${CMAKE_COMMAND}
+ 			-DENABLE_PROGRAMS=OFF
+ 			-DENABLE_TESTING=OFF
+ 			-DCMAKE_INSTALL_PREFIX=${MBEDCRYPTO_INSTALL_PATH}
+@@ -64,30 +77,38 @@ else()
+ 			-Dthirdparty_inc=${MBEDCRYPTO_EXTRA_INCLUDES}
+ 			-GUnix\ Makefiles
+ 			${mbedcrypto_SOURCE_DIR}
+-		WORKING_DIRECTORY
+			WORKING_DIRECTORY
+ 			${mbedcrypto_BINARY_DIR}
+-		RESULT_VARIABLE _exec_error
+-	)
+			RESULT_VARIABLE _exec_error
+			)
+ 
+-	if (_exec_error)
+-		message(FATAL_ERROR "Configuration step of mbedcrypto failed with ${_exec_error}.")
+		if (_exec_error)
+			message(FATAL_ERROR "Configuration step of mbedcrypto failed with ${_exec_error}.")
+		endif()
+ 	endif()
+-endif()
+ 
+-#TODO: add dependnecy to generated project on this file!
+-#TODO: add custom target to rebuild mbedcrypto
+	#TODO: add dependnecy to generated project on this file!
+	#TODO: add custom target to rebuild mbedcrypto
+ 
+-#Build the library
+-execute_process(COMMAND
+	#Build the library
+	execute_process(COMMAND
+ 		${CMAKE_COMMAND} --build ${mbedcrypto_BINARY_DIR} -- install -j8
+ 		RESULT_VARIABLE _exec_error
+-	)
+-if (_exec_error)
+-	message(FATAL_ERROR "Build step of mbedcrypto failed with ${_exec_error}.")
+-endif()
+		)
+	if (_exec_error)
+		message(FATAL_ERROR "Build step of mbedcrypto failed with ${_exec_error}.")
+	endif()
+
+	add_library(mbedcrypto STATIC IMPORTED)
+	set_property(TARGET mbedcrypto PROPERTY IMPORTED_LOCATION "${MBEDCRYPTO_INSTALL_PATH}/lib/${CMAKE_STATIC_LIBRARY_PREFIX}mbedcrypto${CMAKE_STATIC_LIBRARY_SUFFIX}")
+	set_property(TARGET mbedcrypto PROPERTY INTERFACE_INCLUDE_DIRECTORIES "${MBEDCRYPTO_INSTALL_PATH}/include")
+ 
+-#Create an imported target to have clean abstraction in the build-system.
+-add_library(mbedcrypto STATIC IMPORTED)
+-set_property(TARGET mbedcrypto PROPERTY IMPORTED_LOCATION "${MBEDCRYPTO_INSTALL_PATH}/lib/${CMAKE_STATIC_LIBRARY_PREFIX}mbedcrypto${CMAKE_STATIC_LIBRARY_SUFFIX}")
+-set_property(TARGET mbedcrypto PROPERTY INTERFACE_INCLUDE_DIRECTORIES "${MBEDCRYPTO_INSTALL_PATH}/include")
+else()
+
+	find_library(mbedcrypto_lib mbedcrypto REQUIRED)
+	find_path(mbedcrypto_inc mbedtls/version.h REQUIRED)
+	add_library(mbedcrypto STATIC IMPORTED)
+	set_property(TARGET mbedcrypto PROPERTY IMPORTED_LOCATION "${mbedcrypto_lib}")
+	set_property(TARGET mbedcrypto PROPERTY INTERFACE_INCLUDE_DIRECTORIES "${mbedcrypto_inc}")
+ 
+endif()
+diff --git a/external/nanopb/nanopb.cmake b/external/nanopb/nanopb.cmake
+index eda00e4..f6ac047 100644
+--- a/external/nanopb/nanopb.cmake
+++ b/external/nanopb/nanopb.cmake
+@@ -1,12 +1,12 @@
+ #-------------------------------------------------------------------------------
+-# Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+ #
+ # SPDX-License-Identifier: BSD-3-Clause
+ #
+ #-------------------------------------------------------------------------------
+ 
+ #[===[.rst:
+-NonoPB integration for cmake
+NanoPB integration for cmake
+ ----------------------------
+ 
+ This module will:
+@@ -26,107 +26,135 @@ running this module.
+ 
+ #### Get the dependency
+ 
+-set(NANOPB_URL "https://github.com/nanopb/nanopb.git" CACHE STRING "nanopb repository URL")
+-set(NANOPB_REFSPEC "nanopb-0.4.2" CACHE STRING "nanopb git refspec")
+-set(NANOPB_INSTALL_PATH "${CMAKE_CURRENT_BINARY_DIR}/nanopb_install" CACHE PATH "nanopb installation directory")
+-set(NANOPB_PACKAGE_PATH "${NANOPB_INSTALL_PATH}/libnanopb/cmake" CACHE PATH "nanopb CMake package directory")
+if (NOT NANOPB_USE_INSTALLED)
+ 
+-include(FetchContent)
+	include(FetchContent)
+ 
+-# Checking git
+-find_program(GIT_COMMAND "git")
+-if (NOT GIT_COMMAND)
+-	message(FATAL_ERROR "Please install git")
+-endif()
+	set(NANOPB_INSTALL_PATH "${CMAKE_CURRENT_BINARY_DIR}/nanopb_install" CACHE PATH "nanopb installation directory")
+	set(NANOPB_PACKAGE_PATH "${NANOPB_INSTALL_PATH}/libnanopb/cmake" CACHE PATH "nanopb CMake package directory")
+ 
+-# Fetching nanopb
+-FetchContent_Declare(
+-	nanopb
+-	GIT_REPOSITORY ${NANOPB_URL}
+-	GIT_TAG ${NANOPB_REFSPEC}
+-	GIT_SHALLOW TRUE
+-	#See the .patch file for details on why it is needed.
+-	PATCH_COMMAND git stash
+-		COMMAND git apply ${CMAKE_CURRENT_LIST_DIR}/fix-pyhon-name.patch
+-)
+-
+-# FetchContent_GetProperties exports nanopb_SOURCE_DIR and nanopb_BINARY_DIR variables
+-FetchContent_GetProperties(nanopb)
+-if(NOT nanopb_POPULATED)
+-	message(STATUS "Fetching nanopb")
+-	FetchContent_Populate(nanopb)
+-endif()
+	if (NOT NANOPB_SOURCE_PATH)
+ 
+-#### Build the runtime and the generator.
+-if( NOT CMAKE_CROSSCOMPILING)
+-	execute_process(COMMAND
+-		${CMAKE_COMMAND}
+-				-DBUILD_SHARED_LIBS=Off
+-				-DBUILD_STATIC_LIBS=On
+-				-Dnanopb_BUILD_RUNTIME=On
+-				-Dnanopb_BUILD_GENERATOR=On
+-				-Dnanopb_PROTOC_PATH=${nanopb_SOURCE_DIR}/generator/protoc
+-				-Dnanopb_MSVC_STATIC_RUNTIME=Off
+-				-DCMAKE_INSTALL_PREFIX=${NANOPB_INSTALL_PATH}
+-				-DCMAKE_TOOLCHAIN_FILE=${TS_EXTERNAL_LIB_TOOLCHAIN_FILE}
+-				-GUnix\ Makefiles
+-				${nanopb_SOURCE_DIR}
+-			WORKING_DIRECTORY
+-				${nanopb_BINARY_DIR}
+-			RESULT_VARIABLE _exec_error
+-	)
+-else()
+-	execute_process(COMMAND
+-		${CMAKE_COMMAND}
+-				-DBUILD_SHARED_LIBS=Off
+-				-DBUILD_STATIC_LIBS=On
+-				-Dnanopb_BUILD_RUNTIME=On
+-				-Dnanopb_BUILD_GENERATOR=On
+-				-Dnanopb_PROTOC_PATH=${nanopb_SOURCE_DIR}/generator/protoc
+-				-Dnanopb_MSVC_STATIC_RUNTIME=Off
+-				-DCMAKE_INSTALL_PREFIX=${NANOPB_INSTALL_PATH}
+-				-DCMAKE_TOOLCHAIN_FILE=${TS_EXTERNAL_LIB_TOOLCHAIN_FILE}
+-				-DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY
+-				-GUnix\ Makefiles
+-				${nanopb_SOURCE_DIR}
+-			WORKING_DIRECTORY
+-				${nanopb_BINARY_DIR}
+-			RESULT_VARIABLE _exec_error
+-	)
+-endif()
+		set(NANOPB_URL "https://github.com/nanopb/nanopb.git" CACHE STRING "nanopb repository URL")
+		set(NANOPB_REFSPEC "nanopb-0.4.2" CACHE STRING "nanopb git refspec")
+ 
+-if (_exec_error)
+-	message(FATAL_ERROR "Configuration step of nanopb runtime failed with ${_exec_error}.")
+-endif()
+		# Checking git
+		find_program(GIT_COMMAND "git")
+		if (NOT GIT_COMMAND)
+			message(FATAL_ERROR "Please install git")
+		endif()
+
+		# Fetching nanopb
+		FetchContent_Declare(
+			nanopb
+			GIT_REPOSITORY ${NANOPB_URL}
+			GIT_TAG ${NANOPB_REFSPEC}
+			GIT_SHALLOW TRUE
+			#See the .patch file for details on why it is needed.
+			PATCH_COMMAND git stash
+			COMMAND git apply ${CMAKE_CURRENT_LIST_DIR}/fix-pyhon-name.patch
+			)
+
+	else()
+ 
+-execute_process(COMMAND
+		FetchContent_Declare(
+			nanopb
+			SOURCE_DIR ${NANOPB_SOURCE_PATH}
+			)
+
+	endif()
+
+	# FetchContent_GetProperties exports nanopb_SOURCE_DIR and nanopb_BINARY_DIR variables
+	FetchContent_GetProperties(nanopb)
+	if(NOT nanopb_POPULATED)
+		message(STATUS "Fetching nanopb")
+		FetchContent_Populate(nanopb)
+	endif()
+
+	#### Build the runtime and the generator.
+	if( NOT CMAKE_CROSSCOMPILING)
+		execute_process(COMMAND
+			${CMAKE_COMMAND}
+			-DBUILD_SHARED_LIBS=Off
+			-DBUILD_STATIC_LIBS=On
+			-Dnanopb_BUILD_RUNTIME=On
+			-Dnanopb_BUILD_GENERATOR=On
+			-Dnanopb_PROTOC_PATH=${nanopb_SOURCE_DIR}/generator/protoc
+			-Dnanopb_MSVC_STATIC_RUNTIME=Off
+			-DCMAKE_INSTALL_PREFIX=${NANOPB_INSTALL_PATH}
+			-DCMAKE_TOOLCHAIN_FILE=${TS_EXTERNAL_LIB_TOOLCHAIN_FILE}
+			-GUnix\ Makefiles
+			${nanopb_SOURCE_DIR}
+		WORKING_DIRECTORY
+			${nanopb_BINARY_DIR}
+		RESULT_VARIABLE _exec_error
+			)
+	else()
+		execute_process(COMMAND
+			${CMAKE_COMMAND}
+			-DBUILD_SHARED_LIBS=Off
+			-DBUILD_STATIC_LIBS=On
+			-Dnanopb_BUILD_RUNTIME=On
+			-Dnanopb_BUILD_GENERATOR=On
+			-Dnanopb_PROTOC_PATH=${nanopb_SOURCE_DIR}/generator/protoc
+			-Dnanopb_MSVC_STATIC_RUNTIME=Off
+			-DCMAKE_INSTALL_PREFIX=${NANOPB_INSTALL_PATH}
+			-DCMAKE_TOOLCHAIN_FILE=${TS_EXTERNAL_LIB_TOOLCHAIN_FILE}
+			-DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY
+			-GUnix\ Makefiles
+			${nanopb_SOURCE_DIR}
+		WORKING_DIRECTORY
+			${nanopb_BINARY_DIR}
+		RESULT_VARIABLE _exec_error
+			)
+	endif()
+
+	if (_exec_error)
+		message(FATAL_ERROR "Configuration step of nanopb runtime failed with ${_exec_error}.")
+	endif()
+
+	execute_process(COMMAND
+ 		${CMAKE_COMMAND} --build ${nanopb_BINARY_DIR} -- install -j8
+ 		RESULT_VARIABLE _exec_error
+-	)
+-if (_exec_error)
+-	message(FATAL_ERROR "Build step of nanopb runtime failed with ${_exec_error}.")
+-endif()
+		)
+	if (_exec_error)
+		message(FATAL_ERROR "Build step of nanopb runtime failed with ${_exec_error}.")
+	endif()
+ 
+-#### Include Nanopb runtime in the build.
+-find_package(Nanopb
+-			PATHS "${NANOPB_INSTALL_PATH}"
+-			NO_DEFAULT_PATH
+	#### Include Nanopb runtime in the build.
+	find_package(Nanopb
+		PATHS "${NANOPB_INSTALL_PATH}"
+		NO_DEFAULT_PATH
+ 		)
+ 
+-#### Build access to the protobuf compiler
+-#TODO: verify protoc dependencies: python3-protobuf
+-find_package(Python3 COMPONENTS Interpreter)
+else()
+
+	#### Build access to the protobuf compiler
+	#TODO: verify protoc dependencies: python3-protobuf
+	find_package(Nanopb REQUIRED)
+
+endif()
+ 
+find_package(Python3 COMPONENTS Interpreter)
+ if (NOT Python3_Interpreter_FOUND)
+ 	message(FATAL_ERROR "Failed to find python3 interpreter.")
+ endif()
+ 
+-find_file(NANOPB_GENERATOR_PATH
+-			NAMES nanopb_generator.py
+-			PATHS ${nanopb_SOURCE_DIR}/generator
+-			DOC "nanopb protobuf compiler"
+-			NO_DEFAULT_PATH
+if (NOT NANOPB_USE_INSTALLED)
+	find_file(NANOPB_GENERATOR_PATH
+		NAMES nanopb_generator.py
+		PATHS "${nanopb_SOURCE_DIR}/generator"
+		DOC "nanopb protobuf compiler"
+		REQUIRED
+		NO_DEFAULT_PATH
+		)
+else()
+	find_file(NANOPB_GENERATOR_PATH
+		NAMES nanopb_generator.py
+		DOC "nanopb protobuf compiler"
+		REQUIRED
+ 		)
+endif()
+ 
+ if (NOT NANOPB_GENERATOR_PATH)
+ 	message(FATAL_ERROR "Nanopb generator was not found!")
+-- 
+2.29.2
+
@@ -0,0 +1,49 @@
+From 0075dc6cf30df6a2d91ab3870dabed4ac220a468 Mon Sep 17 00:00:00 2001
+From: Ben Horgan <ben.horgan@arm.com>
+Date: Mon, 22 Mar 2021 11:00:40 +0000
+Subject: [PATCH 11/13] aarch64: Allow the stack to be further than 1MB from
+ where it is set up
+
+Trusted-services crypto  was previously building with the linaro 7.5
+ aarch64-linux-gnu but not with arm 10.2 aarch64-none-linux-gnu.
+Build error was:
+aarch64/sp_entrypoint.S:22:(.text.sp_entrypoint+0x0):
+ relocation truncated to fit: R_AARCH64_ADR_PREL_LO21 against `.bss.stacks'
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+Change-Id: Ia422722c986bce50543f026ccbad728e6938f2b0
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ environments/shim/aarch64/sp_entrypoint.S | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/environments/shim/aarch64/sp_entrypoint.S b/environments/shim/aarch64/sp_entrypoint.S
+index 8ef330b..ee7f84d 100644
+--- a/environments/shim/aarch64/sp_entrypoint.S
+++ b/environments/shim/aarch64/sp_entrypoint.S
+@@ -12,17 +12,18 @@
+ 	.globl	sp_entrypoint
+ 
+ .section .bss.stacks
+-	.balign CACHE_WRITEBACK_GRANULE
+	.balign	CACHE_WRITEBACK_GRANULE
+ 	.fill	SP_STACKS_SIZE
+ stacks_end:
+ 
+ func sp_entrypoint
+ 
+ 	/* Setup the stack pointer. */
+-	adr	x0, stacks_end
+	adrp	x0, stacks_end
+	add	x0, x0, :lo12:stacks_end
+ 	mov	sp, x0
+ 	/* Mask FIQs */
+-	msr     daifset, #DAIF_FIQ_BIT
+	msr	daifset, #DAIF_FIQ_BIT
+ 	isb
+ 
+ 	/* And jump to the C entrypoint. */
+-- 
+2.29.2
+
@@ -0,0 +1,93 @@
+From 78ddf721076d2baca395f418973d5eb5d19ec4ab Mon Sep 17 00:00:00 2001
+From: Ben Horgan <ben.horgan@arm.com>
+Date: Tue, 30 Mar 2021 13:15:54 +0000
+Subject: [PATCH 12/13] libc: Add missing libc function declarations
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Change-Id: I00e54db41b3226cc60a89bf4a81edea0a6fbb2a5
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ environments/shim/include/lib/libc/assert.h |  4 +---
+ environments/shim/include/lib/libc/memory.h |  7 +++++++
+ environments/shim/include/lib/libc/stdint.h | 18 +++++++++---------
+ environments/shim/include/lib/libc/stdlib.h |  2 ++
+ 4 files changed, 19 insertions(+), 12 deletions(-)
+ create mode 100644 environments/shim/include/lib/libc/memory.h
+
+diff --git a/environments/shim/include/lib/libc/assert.h b/environments/shim/include/lib/libc/assert.h
+index ec28c26..e32259b 100644
+--- a/environments/shim/include/lib/libc/assert.h
+++ b/environments/shim/include/lib/libc/assert.h
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018 - 2021, ARM Limited and Contributors. All rights reserved.
+  *
+  * SPDX-License-Identifier: BSD-3-Clause
+  */
+@@ -9,8 +9,6 @@
+ 
+ #include <cdefs.h>
+ 
+-#include <common/debug.h>
+-
+ #if ENABLE_ASSERTIONS
+ #define assert(e)	((e) ? (void)0 : __assert(__FILE__, __LINE__, #e))
+ #else
+diff --git a/environments/shim/include/lib/libc/memory.h b/environments/shim/include/lib/libc/memory.h
+new file mode 100644
+index 0000000..823bf26
+--- /dev/null
+++ b/environments/shim/include/lib/libc/memory.h
+@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+diff --git a/environments/shim/include/lib/libc/stdint.h b/environments/shim/include/lib/libc/stdint.h
+index d5dbfc4..b636299 100644
+--- a/environments/shim/include/lib/libc/stdint.h
+++ b/environments/shim/include/lib/libc/stdint.h
+@@ -107,15 +107,15 @@ typedef unsigned short uint16_least_t;
+ typedef unsigned int uint32_least_t;
+ typedef unsigned long long uint64_least_t;
+ 
+-typedef int int8_fast_t;
+-typedef int int16_fast_t;
+-typedef int int32_fast_t;
+-typedef long long int64_fast_t;
+-
+-typedef unsigned int uint8_fast_t;
+-typedef unsigned int uint16_fast_t;
+-typedef unsigned int uint32_fast_t;
+-typedef unsigned long long uint64_fast_t;
+typedef int int_fast8_t;
+typedef int int_fast16_t;
+typedef int int_fast32_t;
+typedef long long int_fast64_t;
+
+typedef unsigned int uint_fast8_t;
+typedef unsigned int uint_fast16_t;
+typedef unsigned int uint_fast32_t;
+typedef unsigned long long uint_fast64_t;
+ 
+ typedef long intptr_t;
+ typedef unsigned long uintptr_t;
+diff --git a/environments/shim/include/lib/libc/stdlib.h b/environments/shim/include/lib/libc/stdlib.h
+index bbd6889..7f01cfb 100644
+--- a/environments/shim/include/lib/libc/stdlib.h
+++ b/environments/shim/include/lib/libc/stdlib.h
+@@ -30,5 +30,7 @@ void srand(unsigned int seed);
+ void malloc_add_pool(void *buf, size_t len);
+ void *malloc(size_t size);
+ void free(void *ptr);
+void *calloc(size_t nmemb, size_t size);
+void *realloc(void *ptr, size_t size);
+ 
+ #endif /* STDLIB_H */
+-- 
+2.29.2
+
@@ -0,0 +1,69 @@
+From 8603e07c95ec9c543c38181f60d0a3ead4a5f237 Mon Sep 17 00:00:00 2001
+From: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Date: Mon, 12 Apr 2021 13:12:41 +0100
+Subject: [PATCH 13/13] libsp: modify FFA ABIs with supported convention
+
+SPMC at SEL2 (hafnium) only supports 64-bit variant of FFA_RXTX_MAP
+
+Upstream-Status: Pending [Not submitted to upstream yet]
+Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+Change-Id: I17ba68bc298fd5d26dbead23dd0750b84319d9c6
+Signed-off-by: Ben Horgan <ben.horgan@arm.com>
+---
+ components/messaging/ffa/libsp/ffa.c     | 6 +++---
+ components/messaging/ffa/libsp/sp_rxtx.c | 4 ++--
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/components/messaging/ffa/libsp/ffa.c b/components/messaging/ffa/libsp/ffa.c
+index 648d3c8..2bdd31b 100644
+--- a/components/messaging/ffa/libsp/ffa.c
+++ b/components/messaging/ffa/libsp/ffa.c
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: BSD-3-Clause
+ /*
+- * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+  */
+ 
+ #include <assert.h>            // for assert
+@@ -133,14 +133,14 @@ ffa_result ffa_rxtx_map(const void *tx_buffer, const void *rx_buffer,
+ 	page_count = SHIFT_U32(page_count & FFA_RXTX_MAP_PAGE_COUNT_MASK,
+ 			       FFA_RXTX_MAP_PAGE_COUNT_SHIFT);
+ 
+-	ffa_svc(FFA_RXTX_MAP_32, (uintptr_t)tx_buffer, (uintptr_t)rx_buffer,
+	ffa_svc(FFA_RXTX_MAP_64, (uintptr_t)tx_buffer, (uintptr_t)rx_buffer,
+ 		page_count, FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ 		FFA_PARAM_MBZ, &result);
+ 
+ 	if (result.a0 == FFA_ERROR)
+ 		return ffa_get_errorcode(&result);
+ 
+-	assert(result.a0 == FFA_SUCCESS_32);
+	assert(result.a0 == FFA_SUCCESS_64);
+ 	return FFA_OK;
+ }
+ 
+diff --git a/components/messaging/ffa/libsp/sp_rxtx.c b/components/messaging/ffa/libsp/sp_rxtx.c
+index a3de270..9468d83 100644
+--- a/components/messaging/ffa/libsp/sp_rxtx.c
+++ b/components/messaging/ffa/libsp/sp_rxtx.c
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: BSD-3-Clause
+ /*
+- * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
+  */
+ 
+ #include "sp_rxtx.h"
+@@ -99,7 +99,7 @@ sp_result sp_rxtx_buffer_alignment_boundary_get(uintptr_t *alignment)
+ 		return SP_RESULT_INVALID_PARAMETERS;
+ 
+ 	/* Querying FFX_RXTX_MAP features */
+-	result = ffa_features(FFA_RXTX_MAP_32, &interface_props);
+	result = ffa_features(FFA_RXTX_MAP_64, &interface_props);
+ 	if (result != FFA_OK) {
+ 		*alignment = 0;
+ 		return SP_RESULT_FFA(result);
+-- 
+2.29.2
+
@@ -0,0 +1,41 @@
+SUMMARY = "Trusted services linux library"
+HOMEPAGE = "https://trusted-services.readthedocs.io/en/latest/index.html"
+
+LICENSE = "BSD-3-Clause"
+LIC_FILES_CHKSUM = "file://license.rst;md5=ea160bac7f690a069c608516b17997f4"
+
+SRC_URI = "git://git.trustedfirmware.org/TS/trusted-services.git;protocol=https;branch=integration \
+           file://0001-Add-a-new-environment-to-run-TS-with-a-shim-layer-in.patch \
+           file://0002-Change-instruction-access-permissions-of-shared-memo.patch \
+           file://0003-Set-in_region_count-to-0-during-memory-retrieve.patch \
+           file://0004-Release-rx-buffer-after-memory-retrieve-request.patch \
+           file://0005-crypto-sp-Create-a-new-deployment-with-the-shim-envi.patch \
+           file://0006-secure-storage-Create-a-new-deployment-with-the-shim.patch \
+           file://0007-crypto-shim-Don-t-link-against-unrequired-libraries.patch \
+           file://0008-libts-arm-linux-Add-version-to-libts.so.patch \
+           file://0009-libts-Add-option-to-use-installed-libts.patch \
+           file://0010-external-Add-option-to-use-local-source-or-installed.patch \
+           file://0011-aarch64-Allow-the-stack-to-be-further-than-1MB-from-.patch \
+           file://0012-libc-Add-missing-libc-function-declarations.patch \
+           file://0013-libsp-modify-FFA-ABIs-with-supported-convention.patch \
+           "
+
+PV = "1.0+git${SRCPV}"
+SRCREV = "eff4b28b6ae461defb2d8c0f614965439ed19386"
+
+S = "${WORKDIR}/git"
+
+inherit python3native cmake
+
+DEPENDS = "python3-pycryptodome-native python3-pycryptodomex-native \
+           python3-pyelftools-native python3-grpcio-tools-native \
+           python3-protobuf-native protobuf-native nanopb-native \
+           ts-mbedcrypto \
+           "
+
+OECMAKE_SOURCEPATH = "${S}/deployments/libts/arm-linux"
+OECMAKE_GENERATOR = "Unix Makefiles"
+EXTRA_OECMAKE = "-DCMAKE_POSITION_INDEPENDENT_CODE=True \
+                 -DCMAKE_SYSTEM_NAME=Linux \
+                 -DCMAKE_SYSTEM_PROCESSOR=arm \
+                "
@@ -0,0 +1,14 @@
+SUMMARY = "Secure storage secure partition"
+
+require sp.inc
+
+TS_DEPLOYMENT = "${S}/deployments/secure-storage/shim"
+
+do_install () {
+    install -d -m 755 ${D}/firmware
+    install -m 0644 "${B}/secure-storage.bin" "${D}/firmware/secure-storage.bin"
+    install -m 0644 "${S}/deployments/secure-storage/shim/secure-storage.dts" \
+        "${D}/firmware/secure-storage.dts"
+}
+
+FILES_${PN} = "/firmware/secure-storage.bin /firmware/secure-storage.dts"
@@ -0,0 +1,68 @@
+HOMEPAGE = "https://trusted-services.readthedocs.io/en/latest/index.html"
+
+PACKAGE_ARCH = "${MACHINE_ARCH}"
+
+LICENSE = "Apache-2.0 & BSD-3-Clause & Zlib"
+LIC_FILES_CHKSUM = "file://license.rst;md5=ea160bac7f690a069c608516b17997f4 \
+                    file://mbedcrypto/LICENSE;md5=302d50a6369f5f22efdb674db908167a \
+                    file://nanopb/LICENSE.txt;md5=9db4b73a55a3994384112efcdb37c01f \
+                    "
+SRC_URI = "git://git.trustedfirmware.org/TS/trusted-services.git;protocol=https;branch=main;name=ts;destsuffix=git \
+           git://github.com/ARMmbed/mbed-crypto.git;protocol=git;branch=development;name=mbed;destsuffix=git/mbedcrypto \
+           git://github.com/nanopb/nanopb.git;name=nanopb;branch=master;destsuffix=git/nanopb \
+           file://0001-Add-a-new-environment-to-run-TS-with-a-shim-layer-in.patch \
+           file://0002-Change-instruction-access-permissions-of-shared-memo.patch \
+           file://0003-Set-in_region_count-to-0-during-memory-retrieve.patch \
+           file://0004-Release-rx-buffer-after-memory-retrieve-request.patch \
+           file://0005-crypto-sp-Create-a-new-deployment-with-the-shim-envi.patch \
+           file://0006-secure-storage-Create-a-new-deployment-with-the-shim.patch \
+           file://0007-crypto-shim-Don-t-link-against-unrequired-libraries.patch \
+           file://0008-libts-arm-linux-Add-version-to-libts.so.patch \
+           file://0009-libts-Add-option-to-use-installed-libts.patch \
+           file://0010-external-Add-option-to-use-local-source-or-installed.patch \
+           file://0011-aarch64-Allow-the-stack-to-be-further-than-1MB-from-.patch \
+           file://0012-libc-Add-missing-libc-function-declarations.patch \
+           file://0013-libsp-modify-FFA-ABIs-with-supported-convention.patch \
+           "
+
+PV = "1.0+git${SRCPV}"
+
+SRCREV_FORMAT = "ts"
+SRCREV_ts = "eff4b28b6ae461defb2d8c0f614965439ed19386"
+SRCREV_mbed = "cf4a40ba0a3086cabb5a8227245191161fd26383"
+SRCREV_nanopb = "df0e92f474f9cca704fe2b31483f0b4d1b1715a4"
+
+S = "${WORKDIR}/git"
+TS_DEPLOYMENTS_DIR := "${S}/deployments/"
+
+inherit deploy python3native
+
+DEPENDS = "python3-pycryptodome-native python3-pycryptodomex-native \
+           python3-pyelftools-native python3-grpcio-tools-native \
+           python3-protobuf-native protobuf-native cmake-native \
+           "
+
+# Baremetal, just need a compiler
+DEPENDS_remove = "virtual/${TARGET_PREFIX}compilerlibs virtual/libc"
+
+export CROSS_COMPILE = "${TARGET_PREFIX}"
+
+B = "${WORKDIR}/build"
+
+do_configure() {
+    cmake \
+      -DMBEDCRYPTO_SOURCE_PATH=${S}/mbedcrypto \
+      -DNANOPB_SOURCE_PATH=${S}/nanopb \
+      -S ${TS_DEPLOYMENT} -B ${B}
+}
+
+do_compile() {
+    cmake --build ${B}
+}
+
+SYSROOT_DIRS = "/firmware"
+
+do_deploy() {
+    cp -rf ${D}/firmware/* ${DEPLOYDIR}/
+}
+addtask deploy after do_install
@@ -0,0 +1,59 @@
+diff --git a/CMakeLists.txt b/CMakeLists.txt
+index b1900bb..d9ca865 100644
+--- a/CMakeLists.txt
+++ b/CMakeLists.txt
+@@ -116,8 +116,13 @@ if(PkgHelpers_AVAILABLE)
+     ${CMAKE_CURRENT_BINARY_DIR}/CppUTestConfig.cmake
+     INSTALL_DESTINATION ${CMAKE_CURRENT_BINARY_DIR}
+     PATH_VARS INCLUDE_DIR CMAKE_CURRENT_BINARY_DIR)
+-  export(TARGETS CppUTest CppUTestExt
+  if(TARGET CppUTestExt)
+    export(TARGETS CppUTest
+     FILE "${CMAKE_CURRENT_BINARY_DIR}/CppUTestTargets.cmake")
+  else()
+    export(TARGETS CppUTest
+    FILE "${CMAKE_CURRENT_BINARY_DIR}/CppUTestTargets.cmake")
+  endif()
+   write_basic_package_version_file(
+     ${CMAKE_CURRENT_BINARY_DIR}/CppUTestConfigVersion.cmake
+     VERSION ${CppUTest_version_major}.${CppUTest_version_minor}
+diff --git a/cmake/Modules/CppUTestConfigurationOptions.cmake b/cmake/Modules/CppUTestConfigurationOptions.cmake
+index 634482c..a00b5eb 100644
+--- a/cmake/Modules/CppUTestConfigurationOptions.cmake
+++ b/cmake/Modules/CppUTestConfigurationOptions.cmake
+@@ -1,19 +1,19 @@
+ if (MSVC)
+-    set(CPP_PLATFORM VisualCpp)
+    set(CPP_PLATFORM VisualCpp CACHE STRING "CppUTest platform.")
+     include_directories(${CppUTestRootDirectory}/include/Platforms/${CPP_PLATFORM})
+     option(STDC_WANT_SECURE_LIB "Use MSVC safe functions" ON)
+     if(STDC_WANT_SECURE_LIB)
+       ADD_DEFINITIONS(-DSTDC_WANT_SECURE_LIB)
+     endif(STDC_WANT_SECURE_LIB)
+ elseif (STD_C)
+-    set(CPP_PLATFORM Gcc)
+    set(CPP_PLATFORM Gcc CACHE STRING "CppUTest platform.")
+ else (MSVC)
+     set(STD_CPP False)
+     set(MEMORY_LEAK_DETECTION False)
+     set(CPPUTEST_CXX_FLAGS "${CPPUTEST_CXX_FLAGS} -nostdinc")
+     set(CPPUTEST_LD_FLAGS "${CPPUTEST_LD_FLAGS} -nostdinc")
+     set(CPPUTEST_STD_C_LIB_DISABLED 1)
+-    set(CPP_PLATFORM GccNoStdC)
+    set(CPP_PLATFORM GccNoStdC CACHE STRING "CppUTest platform.")
+ endif (MSVC)
+ 
+ include("${CppUTestRootDirectory}/cmake/Modules/CppUTestWarningFlags.cmake")
+diff --git a/src/CppUTest/CMakeLists.txt b/src/CppUTest/CMakeLists.txt
+index 736777f..d9a592f 100644
+--- a/src/CppUTest/CMakeLists.txt
+++ b/src/CppUTest/CMakeLists.txt
+@@ -50,7 +50,7 @@ set(CppUTest_headers
+ 
+ add_library(CppUTest STATIC ${CppUTest_src} ${CppUTest_headers})
+ if (WIN32)
+-    target_link_libraries(CppUTest winmm.lib)
+    target_link_libraries(CppUTest winmm)
+ endif (WIN32)
+ install(FILES ${CppUTest_headers} DESTINATION include/CppUTest)
+ install(TARGETS CppUTest
@@ -0,0 +1,30 @@
+SUMMARY = "CppUTest for trusted services"
+DESCRIPTION = "CppUTest unit testing and mocking framework for C/C++"
+HOMEPAGE = "http://cpputest.github.io/"
+
+LICENSE = "BSD-3-Clause"
+LIC_FILES_CHKSUM = "file://COPYING;md5=ce5d5f1fe02bcd1343ced64a06fd4177"
+
+SRC_URI = "git://github.com/cpputest/cpputest.git \
+           file://cpputest-cmake-fix.patch \
+           "
+SRCREV = "e25097614e1c4856036366877a02346c4b36bb5b"
+
+PV = "3.8+git${SRCPV}"
+
+S = "${WORKDIR}/git"
+
+inherit cmake
+
+OECMAKE_GENERATOR = "Unix Makefiles"
+EXTRA_OECMAKE = "-DCMAKE_POSITION_INDEPENDENT_CODE=True \
+                 -DMEMORY_LEAK_DETECTION=OFF \
+                 -DLONGLONG=ON \
+                 -DC++11=ON \
+                 -DTESTS=OFF \
+                 -DEXTENSIONS=OFF \
+                 -DHAVE_FORK=OFF \
+                 -DCPP_PLATFORM=armcc \
+                 -DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY \
+                 "
+FILES_${PN} += "/usr/lib/CppUTest/* /usr/lib/CppUTest/cmake/*"
@@ -0,0 +1,42 @@
+SUMMARY = "Trusted Services test application"
+HOMEPAGE = "https://trusted-services.readthedocs.io/en/latest/index.html"
+
+LICENSE = "BSD-3-Clause"
+LIC_FILES_CHKSUM = "file://license.rst;md5=ea160bac7f690a069c608516b17997f4"
+
+SRC_URI = "git://git.trustedfirmware.org/TS/trusted-services.git;protocol=ssh;branch=main \
+           file://0001-Add-a-new-environment-to-run-TS-with-a-shim-layer-in.patch \
+           file://0002-Change-instruction-access-permissions-of-shared-memo.patch \
+           file://0003-Set-in_region_count-to-0-during-memory-retrieve.patch \
+           file://0004-Release-rx-buffer-after-memory-retrieve-request.patch \
+           file://0005-crypto-sp-Create-a-new-deployment-with-the-shim-envi.patch \
+           file://0006-secure-storage-Create-a-new-deployment-with-the-shim.patch \
+           file://0007-crypto-shim-Don-t-link-against-unrequired-libraries.patch \
+           file://0008-libts-arm-linux-Add-version-to-libts.so.patch \
+           file://0009-libts-Add-option-to-use-installed-libts.patch \
+           file://0010-external-Add-option-to-use-local-source-or-installed.patch \
+           file://0011-aarch64-Allow-the-stack-to-be-further-than-1MB-from-.patch \
+           file://0012-libc-Add-missing-libc-function-declarations.patch \
+           file://0013-libsp-modify-FFA-ABIs-with-supported-convention.patch \
+          "
+
+PV = "1.0+git${SRCPV}"
+SRCREV = "eff4b28b6ae461defb2d8c0f614965439ed19386"
+
+S = "${WORKDIR}/git"
+
+inherit python3native cmake
+
+DEPENDS = "python3-pycryptodome-native python3-pycryptodomex-native \
+           python3-pyelftools-native python3-grpcio-tools-native \
+           python3-protobuf-native protobuf-native nanopb nanopb-native \
+           ts-mbedcrypto libts \
+           "
+
+OECMAKE_SOURCEPATH = "${S}/deployments/ts-demo/arm-linux"
+OECMAKE_GENERATOR = "Unix Makefiles"
+EXTRA_OECMAKE = "-DCMAKE_POSITION_INDEPENDENT_CODE=True \
+                 -DMBEDCRYPTO_USE_INSTALLED=True \
+                 -DNANOPB_USE_INSTALLED=True \
+                 -DLIBTS_USE_INSTALLED=True \
+                 "
@@ -0,0 +1,46 @@
+SUMMARY = "Mbedcrypto for trusted services"
+DESCRIPTION = "A reference implementation of the cryptography \
+interface of the Arm Platform Security Architecture (PSA). Compiled \
+with the configuration for trusted services."
+HOMEPAGE = "https://github.com/ARMmbed/mbed-crypto"
+
+LICENSE = "Apache-2.0 & BSD-3-Clause"
+LIC_FILES_CHKSUM = "file://LICENSE;md5=302d50a6369f5f22efdb674db908167a \
+                    file://ts/license.rst;md5=ea160bac7f690a069c608516b17997f4 \
+                    "
+SRC_URI = "git://github.com/ARMmbed/mbed-crypto.git;protocol=git;branch=development;name=mbed;destsuffix=git \
+           git://git.trustedfirmware.org/TS/trusted-services.git;protocol=https;branch=main;name=ts;destsuffix=git/ts \
+           file://0001-Add-a-new-environment-to-run-TS-with-a-shim-layer-in.patch;patchdir=${S}/ts \
+           file://0002-Change-instruction-access-permissions-of-shared-memo.patch;patchdir=${S}/ts \
+           file://0003-Set-in_region_count-to-0-during-memory-retrieve.patch;patchdir=${S}/ts \
+           file://0004-Release-rx-buffer-after-memory-retrieve-request.patch;patchdir=${S}/ts \
+           file://0005-crypto-sp-Create-a-new-deployment-with-the-shim-envi.patch;patchdir=${S}/ts \
+           file://0006-secure-storage-Create-a-new-deployment-with-the-shim.patch;patchdir=${S}/ts \
+           file://0007-crypto-shim-Don-t-link-against-unrequired-libraries.patch;patchdir=${S}/ts \
+           file://0008-libts-arm-linux-Add-version-to-libts.so.patch;patchdir=${S}/ts \
+           file://0009-libts-Add-option-to-use-installed-libts.patch;patchdir=${S}/ts \
+           file://0010-external-Add-option-to-use-local-source-or-installed.patch;patchdir=${S}/ts \
+           file://0011-aarch64-Allow-the-stack-to-be-further-than-1MB-from-.patch;patchdir=${S}/ts \
+           file://0012-libc-Add-missing-libc-function-declarations.patch;patchdir=${S}/ts \
+           file://0013-libsp-modify-FFA-ABIs-with-supported-convention.patch;patchdir=${S}/ts \
+           "
+
+PV = "3.1.0+git"
+
+SRCREV_FORMAT = "mbed"
+SRCREV_mbed = "cf4a40ba0a3086cabb5a8227245191161fd26383"
+SRCREV_ts = "eff4b28b6ae461defb2d8c0f614965439ed19386"
+
+S = "${WORKDIR}/git"
+
+inherit cmake
+
+MBEDCRYPTO_CONFIG_FILE = "${S}/ts/components/service/crypto/client/cpp/config_mbed_crypto.h"
+
+OECMAKE_GENERATOR = "Unix Makefiles"
+EXTRA_OECMAKE = "-DCMAKE_POSITION_INDEPENDENT_CODE=True \
+                 -DENABLE_PROGRAMS=OFF \
+                 -DENABLE_TESTING=OFF \
+                 -DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY \
+                 -Dthirdparty_def=-DMBEDTLS_CONFIG_FILE=\"${MBEDCRYPTO_CONFIG_FILE}\" \
+                 "
@@ -0,0 +1,42 @@
+SUMMARY = "Trusted Services demo application"
+HOMEPAGE = "https://trusted-services.readthedocs.io/en/latest/index.html"
+
+LICENSE = "BSD-3-Clause"
+LIC_FILES_CHKSUM = "file://license.rst;md5=ea160bac7f690a069c608516b17997f4"
+
+SRC_URI = "git://git.trustedfirmware.org/TS/trusted-services.git;protocol=https;branch=main \
+           file://0001-Add-a-new-environment-to-run-TS-with-a-shim-layer-in.patch \
+           file://0002-Change-instruction-access-permissions-of-shared-memo.patch \
+           file://0003-Set-in_region_count-to-0-during-memory-retrieve.patch \
+           file://0004-Release-rx-buffer-after-memory-retrieve-request.patch \
+           file://0005-crypto-sp-Create-a-new-deployment-with-the-shim-envi.patch \
+           file://0006-secure-storage-Create-a-new-deployment-with-the-shim.patch \
+           file://0007-crypto-shim-Don-t-link-against-unrequired-libraries.patch \
+           file://0008-libts-arm-linux-Add-version-to-libts.so.patch \
+           file://0009-libts-Add-option-to-use-installed-libts.patch \
+           file://0010-external-Add-option-to-use-local-source-or-installed.patch \
+           file://0011-aarch64-Allow-the-stack-to-be-further-than-1MB-from-.patch \
+           file://0012-libc-Add-missing-libc-function-declarations.patch \
+           file://0013-libsp-modify-FFA-ABIs-with-supported-convention.patch \
+          "
+
+PV = "1.0+git${SRCPV}"
+SRCREV = "eff4b28b6ae461defb2d8c0f614965439ed19386"
+
+S = "${WORKDIR}/git"
+
+inherit deploy python3native cmake
+
+DEPENDS = "python3-pycryptodome-native python3-pycryptodomex-native \
+           python3-pyelftools-native python3-grpcio-tools-native \
+           python3-protobuf-native protobuf-native nanopb nanopb-native \
+           ts-mbedcrypto libts ts-cpputest"
+
+OECMAKE_SOURCEPATH = "${S}/deployments/ts-service-test/arm-linux"
+OECMAKE_GENERATOR = "Unix Makefiles"
+EXTRA_OECMAKE = "-DCMAKE_POSITION_INDEPENDENT_CODE=True \
+                 -DMBEDCRYPTO_USE_INSTALLED=True \
+                 -DNANOPB_USE_INSTALLED=True \
+                 -DLIBTS_USE_INSTALLED=True \
+                 -DCPPUTEST_USE_INSTALLED=True \
+                "
Author	SHA1	Message	Date
Tushar Khandelwal	f90f028646	Revert "arm-bsp/tc0: Enable verified u-boot" This reverts commit `29cee51f84`.	2021-04-22 23:27:47 +01:00
Tushar Khandelwal	1cba8aee6d	Revert "arm-bsp/u-boot: update SHA for tc0" This reverts commit `70a9c4991e`.	2021-04-22 23:24:10 +01:00
Tushar Khandelwal	5262d3d174	Revert "arm-bsp/images: Add tc0-kernel-image" This reverts commit `da57312334`.	2021-04-22 23:23:34 +01:00
Tushar Khandelwal	664d2a5f6a	Revert "arm-bsp: Enable SPM build option in yocto framework" This reverts commit `86f9419b9d`.	2021-04-22 23:23:13 +01:00
Tushar Khandelwal	ebee7ce68d	Revert "tc0/spm: boot SP according to boot order specified in manifest" This reverts commit `56514201ad`.	2021-04-22 23:22:02 +01:00
Tushar Khandelwal	cc645908ef	Merge branch 'upstream' into totalcompute	2021-04-22 22:36:21 +01:00
Ben Horgan	36314f2d87	arm-bsp/tc0: Add secure partitions secure-storage and crypo-sp These are added along with the existing optee secure partition. Change-Id: I50ce8adfa264d442cf52863f4f8572e623504ca3 Signed-off-by: Ben Horgan <ben.horgan@arm.com>	2021-04-22 22:25:47 +01:00
Ben Horgan	cddb08a7a2	arm-trusted-services: Add recipes for arm trusted services Signed-off-by: Ben Horgan <ben.horgan@arm.com> Change-Id: I14ac7649ae5899578167efca45d5c19d6248cb8f	2021-04-22 22:25:47 +01:00
Arunachalam Ganapathy	5d47d3f9db	arm-bsp/linux: Add linux-trusted-services driver, FF-A ABI changes for TC0 This adds below patches: - buf driver for trusted service test applications - Fix in FFA-ABI aligning with latest SPMC (hafnium) Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I6b36a73a910f6e10748d78b2ad74603dde42c8a9	2021-04-22 22:25:47 +01:00
Arunachalam Ganapathy	9d1724c3d4	arm-bsp/tc0: Update hafnium revision and add patches - Remove PSCI patches as those changes are upstreamed - Adds Theodul, GICR changes - Reverts FFA Set and verify allocator fix - Adds fix to fetch proper vCPU for UP SP Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I26a7b31558e5bc4ce2fea61b76a3a92615f3e641	2021-04-22 22:25:47 +01:00
Arunachalam Ganapathy	29f0e5982c	arm-bsp/tc0: Add patches in optee-os for FF-A ABI changes Adds below patches: - To use FFA_SECONDARY_EP_REGISTER - To align with latest FFA_ABIs in SPMC (hafnium) Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I4ae386e2dd846e747cbc426270fc0c489ccdfe1f	2021-04-22 22:25:47 +01:00
Arunachalam Ganapathy	853f3e0565	arm-bsp/tc0: Update TF-A revision, add trusted-services support - Update TF-A revision - Add patch for trusted services support - Add patch for GICR changes to support latest tc0 model Change-Id: I3ba1fd9c1f89721fc6349db4e0270c8b42e9fcf0 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>	2021-04-22 22:25:47 +01:00
Arunachalam Ganapathy	806bbb07ed	arm-bsp/tc0: Update SCP firmware revision and add patches Add below patches: - add clock and dvfs support for all cores - fix in CFGM base address calculation Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I2e70736070dd59f6209012dc875f3ea08d811046	2021-04-22 22:25:47 +01:00
Arunachalam Ganapathy	9bb19dd0d6	arm-bsp/tc0: add Theodul DSU support - Adds patches required to support Theodul DSU in optee-os, hafnium - Updates SHA of TF-A, SCP with revision that has Theodul DSU support Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: I62f0990b7de919839be9ab0e3234914624c8afde Signed-off-by: Jon Mason <jon.mason@arm.com>	2021-04-22 22:25:47 +01:00
Arunachalam Ganapathy	88c201ca9d	arm-bsp/linux: add asymmetric AArch32 EL0 support for TC0 This adds patches for asymmetric AArch32 EL0 configuration support for android11-5.4-lts kernel. And enables CONFIG_ASYMMETRIC_AARCH32 and disables CONFIG_KVM in TC0 defconfig. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Iab94b5c48b60aca4a71267ba1be1cb1836002d10 Signed-off-by: Jon Mason <jon.mason@arm.com>	2021-04-22 22:25:47 +01:00
Usama Arif	56514201ad	tc0/spm: boot SP according to boot order specified in manifest This is currently in review at: https://review.trustedfirmware.org/c/hafnium/hafnium/+/4997/36 Signed-off-by: Usama Arif <usama.arif@arm.com>	2020-10-27 17:35:35 +00:00
Arunachalam Ganapathy	86f9419b9d	arm-bsp: Enable SPM build option in yocto framework This patch adds: spm, tf-a-tests recipes. This builds tf-a with SPM at S-EL2 and test secure partitions at S-EL1. Change-Id: Ia2f44f4000aa0786b945bc8fb66c9edb1a0094e8 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Signed-off-by: Usama Arif <usama.arif@arm.com>	2020-10-27 17:35:26 +00:00
Usama Arif	da57312334	arm-bsp/images: Add tc0-kernel-image This depends on trusted-firmware-a which is the last component to be built. Calling bitbake tc0-kernel-image will create all the required images to boot poky. Change-Id: Ia8675b048db4a127d32394f536632ce88fe20826 Signed-off-by: Usama Arif <usama.arif@arm.com>	2020-10-26 18:26:37 +00:00
Usama Arif	70a9c4991e	arm-bsp/u-boot: update SHA for tc0 Change-Id: Ideb4866df92d05bdc07b53f47346ae4f381dfc6d Signed-off-by: Usama Arif <usama.arif@arm.com>	2020-10-26 18:26:35 +00:00
Usama Arif	29cee51f84	arm-bsp/tc0: Enable verified u-boot This involes creating the fitImage which contains both the kernel and ramdisk. The fitImage is also signed. Change-Id: Iaedffd54751585a7ef6b467d63f5f8fb6e744aa7 Signed-off-by: Usama Arif <usama.arif@arm.com>	2020-10-26 18:20:22 +00:00